Add more primitives to data/

2 files changed, 77 insertions, 7 deletions

diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v
index d729549..97ecac7 100644
--- a/data/cells_xilinx_7.v
+++ b/data/cells_xilinx_7.v
@@ -146,3 +146,67 @@ module LDCE (Q, CLR, D, G, GE);
      else if (G_in && GE)
        Q <= D;
 endmodule
+
+module BUFG (O, I);
+   output O;
+   input  I;
+   buf B1 (O, I);
+endmodule
+
+module FDRE (Q, C, CE, D, R);
+
+   parameter [0:0] INIT = 1'b0;
+   parameter [0:0] IS_C_INVERTED = 1'b0;
+   parameter [0:0] IS_D_INVERTED = 1'b0;
+   parameter [0:0] IS_R_INVERTED = 1'b0;
+
+   output Q;
+   reg    Q = INIT;
+
+   input  C, CE, D, R;
+   wire   C_in, D_in, R_in;
+
+   assign C_in = C ^ IS_C_INVERTED;
+   assign D_in = D ^ IS_D_INVERTED;
+   assign R_in = R ^ IS_R_INVERTED;
+
+   always @(posedge C_in)
+     if (R_in)
+       Q <= 0;
+     else if (CE)
+       Q <= D_in;
+
+endmodule
+
+module FDSE (Q, C, CE, D, S);
+
+   parameter INIT = 1'b1;
+   parameter [0:0] IS_C_INVERTED = 1'b0;
+   parameter [0:0] IS_S_INVERTED = 1'b0;
+   parameter [0:0] IS_D_INVERTED = 1'b0;
+
+   output Q;
+
+   input  C, CE, D, S;
+
+   wire   Q;
+   wire   C_in;
+   wire   S_in;
+   wire   D_in;
+   wire   rst_int = 0;
+   wire   set_int = S;
+   reg    q_out;
+
+   initial q_out = INIT;
+
+   assign Q = q_out;
+   assign C_in = IS_C_INVERTED ^ C;
+   assign S_in = IS_S_INVERTED ^ S;
+   assign D_in = IS_D_INVERTED ^ D;
+
+   always @(posedge C_in)
+	 if (S_in)
+	   q_out <=  1;
+	 else if (CE)
+	   q_out <=  D_in;
+endmodule
diff --git a/data/cells_yosys.v b/data/cells_yosys.v
index 48f9c66..adb8adb 100644
--- a/data/cells_yosys.v
+++ b/data/cells_yosys.v
@@ -1,13 +1,19 @@
-// Taken from yosys verilog files.
+// Taken from yosys simcells.v
 
 module \$_DLATCH_N_ (E, D, Q);
-   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
-   input         E, D;
-   output        Q = !E ? D : Q;
+   input E, D;
+   output reg Q;
+   always @* begin
+	  if (E == 0)
+		Q <= D;
+   end
 endmodule
 
 module \$_DLATCH_P_ (E, D, Q);
-   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
-   input         E, D;
-   output        Q = E ? D : Q;
+   input E, D;
+   output reg Q;
+   always @* begin
+	  if (E == 1)
+		Q <= D;
+   end
 endmodule