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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-05 10:17:11 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-05 10:17:11 +0000 |
| commit | a083073ec8ccac04861e06223b117304bd517565 (patch) | |
| tree | e2ea476324a1a36b56fbd5c9246826027be90c07 /data | |
| parent | d70cb8900f1ac53611cf6700313ae88a23013032 (diff) | |
| download | verismith-a083073ec8ccac04861e06223b117304bd517565.tar.gz verismith-a083073ec8ccac04861e06223b117304bd517565.zip | |
Add asynchronous load
Diffstat (limited to 'data')
| -rw-r--r-- | data/cells_cyclone_v.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/data/cells_cyclone_v.v b/data/cells_cyclone_v.v index 6938ac9..4fcd49d 100644 --- a/data/cells_cyclone_v.v +++ b/data/cells_cyclone_v.v @@ -220,8 +220,12 @@ module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, devclrn, devp output reg q = 0; - always @(posedge clk) begin - if (sload == 1'b1) + always @(posedge clk or posedge aload) begin + if (sclr == 1'b1) + q <= 0; + else if (aload == 1'b1) + q <= asdata; + else if (sload == 1'b1) q <= asdata; else q <= d; |