Better format for the Verilog file

1 files changed, 6 insertions, 6 deletions

diff --git a/examples/simple.v b/examples/simple.v
index 10b7f0a..86c2f8b 100644
--- a/examples/simple.v
+++ b/examples/simple.v
@@ -1,9 +1,10 @@
-module and_comb(in1, in2, out);
-   input in1;
-   input in2;
-   output out;
+module and_comb(input wire  in1,
+                input wire  in2,
+                output wire out
+                );
 
    and and1(out, in1, in2);
+
 endmodule
 
 module main;
@@ -16,8 +17,7 @@ module main;
      begin
         a = 1'b1;
         b = 1'b1;
-        #1
-        $display("%d & %d = %d", a, b, c);
+        #1 $display("%d & %d = %d", a, b, c);
         $finish;
      end
 endmodule