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authorYann Herklotz <ymherklotz@gmail.com>2018-11-08 17:39:09 +0000
committerYann Herklotz <ymherklotz@gmail.com>2018-11-08 17:39:09 +0000
commitd16507bca82b3ffe4f583ef8f4893722c9d04239 (patch)
tree334e54cf929aeae7382ec726a00cf8ec6d80a396 /examples
parente7f7d1988ad9a161ba10e36859dc04a92422a4e0 (diff)
downloadverismith-d16507bca82b3ffe4f583ef8f4893722c9d04239.tar.gz
verismith-d16507bca82b3ffe4f583ef8f4893722c9d04239.zip
Rename folder to examples
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diff --git a/examples/simple.v b/examples/simple.v
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+module and_comb(in1, in2, out);
+ input in1;
+ input in2;
+ output out;
+
+ assign out = in1 & in2;
+endmodule
+
+module main;
+ reg a, b;
+ wire c;
+
+ and_comb gate(.in1(a), .in2(b), .out(c));
+
+ initial
+ begin
+ a = 1'b1;
+ b = 1'b1;
+ #1
+ $display("%d & %d = %d", a, b, c);
+ $finish;
+ end
+endmodule