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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:35 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-30 12:03:35 +0100 |
| commit | 2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0 (patch) | |
| tree | e3aa69d19c40261a42a25ee8e5ec860d896919eb /src/Test/VeriFuzz/Graph | |
| parent | b25eee73ce7cf8270ccf633443cee88040eaca67 (diff) | |
| download | verismith-2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0.tar.gz verismith-2de15f8f32d48b09a9a2c92c25b6b0b3bb4492e0.zip | |
[Fix #14] Add size to Port type
Diffstat (limited to 'src/Test/VeriFuzz/Graph')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index 00eb71d..cf996de 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -44,7 +44,7 @@ genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] genPortsAST f c = (port . frNode <$> f c) where - port = Port $ PortNet Wire + port = Port (PortNet Wire) 1 -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items where id = Identifier "gen_module" ports = genPortsAST inputsC c - output = Just $ Port (PortNet Wire) "y" + output = Just $ Port (PortNet Wire) 1 "y" items = genAssignAST c generateAST :: Circuit -> VerilogSrc |