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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 23:41:26 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 23:41:26 +0100 |
| commit | 8e4fab352bad77b91b248c1f50e1b0554793b689 (patch) | |
| tree | 4c6b13fe8adcea4626f2a35567bdc77e4f90c792 /src/Test/VeriFuzz | |
| parent | 05750369a1567b54b2a9d6859138a312d5651093 (diff) | |
| download | verismith-8e4fab352bad77b91b248c1f50e1b0554793b689.tar.gz verismith-8e4fab352bad77b91b248c1f50e1b0554793b689.zip | |
Fix verilog output for output port
Diffstat (limited to 'src/Test/VeriFuzz')
| -rw-r--r-- | src/Test/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs index e1114d2..7861294 100644 --- a/src/Test/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs @@ -47,7 +47,7 @@ genModuleDecl mod = where ports | noIn && noOut = "" - | otherwise = "(" <> out <> (sep ", " $ genModPort <$> mod ^. modInPorts) <> ")" + | otherwise = "(" <> out <> (sep_ ", " $ genModPort <$> mod ^. modInPorts) <> ")" modItems = fromList $ genModuleItem <$> mod ^. moduleItems noOut = isNothing $ mod ^. modOutPort noIn = null $ mod ^. modInPorts |