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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 14:28:30 +0000 |
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| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 14:28:30 +0000 |
| commit | f28188fc54d187b501b861d43592702bc7e460ec (patch) | |
| tree | c1d898d080dcfa44a5461218a047d04883076a23 /src/VeriFuzz/Mutate.hs | |
| parent | a83b3b40f683400914d0f3ae23bd9e69e6e0fd96 (diff) | |
| download | verismith-f28188fc54d187b501b861d43592702bc7e460ec.tar.gz verismith-f28188fc54d187b501b861d43592702bc7e460ec.zip | |
Add export lists
Diffstat (limited to 'src/VeriFuzz/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Mutate.hs | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs index d012358..56db6c4 100644 --- a/src/VeriFuzz/Mutate.hs +++ b/src/VeriFuzz/Mutate.hs @@ -18,7 +18,6 @@ import Data.Maybe (catMaybes, fromMaybe) import Data.Text (Text) import qualified Data.Text as T import VeriFuzz.AST -import VeriFuzz.CodeGen import VeriFuzz.Internal -- | Return if the 'Identifier' is in a 'ModDecl'. @@ -74,8 +73,12 @@ nestUpTo :: Int -> VerilogSrc -> VerilogSrc nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i] allVars :: ModDecl -> [Identifier] -allVars m = (m ^.. modOutPorts . traverse . portName) ++ (m ^.. modInPorts . traverse . portName) +allVars m = + (m ^.. modOutPorts . traverse . portName) + <> (m ^.. modInPorts . traverse . portName) + -- $setup +-- >>> import VeriFuzz.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] []) -- >>> let main = (ModDecl "main" [] [] []) |