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authorYann Herklotz <git@ymhg.org>2019-04-02 13:04:07 +0100
committerYann Herklotz <git@ymhg.org>2019-04-02 13:04:07 +0100
commitcad6bef3afe5919b987bb723cf0907cba39a000d (patch)
tree8a1986b0735cf9cafff8f3eecaa23fe845d464fb /src/VeriFuzz/Random.hs
parentc2accfb8cc182e591021efef7a2ad9b6ebc13a1e (diff)
downloadverismith-cad6bef3afe5919b987bb723cf0907cba39a000d.tar.gz
verismith-cad6bef3afe5919b987bb723cf0907cba39a000d.zip
Switch to Hedgehog in graph and verilog generation
Diffstat (limited to 'src/VeriFuzz/Random.hs')
-rw-r--r--src/VeriFuzz/Random.hs11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/VeriFuzz/Random.hs b/src/VeriFuzz/Random.hs
index 4330543..947f74e 100644
--- a/src/VeriFuzz/Random.hs
+++ b/src/VeriFuzz/Random.hs
@@ -59,14 +59,3 @@ randomDAG = do
-- | Generate a random acyclic DAG with an IO instance.
genRandomDAG :: IO Circuit
genRandomDAG = Hog.sample randomDAG
-
--- fromGraph :: Gen ModDecl
--- fromGraph = do
--- gr <- rDupsCirc <$> Hog.resize 100 randomCircuit
--- return
--- $ initMod
--- . head
--- $ nestUpTo 5 (generateAST gr)
--- ^.. getVerilogSrc
--- . traverse
--- . getDescription