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| author | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
| commit | 186bb5f37770c150bd8e601e9761211af6a9c277 (patch) | |
| tree | 33ccc13403d1c9a168909b1e9987f29028834396 /src/VeriFuzz/Sim/Internal.hs | |
| parent | aefb46596f3f2302540a83b2be8b042232822a2f (diff) | |
| download | verismith-186bb5f37770c150bd8e601e9761211af6a9c277.tar.gz verismith-186bb5f37770c150bd8e601e9761211af6a9c277.zip | |
Fix the generation of modules and add initialisation
Diffstat (limited to 'src/VeriFuzz/Sim/Internal.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Internal.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index 925b155..145042a 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -74,7 +74,7 @@ mainModule = lens get_ set_ set_ (SourceInfo top main) v = SourceInfo top (main & getModule %~ update top v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v - | otherwise = m + | otherwise = m get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top |