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authorYann Herklotz <ymherklotz@gmail.com>2019-01-23 19:36:18 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-01-23 19:36:18 +0000
commit49291d38214cbdbf084fecc931e7e5d5732a742c (patch)
tree8ffafa29fdd18ae0408ad352303b243ba4f730e5 /src/VeriFuzz/Simulator/Yosys.hs
parent12100f95c1d0560b8dd8cd0408a2c4837e9cdde6 (diff)
downloadverismith-49291d38214cbdbf084fecc931e7e5d5732a742c.tar.gz
verismith-49291d38214cbdbf084fecc931e7e5d5732a742c.zip
Add echo do all the simulators
Diffstat (limited to 'src/VeriFuzz/Simulator/Yosys.hs')
-rw-r--r--src/VeriFuzz/Simulator/Yosys.hs3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs
index c63d549..e18de5a 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Simulator/Yosys.hs
@@ -47,6 +47,7 @@ writeSimFile _ m file = do
runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
runSynthYosys sim m outf = do
writefile inpf $ genSource m
+ echoP "Run yosim"
noPrint $ run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
where
inpf = "rtl.v"
@@ -64,6 +65,7 @@ runEquivYosys yosys sim1 sim2 m = do
writefile checkFile $ yosysSatConfig sim1 sim2 m
runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
runMaybeSynth sim2 m
+ echoP "Run yosys"
noPrint $ run_ (yosysPath yosys) [toTextIgnore checkFile]
where
checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
@@ -75,4 +77,5 @@ runEquiv yosys sim1 sim2 m = do
writefile "test.sby" $ sbyConfig root sim1 sim2 m
runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
runMaybeSynth sim2 m
+ echoP "Run SymbiYosys"
noPrint $ run_ "sby" ["test.sby"]