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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:13 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:33:17 +0000 |
| commit | 99fe59abc997ba6f65896a2377881409e257faf9 (patch) | |
| tree | b83a36efac0fd0fcdd3838f3321428d6bd2de6e3 /src/VeriFuzz/Verilog/Helpers.hs | |
| parent | 64a0ae3600073f486462b1d056409954634b0084 (diff) | |
| download | verismith-99fe59abc997ba6f65896a2377881409e257faf9.tar.gz verismith-99fe59abc997ba6f65896a2377881409e257faf9.zip | |
Rename moduleId to modId
Diffstat (limited to 'src/VeriFuzz/Verilog/Helpers.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Helpers.hs | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index 4771329..99e5f38 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -28,7 +28,7 @@ emptyMod = ModDecl "" [] [] [] -- | Set a module name for a module declaration. setModName :: Text -> ModDecl -> ModDecl -setModName str = moduleId .~ Identifier str +setModName str = modId .~ Identifier str -- | Add a input port to the module declaration. addModPort :: Port -> ModDecl -> ModDecl @@ -67,3 +67,6 @@ defaultPort = Port Wire 1 portToExpr :: Port -> Expr portToExpr (Port _ _ i) = Id i + +modName :: ModDecl -> Text +modName = view $ modId . getIdentifier |