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| author | Yann Herklotz <git@yannherklotz.com> | 2020-03-16 13:12:30 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-03-16 13:12:30 +0000 |
| commit | 472aedf5daeb1cb0d095a63eacf259b798f56586 (patch) | |
| tree | 8e7e32b3ff2d762b90d8b460926adb83408a6263 /src/Verismith/Circuit.hs | |
| parent | 010d7343133ebe53a472b9d26fdeb509db31d4c9 (diff) | |
| download | verismith-472aedf5daeb1cb0d095a63eacf259b798f56586.tar.gz verismith-472aedf5daeb1cb0d095a63eacf259b798f56586.zip | |
WIP changes to the AST types
Diffstat (limited to 'src/Verismith/Circuit.hs')
| -rw-r--r-- | src/Verismith/Circuit.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Circuit.hs b/src/Verismith/Circuit.hs index 9ca1de7..cda2f4f 100644 --- a/src/Verismith/Circuit.hs +++ b/src/Verismith/Circuit.hs @@ -34,7 +34,7 @@ import Verismith.Circuit.Random import Verismith.Verilog.AST import Verismith.Verilog.Mutate -fromGraph :: Gen ModDecl +fromGraph :: Gen (ModDecl ann) fromGraph = do gr <- rDupsCirc <$> Hog.resize 100 randomDAG return |