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| author | Yann Herklotz <git@yannherklotz.com> | 2020-04-07 01:31:45 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-07 01:31:45 +0100 |
| commit | 39dfa92affb1271dc6f714dfca0e13ba72e72e24 (patch) | |
| tree | c5e2472eeae15c47ab6ad9ee3783d1e81a7d93b4 /src/Verismith/Verilog/AST.hs | |
| parent | 2b00c249a29236af734c1e5b717b859a2a54a5dc (diff) | |
| download | verismith-39dfa92affb1271dc6f714dfca0e13ba72e72e24.tar.gz verismith-39dfa92affb1271dc6f714dfca0e13ba72e72e24.zip | |
Add annotations and make it compile again
Diffstat (limited to 'src/Verismith/Verilog/AST.hs')
| -rw-r--r-- | src/Verismith/Verilog/AST.hs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/Verismith/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs index 74c3cfb..3d7c96e 100644 --- a/src/Verismith/Verilog/AST.hs +++ b/src/Verismith/Verilog/AST.hs @@ -618,9 +618,11 @@ aModule t = lens get_ set_ SourceInfo top (main & getModule %~ update (getIdentifier t) v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v | otherwise = m + update top v (ModDeclAnn _ m) = update top v m get_ (SourceInfo _ main) = head . filter (f $ getIdentifier t) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top + f top (ModDeclAnn _ m) = f top m -- | May need to change this to Traversal to be safe. For now it will fail when @@ -632,5 +634,7 @@ mainModule = lens get_ set_ SourceInfo top (main & getModule %~ update top v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v | otherwise = m + update top v (ModDeclAnn _ m) = update top v m get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top + f top (ModDeclAnn _ m) = f top m |