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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-11 21:48:58 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-11 21:48:58 +0000
commit4d1efed4ddc19b5394b6ba8b0c6366521f38114b (patch)
tree5b789e7ef715c87b256a8435cff0c2f1376eed76 /src
parentdf3723a3bf1e131181980d5a8d72c9af8a79f5d9 (diff)
downloadverismith-4d1efed4ddc19b5394b6ba8b0c6366521f38114b.tar.gz
verismith-4d1efed4ddc19b5394b6ba8b0c6366521f38114b.zip
Fix versions and tests
Diffstat (limited to 'src')
-rw-r--r--src/VeriFuzz/Mutate.hs4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs
index 61fdd7a..d012358 100644
--- a/src/VeriFuzz/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
@@ -218,10 +218,6 @@ simplify e = e
--
-- >>> GenVerilog . removeId ["x"] $ Id "x" + Id "y"
-- (x + (-1'h0))
---
--- This can be combined with 'simplify' to completely remove an identifier.
---
--- >>> GenVerilog . simplify . removeId ["z"] $ Id "x" + Id "y" - Id "z"
removeId :: [Identifier] -> Expr -> Expr
removeId i expr =
transform trans expr