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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-02 22:54:27 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-02 22:54:27 +0000 |
| commit | ad5d8bced5aec1e887c44e7e3c26a9b74c5a3ba5 (patch) | |
| tree | ae11500ffbfd90a91219e267f7dd34cd97f3e7be /src | |
| parent | 4c20555200628f9f3b32ac4d08ea104dc9ef0560 (diff) | |
| download | verismith-ad5d8bced5aec1e887c44e7e3c26a9b74c5a3ba5.tar.gz verismith-ad5d8bced5aec1e887c44e7e3c26a9b74c5a3ba5.zip | |
Add timeout and timeout check
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index e64104a..d7b0014 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -48,7 +48,7 @@ runSynthYosys sim m outf = do dir <- pwd writefile inpf $ genSource m echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ run (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] + _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] echoP "Yosys: synthesis done" where inpf = "rtl.v" |