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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-23 19:35:52 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-23 19:35:52 +0000 |
| commit | fe0f44b2f1609bb8d5097a85daec51e5f9ffdaf0 (patch) | |
| tree | 4d1cf18625ce7402b7fa85d3bca8a73440f9068c /src | |
| parent | 2ed242865bed7295080a463eee24881867138824 (diff) | |
| download | verismith-fe0f44b2f1609bb8d5097a85daec51e5f9ffdaf0.tar.gz verismith-fe0f44b2f1609bb8d5097a85daec51e5f9ffdaf0.zip | |
Better AST generation from DAG
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Graph/ASTGen.hs | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs index 30dee04..745d849 100644 --- a/src/VeriFuzz/Graph/ASTGen.hs +++ b/src/VeriFuzz/Graph/ASTGen.hs @@ -12,6 +12,7 @@ Generates the AST from the graph directly. module VeriFuzz.Graph.ASTGen where +import Control.Lens ((^..)) import Data.Foldable (fold) import Data.Graph.Inductive (LNode, Node) import qualified Data.Graph.Inductive as G @@ -73,7 +74,9 @@ genModuleDeclAST c = ModDecl i output ports items i = Identifier "gen_module" ports = genPortsAST inputsC c output = [Port Wire 90 "y"] - items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] + a = genAssignAST c + items = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns] + assigns = a ^.. traverse . _ModCA . contAssignNetLVal generateAST :: Circuit -> VerilogSrc generateAST c = VerilogSrc [Description $ genModuleDeclAST c] |