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| author | Yann Herklotz <git@ymhg.org> | 2019-05-12 14:17:48 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-12 14:17:58 +0100 |
| commit | 3c08b4c48abef4811ba73142de4969ef945c5450 (patch) | |
| tree | 697f18c46fcbe5f7271b6e686623d717135417ff /test | |
| parent | 48c2f0470fb51158d0474e1c5931f9e44d4945c2 (diff) | |
| download | verismith-3c08b4c48abef4811ba73142de4969ef945c5450.tar.gz verismith-3c08b4c48abef4811ba73142de4969ef945c5450.zip | |
Add more dependencies to build Yosys on EC2
Diffstat (limited to 'test')
| -rw-r--r-- | test/Reduce.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs index 37a2604..cb90824 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -32,8 +32,8 @@ reduceUnitTests = testGroup "Reducer tests" activeWireTest :: TestTree activeWireTest = testCase "Active wires" $ do - findActiveWires verilog1 \\ ["x", "y", "z", "w"] @?= [] - findActiveWires verilog2 \\ ["x", "y", "z"] @?= [] + findActiveWires verilog1 \\ ["x", "y", "z", "w"] @?= [] + findActiveWires verilog2 \\ ["x", "y", "z"] @?= [] findActiveWires verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= [] where verilog1 = head $ getVerilog [verilog| |