| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'master' into dev/reducerdev/reducer | Yann Herklotz | 2020-05-13 | 2 | -1/+33 |
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| | * | Add distance function (#75) | Yann Herklotz | 2020-05-09 | 2 | -0/+32 |
| * | | Add for loops and events to reduction | Yann Herklotz | 2020-05-12 | 1 | -0/+18 |
| * | | Format with ormolu | Yann Herklotz | 2020-05-12 | 7 | -279/+414 |
| * | | Tests passing for new reduction | Yann Herklotz | 2020-05-11 | 2 | -17/+24 |
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| * | Fix the test suite | Yann Herklotz | 2020-04-07 | 2 | -36/+41 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -1/+1 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 2 | -2/+2 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 2 | -2/+2 |
| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 1 | -8/+31 |
| * | Fix testsuite by adding preprocessor | Yann Herklotz | 2019-11-01 | 1 | -10/+9 |
| * | Test cases pass again | Yann Herklotz | 2019-10-06 | 1 | -12/+0 |
| * | [Fix #63] Make build pass again | Yann Herklotz | 2019-10-06 | 1 | -26/+0 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 5 | -12/+12 |
| * | Change name from VeriFuzz to VeriSmith | Yann Herklotz | 2019-08-29 | 5 | -36/+29 |
| * | Add a benchmark | Yann Herklotz | 2019-07-27 | 1 | -3/+11 |
| * | Add benchmark | Yann Herklotz | 2019-07-27 | 1 | -0/+7 |
| * | Add new maintainer email | Yann Herklotz | 2019-07-23 | 2 | -12/+7 |
| * | Format files | Yann Herklotz | 2019-06-29 | 5 | -20/+35 |
| * | Fix reduction for statements | Yann Herklotz | 2019-05-25 | 1 | -0/+89 |
| * | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 1 | -0/+6 |
| * | Change simple graph check to acyclic check | Yann Herklotz | 2019-05-19 | 1 | -5/+12 |
| * | Add test for removing unused wires | Yann Herklotz | 2019-05-15 | 1 | -0/+54 |
| * | Add test for clean all | Yann Herklotz | 2019-05-14 | 1 | -4/+67 |
| * | Add test for clean function | Yann Herklotz | 2019-05-14 | 1 | -6/+78 |
| * | Format with brittany | Yann Herklotz | 2019-05-13 | 4 | -69/+71 |
| * | Add NonEmpty to tests | Yann Herklotz | 2019-05-13 | 1 | -21/+21 |
| * | Change the arguments to Text in the Parser | Yann Herklotz | 2019-05-13 | 1 | -2/+3 |
| * | Add more dependencies to build Yosys on EC2 | Yann Herklotz | 2019-05-12 | 1 | -2/+2 |
| * | Add working statement reduction | Yann Herklotz | 2019-05-12 | 1 | -0/+85 |
| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 1 | -6/+6 |
| * | Fix warnings for CI | Yann Herklotz | 2019-05-11 | 1 | -2/+1 |
| * | Add reduction unit tests | Yann Herklotz | 2019-05-11 | 1 | -0/+2 |
| * | Add new reduction techniques | Yann Herklotz | 2019-05-11 | 1 | -32/+139 |
| * | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 1 | -9/+45 |
| * | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 2 | -1/+39 |
| * | Add parser and reducer tests | Yann Herklotz | 2019-05-09 | 2 | -0/+106 |
| * | Add new pretty printer with indentation | Yann Herklotz | 2019-05-09 | 2 | -30/+4 |
| * | Support multiple reg assigns in if statements | Yann Herklotz | 2019-05-06 | 1 | -1/+1 |
| * | Fix compiling on CI | Yann Herklotz | 2019-04-19 | 1 | -2/+4 |
| * | Extend property tests to ResultT | Yann Herklotz | 2019-04-17 | 1 | -25/+21 |
| * | Fix tests and remove Parser tests for now | Yann Herklotz | 2019-04-17 | 1 | -3/+54 |
| * | Update property tests | Yann Herklotz | 2019-04-14 | 1 | -18/+17 |
| * | Fix tests passing | Yann Herklotz | 2019-04-13 | 1 | -6/+4 |
| * | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -6/+7 |
| * | Fix hlint hints | Yann Herklotz | 2019-04-02 | 1 | -2/+2 |
| * | Change property tests to use Hedgehog | Yann Herklotz | 2019-04-02 | 1 | -46/+32 |
| * | Run through brittany | Yann Herklotz | 2019-04-01 | 2 | -6/+8 |
| * | Add back fixed doctest | Yann Herklotz | 2019-04-01 | 1 | -1/+12 |
| * | Fix some of the tests | Yann Herklotz | 2019-03-31 | 1 | -2/+3 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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