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| author | Yann Herklotz <git@yannherklotz.com> | 2019-09-18 19:06:32 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-09-18 19:06:32 +0200 |
| commit | 8d96fd2a541a2602544ced741552ebd17714c67d (patch) | |
| tree | 2f53addec05793cf5b3e0274a3e8e9e5f76a7abe /test | |
| parent | d14196cce14d1b4a4a9fba768b9f5238c8626624 (diff) | |
| download | verismith-8d96fd2a541a2602544ced741552ebd17714c67d.tar.gz verismith-8d96fd2a541a2602544ced741552ebd17714c67d.zip | |
Rename main modules
Diffstat (limited to 'test')
| -rw-r--r-- | test/Benchmark.hs | 2 | ||||
| -rw-r--r-- | test/Parser.hs | 8 | ||||
| -rw-r--r-- | test/Property.hs | 8 | ||||
| -rw-r--r-- | test/Reduce.hs | 4 | ||||
| -rw-r--r-- | test/Unit.hs | 2 |
5 files changed, 12 insertions, 12 deletions
diff --git a/test/Benchmark.hs b/test/Benchmark.hs index 7d59e2d..9c81049 100644 --- a/test/Benchmark.hs +++ b/test/Benchmark.hs @@ -2,7 +2,7 @@ module Main where import Control.Lens ((&), (.~)) import Criterion.Main (bench, bgroup, defaultMain, nfAppIO) -import VeriSmith (configProperty, defaultConfig, proceduralIO, +import Verismith (configProperty, defaultConfig, proceduralIO, propSize, propStmntDepth) main :: IO () diff --git a/test/Parser.hs b/test/Parser.hs index b372bbe..959c09b 100644 --- a/test/Parser.hs +++ b/test/Parser.hs @@ -25,10 +25,10 @@ import Test.Tasty import Test.Tasty.Hedgehog import Test.Tasty.HUnit import Text.Parsec -import VeriSmith -import VeriSmith.Internal -import VeriSmith.Verilog.Lex -import VeriSmith.Verilog.Parser +import Verismith +import Verismith.Internal +import Verismith.Verilog.Lex +import Verismith.Verilog.Parser smallConfig :: Config smallConfig = defaultConfig & configProperty . propSize .~ 5 diff --git a/test/Property.hs b/test/Property.hs index afb1d11..bec740c 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -24,10 +24,10 @@ import Parser (parserTests) import Test.Tasty import Test.Tasty.Hedgehog import Text.Parsec -import VeriSmith -import VeriSmith.Result -import VeriSmith.Verilog.Lex -import VeriSmith.Verilog.Parser +import Verismith +import Verismith.Result +import Verismith.Verilog.Lex +import Verismith.Verilog.Parser randomDAG' :: Gen Circuit randomDAG' = Hog.resize 30 randomDAG diff --git a/test/Reduce.hs b/test/Reduce.hs index f3ddf5c..fcc10aa 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -20,8 +20,8 @@ where import Data.List ((\\)) import Test.Tasty import Test.Tasty.HUnit -import VeriSmith -import VeriSmith.Reduce +import Verismith +import Verismith.Reduce reduceUnitTests :: TestTree reduceUnitTests = testGroup diff --git a/test/Unit.hs b/test/Unit.hs index f9283be..f761c68 100644 --- a/test/Unit.hs +++ b/test/Unit.hs @@ -9,7 +9,7 @@ import Parser (parseUnitTests) import Reduce (reduceUnitTests) import Test.Tasty import Test.Tasty.HUnit -import VeriSmith +import Verismith unitTests :: TestTree unitTests = testGroup |