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author | Yann Herklotz <git@yannherklotz.com> | 2020-05-12 21:19:23 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-05-12 21:19:23 +0100 |
commit | edc2b13ecc3c6e8aebf61d3569cd50ddd807fbc2 (patch) | |
tree | 29295320ab5a8a854c379d5b3ade7b7a1120eae7 /test | |
parent | 13c9197202eade844f9e068c22faccf312e4b3dd (diff) | |
download | verismith-edc2b13ecc3c6e8aebf61d3569cd50ddd807fbc2.tar.gz verismith-edc2b13ecc3c6e8aebf61d3569cd50ddd807fbc2.zip |
Add for loops and events to reduction
Diffstat (limited to 'test')
-rw-r--r-- | test/Reduce.hs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs index e6cc8ff..85a0654 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -261,6 +261,7 @@ activeWireTest = testCase "Active wires" $ do findActiveWires "top" verilog2 \\ ["x", "y", "z"] @?= [] findActiveWires "top" verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= [] findActiveWires "top" verilog4 \\ ["x", "y", "w", "a", "b"] @?= [] + findActiveWires "top" verilog5 \\ ["r2", "r1", "x", "y"] @?= [] where verilog1 = sourceInfo @@ -339,6 +340,23 @@ module m2(y, z, x); output z; endmodule |] + verilog5 = + sourceInfo + "top" + [verilog| +module top(y, x); + input x; + output y; + reg r1; + reg r2; + reg r3; + always @* begin + for (r1 = 1; r1 < 2; r1 = r1 + 1) begin + r2 <= 1'b0; + end + end +endmodule +|] halveStatementsTest :: TestTree halveStatementsTest = testCase "Statements" $ do |