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| author | Yann Herklotz <git@yannherklotz.com> | 2019-11-01 13:49:04 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-01 13:49:04 +0000 |
| commit | 7e8dddbdbe74884e4638d6dcf824a0d716d22c40 (patch) | |
| tree | 55c5a7df01093ddace566274f97e9d58cda9fcaf /test | |
| parent | 5c1bda5ecbf284390849849687feb6829261cf22 (diff) | |
| download | verismith-7e8dddbdbe74884e4638d6dcf824a0d716d22c40.tar.gz verismith-7e8dddbdbe74884e4638d6dcf824a0d716d22c40.zip | |
Fix testsuite by adding preprocessor
Diffstat (limited to 'test')
| -rw-r--r-- | test/Parser.hs | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/test/Parser.hs b/test/Parser.hs index 959c09b..2de7114 100644 --- a/test/Parser.hs +++ b/test/Parser.hs @@ -17,10 +17,10 @@ module Parser where import Control.Lens -import Data.Either (either, isRight) -import Hedgehog (Gen, Property, (===)) -import qualified Hedgehog as Hog -import qualified Hedgehog.Gen as Hog +import Data.Either (either, isRight) +import Hedgehog (Gen, Property, (===)) +import qualified Hedgehog as Hog +import qualified Hedgehog.Gen as Hog import Test.Tasty import Test.Tasty.Hedgehog import Test.Tasty.HUnit @@ -29,6 +29,7 @@ import Verismith import Verismith.Internal import Verismith.Verilog.Lex import Verismith.Verilog.Parser +import Verismith.Verilog.Preprocess (uncomment) smallConfig :: Config smallConfig = defaultConfig & configProperty . propSize .~ 5 @@ -38,11 +39,10 @@ randomMod' = Hog.resize 20 (randomMod 3 10) parserInputMod :: Property parserInputMod = Hog.property $ do - v <- Hog.forAll randomMod' + v <- GenVerilog <$> Hog.forAll randomMod' Hog.assert . isRight $ parse parseModDecl "input_test_mod" - (alexScanTokens $ str v) - where str = show . GenVerilog + (alexScanTokens . uncomment "test" $ show v) parserIdempotentMod :: Property parserIdempotentMod = Hog.property $ do @@ -58,11 +58,10 @@ parserIdempotentMod = Hog.property $ do parserInput :: Property parserInput = Hog.property $ do - v <- Hog.forAll (procedural "top" smallConfig) + v <- Hog.forAll (GenVerilog <$> procedural "top" smallConfig) Hog.assert . isRight $ parse parseModDecl "input_test" - (alexScanTokens $ str v) - where str = show . GenVerilog + (alexScanTokens . uncomment "test" $ show v) parserIdempotent :: Property parserIdempotent = Hog.property $ do |