Format with ormolu

7 files changed, 414 insertions, 279 deletions

diff --git a/test/Benchmark.hs b/test/Benchmark.hs
index 9c81049..3454ca2 100644
--- a/test/Benchmark.hs
+++ b/test/Benchmark.hs
@@ -1,15 +1,22 @@
 module Main where
 
-import           Control.Lens   ((&), (.~))
-import           Criterion.Main (bench, bgroup, defaultMain, nfAppIO)
-import           Verismith      (configProperty, defaultConfig, proceduralIO,
-                                 propSize, propStmntDepth)
+import Control.Lens ((&), (.~))
+import Criterion.Main (bench, bgroup, defaultMain, nfAppIO)
+import Verismith
+  ( configProperty,
+    defaultConfig,
+    proceduralIO,
+    propSize,
+    propStmntDepth,
+  )
 
 main :: IO ()
-main = defaultMain
-    [ bgroup "generation"
-        [ bench "default" $ nfAppIO (proceduralIO "top") defaultConfig
-        , bench "depth" . nfAppIO (proceduralIO "top") $ defaultConfig & configProperty . propStmntDepth .~ 10
-        , bench "size" . nfAppIO (proceduralIO "top") $ defaultConfig & configProperty . propSize .~ 40
+main =
+  defaultMain
+    [ bgroup
+        "generation"
+        [ bench "default" $ nfAppIO (proceduralIO "top") defaultConfig,
+          bench "depth" . nfAppIO (proceduralIO "top") $ defaultConfig & configProperty . propStmntDepth .~ 10,
+          bench "size" . nfAppIO (proceduralIO "top") $ defaultConfig & configProperty . propSize .~ 40
         ]
     ]
diff --git a/test/Doctest.hs b/test/Doctest.hs
index 9dc22a4..e18c359 100644
--- a/test/Doctest.hs
+++ b/test/Doctest.hs
@@ -1,10 +1,11 @@
 module Main where
 
-import           Build_doctests                 ( flags
-                                                , module_sources
-                                                , pkgs
-                                                )
-import           Test.DocTest                   ( doctest )
+import Build_doctests
+  ( flags,
+    module_sources,
+    pkgs,
+  )
+import Test.DocTest (doctest)
 
 main :: IO ()
 main = doctest args where args = flags ++ pkgs ++ module_sources
diff --git a/test/Parser.hs b/test/Parser.hs
index 0ce5817..c19f210 100644
--- a/test/Parser.hs
+++ b/test/Parser.hs
@@ -1,35 +1,33 @@
-{-|
-Module      : Parser
-Description : Test the parser.
-Copyright   : (c) 2019, Yann Herklotz Grave
-License     : GPL-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Test the parser.
--}
-
+-- |
+-- Module      : Parser
+-- Description : Test the parser.
+-- Copyright   : (c) 2019, Yann Herklotz Grave
+-- License     : GPL-3
+-- Maintainer  : yann [at] yannherklotz [dot] com
+-- Stability   : experimental
+-- Portability : POSIX
+--
+-- Test the parser.
 module Parser
-    ( parserTests
-    , parseUnitTests
-    )
+  ( parserTests,
+    parseUnitTests,
+  )
 where
 
-import           Control.Lens
-import           Data.Either                  (either, isRight)
-import           Hedgehog                     (Gen, Property, (===))
-import qualified Hedgehog                     as Hog
-import qualified Hedgehog.Gen                 as Hog
-import           Test.Tasty
-import           Test.Tasty.Hedgehog
-import           Test.Tasty.HUnit
-import           Text.Parsec
-import           Verismith
-import           Verismith.Internal
-import           Verismith.Verilog.Lex
-import           Verismith.Verilog.Parser
-import           Verismith.Verilog.Preprocess (uncomment)
+import Control.Lens
+import Data.Either (either, isRight)
+import Hedgehog ((===), Gen, Property)
+import qualified Hedgehog as Hog
+import qualified Hedgehog.Gen as Hog
+import Test.Tasty
+import Test.Tasty.HUnit
+import Test.Tasty.Hedgehog
+import Text.Parsec
+import Verismith
+import Verismith.Internal
+import Verismith.Verilog.Lex
+import Verismith.Verilog.Parser
+import Verismith.Verilog.Preprocess (uncomment)
 
 smallConfig :: Config
 smallConfig = defaultConfig & configProperty . propSize .~ 5
@@ -39,93 +37,101 @@ randomMod' = Hog.resize 20 (randomMod 3 10)
 
 parserInputMod :: Property
 parserInputMod = Hog.property $ do
-    v <- GenVerilog <$> Hog.forAll randomMod' :: Hog.PropertyT IO (GenVerilog (ModDecl ()))
-    Hog.assert . isRight $ parse parseModDecl
-                                 "input_test_mod"
-                                 (alexScanTokens . uncomment "test" $ show v)
+  v <- GenVerilog <$> Hog.forAll randomMod' :: Hog.PropertyT IO (GenVerilog (ModDecl ()))
+  Hog.assert . isRight $
+    parse
+      parseModDecl
+      "input_test_mod"
+      (alexScanTokens . uncomment "test" $ show v)
 
 parserIdempotentMod :: Property
 parserIdempotentMod = Hog.property $ do
-    v <- Hog.forAll randomMod' :: Hog.PropertyT IO (ModDecl ())
-    let sv = vshow v
-    p sv === (p . p) sv
+  v <- Hog.forAll randomMod' :: Hog.PropertyT IO (ModDecl ())
+  let sv = vshow v
+  p sv === (p . p) sv
   where
     vshow = show . GenVerilog
     p sv =
-        either (\x -> show x <> "\n" <> sv) vshow
-            . parse parseModDecl "idempotent_test_mod"
-            $ alexScanTokens sv
+      either (\x -> show x <> "\n" <> sv) vshow
+        . parse parseModDecl "idempotent_test_mod"
+        $ alexScanTokens sv
 
 parserInput :: Property
 parserInput = Hog.property $ do
-    v <- Hog.forAll (GenVerilog <$> (procedural "top" smallConfig :: Gen (Verilog ())))
-    Hog.assert . isRight $ parse parseModDecl
-                                 "input_test"
-                                 (alexScanTokens . uncomment "test" $ show v)
+  v <- Hog.forAll (GenVerilog <$> (procedural "top" smallConfig :: Gen (Verilog ())))
+  Hog.assert . isRight $
+    parse
+      parseModDecl
+      "input_test"
+      (alexScanTokens . uncomment "test" $ show v)
 
 parserIdempotent :: Property
 parserIdempotent = Hog.property $ do
-    v <- Hog.forAll (procedural "top" smallConfig) :: Hog.PropertyT IO (Verilog ())
-    let sv = vshow v
-    p sv === (p . p) sv
+  v <- Hog.forAll (procedural "top" smallConfig) :: Hog.PropertyT IO (Verilog ())
+  let sv = vshow v
+  p sv === (p . p) sv
   where
     vshow = showT . GenVerilog
-    p sv = either (\x -> showT x <> "\n" <> sv) vshow
-        $ parseVerilog "idempotent_test" sv
+    p sv =
+      either (\x -> showT x <> "\n" <> sv) vshow $
+        parseVerilog "idempotent_test" sv
 
 parserTests :: TestTree
-parserTests = testGroup
+parserTests =
+  testGroup
     "Parser properties"
-    [ testProperty "Input Mod"       parserInputMod
-    , testProperty "Input"           parserInput
-    , testProperty "Idempotence Mod" parserIdempotentMod
-    , testProperty "Idempotence"     parserIdempotent
+    [ testProperty "Input Mod" parserInputMod,
+      testProperty "Input" parserInput,
+      testProperty "Idempotence Mod" parserIdempotentMod,
+      testProperty "Idempotence" parserIdempotent
     ]
 
 testParse :: (Eq a, Show a) => Parser a -> String -> String -> a -> TestTree
 testParse p name input golden =
-    testCase name $ case parse p "testcase" (alexScanTokens input) of
-        Left  e      -> assertFailure $ show e
-        Right result -> golden @=? result
+  testCase name $ case parse p "testcase" (alexScanTokens input) of
+    Left e -> assertFailure $ show e
+    Right result -> golden @=? result
 
 testParseFail :: (Eq a, Show a) => Parser a -> String -> String -> TestTree
 testParseFail p name input =
-    testCase name $ case parse p "testcase" (alexScanTokens input) of
-        Left  _ -> return ()
-        Right _ -> assertFailure "Parse incorrectly succeeded"
+  testCase name $ case parse p "testcase" (alexScanTokens input) of
+    Left _ -> return ()
+    Right _ -> assertFailure "Parse incorrectly succeeded"
 
 parseEventUnit :: TestTree
-parseEventUnit = testGroup
+parseEventUnit =
+  testGroup
     "Event"
-    [ testFailure "No empty event" "@()"
-    , test "@*"   EAll
-    , test "@(*)" EAll
-    , test "@(posedge clk)" $ EPosEdge "clk"
-    , test "@(negedge clk)" $ ENegEdge "clk"
-    , test "@(wire1)" $ EId "wire1"
-    , test "@(a or b or c or d)"
-        $ EOr (EId "a") (EOr (EId "b") (EOr (EId "c") (EId "d")))
-    , test "@(a, b, c, d)"
-        $ EComb (EId "a") (EComb (EId "b") (EComb (EId "c") (EId "d")))
-    , test "@(posedge a or negedge b or c or d)"
-        $ EOr (EPosEdge "a") (EOr (ENegEdge "b") (EOr (EId "c") (EId "d")))
+    [ testFailure "No empty event" "@()",
+      test "@*" EAll,
+      test "@(*)" EAll,
+      test "@(posedge clk)" $ EPosEdge "clk",
+      test "@(negedge clk)" $ ENegEdge "clk",
+      test "@(wire1)" $ EId "wire1",
+      test "@(a or b or c or d)" $
+        EOr (EId "a") (EOr (EId "b") (EOr (EId "c") (EId "d"))),
+      test "@(a, b, c, d)" $
+        EComb (EId "a") (EComb (EId "b") (EComb (EId "c") (EId "d"))),
+      test "@(posedge a or negedge b or c or d)" $
+        EOr (EPosEdge "a") (EOr (ENegEdge "b") (EOr (EId "c") (EId "d")))
     ]
   where
     test a = testParse parseEvent ("Test " <> a) a
     testFailure = testParseFail parseEvent
 
 parseAlwaysUnit :: TestTree
-parseAlwaysUnit = testGroup
+parseAlwaysUnit =
+  testGroup
     "Always"
-    [ test "Empty" "always begin end" $ Always (SeqBlock [])
-    , test "Empty with event @*"             "always @* begin end"
-        $ Always (EventCtrl EAll (Just (SeqBlock [])))
-    , test "Empty with event @(posedge clk)" "always @(posedge clk) begin end"
-        $ Always (EventCtrl (EPosEdge "clk") (Just (SeqBlock [])))
+    [ test "Empty" "always begin end" $ Always (SeqBlock []),
+      test "Empty with event @*" "always @* begin end" $
+        Always (EventCtrl EAll (Just (SeqBlock []))),
+      test "Empty with event @(posedge clk)" "always @(posedge clk) begin end" $
+        Always (EventCtrl (EPosEdge "clk") (Just (SeqBlock [])))
     ]
-    where
-      test :: String -> String -> ModItem () -> TestTree
-      test = testParse parseModItem
+  where
+    test :: String -> String -> ModItem () -> TestTree
+    test = testParse parseModItem
 
 parseUnitTests :: TestTree
 parseUnitTests = testGroup "Parser unit" [parseEventUnit, parseAlwaysUnit]
diff --git a/test/Property.hs b/test/Property.hs
index 7e1911e..ddbef0d 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -1,51 +1,51 @@
-{-# LANGUAGE ConstraintKinds     #-}
-{-# LANGUAGE RankNTypes          #-}
+{-# LANGUAGE ConstraintKinds #-}
+{-# LANGUAGE RankNTypes #-}
 {-# LANGUAGE ScopedTypeVariables #-}
-{-# LANGUAGE TypeApplications    #-}
-
-{-# OPTIONS_GHC -Wno-unused-top-binds #-}
+{-# LANGUAGE TypeApplications #-}
 {-# OPTIONS_GHC -Wno-unused-imports #-}
+{-# OPTIONS_GHC -Wno-unused-top-binds #-}
 
 module Property
-    ( propertyTests
-    )
+  ( propertyTests,
+  )
 where
 
-import           Data.Either              (either, isRight)
-import qualified Data.Graph.Inductive     as G
-import           Data.Text                (Text)
-import           Hedgehog                 (Gen, Property, (===))
-import qualified Hedgehog                 as Hog
-import qualified Hedgehog.Gen             as Hog
-import qualified Hedgehog.Range           as Hog
-import           Parser                   (parserTests)
-import           Test.Tasty
-import           Test.Tasty.Hedgehog
-import           Text.Parsec
-import           Verismith
-import           Verismith.Result
-import           Verismith.Verilog.Lex
-import           Verismith.Verilog.Parser
+import Data.Either (either, isRight)
+import qualified Data.Graph.Inductive as G
+import Data.Text (Text)
+import Hedgehog ((===), Gen, Property)
+import qualified Hedgehog as Hog
+import qualified Hedgehog.Gen as Hog
+import qualified Hedgehog.Range as Hog
+import Parser (parserTests)
+import Test.Tasty
+import Test.Tasty.Hedgehog
+import Text.Parsec
+import Verismith
+import Verismith.Result
+import Verismith.Verilog.Lex
+import Verismith.Verilog.Parser
 
 randomDAG' :: Gen Circuit
 randomDAG' = Hog.resize 30 randomDAG
 
 acyclicGraph :: Property
 acyclicGraph = Hog.property $ do
-    xs <- Hog.forAllWith (const "") randomDAG'
-    Hog.assert $ simp xs
+  xs <- Hog.forAllWith (const "") randomDAG'
+  Hog.assert $ simp xs
   where
     simp g =
-        (== G.noNodes (getCircuit g))
-            . sum
-            . fmap length
-            . G.scc
-            . getCircuit
-            $ g
+      (== G.noNodes (getCircuit g))
+        . sum
+        . fmap length
+        . G.scc
+        . getCircuit
+        $ g
 
 propertyTests :: TestTree
-propertyTests = testGroup
+propertyTests =
+  testGroup
     "Property Tests"
-    [ testProperty "acyclic graph generation check" acyclicGraph
-    , parserTests
+    [ testProperty "acyclic graph generation check" acyclicGraph,
+      parserTests
     ]
diff --git a/test/Reduce.hs b/test/Reduce.hs
index 47554bf..e6cc8ff 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -1,50 +1,52 @@
-{-|
-Module      : Reduce
-Description : Test reduction.
-Copyright   : (c) 2019, Yann Herklotz Grave
-License     : GPL-3
-Maintainer  : yann [at] yannherklotz [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Test reduction.
--}
-
 {-# LANGUAGE QuasiQuotes #-}
 
+-- |
+-- Module      : Reduce
+-- Description : Test reduction.
+-- Copyright   : (c) 2019, Yann Herklotz Grave
+-- License     : GPL-3
+-- Maintainer  : yann [at] yannherklotz [dot] com
+-- Stability   : experimental
+-- Portability : POSIX
+--
+-- Test reduction.
 module Reduce
-    ( reduceUnitTests
-    )
+  ( reduceUnitTests,
+  )
 where
 
-import           Data.List        ((\\))
-import           Test.Tasty
-import           Test.Tasty.HUnit
-import           Verismith
-import           Verismith.Reduce
+import Data.List ((\\))
 import Data.Text (Text)
+import Test.Tasty
+import Test.Tasty.HUnit
+import Verismith
+import Verismith.Reduce
 
 sourceInfo :: Text -> Verilog ReduceAnn -> SourceInfo ReduceAnn
 sourceInfo = SourceInfo
 
 reduceUnitTests :: TestTree
-reduceUnitTests = testGroup
+reduceUnitTests =
+  testGroup
     "Reducer tests"
-    [ moduleReducerTest
-    , modItemReduceTest
-    , halveStatementsTest
-    , statementReducerTest
-    , activeWireTest
-    , cleanTest
-    , cleanAllTest
-    , removeDeclTest
+    [ moduleReducerTest,
+      modItemReduceTest,
+      halveStatementsTest,
+      statementReducerTest,
+      activeWireTest,
+      cleanTest,
+      cleanAllTest,
+      removeDeclTest
     ]
 
 removeConstInConcatTest :: TestTree
 removeConstInConcatTest = testCase "Remove const in concat" $ do
-    GenVerilog (removeDecl srcInfo1) @?= golden1
+  GenVerilog (removeDecl srcInfo1) @?= golden1
   where
-    srcInfo1 = sourceInfo "top" [verilog|
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top;
   wire a;
   reg b;
@@ -57,7 +59,11 @@ module top;
   end
 endmodule
 |]
-    golden1 = GenVerilog $ sourceInfo "top" [verilog|
+    golden1 =
+      GenVerilog $
+        sourceInfo
+          "top"
+          [verilog|
 module top;
   wire a;
   reg b;
@@ -73,9 +79,12 @@ endmodule
 
 removeDeclTest :: TestTree
 removeDeclTest = testCase "Remove declarations" $ do
-    GenVerilog (removeDecl srcInfo1) @?= golden1
-    where
-        srcInfo1 = sourceInfo "top" [verilog|
+  GenVerilog (removeDecl srcInfo1) @?= golden1
+  where
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top;
   wire a;
   wire b;
@@ -103,7 +112,11 @@ module top;
   assign b = g;
 endmodule
 |]
-        golden1 = GenVerilog $ sourceInfo "top" [verilog|
+    golden1 =
+      GenVerilog $
+        sourceInfo
+          "top"
+          [verilog|
 module top;
   wire a;
   wire b;
@@ -130,9 +143,12 @@ endmodule
 |]
 
 cleanAllTest = testCase "Clean all" $ do
-    GenVerilog (cleanSourceInfoAll srcInfo1) @?= golden1
-    where
-        srcInfo1 = sourceInfo "top" [verilog|
+  GenVerilog (cleanSourceInfoAll srcInfo1) @?= golden1
+  where
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top;
   wire a;
   wire b;
@@ -160,7 +176,11 @@ module mod2;
   assign b = c + d;
 endmodule
 |]
-        golden1 = GenVerilog $ sourceInfo "top" [verilog|
+    golden1 =
+      GenVerilog $
+        sourceInfo
+          "top"
+          [verilog|
 module top;
   wire a;
   wire b;
@@ -191,10 +211,12 @@ endmodule
 
 cleanTest :: TestTree
 cleanTest = testCase "Clean expression" $ do
-    clean ["wire1", "wire2"] srcInfo1 @?= golden1
-    clean ["wire1", "wire3"] srcInfo2 @?= golden2
-    where
-        srcInfo1 = GenVerilog . sourceInfo "top" $ [verilog|
+  clean ["wire1", "wire2"] srcInfo1 @?= golden1
+  clean ["wire1", "wire3"] srcInfo2 @?= golden2
+  where
+    srcInfo1 =
+      GenVerilog . sourceInfo "top" $
+        [verilog|
 module top;
   wire wire1;
   wire wire2;
@@ -202,7 +224,9 @@ module top;
   assign wire1 = wire2[wire3];
 endmodule
 |]
-        golden1 = GenVerilog . sourceInfo "top" $ [verilog|
+    golden1 =
+      GenVerilog . sourceInfo "top" $
+        [verilog|
 module top;
   wire wire1;
   wire wire2;
@@ -210,7 +234,9 @@ module top;
   assign wire1 = wire2[1'b0];
 endmodule
 |]
-        srcInfo2 = GenVerilog . sourceInfo "top" $ [verilog|
+    srcInfo2 =
+      GenVerilog . sourceInfo "top" $
+        [verilog|
 module top;
   wire wire1;
   wire wire2;
@@ -218,7 +244,9 @@ module top;
   assign wire1 = wire2[wire3:wire1];
 endmodule
 |]
-        golden2 = GenVerilog . sourceInfo "top" $ [verilog|
+    golden2 =
+      GenVerilog . sourceInfo "top" $
+        [verilog|
 module top;
   wire wire1;
   wire wire2;
@@ -227,15 +255,17 @@ module top;
 endmodule
 |]
 
-
 activeWireTest :: TestTree
 activeWireTest = testCase "Active wires" $ do
-    findActiveWires "top" verilog1 \\ ["x", "y", "z", "w"]          @?= []
-    findActiveWires "top" verilog2 \\ ["x", "y", "z"]               @?= []
-    findActiveWires "top" verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= []
-    findActiveWires "top" verilog4 \\ ["x", "y", "w", "a", "b"]     @?= []
-    where
-        verilog1 = sourceInfo "top" [verilog|
+  findActiveWires "top" verilog1 \\ ["x", "y", "z", "w"] @?= []
+  findActiveWires "top" verilog2 \\ ["x", "y", "z"] @?= []
+  findActiveWires "top" verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= []
+  findActiveWires "top" verilog4 \\ ["x", "y", "w", "a", "b"] @?= []
+  where
+    verilog1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   input x;
   output y;
@@ -246,7 +276,10 @@ module top(y, x);
   assign y = w + z;
 endmodule
 |]
-        verilog2 = sourceInfo "top" [verilog|
+    verilog2 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   input x;
   output y;
@@ -255,7 +288,10 @@ module top(y, x);
   assign z = 0;
 endmodule
 |]
-        verilog3 = sourceInfo "top" [verilog|
+    verilog3 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(clk, y, x);
   input clk;
   input x;
@@ -276,7 +312,10 @@ module top(clk, y, x);
   assign y = {r1, r2, r3};
 endmodule
 |]
-        verilog4 = sourceInfo "top" [verilog|
+    verilog4 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   input x;
   output y;
@@ -303,9 +342,12 @@ endmodule
 
 halveStatementsTest :: TestTree
 halveStatementsTest = testCase "Statements" $ do
-    GenVerilog <$> halveStatements "top" (tagAlways "top" srcInfo1) @?= golden1
-    where
-        srcInfo1 = sourceInfo "top" [verilog|
+  GenVerilog <$> halveStatements "top" (tagAlways "top" srcInfo1) @?= golden1
+  where
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(clk, y, x);
   input clk;
   input x;
@@ -327,7 +369,13 @@ module top(clk, y, x);
   assign y = {r1, r2, r3};
 endmodule
 |]
-        golden1 = GenVerilog <$> Dual (tagAlways "top" $ sourceInfo "top" [verilog|
+    golden1 =
+      GenVerilog
+        <$> Dual
+          ( tagAlways "top" $
+              sourceInfo
+                "top"
+                [verilog|
 module top(clk, y, x);
   input clk;
   input x;
@@ -346,7 +394,12 @@ module top(clk, y, x);
   end
   assign y = {r1, r2, r3};
 endmodule
-|]) (tagAlways "top" $ sourceInfo "top" [verilog|
+|]
+          )
+          ( tagAlways "top" $
+              sourceInfo
+                "top"
+                [verilog|
 module top(clk, y, x);
   input clk;
   input x;
@@ -366,13 +419,17 @@ module top(clk, y, x);
   end
   assign y = {r1, r2, r3};
 endmodule
-|])
+|]
+          )
 
 modItemReduceTest :: TestTree
 modItemReduceTest = testCase "Module items" $ do
-    GenVerilog <$> halveModItems "top" srcInfo1 @?= golden1
-    where
-        srcInfo1 = sourceInfo "top" [verilog|
+  GenVerilog <$> halveModItems "top" srcInfo1 @?= golden1
+  where
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   input x;
   output y;
@@ -383,7 +440,12 @@ module top(y, x);
   assign y = w;
 endmodule
 |]
-        golden1 = GenVerilog <$> Dual (sourceInfo "top" [verilog|
+    golden1 =
+      GenVerilog
+        <$> Dual
+          ( sourceInfo
+              "top"
+              [verilog|
 module top(y, x);
   input x;
   output y;
@@ -392,7 +454,11 @@ module top(y, x);
   assign y = 1'b0;
   assign z = x;
 endmodule
-|]) (sourceInfo "top" [verilog|
+|]
+          )
+          ( sourceInfo
+              "top"
+              [verilog|
 module top(y, x);
   input x;
   output y;
@@ -401,14 +467,19 @@ module top(y, x);
   assign y = w;
   assign w = 1'b0;
 endmodule
-|])
+|]
+          )
 
 statementReducerTest :: TestTree
 statementReducerTest = testCase "Statement reducer" $ do
-    GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1
-    GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2
-    where
-        srcInfo1 = tagAlways "top" $ sourceInfo "top" [verilog|
+  GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1
+  GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2
+  where
+    srcInfo1 =
+      tagAlways "top" $
+        sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -428,7 +499,12 @@ module top(y, x);
   end
 endmodule
 |]
-        golden1 = Dual (tagAlways "top" $ sourceInfo "top" [verilog|
+    golden1 =
+      Dual
+        ( tagAlways "top" $
+            sourceInfo
+              "top"
+              [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -445,7 +521,12 @@ module top(y, x);
     d <= 4;
   end
 endmodule
-|]) . tagAlways "top" $ sourceInfo "top" [verilog|
+|]
+        )
+        . tagAlways "top"
+        $ sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -463,7 +544,11 @@ module top(y, x);
   end
 endmodule
 |]
-        srcInfo2 = tagAlways "top" $ sourceInfo "top" [verilog|
+    srcInfo2 =
+      tagAlways "top" $
+        sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -476,7 +561,12 @@ module top(y, x);
   end
 endmodule
 |]
-        golden2 = Dual (tagAlways "top" $ sourceInfo "top" [verilog|
+    golden2 =
+      Dual
+        ( tagAlways "top" $
+            sourceInfo
+              "top"
+              [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -484,7 +574,12 @@ module top(y, x);
   always @(posedge clk)
       y <= 2;
 endmodule
-|]) . tagAlways "top" $ sourceInfo "top" [verilog|
+|]
+        )
+        . tagAlways "top"
+        $ sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -496,10 +591,13 @@ endmodule
 
 moduleReducerTest :: TestTree
 moduleReducerTest = testCase "Module reducer" $ do
-    halveModules srcInfo1 @?= golden1
-    halveModules srcInfo2 @?= golden2
-    where
-        srcInfo1 = sourceInfo "top" [verilog|
+  halveModules srcInfo1 @?= golden1
+  halveModules srcInfo2 @?= golden2
+  where
+    srcInfo1 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -511,13 +609,20 @@ module m(y, x);
   input wire [4:0] x;
 endmodule
 |]
-        golden1 = Single $ sourceInfo "top" [verilog|
+    golden1 =
+      Single $
+        sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
 endmodule
 |]
-        srcInfo2 = sourceInfo "top" [verilog|
+    srcInfo2 =
+      sourceInfo
+        "top"
+        [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -535,7 +640,11 @@ module m2(y, x);
   input wire [4:0] x;
 endmodule
 |]
-        golden2 = Dual (sourceInfo "top" [verilog|
+    golden2 =
+      Dual
+        ( sourceInfo
+            "top"
+            [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
@@ -546,7 +655,11 @@ module m(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
 endmodule
-|]) $ sourceInfo "top" [verilog|
+|]
+        )
+        $ sourceInfo
+          "top"
+          [verilog|
 module top(y, x);
   output wire [4:0] y;
   input wire [4:0] x;
diff --git a/test/Test.hs b/test/Test.hs
index f2609ba..22cdb29 100644
--- a/test/Test.hs
+++ b/test/Test.hs
@@ -1,8 +1,8 @@
 module Main where
 
-import           Property
-import           Test.Tasty
-import           Unit
+import Property
+import Test.Tasty
+import Unit
 
 tests :: TestTree
 tests = testGroup "Tests" [unitTests, propertyTests]
diff --git a/test/Unit.hs b/test/Unit.hs
index f761c68..9cc75fb 100644
--- a/test/Unit.hs
+++ b/test/Unit.hs
@@ -1,101 +1,109 @@
 module Unit
-    ( unitTests
-    )
+  ( unitTests,
+  )
 where
 
-import           Control.Lens
-import           Data.List.NonEmpty (NonEmpty (..))
-import           Parser             (parseUnitTests)
-import           Reduce             (reduceUnitTests)
-import           Test.Tasty
-import           Test.Tasty.HUnit
-import           Verismith
+import Control.Lens
+import Data.List.NonEmpty (NonEmpty (..))
+import Parser (parseUnitTests)
+import Reduce (reduceUnitTests)
+import Test.Tasty
+import Test.Tasty.HUnit
+import Verismith
 
 unitTests :: TestTree
-unitTests = testGroup
+unitTests =
+  testGroup
     "Unit tests"
-    [ testCase "Transformation of AST" $ assertEqual
-        "Successful transformation"
-        transformExpectedResult
-        (transform trans transformTestData)
-    , parseUnitTests
-    , reduceUnitTests
+    [ testCase "Transformation of AST" $
+        assertEqual
+          "Successful transformation"
+          transformExpectedResult
+          (transform trans transformTestData),
+      parseUnitTests,
+      reduceUnitTests
     ]
 
 transformTestData :: Expr
-transformTestData = BinOp
-    (BinOp (BinOp (Id "id1") BinAnd (Id "id2"))
-           BinAnd
-           (BinOp (Id "id1") BinAnd (Id "id2"))
+transformTestData =
+  BinOp
+    ( BinOp
+        (BinOp (Id "id1") BinAnd (Id "id2"))
+        BinAnd
+        (BinOp (Id "id1") BinAnd (Id "id2"))
     )
     BinAnd
-    (BinOp
-        (BinOp
+    ( BinOp
+        ( BinOp
             (BinOp (Id "id1") BinAnd (Id "id2"))
             BinAnd
-            (BinOp
+            ( BinOp
                 (Id "id1")
                 BinAnd
-                (BinOp (BinOp (Id "id1") BinAnd (Id "id2"))
-                       BinAnd
-                       (BinOp (Id "id1") BinAnd (Id "id2"))
+                ( BinOp
+                    (BinOp (Id "id1") BinAnd (Id "id2"))
+                    BinAnd
+                    (BinOp (Id "id1") BinAnd (Id "id2"))
                 )
             )
         )
         BinOr
-        (  Concat
-        $  (  Concat
-           $  (Concat $ (Id "id1") :| [Id "id2", Id "id2"])
-           :| [ Id "id2"
-              , Id "id2"
-              , (  Concat
-                $  (Id "id2")
-                :| [Id "id2", (Concat $ Id "id1" :| [Id "id2"])]
-                )
-              , Id "id2"
-              ]
-           )
-        :| [Id "id1", Id "id2"]
+        ( Concat $
+            ( Concat $
+                (Concat $ (Id "id1") :| [Id "id2", Id "id2"])
+                  :| [ Id "id2",
+                       Id "id2",
+                       ( Concat $
+                           (Id "id2")
+                             :| [Id "id2", (Concat $ Id "id1" :| [Id "id2"])]
+                       ),
+                       Id "id2"
+                     ]
+            )
+              :| [Id "id1", Id "id2"]
         )
     )
 
 transformExpectedResult :: Expr
-transformExpectedResult = BinOp
-    (BinOp (BinOp (Id "id1") BinAnd (Id "Replaced"))
-           BinAnd
-           (BinOp (Id "id1") BinAnd (Id "Replaced"))
+transformExpectedResult =
+  BinOp
+    ( BinOp
+        (BinOp (Id "id1") BinAnd (Id "Replaced"))
+        BinAnd
+        (BinOp (Id "id1") BinAnd (Id "Replaced"))
     )
     BinAnd
-    (BinOp
-        (BinOp
+    ( BinOp
+        ( BinOp
             (BinOp (Id "id1") BinAnd (Id "Replaced"))
             BinAnd
-            (BinOp
+            ( BinOp
                 (Id "id1")
                 BinAnd
-                (BinOp (BinOp (Id "id1") BinAnd (Id "Replaced"))
-                       BinAnd
-                       (BinOp (Id "id1") BinAnd (Id "Replaced"))
+                ( BinOp
+                    (BinOp (Id "id1") BinAnd (Id "Replaced"))
+                    BinAnd
+                    (BinOp (Id "id1") BinAnd (Id "Replaced"))
                 )
             )
         )
         BinOr
-        (  Concat
-        $  (  Concat
-           $  (Concat $ (Id "id1") :| [Id "Replaced", Id "Replaced"])
-           :| [ Id "Replaced"
-              , Id "Replaced"
-              , Concat
-              $  Id "Replaced"
-              :| [Id "Replaced", Concat $ Id "id1" :| [Id "Replaced"]]
-              , Id "Replaced"
-              ]
-           )
-        :| [Id "id1", Id "Replaced"]
+        ( Concat $
+            ( Concat $
+                (Concat $ (Id "id1") :| [Id "Replaced", Id "Replaced"])
+                  :| [ Id "Replaced",
+                       Id "Replaced",
+                       Concat $
+                         Id "Replaced"
+                           :| [Id "Replaced", Concat $ Id "id1" :| [Id "Replaced"]],
+                       Id "Replaced"
+                     ]
+            )
+              :| [Id "id1", Id "Replaced"]
         )
     )
 
 trans :: Expr -> Expr
 trans e = case e of
-    Id i -> if i == Identifier "id2" then Id $ Identifier "Replaced" else Id i
-    _    -> e
+  Id i -> if i == Identifier "id2" then Id $ Identifier "Replaced" else Id i
+  _ -> e