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| author | Yann Herklotz <git@yannherklotz.com> | 2019-05-19 18:17:10 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-19 18:17:10 +0100 |
| commit | 9a051648695d459d4564be58ae4850e159cb3ba3 (patch) | |
| tree | c01c41277f731d06294a49e53b511022e3da5017 /test | |
| parent | 0c791013340788eb4c18af361a57e4e2504a64f7 (diff) | |
| download | verismith-9a051648695d459d4564be58ae4850e159cb3ba3.tar.gz verismith-9a051648695d459d4564be58ae4850e159cb3ba3.zip | |
Change simple graph check to acyclic check
Diffstat (limited to 'test')
| -rw-r--r-- | test/Property.hs | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/test/Property.hs b/test/Property.hs index 7b1771c..001c7d3 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -32,11 +32,18 @@ import VeriFuzz.Verilog.Parser randomDAG' :: Gen Circuit randomDAG' = Hog.resize 30 randomDAG -simpleGraph :: Property -simpleGraph = Hog.property $ do +acyclicGraph :: Property +acyclicGraph = Hog.property $ do xs <- Hog.forAllWith (const "") randomDAG' Hog.assert $ simp xs - where simp = G.isSimple . getCircuit + where + simp g = + (== G.noNodes (getCircuit g)) + . sum + . fmap length + . G.scc + . getCircuit + $ g type GenFunctor f a b c = ( Functor f @@ -76,7 +83,7 @@ propertyResultInterrupted = do propertyTests :: TestTree propertyTests = testGroup "Property Tests" - [ testProperty "simple graph generation check" simpleGraph - , testProperty "fmap for Result" propertyResultInterrupted + [ testProperty "acyclic graph generation check" acyclicGraph + , testProperty "fmap for Result" propertyResultInterrupted , parserTests ] |