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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 22:30:11 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-29 22:30:11 +0100 |
| commit | 4ce63111a9cc7b82d713e1f61f30dcc1a39a71ad (patch) | |
| tree | dd2d6eef0e4059c21a6a26e73032b5a22da8339d /tests/Unit.hs | |
| parent | eb0eb0f85e7e656c43cf9cb27bc142ae5a349efc (diff) | |
| download | verismith-4ce63111a9cc7b82d713e1f61f30dcc1a39a71ad.tar.gz verismith-4ce63111a9cc7b82d713e1f61f30dcc1a39a71ad.zip | |
Add tests for new generation method
Diffstat (limited to 'tests/Unit.hs')
| -rw-r--r-- | tests/Unit.hs | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/Unit.hs b/tests/Unit.hs index 67f642c..de4fa16 100644 --- a/tests/Unit.hs +++ b/tests/Unit.hs @@ -38,12 +38,3 @@ trans e = PrimExpr . PrimId $ Identifier "Replaced" else PrimExpr (PrimId id) _ -> e - -runMain = do - gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) --- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", --- T.putStrLn $ generate gr - --g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc) - let x = generateAST $ Circuit gr - let y = head . reverse $ x ^.. getVerilogSrc . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr - print $ transformOf traverseExpr trans y |