4 files changed, 12 insertions, 9 deletions

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index b3754ec..f940281 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -91,7 +91,7 @@ module VeriFuzz.Verilog.AST
   , stmntSysTask
     -- * Module
   , ModDecl(..)
-  , moduleId
+  , modId
   , modOutPorts
   , modInPorts
   , modItems
@@ -495,7 +495,7 @@ instance QC.Arbitrary ModItem where
                        ]
 
 -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
-data ModDecl = ModDecl { _moduleId    :: Identifier
+data ModDecl = ModDecl { _modId       :: Identifier
                        , _modOutPorts :: [Port]
                        , _modInPorts  :: [Port]
                        , _modItems    :: [ModItem]
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 956472f..58b1d16 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -53,7 +53,7 @@ genDescription desc = genModuleDecl $ desc ^. getDescription
 -- | Generate the 'ModDecl' for a module and convert it to 'Text'.
 genModuleDecl :: ModDecl -> Text
 genModuleDecl m =
-  "module " <> m ^. moduleId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n"
+  "module " <> m ^. modId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n"
  where
   ports | noIn && noOut = ""
         | otherwise     = "(" <> comma (genModPort <$> outIn) <> ")"
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs
index 4771329..99e5f38 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Verilog/Helpers.hs
@@ -28,7 +28,7 @@ emptyMod = ModDecl "" [] [] []
 
 -- | Set a module name for a module declaration.
 setModName :: Text -> ModDecl -> ModDecl
-setModName str = moduleId .~ Identifier str
+setModName str = modId .~ Identifier str
 
 -- | Add a input port to the module declaration.
 addModPort :: Port -> ModDecl -> ModDecl
@@ -67,3 +67,6 @@ defaultPort = Port Wire 1
 
 portToExpr :: Port -> Expr
 portToExpr (Port _ _ i) = Id i
+
+modName :: ModDecl -> Text
+modName = view $ modId . getIdentifier
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 82d3db9..dca0dd9 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -92,8 +92,8 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
  where
   out   = Decl Nothing <$> m ^. modOutPorts
   regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg False)
-  inst  = ModInst (m ^. moduleId) (m ^. moduleId <> (Identifier . showT $ count + 1)) conns
-  count = length . filter (== m ^. moduleId) $ main ^.. modItems . traverse . modInstId
+  inst  = ModInst (m ^. modId) (m ^. modId <> (Identifier . showT $ count + 1)) conns
+  count = length . filter (== m ^. modId) $ main ^.. modItems . traverse . modInstId
   conns = ModConn . Id <$> allVars m
 
 -- | Instantiate without adding wire declarations. It also does not count the
@@ -103,7 +103,7 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
 -- m m(y, x);
 -- <BLANKLINE>
 instantiateMod_ :: ModDecl -> ModItem
-instantiateMod_ m = ModInst (m ^. moduleId) (m ^. moduleId) conns
+instantiateMod_ m = ModInst (m ^. modId) (m ^. modId) conns
  where
   conns =
     ModConn
@@ -131,8 +131,8 @@ makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a
 -- | Make top level module for equivalence verification. Also takes in how many
 -- modules to instantiate.
 makeTop :: Int -> ModDecl -> ModDecl
-makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt
+makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt
  where
   ys    = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i]
   modIt = instantiateMod_ . modN <$> [1 .. i]
-  modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]
+  modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]