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-rw-r--r--src/Verismith/Verilog/CodeGen.hs3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/Verismith/Verilog/CodeGen.hs b/src/Verismith/Verilog/CodeGen.hs
index 3c5d4c5..9c7a6da 100644
--- a/src/Verismith/Verilog/CodeGen.hs
+++ b/src/Verismith/Verilog/CodeGen.hs
@@ -113,10 +113,11 @@ portDir PortInOut = "inout"
-- | Generate a '(ModItem ann)'.
moduleItem :: Show ann => ModItem ann -> Doc a
moduleItem (ModCA ca) = contAssign ca
-moduleItem (ModInst i name conn) =
+moduleItem (ModInst i param name conn) =
(<> semi) $
hsep
[ identifier i,
+ "#" <> (parens . hsep $ punctuate comma (mConn <$> param)),
identifier name,
parens . hsep $ punctuate comma (mConn <$> conn)
]