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-rw-r--r--src/Test/VeriFuzz/Simulator/General.hs8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/Test/VeriFuzz/Simulator/General.hs b/src/Test/VeriFuzz/Simulator/General.hs
index b513b79..8c5c7ec 100644
--- a/src/Test/VeriFuzz/Simulator/General.hs
+++ b/src/Test/VeriFuzz/Simulator/General.hs
@@ -45,11 +45,11 @@ class (Simulator a) => Synthesize a where
-> FilePath -- ^ Output verilog file for the module
-> Sh () -- ^ does not return any values
-timeout :: Text -> [Text] -> Sh Text
-timeout = command1 "timeout" ["180"]
+timeout :: FilePath -> [Text] -> Sh Text
+timeout = command1 "timeout" ["180"] . toTextIgnore
-timeout_ :: Text -> [Text] -> Sh ()
-timeout_ = command1_ "timeout" ["180"]
+timeout_ :: FilePath -> [Text] -> Sh ()
+timeout_ = command1_ "timeout" ["180"] . toTextIgnore
synthesizers :: [Text]
synthesizers = ["yosys", "xst"]