aboutsummaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/Test/VeriFuzz/Verilog/AST.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 65be816..33ccdb4 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -194,7 +194,7 @@ data ModItem = ModCA ContAssign
-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
data ModDecl = ModDecl { _moduleId :: Identifier
- , _modOutPort :: Maybe Port
+ , _modOutPorts :: [Port]
, _modInPorts :: [Port]
, _moduleItems :: [ModItem]
} deriving (Show, Eq, Ord)