| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add Cyclone 10 LP and GX | Yann Herklotz | 2019-11-14 | 1 | -33/+473 |
| | | |||||
| * | Add enable to dffeas | Yann Herklotz | 2019-11-12 | 1 | -8/+10 |
| | | |||||
| * | Remove second trigger for always block | Yann Herklotz | 2019-11-12 | 1 | -1/+1 |
| | | |||||
| * | Add asynchronous load | Yann Herklotz | 2019-11-05 | 1 | -2/+6 |
| | | |||||
| * | Fix dffeas specification | Yann Herklotz | 2019-10-31 | 1 | -4/+2 |
| | | |||||
| * | Fix cyclone_v cell declaration | Yann Herklotz | 2019-06-02 | 1 | -46/+12 |
| | | |||||
| * | Fix a warning in cells_cyclone_v.v | Yann Herklotz | 2019-05-06 | 1 | -241/+241 |
| | | |||||
| * | Add new modules to fix Quartus equivalence check | Yann Herklotz | 2019-04-21 | 1 | -1/+54 |
| | | |||||
| * | Add data folder with extra modules | Yann Herklotz | 2019-01-19 | 1 | -0/+238 |
| These modules are required for comparing modules that are generated by synthesising in different simulators, as they will each synthesise to specific hardware with assumptions on what is available | |||||
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |