| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename types to circuit | Yann Herklotz | 2018-12-15 | 1 | -22/+0 |
| * | [Fix #8] Add Circuit newtype | Yann Herklotz | 2018-12-02 | 1 | -0/+3 |
| * | Remove Nor and Nand from types | Yann Herklotz | 2018-11-16 | 1 | -4/+2 |
| * | Add style to the files | Yann Herklotz | 2018-11-14 | 1 | -3/+3 |
| * | Random generation of DAG | Yann Herklotz | 2018-11-09 | 1 | -2/+15 |
| * | Add initial module files | Yann Herklotz | 2018-11-09 | 1 | -0/+8 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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