| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 5 | -1183/+0 |
| * | Rename module names so that I can move them | Yann Herklotz | 2019-01-10 | 4 | -95/+240 |
| * | Add show instance to Identifier | Yann Herklotz | 2019-01-09 | 1 | -4/+8 |
| * | [Fix #20] Add more examples and finish makeTop | Yann Herklotz | 2019-01-09 | 1 | -0/+31 |
| * | Add conversion ByteString -> Integer | Yann Herklotz | 2019-01-02 | 1 | -3/+2 |
| * | Add num instance for the delay | Yann Herklotz | 2019-01-02 | 1 | -0/+9 |
| * | Fix indentation | Yann Herklotz | 2019-01-02 | 1 | -10/+10 |
| * | Remove Monoid instance for LVal, as it does not quite fit | Yann Herklotz | 2019-01-01 | 1 | -9/+0 |
| * | Add helper function to turn port into expr | Yann Herklotz | 2019-01-01 | 1 | -0/+3 |
| * | Add monoid instance for LVal | Yann Herklotz | 2019-01-01 | 1 | -1/+10 |
| * | Fix Monoid instance for Expr | Yann Herklotz | 2019-01-01 | 1 | -1/+1 |
| * | Add back monoid instance for statement | Yann Herklotz | 2019-01-01 | 1 | -0/+3 |
| * | Fix logic in CodeGen with maybe | Yann Herklotz | 2019-01-01 | 1 | -2/+4 |
| * | Fix linting warnings | Yann Herklotz | 2019-01-01 | 3 | -8/+8 |
| * | Formatting | Yann Herklotz | 2019-01-01 | 1 | -3/+3 |
| * | Remove empty statement and Monoid instance | Yann Herklotz | 2019-01-01 | 1 | -4/+0 |
| * | Fix Semigroup instances | Yann Herklotz | 2019-01-01 | 1 | -4/+8 |
| * | Add documentation | Yann Herklotz | 2019-01-01 | 1 | -0/+10 |
| * | Add string instance to expression | Yann Herklotz | 2019-01-01 | 1 | -12/+42 |
| * | Add missing case in function | Yann Herklotz | 2018-12-31 | 1 | -0/+2 |
| * | Add show instance and add concat to reglval | Yann Herklotz | 2018-12-31 | 4 | -42/+88 |
| * | Fix build errors | Yann Herklotz | 2018-12-31 | 1 | -0/+1 |
| * | Remove sep and fromList in favour of fold | Yann Herklotz | 2018-12-31 | 1 | -3/+3 |
| * | Separate arbitrary from types | Yann Herklotz | 2018-12-31 | 1 | -0/+184 |
| * | Large refactor | Yann Herklotz | 2018-12-31 | 4 | -317/+138 |
| * | Finish module instantiation | Yann Herklotz | 2018-12-31 | 2 | -5/+16 |
| * | Add direction to Decl and add doctest | Yann Herklotz | 2018-12-31 | 4 | -11/+26 |
| * | [Fix #17] Add size to ports | Yann Herklotz | 2018-12-31 | 2 | -5/+13 |
| * | Add doctest test | Yann Herklotz | 2018-12-31 | 1 | -0/+8 |
| * | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 3 | -13/+16 |
| * | Change modPort type from Maybe to List | Yann Herklotz | 2018-12-30 | 1 | -1/+1 |
| * | [Fix #14] Add size to Port type | Yann Herklotz | 2018-12-30 | 3 | -12/+21 |
| * | Move helper functions | Yann Herklotz | 2018-12-30 | 1 | -0/+76 |
| * | Fix verilog output for output port | Yann Herklotz | 2018-12-29 | 1 | -1/+1 |
| * | Make generation more controlled | Yann Herklotz | 2018-12-29 | 1 | -2/+4 |
| * | Rearrange instances | Yann Herklotz | 2018-12-29 | 1 | -5/+5 |
| * | Changes to the API | Yann Herklotz | 2018-12-29 | 3 | -23/+33 |
| * | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 3 | -9/+9 |
| * | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 3 | -0/+751 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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