| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add functions and fix EMI | Yann Herklotz | 2021-05-21 | 1 | -12/+28 |
| * | Add new simulation for EMI | Yann Herklotz | 2021-05-19 | 1 | -18/+28 |
| * | Add more top-level changes | Yann Herklotz | 2021-05-19 | 1 | -0/+52 |
| * | Add debug to reduction | Yann Herklotz | 2020-05-12 | 1 | -2/+2 |
| * | Format with ormolu | Yann Herklotz | 2020-05-12 | 1 | -353/+389 |
| * | Fix types with annotations | Yann Herklotz | 2020-05-11 | 1 | -9/+10 |
| * | Remove DRBG dependency | Yann Herklotz | 2020-04-07 | 1 | -15/+2 |
| * | Add annotations and make it compile again | Yann Herklotz | 2020-04-07 | 1 | -5/+5 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -9/+9 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Add configuration for default Yosys location | Yann Herklotz | 2019-12-26 | 1 | -5/+8 |
| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 1 | -8/+13 |
| * | More minimisation | Yann Herklotz | 2019-12-03 | 1 | -3/+9 |
| * | Add output of v file during reduction | Yann Herklotz | 2019-11-24 | 1 | -22/+4 |
| * | Show the result as it is run | Yann Herklotz | 2019-11-24 | 1 | -4/+4 |
| * | Add cross-check between netlists | Yann Herklotz | 2019-11-24 | 1 | -9/+11 |
| * | Fix counter-example simulation run | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add reduction for simulation failures | Yann Herklotz | 2019-11-12 | 1 | -12/+55 |
| * | Add counter example parsing | Yann Herklotz | 2019-11-10 | 1 | -2/+2 |
| * | Add data-file installation path | Yann Herklotz | 2019-10-29 | 1 | -13/+16 |
| * | Run simulation on all tools passing synthesis | Yann Herklotz | 2019-10-28 | 1 | -20/+27 |
| * | Add mtl dependency to enable easier use of transformers | Yann Herklotz | 2019-10-27 | 1 | -104/+140 |
| * | Change location of the html reports | Yann Herklotz | 2019-10-18 | 1 | -3/+5 |
| * | Add -k functionality | Yann Herklotz | 2019-10-18 | 1 | -4/+26 |
| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 1 | -21/+16 |
| * | [Fix #63] Make build pass again | Yann Herklotz | 2019-10-06 | 1 | -9/+5 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+466 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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