| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix parser for a larger set of inputs | Yann Herklotz | 2021-04-26 | 1 | -4/+4 |
| * | Remove removeDecl as that pass is already there | Yann Herklotz | 2020-05-13 | 1 | -1/+1 |
| * | Add for loops and events to reduction | Yann Herklotz | 2020-05-12 | 1 | -1/+18 |
| * | Add line count to reduction | Yann Herklotz | 2020-05-12 | 1 | -3/+5 |
| * | Remove single module instead of all | Yann Herklotz | 2020-05-12 | 1 | -25/+30 |
| * | Add debug to reduction | Yann Herklotz | 2020-05-12 | 1 | -2/+12 |
| * | Format with ormolu | Yann Herklotz | 2020-05-12 | 1 | -323/+350 |
| * | Tests passing for new reduction | Yann Herklotz | 2020-05-11 | 1 | -0/+4 |
| * | Add reduction annotations | Yann Herklotz | 2020-05-11 | 1 | -92/+134 |
| * | Add annotations and make it compile again | Yann Herklotz | 2020-04-07 | 1 | -5/+11 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -60/+57 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Add correct cleaning function back | Yann Herklotz | 2019-12-26 | 1 | -1/+1 |
| * | Add reduction stage back | Yann Herklotz | 2019-12-26 | 1 | -0/+1 |
| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 1 | -3/+4 |
| * | Add extension to simulation reduction | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add output of v file during reduction | Yann Herklotz | 2019-11-24 | 1 | -13/+16 |
| * | Add reduction for simulation failures | Yann Herklotz | 2019-11-12 | 1 | -5/+28 |
| * | Add counter example parsing | Yann Herklotz | 2019-11-10 | 1 | -3/+3 |
| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 1 | -1/+19 |
| * | Add data-file installation path | Yann Herklotz | 2019-10-29 | 1 | -3/+4 |
| * | Rename Sim to Tool | Yann Herklotz | 2019-10-18 | 1 | -2/+2 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+609 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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