| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Fix build errors | Yann Herklotz | 2018-12-31 | 2 | -2/+5 | |
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| * | Remove sep and fromList in favour of fold | Yann Herklotz | 2018-12-31 | 3 | -26/+7 | |
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| * | Separate arbitrary from types | Yann Herklotz | 2018-12-31 | 1 | -0/+184 | |
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| * | Adding code to Icarus | Yann Herklotz | 2018-12-31 | 1 | -3/+15 | |
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| * | Large refactor | Yann Herklotz | 2018-12-31 | 7 | -326/+149 | |
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| * | Finish module instantiation | Yann Herklotz | 2018-12-31 | 2 | -5/+16 | |
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| * | Add direction to Decl and add doctest | Yann Herklotz | 2018-12-31 | 4 | -11/+26 | |
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| * | [Fix #17] Add size to ports | Yann Herklotz | 2018-12-31 | 2 | -5/+13 | |
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| * | Add doctest test | Yann Herklotz | 2018-12-31 | 1 | -0/+8 | |
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| * | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 4 | -14/+17 | |
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| * | Change modPort type from Maybe to List | Yann Herklotz | 2018-12-30 | 1 | -1/+1 | |
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| * | [Fix #14] Add size to Port type | Yann Herklotz | 2018-12-30 | 4 | -14/+23 | |
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| * | Move helper functions | Yann Herklotz | 2018-12-30 | 3 | -5/+7 | |
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| * | Add remove duplicates | Yann Herklotz | 2018-12-29 | 2 | -6/+18 | |
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| * | Add internal function for fix | Yann Herklotz | 2018-12-29 | 1 | -0/+6 | |
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| * | Fix verilog output for output port | Yann Herklotz | 2018-12-29 | 1 | -1/+1 | |
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| * | Add alternative generation method | Yann Herklotz | 2018-12-29 | 1 | -0/+29 | |
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| * | Add new generation method | Yann Herklotz | 2018-12-29 | 1 | -14/+14 | |
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| * | Style changes | Yann Herklotz | 2018-12-29 | 1 | -7/+7 | |
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| * | Make generation more controlled | Yann Herklotz | 2018-12-29 | 1 | -2/+4 | |
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| * | Rearrange instances | Yann Herklotz | 2018-12-29 | 1 | -5/+5 | |
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| * | Changes to the API | Yann Herklotz | 2018-12-29 | 5 | -43/+60 | |
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| * | Add simulator code | Yann Herklotz | 2018-12-29 | 3 | -8/+24 | |
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| * | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 17 | -51/+51 | |
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| * | Add simulator module | Yann Herklotz | 2018-12-28 | 5 | -0/+215 | |
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| * | Fix imports and cabal file | Yann Herklotz | 2018-12-28 | 3 | -16/+13 | |
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| * | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 4 | -21/+104 | |
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| * | Add instantiation function | Yann Herklotz | 2018-12-27 | 1 | -2/+7 | |
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| * | Remove OverloadedStrings in favour of declaration in module | Yann Herklotz | 2018-12-27 | 5 | -10/+1 | |
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| * | Format fixes | Yann Herklotz | 2018-12-27 | 1 | -20/+20 | |
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| * | Small style change | Yann Herklotz | 2018-12-27 | 1 | -1/+1 | |
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| * | Improve expression and statement generation | Yann Herklotz | 2018-12-27 | 1 | -20/+96 | |
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| * | Add documentation to main module | Yann Herklotz | 2018-12-25 | 1 | -0/+13 | |
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| * | Add code generation for new types | Yann Herklotz | 2018-12-25 | 1 | -20/+130 | |
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| * | Type fixes | Yann Herklotz | 2018-12-25 | 1 | -7/+8 | |
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| * | Rename Node to Int | Yann Herklotz | 2018-12-25 | 1 | -1/+1 | |
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| * | [Close #10, Fix #12] Add Mutations for wires | Yann Herklotz | 2018-12-25 | 1 | -7/+13 | |
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| * | Add more types | Yann Herklotz | 2018-12-25 | 1 | -41/+181 | |
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| * | Add Helpers.hs | Yann Herklotz | 2018-12-25 | 1 | -0/+75 | |
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| * | Fix nesting, generation broken for nested groups | Yann Herklotz | 2018-12-23 | 1 | -3/+17 | |
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| * | Add nesting to the SourceText | Yann Herklotz | 2018-12-23 | 1 | -1/+16 | |
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| * | [Fix #11] Implement the traversal | Yann Herklotz | 2018-12-23 | 1 | -18/+32 | |
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| * | Start implementing the nesting functionality | Yann Herklotz | 2018-12-23 | 1 | -2/+23 | |
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| * | Derive `Eq` for the Verilog AST. | Yann Herklotz | 2018-12-22 | 2 | -13/+14 | |
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| * | Add unimplemented nestId function | Yann Herklotz | 2018-12-22 | 1 | -0/+4 | |
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| * | Add Mutate module to VeriFuzz | Yann Herklotz | 2018-12-22 | 2 | -0/+17 | |
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| * | Format ASTGen | Yann Herklotz | 2018-12-22 | 1 | -6/+3 | |
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| * | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 4 | -19/+33 | |
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| * | Add shared code to code generation | Yann Herklotz | 2018-12-22 | 1 | -0/+34 | |
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| * | Add more functions to the code generation | Yann Herklotz | 2018-12-22 | 2 | -25/+21 | |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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