[Fix #13, Fix #15] Fix type errors and add inst functions

4 files changed, 17 insertions, 14 deletions

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index cf996de..3c000ea 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items
   where
     id = Identifier "gen_module"
     ports = genPortsAST inputsC c
-    output = Just $ Port (PortNet Wire) 1 "y"
+    output = [Port (PortNet Wire) 1 "y"]
     items = genAssignAST c
 
 generateAST :: Circuit -> VerilogSrc
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index 7861294..e3e6ecf 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -47,11 +47,11 @@ genModuleDecl mod =
   where
     ports
       | noIn && noOut = ""
-      | otherwise = "(" <> out <> (sep_ ", " $ genModPort <$> mod ^. modInPorts) <> ")"
+      | otherwise = "(" <> (sep_ ", " $ genModPort <$> outIn) <> ")"
     modItems = fromList $ genModuleItem <$> mod ^. moduleItems
-    noOut = isNothing $ mod ^. modOutPort
+    noOut = null $ mod ^. modOutPorts
     noIn = null $ mod ^. modInPorts
-    out = fromMaybe "" . safe head $ mod ^.. modOutPort . _Just . portName . getIdentifier
+    outIn = (mod ^. modOutPorts) ++ (mod ^. modInPorts)
 
 genModPort :: Port -> Text
 genModPort port = port ^. portName . getIdentifier
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 4410532..6712d32 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -32,7 +32,7 @@ numExpr = ((PrimExpr . PrimNum) .) . Number
 
 -- | Create an empty module.
 emptyMod :: ModDecl
-emptyMod = ModDecl "" Nothing [] []
+emptyMod = ModDecl "" [] [] []
 
 -- | Set a module name for a module declaration.
 setModName :: Text -> ModDecl -> ModDecl
@@ -47,7 +47,7 @@ addDescription desc = getVerilogSrc %~ (:) desc
 
 testBench :: ModDecl
 testBench =
-  ModDecl "main" Nothing []
+  ModDecl "main" [] []
   [ regDecl "a"
   , regDecl "b"
   , wireDecl "c"
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 6993fef..e9d7aed 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -21,11 +21,9 @@ import           Test.VeriFuzz.Verilog.AST
 
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
-inPort id mod = inInput || inOutput
+inPort id mod = inInput
   where
-    inInput = any (\a -> a ^. portName == id) $ mod ^. modInPorts
-    inOutput = fromMaybe False . safe head $ (==id) <$>
-      mod ^.. modOutPort . _Just . portName
+    inInput = any (\a -> a ^. portName == id) $ mod ^. modInPorts ++ mod ^. modOutPorts
 
 -- | Find the last assignment of a specific wire/reg to an expression, and
 -- returns that expression.
@@ -78,12 +76,17 @@ nestUpTo i src =
   foldl (flip nestSource) src $ Identifier . fromNode <$> [1..i]
 
 -- | Add a Module Instantiation using 'ModInst' from the first module passed to
--- it to the body of the second module.
+-- it to the body of the second module. It first has to make all the inputs into
+-- @reg@.
 instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod mod main =
-  main
+  main & moduleItems %~ ((out ++ regIn)++)
+  where
+    out = Decl <$> mod ^. modOutPorts
+    regIn = Decl <$> (mod ^. modInPorts & traverse . portType .~ Reg False)
 
 -- | Initialise all the inputs and outputs to a module.
 initMod :: ModDecl -> ModDecl
-initMod mod =
-  mod
+initMod mod = mod & moduleItems %~ (inOut++)
+  where
+    inOut = Decl <$> (mod ^. modOutPorts) ++ (mod ^. modInPorts)