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author | Yann Herklotz <git@yannherklotz.com> | 2023-05-11 19:38:03 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2023-05-11 19:38:03 +0100 |
commit | 47c1289ff658a5aec71635d79ffe30bb29a07876 (patch) | |
tree | 56cf6b959e37fed88c492d34defd3d7ec40e7148 /content/zettel/1c2d.md | |
parent | fbe0fc62120348f582dc4db2b614078943d0764b (diff) | |
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diff --git a/content/zettel/1c2d.md b/content/zettel/1c2d.md new file mode 100644 index 0000000..6ed9cb6 --- /dev/null +++ b/content/zettel/1c2d.md @@ -0,0 +1,35 @@ ++++ +title = "Hardware Scheduling" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["1c2c", "1c1"] +forwardlinks = ["1c2e"] +zettelid = "1c2d" ++++ + +Hardware scheduling is a bit different to software scheduling, however, +it is quite similar to the instruction scheduling in the KVX processor +\[1\]. However, there are a few difference, for example, I think for the +transformation from software to hardware, I really have to get rid of +the notion that there is a program counter in hardware, because that is +really not the case. Instead, we have a variable that keeps track of the +current state, but technically we could have many of those and they +could all be executing at the same time. + +<div id="refs" class="references csl-bib-body" markdown="1"> + +<div id="ref-six20_certif_effic_instr_sched" class="csl-entry" +markdown="1"> + +<span class="csl-left-margin">\[1\] +</span><span class="csl-right-inline">C. Six, S. Boulmé, and D. +Monniaux, “Certified and efficient instruction scheduling: Application +to interlocked VLIW processors,” *Proc. ACM Program. Lang.*, vol. 4, no. +OOPSLA, Nov. 2020, doi: [10.1145/3428197].</span> + +</div> + +</div> + + [10.1145/3428197]: https://doi.org/10.1145/3428197 |