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+title = "Hardware Scheduling"
+author = "Yann Herklotz"
+tags = []
+categories = []
+backlinks = ["1c2c", "1c1"]
+forwardlinks = ["1c2e"]
+zettelid = "1c2d"
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+
+Hardware scheduling is a bit different to software scheduling, however,
+it is quite similar to the instruction scheduling in the KVX processor
+\[1\]. However, there are a few difference, for example, I think for the
+transformation from software to hardware, I really have to get rid of
+the notion that there is a program counter in hardware, because that is
+really not the case. Instead, we have a variable that keeps track of the
+current state, but technically we could have many of those and they
+could all be executing at the same time.
+
+<div id="refs" class="references csl-bib-body" markdown="1">
+
+<div id="ref-six20_certif_effic_instr_sched" class="csl-entry"
+markdown="1">
+
+<span class="csl-left-margin">\[1\]
+</span><span class="csl-right-inline">C. Six, S. Boulmé, and D.
+Monniaux, “Certified and efficient instruction scheduling: Application
+to interlocked VLIW processors,” *Proc. ACM Program. Lang.*, vol. 4, no.
+OOPSLA, Nov. 2020, doi: [10.1145/3428197].</span>
+
+</div>
+
+</div>
+
+  [10.1145/3428197]: https://doi.org/10.1145/3428197