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diff --git a/content/zettel/1b5.md b/content/zettel/1b5.md new file mode 100644 index 0000000..c060e4a --- /dev/null +++ b/content/zettel/1b5.md @@ -0,0 +1,17 @@ ++++ +title = "Global State" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["1b4"] +forwardlinks = ["1b6"] +zettelid = "1b5" ++++ + +It is quite tricky to synthesise global state, as global variables are +not a thing in Verilog. There are therefore two alternatives, either all +the global variables have to be passed to all the modules, or memory has +to be used to store the global state and it then has to be retrieved. +However, to start out, if only one module is generated, and if module +instantiations are never used, then global variables can just be +supported by defining them in the main module. |