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diff --git a/content/zettel/5a2.md b/content/zettel/5a2.md new file mode 100644 index 0000000..4880931 --- /dev/null +++ b/content/zettel/5a2.md @@ -0,0 +1,19 @@ ++++ +title = "Hardware pipelining" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["5a1"] +forwardlinks = ["5a2a"] +zettelid = "5a2" ++++ + +Pipelining is a common optimisation way to optimise hardware and use up +more resources in the FPGA. There are various ways in which this can be +done from an arbitrary circuit, so instead of representing the circuit +as a single state machine, which can only execute one state at a time, +pipelined hardware will process different parts of the input at +different iterations. As a source for a lot of this information, I am +using a blog post by ZipCPU [^1]. + +[^1]: <https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html> |