blob: 4880931a22630b47339a31e12e74a024004e6eaf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
|
+++
title = "Hardware pipelining"
author = "Yann Herklotz"
tags = []
categories = []
backlinks = ["5a1"]
forwardlinks = ["5a2a"]
zettelid = "5a2"
+++
Pipelining is a common optimisation way to optimise hardware and use up
more resources in the FPGA. There are various ways in which this can be
done from an arbitrary circuit, so instead of representing the circuit
as a single state machine, which can only execute one state at a time,
pipelined hardware will process different parts of the input at
different iterations. As a source for a lot of this information, I am
using a blog post by ZipCPU [^1].
[^1]: <https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html>
|
