diff options
Diffstat (limited to 'bcd_to_display/output_files/bcd_to_display.sta.rpt')
| -rw-r--r-- | bcd_to_display/output_files/bcd_to_display.sta.rpt | 676 |
1 files changed, 676 insertions, 0 deletions
diff --git a/bcd_to_display/output_files/bcd_to_display.sta.rpt b/bcd_to_display/output_files/bcd_to_display.sta.rpt new file mode 100644 index 0000000..f257f10 --- /dev/null +++ b/bcd_to_display/output_files/bcd_to_display.sta.rpt @@ -0,0 +1,676 @@ +TimeQuest Timing Analyzer report for bcd_to_display +Fri Feb 26 16:37:05 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Propagation Delay + 13. Minimum Propagation Delay + 14. Slow 1200mV 85C Model Metastability Report + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Propagation Delay + 22. Minimum Propagation Delay + 23. Slow 1200mV 0C Model Metastability Report + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Propagation Delay + 30. Minimum Propagation Delay + 31. Fast 1200mV 0C Model Metastability Report + 32. Multicorner Timing Analysis Summary + 33. Progagation Delay + 34. Minimum Progagation Delay + 35. Board Trace Model Assignments + 36. Input Transition Times + 37. Slow Corner Signal Integrity Metrics + 38. Fast Corner Signal Integrity Metrics + 39. Clock Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths + 43. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+--------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ; +; Revision Name ; bcd_to_display ; +; Device Family ; Cyclone III ; +; Device Name ; EP3C16F484C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+--------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; < 0.1% ; +; Processors 5-8 ; 0.0% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 7.077 ; 7.052 ; 7.481 ; 7.465 ; +; BCDin[0] ; DISPout[1] ; 6.563 ; 6.586 ; 6.973 ; 7.005 ; +; BCDin[0] ; DISPout[2] ; ; 6.563 ; 6.944 ; ; +; BCDin[0] ; DISPout[3] ; 6.246 ; 6.261 ; 6.657 ; 6.681 ; +; BCDin[0] ; DISPout[4] ; 6.408 ; ; ; 6.881 ; +; BCDin[0] ; DISPout[5] ; 6.553 ; ; ; 6.963 ; +; BCDin[0] ; DISPout[6] ; 6.139 ; ; ; 6.606 ; +; BCDin[1] ; DISPout[0] ; ; 6.998 ; 7.482 ; ; +; BCDin[1] ; DISPout[1] ; 6.555 ; 6.481 ; 6.913 ; 6.996 ; +; BCDin[1] ; DISPout[2] ; 6.517 ; ; ; 6.940 ; +; BCDin[1] ; DISPout[3] ; 6.184 ; 6.208 ; 6.658 ; 6.630 ; +; BCDin[1] ; DISPout[4] ; ; 6.407 ; 6.819 ; ; +; BCDin[1] ; DISPout[5] ; 6.531 ; ; ; 6.928 ; +; BCDin[1] ; DISPout[6] ; 6.075 ; 6.144 ; 6.530 ; 6.556 ; +; BCDin[2] ; DISPout[0] ; 7.093 ; 6.995 ; 7.436 ; 7.465 ; +; BCDin[2] ; DISPout[1] ; 6.588 ; ; ; 7.019 ; +; BCDin[2] ; DISPout[2] ; ; 6.544 ; 6.983 ; ; +; BCDin[2] ; DISPout[3] ; 6.271 ; 6.213 ; 6.616 ; 6.685 ; +; BCDin[2] ; DISPout[4] ; 6.432 ; ; ; 6.882 ; +; BCDin[2] ; DISPout[5] ; ; 6.536 ; 7.005 ; ; +; BCDin[2] ; DISPout[6] ; 6.119 ; 6.192 ; 6.572 ; 6.587 ; +; BCDin[3] ; DISPout[0] ; ; 7.093 ; 7.569 ; ; +; BCDin[3] ; DISPout[2] ; ; 6.606 ; 7.032 ; ; +; BCDin[3] ; DISPout[3] ; ; 6.309 ; 6.747 ; ; +; BCDin[3] ; DISPout[5] ; ; 6.596 ; 7.054 ; ; +; BCDin[3] ; DISPout[6] ; ; 6.237 ; 6.640 ; ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 6.909 ; 6.886 ; 7.302 ; 7.288 ; +; BCDin[0] ; DISPout[1] ; 6.416 ; 6.439 ; 6.814 ; 6.846 ; +; BCDin[0] ; DISPout[2] ; ; 6.415 ; 6.785 ; ; +; BCDin[0] ; DISPout[3] ; 6.109 ; 6.125 ; 6.508 ; 6.533 ; +; BCDin[0] ; DISPout[4] ; 6.261 ; ; ; 6.722 ; +; BCDin[0] ; DISPout[5] ; 6.404 ; ; ; 6.804 ; +; BCDin[0] ; DISPout[6] ; 6.003 ; ; ; 6.459 ; +; BCDin[1] ; DISPout[0] ; ; 6.793 ; 7.221 ; ; +; BCDin[1] ; DISPout[1] ; 6.400 ; 6.335 ; 6.749 ; 6.821 ; +; BCDin[1] ; DISPout[2] ; 6.369 ; ; ; 6.780 ; +; BCDin[1] ; DISPout[3] ; 6.048 ; 6.033 ; 6.428 ; 6.483 ; +; BCDin[1] ; DISPout[4] ; ; 6.248 ; 6.633 ; ; +; BCDin[1] ; DISPout[5] ; 6.340 ; ; ; 6.755 ; +; BCDin[1] ; DISPout[6] ; 5.940 ; 5.958 ; 6.321 ; 6.409 ; +; BCDin[2] ; DISPout[0] ; 6.924 ; 6.830 ; 7.259 ; 7.287 ; +; BCDin[2] ; DISPout[1] ; 6.366 ; ; ; 6.792 ; +; BCDin[2] ; DISPout[2] ; ; 6.396 ; 6.822 ; ; +; BCDin[2] ; DISPout[3] ; 6.088 ; 6.078 ; 6.469 ; 6.512 ; +; BCDin[2] ; DISPout[4] ; 6.256 ; ; ; 6.709 ; +; BCDin[2] ; DISPout[5] ; ; 6.353 ; 6.765 ; ; +; BCDin[2] ; DISPout[6] ; 5.983 ; 6.006 ; 6.364 ; 6.440 ; +; BCDin[3] ; DISPout[0] ; ; 6.921 ; 7.383 ; ; +; BCDin[3] ; DISPout[2] ; ; 6.454 ; 6.867 ; ; +; BCDin[3] ; DISPout[3] ; ; 6.167 ; 6.592 ; ; +; BCDin[3] ; DISPout[5] ; ; 6.441 ; 6.887 ; ; +; BCDin[3] ; DISPout[6] ; ; 6.094 ; 6.486 ; ; ++------------+-------------+-------+-------+-------+-------+ + + +---------------------------------------------- +; Slow 1200mV 85C Model Metastability Report ; +---------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 6.545 ; 6.578 ; 6.884 ; 6.925 ; +; BCDin[0] ; DISPout[1] ; 6.091 ; 6.133 ; 6.436 ; 6.486 ; +; BCDin[0] ; DISPout[2] ; ; 6.110 ; 6.417 ; ; +; BCDin[0] ; DISPout[3] ; 5.805 ; 5.834 ; 6.144 ; 6.181 ; +; BCDin[0] ; DISPout[4] ; 5.951 ; ; ; 6.363 ; +; BCDin[0] ; DISPout[5] ; 6.073 ; ; ; 6.445 ; +; BCDin[0] ; DISPout[6] ; 5.697 ; ; ; 6.110 ; +; BCDin[1] ; DISPout[0] ; ; 6.506 ; 6.872 ; ; +; BCDin[1] ; DISPout[1] ; 6.062 ; 6.016 ; 6.365 ; 6.459 ; +; BCDin[1] ; DISPout[2] ; 6.039 ; ; ; 6.410 ; +; BCDin[1] ; DISPout[3] ; 5.725 ; 5.762 ; 6.133 ; 6.120 ; +; BCDin[1] ; DISPout[4] ; ; 5.936 ; 6.279 ; ; +; BCDin[1] ; DISPout[5] ; 6.035 ; ; ; 6.396 ; +; BCDin[1] ; DISPout[6] ; 5.616 ; 5.698 ; 6.010 ; 6.046 ; +; BCDin[2] ; DISPout[0] ; 6.530 ; 6.496 ; 6.832 ; 6.911 ; +; BCDin[2] ; DISPout[1] ; 6.081 ; ; ; 6.483 ; +; BCDin[2] ; DISPout[2] ; ; 6.058 ; 6.440 ; ; +; BCDin[2] ; DISPout[3] ; 5.795 ; 5.757 ; 6.099 ; 6.174 ; +; BCDin[2] ; DISPout[4] ; 5.941 ; ; ; 6.348 ; +; BCDin[2] ; DISPout[5] ; ; 6.048 ; 6.445 ; ; +; BCDin[2] ; DISPout[6] ; 5.643 ; 5.729 ; 6.052 ; 6.080 ; +; BCDin[3] ; DISPout[0] ; ; 6.601 ; 6.948 ; ; +; BCDin[3] ; DISPout[2] ; ; 6.135 ; 6.481 ; ; +; BCDin[3] ; DISPout[3] ; ; 5.862 ; 6.214 ; ; +; BCDin[3] ; DISPout[5] ; ; 6.124 ; 6.486 ; ; +; BCDin[3] ; DISPout[6] ; ; 5.788 ; 6.109 ; ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 6.401 ; 6.433 ; 6.732 ; 6.770 ; +; BCDin[0] ; DISPout[1] ; 5.965 ; 6.006 ; 6.302 ; 6.349 ; +; BCDin[0] ; DISPout[2] ; ; 5.984 ; 6.283 ; ; +; BCDin[0] ; DISPout[3] ; 5.690 ; 5.718 ; 6.021 ; 6.055 ; +; BCDin[0] ; DISPout[4] ; 5.825 ; ; ; 6.227 ; +; BCDin[0] ; DISPout[5] ; 5.945 ; ; ; 6.308 ; +; BCDin[0] ; DISPout[6] ; 5.580 ; ; ; 5.984 ; +; BCDin[1] ; DISPout[0] ; ; 6.330 ; 6.647 ; ; +; BCDin[1] ; DISPout[1] ; 5.933 ; 5.892 ; 6.229 ; 6.312 ; +; BCDin[1] ; DISPout[2] ; 5.913 ; ; ; 6.274 ; +; BCDin[1] ; DISPout[3] ; 5.612 ; 5.615 ; 5.937 ; 5.996 ; +; BCDin[1] ; DISPout[4] ; ; 5.802 ; 6.122 ; ; +; BCDin[1] ; DISPout[5] ; 5.868 ; ; ; 6.247 ; +; BCDin[1] ; DISPout[6] ; 5.503 ; 5.539 ; 5.830 ; 5.922 ; +; BCDin[2] ; DISPout[0] ; 6.387 ; 6.354 ; 6.680 ; 6.755 ; +; BCDin[2] ; DISPout[1] ; 5.895 ; ; ; 6.286 ; +; BCDin[2] ; DISPout[2] ; ; 5.934 ; 6.304 ; ; +; BCDin[2] ; DISPout[3] ; 5.637 ; 5.644 ; 5.977 ; 6.028 ; +; BCDin[2] ; DISPout[4] ; 5.793 ; ; ; 6.203 ; +; BCDin[2] ; DISPout[5] ; ; 5.895 ; 6.238 ; ; +; BCDin[2] ; DISPout[6] ; 5.530 ; 5.570 ; 5.872 ; 5.956 ; +; BCDin[3] ; DISPout[0] ; ; 6.451 ; 6.789 ; ; +; BCDin[3] ; DISPout[2] ; ; 6.005 ; 6.341 ; ; +; BCDin[3] ; DISPout[3] ; ; 5.740 ; 6.085 ; ; +; BCDin[3] ; DISPout[5] ; ; 5.992 ; 6.344 ; ; +; BCDin[3] ; DISPout[6] ; ; 5.666 ; 5.978 ; ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Slow 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + ++----------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 4.294 ; 4.227 ; 4.864 ; 4.804 ; +; BCDin[0] ; DISPout[1] ; 3.983 ; 3.961 ; 4.553 ; 4.538 ; +; BCDin[0] ; DISPout[2] ; ; 3.942 ; 4.528 ; ; +; BCDin[0] ; DISPout[3] ; 3.763 ; 3.760 ; 4.333 ; 4.337 ; +; BCDin[0] ; DISPout[4] ; 3.874 ; ; ; 4.393 ; +; BCDin[0] ; DISPout[5] ; 3.954 ; ; ; 4.511 ; +; BCDin[0] ; DISPout[6] ; 3.695 ; ; ; 4.233 ; +; BCDin[1] ; DISPout[0] ; ; 4.173 ; 4.819 ; ; +; BCDin[1] ; DISPout[1] ; 3.951 ; 3.879 ; 4.478 ; 4.497 ; +; BCDin[1] ; DISPout[2] ; 3.913 ; ; ; 4.454 ; +; BCDin[1] ; DISPout[3] ; 3.698 ; 3.706 ; 4.288 ; 4.268 ; +; BCDin[1] ; DISPout[4] ; ; 3.763 ; 4.399 ; ; +; BCDin[1] ; DISPout[5] ; 3.912 ; ; ; 4.449 ; +; BCDin[1] ; DISPout[6] ; 3.631 ; 3.610 ; 4.205 ; 4.165 ; +; BCDin[2] ; DISPout[0] ; 4.269 ; 4.169 ; 4.800 ; 4.770 ; +; BCDin[2] ; DISPout[1] ; 3.968 ; ; ; 4.517 ; +; BCDin[2] ; DISPout[2] ; ; 3.908 ; 4.512 ; ; +; BCDin[2] ; DISPout[3] ; 3.743 ; 3.707 ; 4.277 ; 4.311 ; +; BCDin[2] ; DISPout[4] ; 3.852 ; ; ; 4.365 ; +; BCDin[2] ; DISPout[5] ; ; 3.910 ; 4.519 ; ; +; BCDin[2] ; DISPout[6] ; 3.657 ; 3.637 ; 4.247 ; 4.200 ; +; BCDin[3] ; DISPout[0] ; ; 4.232 ; 4.880 ; ; +; BCDin[3] ; DISPout[2] ; ; 3.948 ; 4.545 ; ; +; BCDin[3] ; DISPout[3] ; ; 3.770 ; 4.354 ; ; +; BCDin[3] ; DISPout[5] ; ; 3.951 ; 4.551 ; ; +; BCDin[3] ; DISPout[6] ; ; 3.670 ; 4.290 ; ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 4.194 ; 4.129 ; 4.758 ; 4.700 ; +; BCDin[0] ; DISPout[1] ; 3.896 ; 3.874 ; 4.460 ; 4.445 ; +; BCDin[0] ; DISPout[2] ; ; 3.855 ; 4.434 ; ; +; BCDin[0] ; DISPout[3] ; 3.683 ; 3.679 ; 4.247 ; 4.250 ; +; BCDin[0] ; DISPout[4] ; 3.786 ; ; ; 4.300 ; +; BCDin[0] ; DISPout[5] ; 3.866 ; ; ; 4.417 ; +; BCDin[0] ; DISPout[6] ; 3.615 ; ; ; 4.148 ; +; BCDin[1] ; DISPout[0] ; ; 4.054 ; 4.666 ; ; +; BCDin[1] ; DISPout[1] ; 3.859 ; 3.794 ; 4.384 ; 4.396 ; +; BCDin[1] ; DISPout[2] ; 3.826 ; ; ; 4.363 ; +; BCDin[1] ; DISPout[3] ; 3.619 ; 3.604 ; 4.155 ; 4.183 ; +; BCDin[1] ; DISPout[4] ; ; 3.669 ; 4.292 ; ; +; BCDin[1] ; DISPout[5] ; 3.804 ; ; ; 4.353 ; +; BCDin[1] ; DISPout[6] ; 3.551 ; 3.502 ; 4.087 ; 4.081 ; +; BCDin[2] ; DISPout[0] ; 4.170 ; 4.074 ; 4.696 ; 4.668 ; +; BCDin[2] ; DISPout[1] ; 3.839 ; ; ; 4.383 ; +; BCDin[2] ; DISPout[2] ; ; 3.823 ; 4.417 ; ; +; BCDin[2] ; DISPout[3] ; 3.643 ; 3.629 ; 4.193 ; 4.214 ; +; BCDin[2] ; DISPout[4] ; 3.753 ; ; ; 4.268 ; +; BCDin[2] ; DISPout[5] ; ; 3.802 ; 4.381 ; ; +; BCDin[2] ; DISPout[6] ; 3.578 ; 3.530 ; 4.128 ; 4.115 ; +; BCDin[3] ; DISPout[0] ; ; 4.132 ; 4.771 ; ; +; BCDin[3] ; DISPout[2] ; ; 3.859 ; 4.448 ; ; +; BCDin[3] ; DISPout[3] ; ; 3.687 ; 4.265 ; ; +; BCDin[3] ; DISPout[5] ; ; 3.861 ; 4.454 ; ; +; BCDin[3] ; DISPout[6] ; ; 3.589 ; 4.201 ; ; ++------------+-------------+-------+-------+-------+-------+ + + +--------------------------------------------- +; Fast 1200mV 0C Model Metastability Report ; +--------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++----------------------------------------------------------+ +; Progagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 7.077 ; 7.052 ; 7.481 ; 7.465 ; +; BCDin[0] ; DISPout[1] ; 6.563 ; 6.586 ; 6.973 ; 7.005 ; +; BCDin[0] ; DISPout[2] ; ; 6.563 ; 6.944 ; ; +; BCDin[0] ; DISPout[3] ; 6.246 ; 6.261 ; 6.657 ; 6.681 ; +; BCDin[0] ; DISPout[4] ; 6.408 ; ; ; 6.881 ; +; BCDin[0] ; DISPout[5] ; 6.553 ; ; ; 6.963 ; +; BCDin[0] ; DISPout[6] ; 6.139 ; ; ; 6.606 ; +; BCDin[1] ; DISPout[0] ; ; 6.998 ; 7.482 ; ; +; BCDin[1] ; DISPout[1] ; 6.555 ; 6.481 ; 6.913 ; 6.996 ; +; BCDin[1] ; DISPout[2] ; 6.517 ; ; ; 6.940 ; +; BCDin[1] ; DISPout[3] ; 6.184 ; 6.208 ; 6.658 ; 6.630 ; +; BCDin[1] ; DISPout[4] ; ; 6.407 ; 6.819 ; ; +; BCDin[1] ; DISPout[5] ; 6.531 ; ; ; 6.928 ; +; BCDin[1] ; DISPout[6] ; 6.075 ; 6.144 ; 6.530 ; 6.556 ; +; BCDin[2] ; DISPout[0] ; 7.093 ; 6.995 ; 7.436 ; 7.465 ; +; BCDin[2] ; DISPout[1] ; 6.588 ; ; ; 7.019 ; +; BCDin[2] ; DISPout[2] ; ; 6.544 ; 6.983 ; ; +; BCDin[2] ; DISPout[3] ; 6.271 ; 6.213 ; 6.616 ; 6.685 ; +; BCDin[2] ; DISPout[4] ; 6.432 ; ; ; 6.882 ; +; BCDin[2] ; DISPout[5] ; ; 6.536 ; 7.005 ; ; +; BCDin[2] ; DISPout[6] ; 6.119 ; 6.192 ; 6.572 ; 6.587 ; +; BCDin[3] ; DISPout[0] ; ; 7.093 ; 7.569 ; ; +; BCDin[3] ; DISPout[2] ; ; 6.606 ; 7.032 ; ; +; BCDin[3] ; DISPout[3] ; ; 6.309 ; 6.747 ; ; +; BCDin[3] ; DISPout[5] ; ; 6.596 ; 7.054 ; ; +; BCDin[3] ; DISPout[6] ; ; 6.237 ; 6.640 ; ; ++------------+-------------+-------+-------+-------+-------+ + + ++----------------------------------------------------------+ +; Minimum Progagation Delay ; ++------------+-------------+-------+-------+-------+-------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+-------+-------+-------+-------+ +; BCDin[0] ; DISPout[0] ; 4.194 ; 4.129 ; 4.758 ; 4.700 ; +; BCDin[0] ; DISPout[1] ; 3.896 ; 3.874 ; 4.460 ; 4.445 ; +; BCDin[0] ; DISPout[2] ; ; 3.855 ; 4.434 ; ; +; BCDin[0] ; DISPout[3] ; 3.683 ; 3.679 ; 4.247 ; 4.250 ; +; BCDin[0] ; DISPout[4] ; 3.786 ; ; ; 4.300 ; +; BCDin[0] ; DISPout[5] ; 3.866 ; ; ; 4.417 ; +; BCDin[0] ; DISPout[6] ; 3.615 ; ; ; 4.148 ; +; BCDin[1] ; DISPout[0] ; ; 4.054 ; 4.666 ; ; +; BCDin[1] ; DISPout[1] ; 3.859 ; 3.794 ; 4.384 ; 4.396 ; +; BCDin[1] ; DISPout[2] ; 3.826 ; ; ; 4.363 ; +; BCDin[1] ; DISPout[3] ; 3.619 ; 3.604 ; 4.155 ; 4.183 ; +; BCDin[1] ; DISPout[4] ; ; 3.669 ; 4.292 ; ; +; BCDin[1] ; DISPout[5] ; 3.804 ; ; ; 4.353 ; +; BCDin[1] ; DISPout[6] ; 3.551 ; 3.502 ; 4.087 ; 4.081 ; +; BCDin[2] ; DISPout[0] ; 4.170 ; 4.074 ; 4.696 ; 4.668 ; +; BCDin[2] ; DISPout[1] ; 3.839 ; ; ; 4.383 ; +; BCDin[2] ; DISPout[2] ; ; 3.823 ; 4.417 ; ; +; BCDin[2] ; DISPout[3] ; 3.643 ; 3.629 ; 4.193 ; 4.214 ; +; BCDin[2] ; DISPout[4] ; 3.753 ; ; ; 4.268 ; +; BCDin[2] ; DISPout[5] ; ; 3.802 ; 4.381 ; ; +; BCDin[2] ; DISPout[6] ; 3.578 ; 3.530 ; 4.128 ; 4.115 ; +; BCDin[3] ; DISPout[0] ; ; 4.132 ; 4.771 ; ; +; BCDin[3] ; DISPout[2] ; ; 3.859 ; 4.448 ; ; +; BCDin[3] ; DISPout[3] ; ; 3.687 ; 4.265 ; ; +; BCDin[3] ; DISPout[5] ; ; 3.861 ; 4.454 ; ; +; BCDin[3] ; DISPout[6] ; ; 3.589 ; 4.201 ; ; ++------------+-------------+-------+-------+-------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; DISPout[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DISPout[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; BCDin[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; BCDin[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; BCDin[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; BCDin[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DISPout[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.36 V ; -0.00946 V ; 0.111 V ; 0.027 V ; 6.46e-10 s ; 6.2e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.36 V ; -0.00946 V ; 0.111 V ; 0.027 V ; 6.46e-10 s ; 6.2e-10 s ; Yes ; Yes ; +; DISPout[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; DISPout[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.36 V ; -0.00946 V ; 0.111 V ; 0.027 V ; 6.46e-10 s ; 6.2e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.36 V ; -0.00946 V ; 0.111 V ; 0.027 V ; 6.46e-10 s ; 6.2e-10 s ; Yes ; Yes ; +; DISPout[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; DISPout[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; DISPout[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; DISPout[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; 2.32 V ; 7.25e-07 V ; 2.35 V ; -0.0111 V ; 0.113 V ; 0.035 V ; 7.76e-10 s ; 8.04e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 5.68e-07 V ; 2.35 V ; -0.0132 V ; 0.2 V ; 0.027 V ; 5.26e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; 2.32 V ; 9.36e-07 V ; 2.35 V ; -0.00444 V ; 0.18 V ; 0.019 V ; 7.23e-10 s ; 9.82e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DISPout[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.72 V ; -0.0408 V ; 0.163 V ; 0.075 V ; 4.51e-10 s ; 4.33e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.72 V ; -0.0408 V ; 0.163 V ; 0.075 V ; 4.51e-10 s ; 4.33e-10 s ; No ; Yes ; +; DISPout[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; DISPout[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.72 V ; -0.0408 V ; 0.163 V ; 0.075 V ; 4.51e-10 s ; 4.33e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.72 V ; -0.0408 V ; 0.163 V ; 0.075 V ; 4.51e-10 s ; 4.33e-10 s ; No ; Yes ; +; DISPout[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; DISPout[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; DISPout[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; DISPout[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; 2.62 V ; 2.78e-08 V ; 2.71 V ; -0.0349 V ; 0.253 V ; 0.069 V ; 4.96e-10 s ; 5.19e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; 2.62 V ; 2.22e-08 V ; 2.72 V ; -0.0747 V ; 0.28 V ; 0.169 V ; 3.1e-10 s ; 3.01e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; 2.62 V ; 3.53e-08 V ; 2.7 V ; -0.0212 V ; 0.204 V ; 0.049 V ; 4.85e-10 s ; 6.73e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 4 ; 4 ; +; Unconstrained Input Port Paths ; 26 ; 26 ; +; Unconstrained Output Ports ; 7 ; 7 ; +; Unconstrained Output Port Paths ; 26 ; 26 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version + Info: Processing started: Fri Feb 26 16:37:02 2016 +Info: Command: quartus_sta bcd_to_display -c bcd_to_display +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'bcd_to_display.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 476 megabytes + Info: Processing ended: Fri Feb 26 16:37:05 2016 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:01 + + |