FPGA-2015 - A collection of Quartus projects to learn FPGA design.

Branch	Commit message	Author	Age
master	adding missing files	zedarider	7 years


Age	Commit message	Author	Files	Lines
2016-10-31	adding missing filesHEAD master	zedarider	1	-0/+0
2016-03-11	Adding note_reader project	zedarider	1	-0/+0
2016-03-09	Reorganising folders	zedarider	2645	-550194/+0
2016-03-09	improving sobel	zedarider	1	-11/+9
2016-03-08	Fixing the README file	zedarider	1	-0/+0
2016-03-08	adding working sobel filter	zedarider	1294	-0/+360650
2016-03-02	adding verilog stop clock made purely in verilog	zedarider	117	-0/+32205
2016-03-01	adding dot_product project	zedarider	1351	-0/+189546
2016-02-27	Adding Title	Yann Herklotz	1	-2/+3
2016-02-26	Adding README.md	zedarider	1	-0/+5
[...]

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