| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | README.md | 275 | logstatsplain |
| d--------- | adder | 505 | logstatsplain |
| d--------- | bcd_to_display | 416 | logstatsplain |
| d--------- | blinken_lights | 605 | logstatsplain |
| d--------- | comb_multiply | 400 | logstatsplain |
| d--------- | glue_logic | 273 | logstatsplain |
| d--------- | one_hertz_clock | 297 | logstatsplain |
| d--------- | pipelined_multiply | 229 | logstatsplain |
| d--------- | registered_multiply | 299 | logstatsplain |
| d--------- | stopClockVerilog | 537 | logstatsplain |
| d--------- | stopwatch | 273 | logstatsplain |
| d--------- | ten_bit_adder | 475 | logstatsplain |
| d--------- | ten_bit_adder_NO_BUS | 446 | logstatsplain |
| d--------- | ten_counter | 466 | logstatsplain |
| d--------- | ten_d_flip_flop | 381 | logstatsplain |
 |
index : FPGA-2015 | |
| A collection of Quartus projects to learn FPGA design. |
| aboutsummaryrefslogtreecommitdiffstats |