| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | adding missing filesHEADmaster | zedarider | 2016-10-31 | 1 | -0/+0 |
| * | Adding note_reader project | zedarider | 2016-03-11 | 1 | -0/+0 |
| * | Reorganising folders | zedarider | 2016-03-09 | 2645 | -550194/+0 |
| * | improving sobel | zedarider | 2016-03-09 | 1 | -11/+9 |
| * | Fixing the README file | zedarider | 2016-03-08 | 1 | -0/+0 |
| * | adding working sobel filter | zedarider | 2016-03-08 | 1294 | -0/+360650 |
| * | adding verilog stop clock made purely in verilog | zedarider | 2016-03-02 | 117 | -0/+32205 |
| * | adding dot_product project | zedarider | 2016-03-01 | 1351 | -0/+189546 |
| * | Adding Title | Yann Herklotz | 2016-02-27 | 1 | -2/+3 |
| * | Adding README.md | zedarider | 2016-02-26 | 1 | -0/+5 |
| * | adding fpga lab projects | zedarider | 2016-02-26 | 1315 | -0/+138416 |
 |
index : FPGA-2015 | |
| A collection of Quartus projects to learn FPGA design. |
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