adding fpga lab projects

1315 files changed, 138416 insertions, 0 deletions

diff --git a/adder/5_bit_adder.ipinfo b/adder/5_bit_adder.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/adder/5_bit_adder.ipinfo
diff --git a/adder/db/.cmp.kpt b/adder/db/.cmp.kpt
new file mode 100644
index 0000000..a82c41b
--- /dev/null
+++ b/adder/db/.cmp.kpt
diff --git a/adder/db/full_adder.(0).cnf.cdb b/adder/db/full_adder.(0).cnf.cdb
new file mode 100644
index 0000000..0d41d22
--- /dev/null
+++ b/adder/db/full_adder.(0).cnf.cdb
diff --git a/adder/db/full_adder.(0).cnf.hdb b/adder/db/full_adder.(0).cnf.hdb
new file mode 100644
index 0000000..cf52d24
--- /dev/null
+++ b/adder/db/full_adder.(0).cnf.hdb
diff --git a/adder/db/full_adder.asm.qmsg b/adder/db/full_adder.asm.qmsg
new file mode 100644
index 0000000..9939732
--- /dev/null
+++ b/adder/db/full_adder.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747308248 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747308249 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:15:08 2016 " "Processing started: Wed Feb 17 22:15:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747308249 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455747308249 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455747308249 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455747309433 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455747309471 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747310234 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:15:10 2016 " "Processing ended: Wed Feb 17 22:15:10 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747310234 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747310234 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747310234 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455747310234 ""}
diff --git a/adder/db/full_adder.asm.rdb b/adder/db/full_adder.asm.rdb
new file mode 100644
index 0000000..ae2ac2a
--- /dev/null
+++ b/adder/db/full_adder.asm.rdb
diff --git a/adder/db/full_adder.asm_labs.ddb b/adder/db/full_adder.asm_labs.ddb
new file mode 100644
index 0000000..ca2135c
--- /dev/null
+++ b/adder/db/full_adder.asm_labs.ddb
diff --git a/adder/db/full_adder.cbx.xml b/adder/db/full_adder.cbx.xml
new file mode 100644
index 0000000..93a9c76
--- /dev/null
+++ b/adder/db/full_adder.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="full_adder">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/adder/db/full_adder.cmp.bpm b/adder/db/full_adder.cmp.bpm
new file mode 100644
index 0000000..034b7b0
--- /dev/null
+++ b/adder/db/full_adder.cmp.bpm
diff --git a/adder/db/full_adder.cmp.cdb b/adder/db/full_adder.cmp.cdb
new file mode 100644
index 0000000..c646a06
--- /dev/null
+++ b/adder/db/full_adder.cmp.cdb
diff --git a/adder/db/full_adder.cmp.hdb b/adder/db/full_adder.cmp.hdb
new file mode 100644
index 0000000..fcf13b7
--- /dev/null
+++ b/adder/db/full_adder.cmp.hdb
diff --git a/adder/db/full_adder.cmp.idb b/adder/db/full_adder.cmp.idb
new file mode 100644
index 0000000..868118f
--- /dev/null
+++ b/adder/db/full_adder.cmp.idb
diff --git a/adder/db/full_adder.cmp.logdb b/adder/db/full_adder.cmp.logdb
new file mode 100644
index 0000000..ec048ac
--- /dev/null
+++ b/adder/db/full_adder.cmp.logdb
@@ -0,0 +1,47 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;5;0;0;5;5;0;2;0;0;3;0;2;3;0;0;0;2;0;0;0;0;0;5;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,5;5;5;5;5;0;5;5;0;0;5;3;5;5;2;5;3;2;5;5;5;3;5;5;5;5;5;0;5;5,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SUM,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Cout,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Cin,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/adder/db/full_adder.cmp.rdb b/adder/db/full_adder.cmp.rdb
new file mode 100644
index 0000000..effca05
--- /dev/null
+++ b/adder/db/full_adder.cmp.rdb
diff --git a/adder/db/full_adder.cmp_merge.kpt b/adder/db/full_adder.cmp_merge.kpt
new file mode 100644
index 0000000..d7a2153
--- /dev/null
+++ b/adder/db/full_adder.cmp_merge.kpt
diff --git a/adder/db/full_adder.db_info b/adder/db/full_adder.db_info
new file mode 100644
index 0000000..f738f8e
--- /dev/null
+++ b/adder/db/full_adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Feb 17 21:43:52 2016
diff --git a/adder/db/full_adder.eda.qmsg b/adder/db/full_adder.eda.qmsg
new file mode 100644
index 0000000..5a9dd41
--- /dev/null
+++ b/adder/db/full_adder.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747318669 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747318670 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:15:18 2016 " "Processing started: Wed Feb 17 22:15:18 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747318670 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747318670 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747318670 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_6_1200mv_85c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319706 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_6_1200mv_0c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319737 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_min_1200mv_0c_fast.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319774 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319813 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319858 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319883 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319932 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "full_adder_vhd.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/ simulation " "Generated file full_adder_vhd.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455747319967 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "477 " "Peak virtual memory: 477 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747320070 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:15:20 2016 " "Processing ended: Wed Feb 17 22:15:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747320070 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747320070 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747320070 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747320070 ""}
diff --git a/adder/db/full_adder.fit.qmsg b/adder/db/full_adder.fit.qmsg
new file mode 100644
index 0000000..d09e783
--- /dev/null
+++ b/adder/db/full_adder.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455747298918 ""}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "full_adder EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design full_adder" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455747299100 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747299160 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747299160 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455747299265 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455747299283 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747299848 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747299848 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455747299848 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747299850 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747299850 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747299850 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 27 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747299850 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 29 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747299850 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455747299850 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455747299851 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "5 5 " "No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SUM " "Pin SUM not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { SUM } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 184 848 1024 200 "SUM" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SUM } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 3 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747300255 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cout " "Pin Cout not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cout } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 264 896 1072 280 "Cout" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747300255 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X " "Pin X not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 208 360 528 224 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747300255 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y " "Pin Y not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 224 360 528 240 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747300255 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cin " "Pin Cin not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cin } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 240 360 528 256 "Cin" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cin } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747300255 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455747300255 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455747300487 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455747300488 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455747300488 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455747300489 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455747300489 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455747300490 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455747300490 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455747300492 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747300492 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747300492 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747300493 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747300493 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455747300494 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455747300494 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455747300495 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455747300494 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "5 unused 2.5V 3 2 0 " "Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 3 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455747300496 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455747300496 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455747300496 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 0 2 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747300497 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455747300497 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455747300497 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747300507 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455747302147 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747302229 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455747302241 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455747302513 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747302514 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455747303027 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X21_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9" {  } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} 11 0 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455747303866 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455747303866 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747303912 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455747303912 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455747303912 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455747303912 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455747303923 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747304046 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747304306 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747304460 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747304666 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747305150 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455747305639 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "920 " "Peak virtual memory: 920 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747306220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:15:06 2016 " "Processing ended: Wed Feb 17 22:15:06 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747306220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747306220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747306220 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455747306220 ""}
diff --git a/adder/db/full_adder.hier_info b/adder/db/full_adder.hier_info
new file mode 100644
index 0000000..199be39
--- /dev/null
+++ b/adder/db/full_adder.hier_info
@@ -0,0 +1,14 @@
+|full_adder
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/adder/db/full_adder.hif b/adder/db/full_adder.hif
new file mode 100644
index 0000000..07c23ac
--- /dev/null
+++ b/adder/db/full_adder.hif
diff --git a/adder/db/full_adder.ipinfo b/adder/db/full_adder.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/adder/db/full_adder.ipinfo
diff --git a/adder/db/full_adder.lpc.html b/adder/db/full_adder.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/adder/db/full_adder.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/adder/db/full_adder.lpc.rdb b/adder/db/full_adder.lpc.rdb
new file mode 100644
index 0000000..547d515
--- /dev/null
+++ b/adder/db/full_adder.lpc.rdb
diff --git a/adder/db/full_adder.lpc.txt b/adder/db/full_adder.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/adder/db/full_adder.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/adder/db/full_adder.map.ammdb b/adder/db/full_adder.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/adder/db/full_adder.map.ammdb
diff --git a/adder/db/full_adder.map.bpm b/adder/db/full_adder.map.bpm
new file mode 100644
index 0000000..d0c40e6
--- /dev/null
+++ b/adder/db/full_adder.map.bpm
diff --git a/adder/db/full_adder.map.cdb b/adder/db/full_adder.map.cdb
new file mode 100644
index 0000000..f748631
--- /dev/null
+++ b/adder/db/full_adder.map.cdb
diff --git a/adder/db/full_adder.map.hdb b/adder/db/full_adder.map.hdb
new file mode 100644
index 0000000..d4dab90
--- /dev/null
+++ b/adder/db/full_adder.map.hdb
diff --git a/adder/db/full_adder.map.kpt b/adder/db/full_adder.map.kpt
new file mode 100644
index 0000000..66234ed
--- /dev/null
+++ b/adder/db/full_adder.map.kpt
diff --git a/adder/db/full_adder.map.logdb b/adder/db/full_adder.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/db/full_adder.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/db/full_adder.map.qmsg b/adder/db/full_adder.map.qmsg
new file mode 100644
index 0000000..5e395de
--- /dev/null
+++ b/adder/db/full_adder.map.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747295029 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747295030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:14:54 2016 " "Processing started: Wed Feb 17 22:14:54 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747295030 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747295030 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747295030 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747295595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455747295664 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455747295664 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "full_adder " "Elaborating entity \"full_adder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455747295688 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455747296319 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455747296581 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455747296581 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455747296644 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455747296644 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455747296644 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455747296644 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "557 " "Peak virtual memory: 557 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747296669 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:14:56 2016 " "Processing ended: Wed Feb 17 22:14:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747296669 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747296669 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747296669 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747296669 ""}
diff --git a/adder/db/full_adder.map.rdb b/adder/db/full_adder.map.rdb
new file mode 100644
index 0000000..16552df
--- /dev/null
+++ b/adder/db/full_adder.map.rdb
diff --git a/adder/db/full_adder.map_bb.cdb b/adder/db/full_adder.map_bb.cdb
new file mode 100644
index 0000000..72cadb9
--- /dev/null
+++ b/adder/db/full_adder.map_bb.cdb
diff --git a/adder/db/full_adder.map_bb.hdb b/adder/db/full_adder.map_bb.hdb
new file mode 100644
index 0000000..14e4c28
--- /dev/null
+++ b/adder/db/full_adder.map_bb.hdb
diff --git a/adder/db/full_adder.map_bb.logdb b/adder/db/full_adder.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/db/full_adder.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/db/full_adder.pre_map.hdb b/adder/db/full_adder.pre_map.hdb
new file mode 100644
index 0000000..b45adfd
--- /dev/null
+++ b/adder/db/full_adder.pre_map.hdb
diff --git a/adder/db/full_adder.pti_db_list.ddb b/adder/db/full_adder.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/adder/db/full_adder.pti_db_list.ddb
diff --git a/adder/db/full_adder.root_partition.map.reg_db.cdb b/adder/db/full_adder.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..2b20040
--- /dev/null
+++ b/adder/db/full_adder.root_partition.map.reg_db.cdb
diff --git a/adder/db/full_adder.routing.rdb b/adder/db/full_adder.routing.rdb
new file mode 100644
index 0000000..9c52e8d
--- /dev/null
+++ b/adder/db/full_adder.routing.rdb
diff --git a/adder/db/full_adder.rtlv.hdb b/adder/db/full_adder.rtlv.hdb
new file mode 100644
index 0000000..a13ac8a
--- /dev/null
+++ b/adder/db/full_adder.rtlv.hdb
diff --git a/adder/db/full_adder.rtlv_sg.cdb b/adder/db/full_adder.rtlv_sg.cdb
new file mode 100644
index 0000000..c16a609
--- /dev/null
+++ b/adder/db/full_adder.rtlv_sg.cdb
diff --git a/adder/db/full_adder.rtlv_sg_swap.cdb b/adder/db/full_adder.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..9bd828b
--- /dev/null
+++ b/adder/db/full_adder.rtlv_sg_swap.cdb
diff --git a/adder/db/full_adder.sgdiff.cdb b/adder/db/full_adder.sgdiff.cdb
new file mode 100644
index 0000000..d6ea4b5
--- /dev/null
+++ b/adder/db/full_adder.sgdiff.cdb
diff --git a/adder/db/full_adder.sgdiff.hdb b/adder/db/full_adder.sgdiff.hdb
new file mode 100644
index 0000000..f2fc383
--- /dev/null
+++ b/adder/db/full_adder.sgdiff.hdb
diff --git a/adder/db/full_adder.sld_design_entry.sci b/adder/db/full_adder.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/adder/db/full_adder.sld_design_entry.sci
diff --git a/adder/db/full_adder.sld_design_entry_dsc.sci b/adder/db/full_adder.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/adder/db/full_adder.sld_design_entry_dsc.sci
diff --git a/adder/db/full_adder.smart_action.txt b/adder/db/full_adder.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/adder/db/full_adder.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/adder/db/full_adder.sta.qmsg b/adder/db/full_adder.sta.qmsg
new file mode 100644
index 0000000..bd67e79
--- /dev/null
+++ b/adder/db/full_adder.sta.qmsg
@@ -0,0 +1,48 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747312809 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747312810 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:15:12 2016 " "Processing started: Wed Feb 17 22:15:12 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747312810 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747312810 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta full_adder -c full_adder " "Command: quartus_sta full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747312811 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455747313222 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747313873 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747313954 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747313954 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455747314349 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747314349 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747314350 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747314350 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455747314350 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747314350 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455747314351 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455747314364 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455747314370 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314371 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314387 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314392 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314397 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314401 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747314408 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747314446 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455747314488 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455747314931 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747315002 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747315002 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747315003 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747315003 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315003 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315018 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315027 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315036 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315043 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315048 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747315075 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747315353 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747315353 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747315353 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747315354 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315359 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315366 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315371 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315377 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747315395 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747316139 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747316139 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "519 " "Peak virtual memory: 519 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747316277 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:15:16 2016 " "Processing ended: Wed Feb 17 22:15:16 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747316277 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747316277 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747316277 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747316277 ""}
diff --git a/adder/db/full_adder.sta.rdb b/adder/db/full_adder.sta.rdb
new file mode 100644
index 0000000..23b198d
--- /dev/null
+++ b/adder/db/full_adder.sta.rdb
diff --git a/adder/db/full_adder.sta_cmp.6_slow_1200mv_85c.tdb b/adder/db/full_adder.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..8a4aadc
--- /dev/null
+++ b/adder/db/full_adder.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/adder/db/full_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd b/adder/db/full_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..a413810
--- /dev/null
+++ b/adder/db/full_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
diff --git a/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd b/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
new file mode 100644
index 0000000..a546d32
--- /dev/null
+++ b/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
diff --git a/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd b/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..e9b1d75
--- /dev/null
+++ b/adder/db/full_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
diff --git a/adder/db/full_adder.tis_db_list.ddb b/adder/db/full_adder.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/adder/db/full_adder.tis_db_list.ddb
diff --git a/adder/db/full_adder.tiscmp.fast_1200mv_0c.ddb b/adder/db/full_adder.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..8a7f087
--- /dev/null
+++ b/adder/db/full_adder.tiscmp.fast_1200mv_0c.ddb
diff --git a/adder/db/full_adder.tiscmp.slow_1200mv_0c.ddb b/adder/db/full_adder.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..5d0cb76
--- /dev/null
+++ b/adder/db/full_adder.tiscmp.slow_1200mv_0c.ddb
diff --git a/adder/db/full_adder.tiscmp.slow_1200mv_85c.ddb b/adder/db/full_adder.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..cd1e5c3
--- /dev/null
+++ b/adder/db/full_adder.tiscmp.slow_1200mv_85c.ddb
diff --git a/adder/db/full_adder.tmw_info b/adder/db/full_adder.tmw_info
new file mode 100644
index 0000000..6b1853a
--- /dev/null
+++ b/adder/db/full_adder.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:27
+start_analysis_synthesis:s:00:00:04-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:09-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
+start_eda_netlist_writer:s:00:00:04-start_full_compilation
diff --git a/adder/db/full_adder.vpr.ammdb b/adder/db/full_adder.vpr.ammdb
new file mode 100644
index 0000000..0f002e0
--- /dev/null
+++ b/adder/db/full_adder.vpr.ammdb
diff --git a/adder/db/logic_util_heursitic.dat b/adder/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..1ded2aa
--- /dev/null
+++ b/adder/db/logic_util_heursitic.dat
diff --git a/adder/db/prev_cmp_full_adder.qmsg b/adder/db/prev_cmp_full_adder.qmsg
new file mode 100644
index 0000000..b7ef6fd
--- /dev/null
+++ b/adder/db/prev_cmp_full_adder.qmsg
@@ -0,0 +1,124 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747220639 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:40 2016 " "Processing started: Wed Feb 17 22:13:40 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747221185 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455747221263 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455747221263 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "full_adder " "Elaborating entity \"full_adder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455747221292 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455747221913 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455747222151 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455747222151 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455747222199 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455747222199 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455747222199 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455747222199 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "561 " "Peak virtual memory: 561 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:42 2016 " "Processing ended: Wed Feb 17 22:13:42 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747224308 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747224309 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:43 2016 " "Processing started: Wed Feb 17 22:13:43 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747224309 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455747224309 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455747224310 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455747224597 ""}
+{ "Info" "0" "" "Project  = full_adder" {  } {  } 0 0 "Project  = full_adder" 0 0 "Fitter" 0 0 1455747224598 ""}
+{ "Info" "0" "" "Revision = full_adder" {  } {  } 0 0 "Revision = full_adder" 0 0 "Fitter" 0 0 1455747224598 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455747224695 ""}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "full_adder EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design full_adder" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455747224871 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747224925 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747224925 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455747225031 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455747225056 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747225637 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747225637 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455747225637 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 27 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 29 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455747225639 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455747225640 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "5 5 " "No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SUM " "Pin SUM not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { SUM } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 184 848 1024 200 "SUM" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SUM } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 3 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cout " "Pin Cout not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cout } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 264 896 1072 280 "Cout" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X " "Pin X not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 208 360 528 224 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 4 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y " "Pin Y not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 224 360 528 240 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cin " "Pin Cin not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cin } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 240 360 528 256 "Cin" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cin } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455747225979 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455747226208 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455747226209 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455747226209 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455747226209 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455747226210 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455747226210 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455747226210 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455747226212 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747226212 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747226212 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747226212 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747226213 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455747226213 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455747226213 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455747226213 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455747226213 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "5 unused 2.5V 3 2 0 " "Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 3 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455747226215 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455747226215 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455747226215 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 0 2 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455747226215 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455747226215 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747226221 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455747227476 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747227528 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455747227535 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455747227735 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747227735 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455747229049 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X21_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9" {  } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} 11 0 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455747229654 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455747229654 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747229688 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455747229688 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455747229688 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455747229688 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455747229698 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747229838 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747230025 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747230133 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747230335 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747230763 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455747231303 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "908 " "Peak virtual memory: 908 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:51 2016 " "Processing ended: Wed Feb 17 22:13:51 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455747231770 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455747234295 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747234296 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:54 2016 " "Processing started: Wed Feb 17 22:13:54 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747234296 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455747234296 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455747234297 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455747235443 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455747235657 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:56 2016 " "Processing ended: Wed Feb 17 22:13:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455747236557 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455747237346 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455747239084 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:58 2016 " "Processing started: Wed Feb 17 22:13:58 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta full_adder -c full_adder " "Command: quartus_sta full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455747239280 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747239816 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747239903 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747239903 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455747240351 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747240352 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747240352 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747240353 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455747240353 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747240353 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455747240354 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455747240362 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455747240367 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240368 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240385 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240397 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240401 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240405 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240410 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747240423 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455747240461 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455747241333 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747241396 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747241396 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747241397 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747241397 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241397 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241405 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241410 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241416 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241421 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241425 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747241436 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747241665 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747241666 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747241666 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747241666 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241671 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241676 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241683 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241709 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241729 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747242284 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747242284 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "512 " "Peak virtual memory: 512 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:14:02 2016 " "Processing ended: Wed Feb 17 22:14:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747244542 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:14:04 2016 " "Processing started: Wed Feb 17 22:14:04 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""}
+{ "Error" "EMSG_PDB_READ_PERMISSION_DENIED" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb " "Can't read database file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb" {  } {  } 0 114012 "Can't read database file %1!s!" 0 0 "Quartus II" 0 -1 1455747244960 ""}
+{ "Error" "EMSG_PDB_READ_PERMISSION_DENIED" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb " "Can't read database file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb" {  } {  } 0 114012 "Can't read database file %1!s!" 0 0 "Quartus II" 0 -1 1455747244960 ""}
+{ "Error" "EQNETO_PARTITION_MERGE_NOT_RUN" "full_adder " "Run Partition Merge with top-level entity name \"full_adder\" before running EDA Netlist Writer" {  } {  } 0 199062 "Run Partition Merge with top-level entity name \"%1!s!\" before running EDA Netlist Writer" 0 0 "Quartus II" 0 -1 1455747244960 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "EDA Netlist Writer 3 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 17 22:14:04 2016 " "Processing ended: Wed Feb 17 22:14:04 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 12 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 12 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747245561 ""}
diff --git a/adder/full_adder.bdf b/adder/full_adder.bdf
new file mode 100644
index 0000000..ef43de4
--- /dev/null
+++ b/adder/full_adder.bdf
@@ -0,0 +1,446 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 360 208 528 224)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "X" (rect 5 0 11 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 360 224 528 240)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y" (rect 5 0 14 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 360 240 528 256)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Cin" (rect 5 0 22 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 848 184 1024 200)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "SUM" (rect 90 0 113 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 896 264 1072 280)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "Cout" (rect 90 0 113 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 648 152 712 200)
+	(text "XNOR" (rect 1 0 28 10)(font "Arial" (font_size 6)))
+	(text "inst" (rect 3 37 20 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 8 19 20)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 8 19 20)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 11 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 11 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 56 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 13)(pt 25 13))
+		(line (pt 14 36)(pt 25 36))
+		(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+		(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+		(arc (pt 2 29)(pt 2 19)(rect -19 8 14 41))
+		(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+		(circle (rect 48 20 56 28))
+	)
+)
+(symbol
+	(rect 744 168 808 216)
+	(text "XNOR" (rect 1 0 28 10)(font "Arial" (font_size 6)))
+	(text "inst2" (rect 3 37 26 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 8 19 20)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 8 19 20)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 11 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 11 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 56 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 13)(pt 25 13))
+		(line (pt 14 36)(pt 25 36))
+		(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+		(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+		(arc (pt 2 29)(pt 2 19)(rect -19 8 14 41))
+		(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+		(circle (rect 48 20 56 28))
+	)
+)
+(symbol
+	(rect 808 248 872 296)
+	(text "OR3" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst3" (rect 3 37 26 49)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
+		(line (pt 0 24)(pt 18 24))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 16 16))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
+		(line (pt 49 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 13)(pt 25 13))
+		(line (pt 14 36)(pt 25 36))
+		(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
+		(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
+		(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
+	)
+)
+(symbol
+	(rect 720 232 784 280)
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst4" (rect 3 37 26 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12))
+		(line (pt 14 37)(pt 31 37))
+		(line (pt 14 12)(pt 14 37))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
+	)
+)
+(symbol
+	(rect 640 248 704 296)
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst5" (rect 3 37 26 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12))
+		(line (pt 14 37)(pt 31 37))
+		(line (pt 14 12)(pt 14 37))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
+	)
+)
+(symbol
+	(rect 552 264 616 312)
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst6" (rect 3 37 26 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12))
+		(line (pt 14 37)(pt 31 37))
+		(line (pt 14 12)(pt 14 37))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
+	)
+)
+(connector
+	(pt 712 176)
+	(pt 744 176)
+)
+(connector
+	(pt 744 176)
+	(pt 744 184)
+)
+(connector
+	(pt 784 256)
+	(pt 808 256)
+)
+(connector
+	(pt 808 256)
+	(pt 808 264)
+)
+(connector
+	(pt 808 272)
+	(pt 704 272)
+)
+(connector
+	(pt 616 288)
+	(pt 808 288)
+)
+(connector
+	(pt 808 288)
+	(pt 808 280)
+)
+(connector
+	(pt 720 264)
+	(pt 704 264)
+)
+(connector
+	(pt 704 264)
+	(pt 704 216)
+)
+(connector
+	(pt 640 264)
+	(pt 640 248)
+)
+(connector
+	(pt 640 280)
+	(pt 624 280)
+)
+(connector
+	(pt 624 280)
+	(pt 624 232)
+)
+(connector
+	(pt 552 280)
+	(pt 552 216)
+)
+(connector
+	(pt 552 296)
+	(pt 544 296)
+)
+(connector
+	(pt 544 296)
+	(pt 544 232)
+)
+(connector
+	(text "X" (rect 538 200 543 212)(font "Arial" ))
+	(pt 528 216)
+	(pt 552 216)
+)
+(connector
+	(text "Y" (rect 538 216 546 228)(font "Arial" ))
+	(pt 528 232)
+	(pt 544 232)
+)
+(connector
+	(pt 640 248)
+	(pt 720 248)
+)
+(connector
+	(pt 616 200)
+	(pt 744 200)
+)
+(connector
+	(pt 616 200)
+	(pt 616 248)
+)
+(connector
+	(text "Cin" (rect 538 232 554 244)(font "Arial" ))
+	(pt 528 248)
+	(pt 616 248)
+)
+(connector
+	(pt 616 248)
+	(pt 640 248)
+)
+(connector
+	(pt 648 184)
+	(pt 600 184)
+)
+(connector
+	(pt 600 232)
+	(pt 600 184)
+)
+(connector
+	(pt 544 232)
+	(pt 600 232)
+)
+(connector
+	(pt 600 232)
+	(pt 624 232)
+)
+(connector
+	(pt 648 168)
+	(pt 584 168)
+)
+(connector
+	(pt 584 216)
+	(pt 584 168)
+)
+(connector
+	(pt 552 216)
+	(pt 584 216)
+)
+(connector
+	(pt 584 216)
+	(pt 704 216)
+)
+(connector
+	(text "SUM" (rect 818 176 841 188)(font "Arial" ))
+	(pt 808 192)
+	(pt 848 192)
+)
+(connector
+	(text "Carry" (rect 882 256 910 268)(font "Arial" ))
+	(pt 872 272)
+	(pt 896 272)
+)
+(junction (pt 552 216))
+(junction (pt 544 232))
+(junction (pt 640 248))
+(junction (pt 616 248))
+(junction (pt 600 232))
+(junction (pt 584 216))
diff --git a/adder/full_adder.bsf b/adder/full_adder.bsf
new file mode 100644
index 0000000..d3aa6df
--- /dev/null
+++ b/adder/full_adder.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 112 112)
+	(text "full_adder" (rect 5 0 61 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "X" (rect 0 0 8 14)(font "Arial" (font_size 8)))
+		(text "X" (rect 21 27 29 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "Y" (rect 0 0 9 14)(font "Arial" (font_size 8)))
+		(text "Y" (rect 21 43 30 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Cin" (rect 0 0 17 14)(font "Arial" (font_size 8)))
+		(text "Cin" (rect 21 59 38 73)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "SUM" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "SUM" (rect 50 27 75 41)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 80 32))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "Cout" (rect 50 43 75 57)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 80 48))
+	)
+	(drawing
+		(rectangle (rect 16 16 80 80))
+	)
+)
diff --git a/adder/full_adder.qpf b/adder/full_adder.qpf
new file mode 100644
index 0000000..e04ff52
--- /dev/null
+++ b/adder/full_adder.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:43:52  February 17, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:43:52  February 17, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "full_adder"
diff --git a/adder/full_adder.qsf b/adder/full_adder.qsf
new file mode 100644
index 0000000..01c0578
--- /dev/null
+++ b/adder/full_adder.qsf
@@ -0,0 +1,52 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:43:52  February 17, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		full_adder_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name DEVICE auto
+set_global_assignment -name TOP_LEVEL_ENTITY full_adder
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:43:52  FEBRUARY 17, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE full_adder.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/adder/full_adder.qws b/adder/full_adder.qws
new file mode 100644
index 0000000..76120b3
--- /dev/null
+++ b/adder/full_adder.qws
diff --git a/adder/incremental_db/README b/adder/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/adder/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/adder/incremental_db/compiled_partitions/full_adder.db_info b/adder/incremental_db/compiled_partitions/full_adder.db_info
new file mode 100644
index 0000000..517b444
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Feb 17 22:13:41 2016
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.ammdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.ammdb
new file mode 100644
index 0000000..37b96bc
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.ammdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.cdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.cdb
new file mode 100644
index 0000000..f68d640
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.cdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.dfp b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.dfp
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.hdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.hdb
new file mode 100644
index 0000000..4531c66
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.hdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.logdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.rcfdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..5113c2e
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.cmp.rcfdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.cdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.cdb
new file mode 100644
index 0000000..e620b61
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.cdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.dpi b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.dpi
new file mode 100644
index 0000000..374b4e9
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.dpi
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.cdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..6b71689
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.cdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hb_info b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hb_info
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..1a5c690
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.hdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.sig b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..91e140d
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+6d99a1516c2e2beefe1f386eab1dd580
\ No newline at end of file
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hdb b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hdb
new file mode 100644
index 0000000..5ee9717
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.hdb
diff --git a/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.kpt b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.kpt
new file mode 100644
index 0000000..3367e3e
--- /dev/null
+++ b/adder/incremental_db/compiled_partitions/full_adder.root_partition.map.kpt
diff --git a/adder/output_files/full_adder.asm.rpt b/adder/output_files/full_adder.asm.rpt
new file mode 100644
index 0000000..1790a63
--- /dev/null
+++ b/adder/output_files/full_adder.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for full_adder
+Wed Feb 17 22:15:10 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Feb 17 22:15:10 2016 ;
+; Revision Name         ; full_adder                            ;
+; Top-level Entity Name ; full_adder                            ;
+; Family                ; Cyclone IV GX                         ;
+; Device                ; EP4CGX15BF14C6                        ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                         ;
++---------------------------------------------------------------------------------------------------+
+; File Name                                                                                         ;
++---------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.sof ;
++---------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.sof ;
++----------------+------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                    ;
++----------------+------------------------------------------------------------------------------------------------------------+
+; Device         ; EP4CGX15BF14C6                                                                                             ;
+; JTAG usercode  ; 0x000BBC25                                                                                                 ;
+; Checksum       ; 0x000BBC25                                                                                                 ;
++----------------+------------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Feb 17 22:15:08 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 518 megabytes
+    Info: Processing ended: Wed Feb 17 22:15:10 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/adder/output_files/full_adder.done b/adder/output_files/full_adder.done
new file mode 100644
index 0000000..14204d0
--- /dev/null
+++ b/adder/output_files/full_adder.done
@@ -0,0 +1 @@
+Wed Feb 17 22:15:20 2016
diff --git a/adder/output_files/full_adder.eda.rpt b/adder/output_files/full_adder.eda.rpt
new file mode 100644
index 0000000..561e7b6
--- /dev/null
+++ b/adder/output_files/full_adder.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for full_adder
+Wed Feb 17 22:15:19 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Feb 17 22:15:19 2016 ;
+; Revision Name             ; full_adder                            ;
+; Top-level Entity Name     ; full_adder                            ;
+; Family                    ; Cyclone IV GX                         ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                                      ;
++---------------------------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                                                 ;
++---------------------------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder.vho                        ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/full_adder_vhd.sdo                    ;
++---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Feb 17 22:15:18 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder
+Info (204019): Generated file full_adder_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file full_adder_vhd.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 477 megabytes
+    Info: Processing ended: Wed Feb 17 22:15:20 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/adder/output_files/full_adder.fit.rpt b/adder/output_files/full_adder.fit.rpt
new file mode 100644
index 0000000..003d8f3
--- /dev/null
+++ b/adder/output_files/full_adder.fit.rpt
@@ -0,0 +1,893 @@
+Fitter report for full_adder
+Wed Feb 17 22:15:05 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Routing Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. I/O Rules Summary
+ 27. I/O Rules Details
+ 28. I/O Rules Matrix
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Wed Feb 17 22:15:05 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; full_adder                                 ;
+; Top-level Entity Name              ; full_adder                                 ;
+; Family                             ; Cyclone IV GX                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 2 / 14,400 ( < 1 % )                       ;
+;     Total combinational functions  ; 2 / 14,400 ( < 1 % )                       ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 5 / 81 ( 6 % )                             ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; auto                                  ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Generate GXB Reconfig MIF                                                  ; Off                                   ; Off                                   ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_40MHz                            ; FREQ_40MHz                            ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; SUM      ; Incomplete set of assignments ;
+; Cout     ; Incomplete set of assignments ;
+; X        ; Incomplete set of assignments ;
+; Y        ; Incomplete set of assignments ;
+; Cin      ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 23 ) ; 0.00 % ( 0 / 23 )          ; 0.00 % ( 0 / 23 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 23 ) ; 0.00 % ( 0 / 23 )          ; 0.00 % ( 0 / 23 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 13 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.pin.
+
+
++--------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                      ;
++---------------------------------------------+----------------------+
+; Resource                                    ; Usage                ;
++---------------------------------------------+----------------------+
+; Total logic elements                        ; 2 / 14,400 ( < 1 % ) ;
+;     -- Combinational with no register       ; 2                    ;
+;     -- Register only                        ; 0                    ;
+;     -- Combinational with a register        ; 0                    ;
+;                                             ;                      ;
+; Logic element usage by number of LUT inputs ;                      ;
+;     -- 4 input functions                    ; 0                    ;
+;     -- 3 input functions                    ; 2                    ;
+;     -- <=2 input functions                  ; 0                    ;
+;     -- Register only                        ; 0                    ;
+;                                             ;                      ;
+; Logic elements by mode                      ;                      ;
+;     -- normal mode                          ; 2                    ;
+;     -- arithmetic mode                      ; 0                    ;
+;                                             ;                      ;
+; Total registers*                            ; 0 / 14,733 ( 0 % )   ;
+;     -- Dedicated logic registers            ; 0 / 14,400 ( 0 % )   ;
+;     -- I/O registers                        ; 0 / 333 ( 0 % )      ;
+;                                             ;                      ;
+; Total LABs:  partially or completely used   ; 1 / 900 ( < 1 % )    ;
+; Virtual pins                                ; 0                    ;
+; I/O pins                                    ; 5 / 81 ( 6 % )       ;
+;     -- Clock pins                           ; 0 / 6 ( 0 % )        ;
+;     -- Dedicated input pins                 ; 0 / 12 ( 0 % )       ;
+;                                             ;                      ;
+; Global signals                              ; 0                    ;
+; M9Ks                                        ; 0 / 60 ( 0 % )       ;
+; Total block memory bits                     ; 0 / 552,960 ( 0 % )  ;
+; Total block memory implementation bits      ; 0 / 552,960 ( 0 % )  ;
+; PLLs                                        ; 0 / 3 ( 0 % )        ;
+; Global clocks                               ; 0 / 20 ( 0 % )       ;
+; JTAGs                                       ; 0 / 1 ( 0 % )        ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
+; GXB Receiver channel PCSs                   ; 0 / 2 ( 0 % )        ;
+; GXB Receiver channel PMAs                   ; 0 / 2 ( 0 % )        ;
+; GXB Transmitter channel PCSs                ; 0 / 2 ( 0 % )        ;
+; GXB Transmitter channel PMAs                ; 0 / 2 ( 0 % )        ;
+; Impedance control blocks                    ; 0 / 3 ( 0 % )        ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
+; Maximum fan-out                             ; 2                    ;
+; Highest non-global fan-out                  ; 2                    ;
+; Total fan-out                               ; 18                   ;
+; Average fan-out                             ; 0.82                 ;
++---------------------------------------------+----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                        ;
++---------------------------------------------+---------------------+--------------------------------+
+; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
++---------------------------------------------+---------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                 ; Low                            ;
+;                                             ;                     ;                                ;
+; Total logic elements                        ; 2 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % )              ;
+;     -- Combinational with no register       ; 2                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;     -- Combinational with a register        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic element usage by number of LUT inputs ;                     ;                                ;
+;     -- 4 input functions                    ; 0                   ; 0                              ;
+;     -- 3 input functions                    ; 2                   ; 0                              ;
+;     -- <=2 input functions                  ; 0                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic elements by mode                      ;                     ;                                ;
+;     -- normal mode                          ; 2                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Total registers                             ; 0                   ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 14400 ( 0 % )   ; 0 / 14400 ( 0 % )              ;
+;     -- I/O registers                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Total LABs:  partially or completely used   ; 1 / 900 ( < 1 % )   ; 0 / 900 ( 0 % )                ;
+;                                             ;                     ;                                ;
+; Virtual pins                                ; 0                   ; 0                              ;
+; I/O pins                                    ; 5                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0                   ; 0                              ;
+; Total memory bits                           ; 0                   ; 0                              ;
+; Total RAM block bits                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Connections                                 ;                     ;                                ;
+;     -- Input Connections                    ; 0                   ; 0                              ;
+;     -- Registered Input Connections         ; 0                   ; 0                              ;
+;     -- Output Connections                   ; 0                   ; 0                              ;
+;     -- Registered Output Connections        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Internal Connections                        ;                     ;                                ;
+;     -- Total Connections                    ; 13                  ; 5                              ;
+;     -- Registered Connections               ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; External Connections                        ;                     ;                                ;
+;     -- Top                                  ; 0                   ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Partition Interface                         ;                     ;                                ;
+;     -- Input Ports                          ; 3                   ; 0                              ;
+;     -- Output Ports                         ; 2                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Registered Ports                            ;                     ;                                ;
+;     -- Registered Input Ports               ; 0                   ; 0                              ;
+;     -- Registered Output Ports              ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Port Connectivity                           ;                     ;                                ;
+;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
++---------------------------------------------+---------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; Cin  ; N10   ; 4        ; 26           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X    ; M4    ; 3        ; 8            ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y    ; L4    ; 3        ; 8            ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Cout ; L11   ; 4        ; 31           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; SUM  ; M6    ; 3        ; 12           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                            ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; Location ; Pin Name              ; Reserved As              ; User Signal Name ; Pin Type                  ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; L3       ; MSEL2                 ; -                        ; -                ; Dedicated Programming Pin ;
+; N3       ; MSEL1                 ; -                        ; -                ; Dedicated Programming Pin ;
+; K5       ; MSEL0                 ; -                        ; -                ; Dedicated Programming Pin ;
+; J5       ; CONF_DONE             ; -                        ; -                ; Dedicated Programming Pin ;
+; K6       ; nSTATUS               ; -                        ; -                ; Dedicated Programming Pin ;
+; N5       ; DIFFIO_B1n, NCEO      ; Use as programming pin   ; ~ALTERA_NCEO~    ; Dual Purpose Pin          ;
+; M6       ; DIFFIO_B2p, INIT_DONE ; Use as regular IO        ; SUM              ; Dual Purpose Pin          ;
+; A5       ; DATA0                 ; As input tri-stated      ; ~ALTERA_DATA0~   ; Dual Purpose Pin          ;
+; B5       ; ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO~    ; Dual Purpose Pin          ;
+; C5       ; NCSO                  ; As input tri-stated      ; ~ALTERA_NCSO~    ; Dual Purpose Pin          ;
+; A4       ; DCLK                  ; As output driving ground ; ~ALTERA_DCLK~    ; Dual Purpose Pin          ;
+; D5       ; nCONFIG               ; -                        ; -                ; Dedicated Programming Pin ;
+; C4       ; nCE                   ; -                        ; -                ; Dedicated Programming Pin ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------+
+; I/O Bank Usage                                                               ;
++----------+-----------------+---------------+--------------+------------------+
+; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ;
++----------+-----------------+---------------+--------------+------------------+
+; QL0      ; 0 / 8 ( 0 % )   ; --            ; --           ; --               ;
+; 3        ; 4 / 8 ( 50 % )  ; 2.5V          ; --           ; --               ;
+; 3A       ; 0 / 2 ( 0 % )   ; --            ; --           ; 2.5V             ;
+; 4        ; 2 / 14 ( 14 % ) ; 2.5V          ; --           ; --               ;
+; 5        ; 0 / 12 ( 0 % )  ; 2.5V          ; --           ; --               ;
+; 6        ; 0 / 12 ( 0 % )  ; 2.5V          ; --           ; --               ;
+; 7        ; 0 / 14 ( 0 % )  ; 2.5V          ; --           ; --               ;
+; 8A       ; 0 / 2 ( 0 % )   ; --            ; --           ; 2.5V             ;
+; 8        ; 0 / 5 ( 0 % )   ; 2.5V          ; --           ; --               ;
+; 9        ; 4 / 4 ( 100 % ) ; 2.5V          ; --           ; --               ;
++----------+-----------------+---------------+--------------+------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                               ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                   ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ; 99         ; 9        ; #TDO                                             ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ; 98         ; 9        ; #TMS                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A3       ; 96         ; 9        ; #TDI                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A4       ; 93         ; 9        ; ~ALTERA_DCLK~                                    ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A5       ; 90         ; 9        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A6       ; 89         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 87         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 88         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 81         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A10      ; 82         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A11      ; 79         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A12      ; 80         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A13      ; 73         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 97         ; 9        ; #TCK                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; B4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B5       ; 91         ; 9        ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; B6       ; 86         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B8       ; 77         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B10      ; 76         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B11      ; 75         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B13      ; 74         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C1       ; 9          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C2       ; 8          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C3       ;            ; 9        ; VCCIO9                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C4       ; 95         ; 9        ; ^nCE                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C5       ; 92         ; 9        ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; C6       ; 85         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C7       ;            ; 8        ; VCCIO8                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C8       ; 78         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C10      ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C11      ; 69         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C12      ; 70         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C13      ; 71         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D3       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ; 94         ; 9        ; ^nCONFIG                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; D6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D7       ;            ; 8A       ; VCC_CLKIN8A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 65         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D11      ; 68         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D12      ; 67         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D13      ; 72         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E1       ; 11         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E2       ; 10         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 83         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E7       ; 84         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E10      ; 66         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E13      ; 63         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; F1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F9       ; 64         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F10      ; 62         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F11      ; 61         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F12      ; 58         ; 6        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; F13      ; 57         ; 6        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G1       ; 13         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G2       ; 12         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G3       ;            ; --       ; VCCH_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G6       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ; 60         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G10      ; 59         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G13      ; 55         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H10      ; 52         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H12      ; 51         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H13      ; 56         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J1       ; 15         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J2       ; 14         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J3       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J4       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J5       ; 19         ; 3        ; ^CONF_DONE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 29         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J7       ; 30         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J13      ; 53         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 18         ; 3        ; ^MSEL0                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 20         ; 3        ; ^nSTATUS                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ;            ; 3A       ; VCC_CLKIN3A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K8       ; 35         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; K9       ; 36         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K10      ; 43         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K11      ; 48         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K12      ; 47         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K13      ; 54         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L1       ;            ;          ; RREF                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 16         ; 3        ; ^MSEL2                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 21         ; 3        ; Y                                                ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L5       ; 27         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L6       ;            ; 3        ; VCCIO3                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L7       ; 28         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; L8       ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L9       ; 37         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L10      ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L11      ; 44         ; 4        ; Cout                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L12      ; 50         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L13      ; 49         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M2       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; M3       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M4       ; 22         ; 3        ; X                                                ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 25         ; 3        ; SUM                                              ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M7       ; 31         ; 4        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; M8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M9       ; 38         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M10      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ; 41         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ; 46         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N2       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N3       ; 17         ; 3        ; ^MSEL1                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ; 23         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N5       ; 24         ; 3        ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN       ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N6       ; 26         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N7       ; 32         ; 4        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; N8       ; 33         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N9       ; 34         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N10      ; 39         ; 4        ; Cin                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N11      ; 40         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N12      ; 42         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N13      ; 45         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                       ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |full_adder                ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 5    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |full_adder         ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                  ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; SUM  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Cout ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; X    ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y    ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Cin  ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; X                   ;                   ;         ;
+;      - inst2~0      ; 0                 ; 6       ;
+;      - inst3~0      ; 0                 ; 6       ;
+; Y                   ;                   ;         ;
+;      - inst2~0      ; 0                 ; 6       ;
+;      - inst3~0      ; 0                 ; 6       ;
+; Cin                 ;                   ;         ;
+;      - inst2~0      ; 0                 ; 6       ;
+;      - inst3~0      ; 0                 ; 6       ;
++---------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------+---------------------+
+; Name      ; Fan-Out             ;
++-----------+---------------------+
+; Cin~input ; 2                   ;
+; Y~input   ; 2                   ;
+; X~input   ; 2                   ;
+; inst3~0   ; 1                   ;
+; inst2~0   ; 1                   ;
++-----------+---------------------+
+
+
++----------------------------------------------------------+
+; Routing Usage Summary                                    ;
++-----------------------------------+----------------------+
+; Routing Resource Type             ; Usage                ;
++-----------------------------------+----------------------+
+; Block interconnects               ; 5 / 42,960 ( < 1 % ) ;
+; C16 interconnects                 ; 1 / 1,518 ( < 1 % )  ;
+; C4 interconnects                  ; 4 / 26,928 ( < 1 % ) ;
+; Direct links                      ; 0 / 42,960 ( 0 % )   ;
+; GXB block output buffers          ; 0 / 1,200 ( 0 % )    ;
+; Global clocks                     ; 0 / 20 ( 0 % )       ;
+; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % )        ;
+; Interquad TXRX Clocks             ; 0 / 8 ( 0 % )        ;
+; Interquad TXRX PCSRX outputs      ; 0 / 4 ( 0 % )        ;
+; Interquad TXRX PCSTX outputs      ; 0 / 4 ( 0 % )        ;
+; Local interconnects               ; 0 / 14,400 ( 0 % )   ;
+; R24 interconnects                 ; 2 / 1,710 ( < 1 % )  ;
+; R4 interconnects                  ; 7 / 37,740 ( < 1 % ) ;
++-----------------------------------+----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements                                                       ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 2.00) ; Number of LABs  (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1                                          ; 0                           ;
+; 2                                          ; 1                           ;
+; 3                                          ; 0                           ;
+; 4                                          ; 0                           ;
+; 5                                          ; 0                           ;
+; 6                                          ; 0                           ;
+; 7                                          ; 0                           ;
+; 8                                          ; 0                           ;
+; 9                                          ; 0                           ;
+; 10                                         ; 0                           ;
+; 11                                         ; 0                           ;
+; 12                                         ; 0                           ;
+; 13                                         ; 0                           ;
+; 14                                         ; 0                           ;
+; 15                                         ; 0                           ;
+; 16                                         ; 0                           ;
++--------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Signals Sourced                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 2.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 2.00) ; Number of LABs  (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 3.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 5         ; 0            ; 0            ; 5         ; 5         ; 0            ; 2            ; 0            ; 0            ; 3            ; 0            ; 2            ; 3            ; 0            ; 0            ; 0            ; 2            ; 0            ; 0            ; 0            ; 0            ; 0            ; 5         ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 5            ; 5            ; 5            ; 5            ; 5            ; 0         ; 5            ; 5            ; 0         ; 0         ; 5            ; 3            ; 5            ; 5            ; 2            ; 5            ; 3            ; 2            ; 5            ; 5            ; 5            ; 3            ; 5            ; 5            ; 5            ; 5            ; 5            ; 0         ; 5            ; 5            ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; SUM                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Cout               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y                  ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Cin                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                         ;
++------------------------------------------------------------------+----------------------------+
+; Option                                                           ; Setting                    ;
++------------------------------------------------------------------+----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                        ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                        ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                        ;
+; Enable INIT_DONE output                                          ; Off                        ;
+; Configuration scheme                                             ; Active Serial              ;
+; Error detection CRC                                              ; Off                        ;
+; Enable input tri-state on active configuration pins in user mode ; Off                        ;
+; Active Serial clock source                                       ; 40 MHz Internal Oscillator ;
+; Configuration Voltage Level                                      ; Auto                       ;
+; Force Configuration Voltage Level                                ; Off                        ;
+; nCEO                                                             ; As output driving ground   ;
+; Data[0]                                                          ; As input tri-stated        ;
+; Data[1]/ASDO                                                     ; As input tri-stated        ;
+; Data[7..2]                                                       ; Unreserved                 ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated        ;
+; DCLK                                                             ; As output driving ground   ;
+; Base pin-out file on sameframe device                            ; Off                        ;
++------------------------------------------------------------------+----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119004): Automatically selected device EP4CGX15BF14C6 for design full_adder
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CGX30BF14C6 is compatible
+    Info (176445): Device EP4CGX22BF14C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5
+    Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5
+    Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 5 pins of 5 total pins
+    Info (169086): Pin SUM not assigned to an exact location on the device
+    Info (169086): Pin Cout not assigned to an exact location on the device
+    Info (169086): Pin X not assigned to an exact location on the device
+    Info (169086): Pin Y not assigned to an exact location on the device
+    Info (169086): Pin Cin not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 3 input, 2 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available
+        Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available
+        Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Info (144001): Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 920 megabytes
+    Info: Processing ended: Wed Feb 17 22:15:06 2016
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:07
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg.
+
+
diff --git a/adder/output_files/full_adder.fit.smsg b/adder/output_files/full_adder.fit.smsg
new file mode 100644
index 0000000..ed080d6
--- /dev/null
+++ b/adder/output_files/full_adder.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/adder/output_files/full_adder.fit.summary b/adder/output_files/full_adder.fit.summary
new file mode 100644
index 0000000..dbb079b
--- /dev/null
+++ b/adder/output_files/full_adder.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Wed Feb 17 22:15:05 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : full_adder
+Top-level Entity Name : full_adder
+Family : Cyclone IV GX
+Device : EP4CGX15BF14C6
+Timing Models : Final
+Total logic elements : 2 / 14,400 ( < 1 % )
+    Total combinational functions : 2 / 14,400 ( < 1 % )
+    Dedicated logic registers : 0 / 14,400 ( 0 % )
+Total registers : 0
+Total pins : 5 / 81 ( 6 % )
+Total virtual pins : 0
+Total memory bits : 0 / 552,960 ( 0 % )
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0 / 2 ( 0 % )
+Total GXB Receiver Channel PMA : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PCS : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PMA : 0 / 2 ( 0 % )
+Total PLLs : 0 / 3 ( 0 % )
diff --git a/adder/output_files/full_adder.flow.rpt b/adder/output_files/full_adder.flow.rpt
new file mode 100644
index 0000000..36a4f30
--- /dev/null
+++ b/adder/output_files/full_adder.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for full_adder
+Wed Feb 17 22:15:19 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Wed Feb 17 22:15:19 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; full_adder                                 ;
+; Top-level Entity Name              ; full_adder                                 ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 2 / 14,400 ( < 1 % )                       ;
+;     Total combinational functions  ; 2 / 14,400 ( < 1 % )                       ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 5 / 81 ( 6 % )                             ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/17/2016 22:14:55 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; full_adder          ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145574729504128 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 546 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:07     ; 1.0                     ; 920 MB              ; 00:00:06                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 510 MB              ; 00:00:02                           ;
+; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 519 MB              ; 00:00:03                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 465 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:16     ; --                      ; --                  ; 00:00:13                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder
+quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder
+quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder
+quartus_sta full_adder -c full_adder
+quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder
+
+
+
diff --git a/adder/output_files/full_adder.jdi b/adder/output_files/full_adder.jdi
new file mode 100644
index 0000000..1ab87a6
--- /dev/null
+++ b/adder/output_files/full_adder.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="c7f25cea94aeb6dd9c30"/>
+  </project>
+  <file_info>
+    <file device="EP4CGX15BF14C6" path="full_adder.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/adder/output_files/full_adder.map.rpt b/adder/output_files/full_adder.map.rpt
new file mode 100644
index 0000000..4d81543
--- /dev/null
+++ b/adder/output_files/full_adder.map.rpt
@@ -0,0 +1,244 @@
+Analysis & Synthesis report for full_adder
+Wed Feb 17 22:14:56 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Wed Feb 17 22:14:56 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; full_adder                                 ;
+; Top-level Entity Name              ; full_adder                                 ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 2                                          ;
+;     Total combinational functions  ; 2                                          ;
+;     Dedicated logic registers      ; 0                                          ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 5                                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0                                          ;
+; Total GXB Receiver Channel PMA     ; 0                                          ;
+; Total GXB Transmitter Channel PCS  ; 0                                          ;
+; Total GXB Transmitter Channel PMA  ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Top-level entity name                                                      ; full_adder         ; full_adder         ;
+; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                   ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                         ; Library ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+---------+
+; full_adder.bdf                   ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++--------------------------+------------------+
+; Resource                 ; Usage            ;
++--------------------------+------------------+
+; I/O pins                 ; 5                ;
+; DSP block 9-bit elements ; 0                ;
+; Maximum fan-out node     ; X~input          ;
+; Maximum fan-out          ; 2                ;
+; Total fan-out            ; 13               ;
+; Average fan-out          ; 1.08             ;
++--------------------------+------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+; |full_adder                ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 5    ; 0            ; |full_adder         ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Feb 17 22:14:54 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12127): Elaborating entity "full_adder" for the top level hierarchy
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 7 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 3 input pins
+    Info (21059): Implemented 2 output pins
+    Info (21061): Implemented 2 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 557 megabytes
+    Info: Processing ended: Wed Feb 17 22:14:56 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/adder/output_files/full_adder.map.summary b/adder/output_files/full_adder.map.summary
new file mode 100644
index 0000000..7028b90
--- /dev/null
+++ b/adder/output_files/full_adder.map.summary
@@ -0,0 +1,18 @@
+Analysis & Synthesis Status : Successful - Wed Feb 17 22:14:56 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : full_adder
+Top-level Entity Name : full_adder
+Family : Cyclone IV GX
+Total logic elements : 2
+    Total combinational functions : 2
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 5
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0
+Total GXB Receiver Channel PMA : 0
+Total GXB Transmitter Channel PCS : 0
+Total GXB Transmitter Channel PMA : 0
+Total PLLs : 0
diff --git a/adder/output_files/full_adder.pin b/adder/output_files/full_adder.pin
new file mode 100644
index 0000000..097368c
--- /dev/null
+++ b/adder/output_files/full_adder.pin
@@ -0,0 +1,246 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ --					Bank 9:	2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --           	    either individually through a 10k Ohm resistor to GND or tie all pins
+ --           	    together and connect through a single 10k Ohm resistor to GND.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_GND*      : Unused GXB Receiver or dedicated reference clock pin. This pin
+ --                 must be connected to GXB_GND through a 10k Ohm resistor.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "full_adder"  ASSIGNED TO AN: EP4CGX15BF14C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+TDO                          : A1        : output :                   :         : 9         :                
+TMS                          : A2        : input  :                   :         : 9         :                
+TDI                          : A3        : input  :                   :         : 9         :                
+~ALTERA_DCLK~                : A4        : output : 2.5 V             :         : 9         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : A5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+GND+                         : A10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+GND                          : B1        : gnd    :                   :         :           :                
+GND                          : B2        : gnd    :                   :         :           :                
+TCK                          : B3        : input  :                   :         : 9         :                
+GND                          : B4        : gnd    :                   :         :           :                
+~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : B5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+GND                          : B7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 7         :                
+GND                          : B9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7         :                
+GND                          : B12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+GXB_NC                       : C1        :        :                   :         : QL0       :                
+GXB_NC                       : C2        :        :                   :         : QL0       :                
+VCCIO9                       : C3        : power  :                   : 2.5V    : 9         :                
+nCE                          : C4        :        :                   :         : 9         :                
+~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 7         :                
+VCCIO7                       : C9        : power  :                   : 2.5V    : 7         :                
+VCCIO7                       : C10       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : D1        : gnd    :                   :         :           :                
+GND                          : D2        : gnd    :                   :         :           :                
+VCCD_PLL                     : D3        : power  :                   : 1.2V    :           :                
+VCCA                         : D4        : power  :                   : 2.5V    :           :                
+nCONFIG                      : D5        :        :                   :         : 9         :                
+GND                          : D6        : gnd    :                   :         :           :                
+VCC_CLKIN8A                  : D7        : power  :                   : 2.5V    : 8A        :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCA                         : D9        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+GXB_GND*                     : E1        :        :                   :         : QL0       :                
+GXB_GND*                     : E2        :        :                   :         : QL0       :                
+GND                          : E3        : gnd    :                   :         :           :                
+VCCINT                       : E4        : power  :                   : 1.2V    :           :                
+GND                          : E5        : gnd    :                   :         :           :                
+GXB_GND*                     : E6        :        :                   :         : 8A        :                
+GXB_GND*                     : E7        :        :                   :         : 8A        :                
+VCCINT                       : E8        : power  :                   : 1.2V    :           :                
+GND                          : E9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 6         :                
+VCCIO6                       : E11       : power  :                   : 2.5V    : 6         :                
+GND                          : E12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 6         :                
+GND                          : F1        : gnd    :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+VCCL_GXB                     : F3        : power  :                   : 1.2V    :           :                
+GND                          : F4        : gnd    :                   :         :           :                
+VCCINT                       : F5        : power  :                   : 1.2V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+GND                          : F8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 6         :                
+GND+                         : F12       :        :                   :         : 6         :                
+GND+                         : F13       :        :                   :         : 6         :                
+GXB_NC                       : G1        :        :                   :         : QL0       :                
+GXB_NC                       : G2        :        :                   :         : QL0       :                
+VCCH_GXB                     : G3        : power  :                   : 2.5V    :           :                
+VCCINT                       : G4        : power  :                   : 1.2V    :           :                
+GND                          : G5        : gnd    :                   :         :           :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+GND                          : G7        : gnd    :                   :         :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 6         :                
+VCCIO6                       : G11       : power  :                   : 2.5V    : 6         :                
+GND                          : G12       : gnd    :                   :         :           :                
+GND+                         : G13       :        :                   :         : 5         :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+VCCL_GXB                     : H3        : power  :                   : 1.2V    :           :                
+GND                          : H4        : gnd    :                   :         :           :                
+VCCINT                       : H5        : power  :                   : 1.2V    :           :                
+GND                          : H6        : gnd    :                   :         :           :                
+VCCINT                       : H7        : power  :                   : 1.2V    :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+VCCA                         : H9        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 5         :                
+VCCIO5                       : H11       : power  :                   : 2.5V    : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 5         :                
+GND+                         : H13       :        :                   :         : 5         :                
+GXB_GND*                     : J1        :        :                   :         : QL0       :                
+GXB_GND*                     : J2        :        :                   :         : QL0       :                
+VCCA_GXB                     : J3        : power  :                   : 2.5V    :           :                
+VCCD_PLL                     : J4        : power  :                   : 1.2V    :           :                
+CONF_DONE                    : J5        :        :                   :         : 3         :                
+GXB_GND*                     : J6        :        :                   :         : 3A        :                
+GXB_GND*                     : J7        :        :                   :         : 3A        :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCD_PLL                     : J10       : power  :                   : 1.2V    :           :                
+VCCIO5                       : J11       : power  :                   : 2.5V    : 5         :                
+GND                          : J12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 5         :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+GND                          : K3        : gnd    :                   :         :           :                
+VCCA                         : K4        : power  :                   : 2.5V    :           :                
+MSEL0                        : K5        :        :                   :         : 3         :                
+nSTATUS                      : K6        :        :                   :         : 3         :                
+VCC_CLKIN3A                  : K7        : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K10       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K11       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K13       :        :                   :         : 5         :                
+RREF                         : L1        :        :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+MSEL2                        : L3        :        :                   :         : 3         :                
+Y                            : L4        : input  : 2.5 V             :         : 3         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L5        :        :                   :         : 3         :                
+VCCIO3                       : L6        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 3         :                
+VCCIO4                       : L8        : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L9        :        :                   :         : 4         :                
+VCCIO4                       : L10       : power  :                   : 2.5V    : 4         :                
+Cout                         : L11       : output : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L12       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L13       :        :                   :         : 5         :                
+GND                          : M1        : gnd    :                   :         :           :                
+VCCA_GXB                     : M2        : power  :                   : 2.5V    :           :                
+NC                           : M3        :        :                   :         :           :                
+X                            : M4        : input  : 2.5 V             :         : 3         : N              
+GND                          : M5        : gnd    :                   :         :           :                
+SUM                          : M6        : output : 2.5 V             :         : 3         : N              
+GND+                         : M7        :        :                   :         : 4         :                
+GND                          : M8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 4         :                
+GND                          : M10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M11       :        :                   :         : 4         :                
+GND                          : M12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M13       :        :                   :         : 5         :                
+VCCL_GXB                     : N1        : power  :                   : 1.2V    :           :                
+NC                           : N2        :        :                   :         :           :                
+MSEL1                        : N3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N4        :        :                   :         : 3         :                
+~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : N5        : output : 2.5 V             :         : 3         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+GND+                         : N7        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 4         :                
+Cin                          : N10       : input  : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N13       :        :                   :         : 5         :                
diff --git a/adder/output_files/full_adder.sof b/adder/output_files/full_adder.sof
new file mode 100644
index 0000000..09980a8
--- /dev/null
+++ b/adder/output_files/full_adder.sof
diff --git a/adder/output_files/full_adder.sta.rpt b/adder/output_files/full_adder.sta.rpt
new file mode 100644
index 0000000..f237c3c
--- /dev/null
+++ b/adder/output_files/full_adder.sta.rpt
@@ -0,0 +1,505 @@
+TimeQuest Timing Analyzer report for full_adder
+Wed Feb 17 22:15:16 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Propagation Delay
+ 34. Minimum Propagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 38. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 39. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 40. Clock Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths
+ 44. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; full_adder                                         ;
+; Device Family      ; Cyclone IV GX                                      ;
+; Device Name        ; EP4CGX15BF14C6                                     ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 8.391 ;       ;       ; 8.732 ;
+; Cin        ; SUM         ; 7.822 ; 7.666 ; 8.288 ; 8.164 ;
+; X          ; Cout        ; 8.048 ;       ;       ; 8.353 ;
+; X          ; SUM         ; 7.483 ; 7.353 ; 7.927 ; 7.794 ;
+; Y          ; Cout        ; 7.770 ;       ;       ; 8.036 ;
+; Y          ; SUM         ; 7.192 ; 7.038 ; 7.621 ; 7.458 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 8.099 ;       ;       ; 8.430 ;
+; Cin        ; SUM         ; 7.557 ; 7.403 ; 8.012 ; 7.889 ;
+; X          ; Cout        ; 7.721 ;       ;       ; 8.010 ;
+; X          ; SUM         ; 7.171 ; 7.046 ; 7.614 ; 7.452 ;
+; Y          ; Cout        ; 7.505 ;       ;       ; 7.763 ;
+; Y          ; SUM         ; 6.955 ; 6.803 ; 7.373 ; 7.212 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 7.460 ;       ;       ; 7.666 ;
+; Cin        ; SUM         ; 6.958 ; 6.763 ; 7.320 ; 7.154 ;
+; X          ; Cout        ; 7.139 ;       ;       ; 7.325 ;
+; X          ; SUM         ; 6.638 ; 6.467 ; 6.994 ; 6.819 ;
+; Y          ; Cout        ; 6.885 ;       ;       ; 7.044 ;
+; Y          ; SUM         ; 6.374 ; 6.181 ; 6.723 ; 6.522 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 7.198 ;       ;       ; 7.401 ;
+; Cin        ; SUM         ; 6.721 ; 6.530 ; 7.076 ; 6.913 ;
+; X          ; Cout        ; 6.844 ;       ;       ; 7.021 ;
+; X          ; SUM         ; 6.358 ; 6.197 ; 6.713 ; 6.517 ;
+; Y          ; Cout        ; 6.648 ;       ;       ; 6.805 ;
+; Y          ; SUM         ; 6.162 ; 5.973 ; 6.502 ; 6.307 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 4.812 ;       ;       ; 5.483 ;
+; Cin        ; SUM         ; 4.496 ; 4.512 ; 5.107 ; 5.141 ;
+; X          ; Cout        ; 4.631 ;       ;       ; 5.247 ;
+; X          ; SUM         ; 4.312 ; 4.341 ; 4.886 ; 4.906 ;
+; Y          ; Cout        ; 4.475 ;       ;       ; 5.067 ;
+; Y          ; SUM         ; 4.150 ; 4.169 ; 4.703 ; 4.715 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 4.643 ;       ;       ; 5.302 ;
+; Cin        ; SUM         ; 4.342 ; 4.356 ; 4.943 ; 4.977 ;
+; X          ; Cout        ; 4.441 ;       ;       ; 5.043 ;
+; X          ; SUM         ; 4.131 ; 4.157 ; 4.698 ; 4.706 ;
+; Y          ; Cout        ; 4.319 ;       ;       ; 4.902 ;
+; Y          ; SUM         ; 4.009 ; 4.028 ; 4.556 ; 4.568 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 8.391 ;       ;       ; 8.732 ;
+; Cin        ; SUM         ; 7.822 ; 7.666 ; 8.288 ; 8.164 ;
+; X          ; Cout        ; 8.048 ;       ;       ; 8.353 ;
+; X          ; SUM         ; 7.483 ; 7.353 ; 7.927 ; 7.794 ;
+; Y          ; Cout        ; 7.770 ;       ;       ; 8.036 ;
+; Y          ; SUM         ; 7.192 ; 7.038 ; 7.621 ; 7.458 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; Cin        ; Cout        ; 4.643 ;       ;       ; 5.302 ;
+; Cin        ; SUM         ; 4.342 ; 4.356 ; 4.943 ; 4.977 ;
+; X          ; Cout        ; 4.441 ;       ;       ; 5.043 ;
+; X          ; SUM         ; 4.131 ; 4.157 ; 4.698 ; 4.706 ;
+; Y          ; Cout        ; 4.319 ;       ;       ; 4.902 ;
+; Y          ; SUM         ; 4.009 ; 4.028 ; 4.556 ; 4.568 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; SUM           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Cout          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------------+
+; Input Transition Times                                            ;
++----------------+--------------+-----------------+-----------------+
+; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------------+--------------+-----------------+-----------------+
+; X              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Cin            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; SUM           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.94e-09 V                   ; 2.39 V              ; -0.0344 V           ; 0.156 V                              ; 0.089 V                              ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.94e-09 V                  ; 2.39 V             ; -0.0344 V          ; 0.156 V                             ; 0.089 V                             ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; SUM           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00439 V          ; 0.088 V                              ; 0.007 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00439 V         ; 0.088 V                             ; 0.007 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; SUM           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0542 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0542 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 3     ; 3    ;
+; Unconstrained Input Port Paths  ; 6     ; 6    ;
+; Unconstrained Output Ports      ; 2     ; 2    ;
+; Unconstrained Output Port Paths ; 6     ; 6    ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Feb 17 22:15:12 2016
+Info: Command: quartus_sta full_adder -c full_adder
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 519 megabytes
+    Info: Processing ended: Wed Feb 17 22:15:16 2016
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/adder/output_files/full_adder.sta.summary b/adder/output_files/full_adder.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/adder/output_files/full_adder.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/adder/simulation/modelsim/full_adder.sft b/adder/simulation/modelsim/full_adder.sft
new file mode 100644
index 0000000..304e93c
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {full_adder_6_1200mv_85c_slow.vho full_adder_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {full_adder_6_1200mv_0c_slow.vho full_adder_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {full_adder_min_1200mv_0c_fast.vho full_adder_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/adder/simulation/modelsim/full_adder.vho b/adder/simulation/modelsim/full_adder.vho
new file mode 100644
index 0000000..57bbaa9
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder.vho
@@ -0,0 +1,180 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/17/2016 22:15:19"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	full_adder IS
+    PORT (
+	SUM : OUT std_logic;
+	X : IN std_logic;
+	Y : IN std_logic;
+	Cin : IN std_logic;
+	Cout : OUT std_logic
+	);
+END full_adder;
+
+-- Design Ports Information
+-- SUM	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cout	=>  Location: PIN_L11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cin	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF full_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_SUM : std_logic;
+SIGNAL ww_X : std_logic;
+SIGNAL ww_Y : std_logic;
+SIGNAL ww_Cin : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL \SUM~output_o\ : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \X~input_o\ : std_logic;
+SIGNAL \Cin~input_o\ : std_logic;
+SIGNAL \Y~input_o\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst3~0_combout\ : std_logic;
+
+BEGIN
+
+SUM <= ww_SUM;
+ww_X <= X;
+ww_Y <= Y;
+ww_Cin <= Cin;
+Cout <= ww_Cout;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X12_Y0_N9
+\SUM~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \SUM~output_o\);
+
+-- Location: IOOBUF_X31_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOIBUF_X8_Y0_N1
+\X~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X,
+	o => \X~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Cin~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Cin,
+	o => \Cin~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y,
+	o => \Y~input_o\);
+
+-- Location: LCCOMB_X8_Y1_N24
+\inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \X~input_o\ $ (\Cin~input_o\ $ (\Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010101011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst2~0_combout\);
+
+-- Location: LCCOMB_X8_Y1_N2
+\inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~0_combout\ = (\X~input_o\ & ((\Cin~input_o\) # (\Y~input_o\))) # (!\X~input_o\ & (\Cin~input_o\ & \Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst3~0_combout\);
+
+ww_SUM <= \SUM~output_o\;
+
+ww_Cout <= \Cout~output_o\;
+END structure;
+
+
diff --git a/adder/simulation/modelsim/full_adder_6_1200mv_0c_slow.vho b/adder/simulation/modelsim/full_adder_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..57bbaa9
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_6_1200mv_0c_slow.vho
@@ -0,0 +1,180 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/17/2016 22:15:19"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	full_adder IS
+    PORT (
+	SUM : OUT std_logic;
+	X : IN std_logic;
+	Y : IN std_logic;
+	Cin : IN std_logic;
+	Cout : OUT std_logic
+	);
+END full_adder;
+
+-- Design Ports Information
+-- SUM	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cout	=>  Location: PIN_L11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cin	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF full_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_SUM : std_logic;
+SIGNAL ww_X : std_logic;
+SIGNAL ww_Y : std_logic;
+SIGNAL ww_Cin : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL \SUM~output_o\ : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \X~input_o\ : std_logic;
+SIGNAL \Cin~input_o\ : std_logic;
+SIGNAL \Y~input_o\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst3~0_combout\ : std_logic;
+
+BEGIN
+
+SUM <= ww_SUM;
+ww_X <= X;
+ww_Y <= Y;
+ww_Cin <= Cin;
+Cout <= ww_Cout;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X12_Y0_N9
+\SUM~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \SUM~output_o\);
+
+-- Location: IOOBUF_X31_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOIBUF_X8_Y0_N1
+\X~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X,
+	o => \X~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Cin~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Cin,
+	o => \Cin~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y,
+	o => \Y~input_o\);
+
+-- Location: LCCOMB_X8_Y1_N24
+\inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \X~input_o\ $ (\Cin~input_o\ $ (\Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010101011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst2~0_combout\);
+
+-- Location: LCCOMB_X8_Y1_N2
+\inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~0_combout\ = (\X~input_o\ & ((\Cin~input_o\) # (\Y~input_o\))) # (!\X~input_o\ & (\Cin~input_o\ & \Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst3~0_combout\);
+
+ww_SUM <= \SUM~output_o\;
+
+ww_Cout <= \Cout~output_o\;
+END structure;
+
+
diff --git a/adder/simulation/modelsim/full_adder_6_1200mv_0c_vhd_slow.sdo b/adder/simulation/modelsim/full_adder_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..5b46126
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,114 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "full_adder")
+  (DATE "02/17/2016 22:15:19")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\SUM\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (814:814:814) (741:741:741))
+        (IOPATH i o (2324:2324:2324) (2217:2217:2217))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1434:1434:1434) (1335:1335:1335))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Cin\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2684:2684:2684) (2884:2884:2884))
+        (PORT datac (3102:3102:3102) (3326:3326:3326))
+        (PORT datad (2629:2629:2629) (2825:2825:2825))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2689:2689:2689) (2890:2890:2890))
+        (PORT datac (3097:3097:3097) (3321:3321:3321))
+        (PORT datad (2633:2633:2633) (2830:2830:2830))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/adder/simulation/modelsim/full_adder_6_1200mv_85c_slow.vho b/adder/simulation/modelsim/full_adder_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..57bbaa9
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_6_1200mv_85c_slow.vho
@@ -0,0 +1,180 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/17/2016 22:15:19"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	full_adder IS
+    PORT (
+	SUM : OUT std_logic;
+	X : IN std_logic;
+	Y : IN std_logic;
+	Cin : IN std_logic;
+	Cout : OUT std_logic
+	);
+END full_adder;
+
+-- Design Ports Information
+-- SUM	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cout	=>  Location: PIN_L11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cin	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF full_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_SUM : std_logic;
+SIGNAL ww_X : std_logic;
+SIGNAL ww_Y : std_logic;
+SIGNAL ww_Cin : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL \SUM~output_o\ : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \X~input_o\ : std_logic;
+SIGNAL \Cin~input_o\ : std_logic;
+SIGNAL \Y~input_o\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst3~0_combout\ : std_logic;
+
+BEGIN
+
+SUM <= ww_SUM;
+ww_X <= X;
+ww_Y <= Y;
+ww_Cin <= Cin;
+Cout <= ww_Cout;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X12_Y0_N9
+\SUM~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \SUM~output_o\);
+
+-- Location: IOOBUF_X31_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOIBUF_X8_Y0_N1
+\X~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X,
+	o => \X~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Cin~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Cin,
+	o => \Cin~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y,
+	o => \Y~input_o\);
+
+-- Location: LCCOMB_X8_Y1_N24
+\inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \X~input_o\ $ (\Cin~input_o\ $ (\Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010101011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst2~0_combout\);
+
+-- Location: LCCOMB_X8_Y1_N2
+\inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~0_combout\ = (\X~input_o\ & ((\Cin~input_o\) # (\Y~input_o\))) # (!\X~input_o\ & (\Cin~input_o\ & \Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst3~0_combout\);
+
+ww_SUM <= \SUM~output_o\;
+
+ww_Cout <= \Cout~output_o\;
+END structure;
+
+
diff --git a/adder/simulation/modelsim/full_adder_6_1200mv_85c_vhd_slow.sdo b/adder/simulation/modelsim/full_adder_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..31e3195
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,114 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "full_adder")
+  (DATE "02/17/2016 22:15:19")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\SUM\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (876:876:876) (834:834:834))
+        (IOPATH i o (2629:2629:2629) (2527:2527:2527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1544:1544:1544) (1498:1498:1498))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Cin\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3107:3107:3107) (3375:3375:3375))
+        (PORT datac (3557:3557:3557) (3870:3870:3870))
+        (PORT datad (3050:3050:3050) (3306:3306:3306))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3112:3112:3112) (3381:3381:3381))
+        (PORT datac (3553:3553:3553) (3865:3865:3865))
+        (PORT datad (3055:3055:3055) (3311:3311:3311))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/adder/simulation/modelsim/full_adder_min_1200mv_0c_fast.vho b/adder/simulation/modelsim/full_adder_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..57bbaa9
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_min_1200mv_0c_fast.vho
@@ -0,0 +1,180 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/17/2016 22:15:19"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	full_adder IS
+    PORT (
+	SUM : OUT std_logic;
+	X : IN std_logic;
+	Y : IN std_logic;
+	Cin : IN std_logic;
+	Cout : OUT std_logic
+	);
+END full_adder;
+
+-- Design Ports Information
+-- SUM	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cout	=>  Location: PIN_L11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Cin	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF full_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_SUM : std_logic;
+SIGNAL ww_X : std_logic;
+SIGNAL ww_Y : std_logic;
+SIGNAL ww_Cin : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL \SUM~output_o\ : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \X~input_o\ : std_logic;
+SIGNAL \Cin~input_o\ : std_logic;
+SIGNAL \Y~input_o\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst3~0_combout\ : std_logic;
+
+BEGIN
+
+SUM <= ww_SUM;
+ww_X <= X;
+ww_Y <= Y;
+ww_Cin <= Cin;
+Cout <= ww_Cout;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X12_Y0_N9
+\SUM~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \SUM~output_o\);
+
+-- Location: IOOBUF_X31_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOIBUF_X8_Y0_N1
+\X~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X,
+	o => \X~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Cin~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Cin,
+	o => \Cin~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y,
+	o => \Y~input_o\);
+
+-- Location: LCCOMB_X8_Y1_N24
+\inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \X~input_o\ $ (\Cin~input_o\ $ (\Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010101011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst2~0_combout\);
+
+-- Location: LCCOMB_X8_Y1_N2
+\inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~0_combout\ = (\X~input_o\ & ((\Cin~input_o\) # (\Y~input_o\))) # (!\X~input_o\ & (\Cin~input_o\ & \Y~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X~input_o\,
+	datac => \Cin~input_o\,
+	datad => \Y~input_o\,
+	combout => \inst3~0_combout\);
+
+ww_SUM <= \SUM~output_o\;
+
+ww_Cout <= \Cout~output_o\;
+END structure;
+
+
diff --git a/adder/simulation/modelsim/full_adder_min_1200mv_0c_vhd_fast.sdo b/adder/simulation/modelsim/full_adder_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..faa87a0
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,114 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "full_adder")
+  (DATE "02/17/2016 22:15:19")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\SUM\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (450:450:450) (482:482:482))
+        (IOPATH i o (1600:1600:1600) (1589:1589:1589))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (826:826:826) (900:900:900))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Cin\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1805:1805:1805) (1994:1994:1994))
+        (PORT datac (2054:2054:2054) (2300:2300:2300))
+        (PORT datad (1780:1780:1780) (1954:1954:1954))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1810:1810:1810) (1999:1999:1999))
+        (PORT datac (2049:2049:2049) (2295:2295:2295))
+        (PORT datad (1784:1784:1784) (1959:1959:1959))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/adder/simulation/modelsim/full_adder_modelsim.xrf b/adder/simulation/modelsim/full_adder_modelsim.xrf
new file mode 100644
index 0000000..f18a2ea
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_modelsim.xrf
@@ -0,0 +1,11 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf
+source_file = 1, C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.cbx.xml
+design_name = full_adder
+instance = comp, \SUM~output\, SUM~output, full_adder, 1
+instance = comp, \Cout~output\, Cout~output, full_adder, 1
+instance = comp, \X~input\, X~input, full_adder, 1
+instance = comp, \Cin~input\, Cin~input, full_adder, 1
+instance = comp, \Y~input\, Y~input, full_adder, 1
+instance = comp, \inst2~0\, inst2~0, full_adder, 1
+instance = comp, \inst3~0\, inst3~0, full_adder, 1
diff --git a/adder/simulation/modelsim/full_adder_vhd.sdo b/adder/simulation/modelsim/full_adder_vhd.sdo
new file mode 100644
index 0000000..31e3195
--- /dev/null
+++ b/adder/simulation/modelsim/full_adder_vhd.sdo
@@ -0,0 +1,114 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "full_adder")
+  (DATE "02/17/2016 22:15:19")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\SUM\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (876:876:876) (834:834:834))
+        (IOPATH i o (2629:2629:2629) (2527:2527:2527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1544:1544:1544) (1498:1498:1498))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Cin\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3107:3107:3107) (3375:3375:3375))
+        (PORT datac (3557:3557:3557) (3870:3870:3870))
+        (PORT datad (3050:3050:3050) (3306:3306:3306))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3112:3112:3112) (3381:3381:3381))
+        (PORT datac (3553:3553:3553) (3865:3865:3865))
+        (PORT datad (3055:3055:3055) (3311:3311:3311))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/adder/ten_bit_adder.ipinfo b/adder/ten_bit_adder.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/adder/ten_bit_adder.ipinfo
diff --git a/adder/ten_bit_adder_NO_BUS.ipinfo b/adder/ten_bit_adder_NO_BUS.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/adder/ten_bit_adder_NO_BUS.ipinfo
diff --git a/bcd_to_display/Waveform.vwf b/bcd_to_display/Waveform.vwf
new file mode 100644
index 0000000..3cfde12
--- /dev/null
+++ b/bcd_to_display/Waveform.vwf
@@ -0,0 +1,399 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("BCDin")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 4;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("BCDin[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("DISPout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 7;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("DISPout[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+TRANSITION_LIST("BCDin[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("BCDin[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("BCDin[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("BCDin[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("DISPout[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2, 3, 4;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+	CHILDREN = 6, 7, 8, 9, 10, 11, 12;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 11;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 12;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
diff --git a/bcd_to_display/bcd_to_display.bdf b/bcd_to_display/bcd_to_display.bdf
new file mode 100644
index 0000000..6465913
--- /dev/null
+++ b/bcd_to_display/bcd_to_display.bdf
@@ -0,0 +1,1926 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 0 552 168 568)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BCDin[3..0]" (rect 5 0 62 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 1152 552 1328 568)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DISPout[6..0]" (rect 90 0 157 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 576 160 624 192)
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst3" (rect 3 21 26 33)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 13 16))
+	)
+	(port
+		(pt 48 16)
+		(output)
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(line (pt 39 16)(pt 48 16))
+	)
+	(drawing
+		(line (pt 13 25)(pt 13 7))
+		(line (pt 13 7)(pt 31 16))
+		(line (pt 13 25)(pt 31 16))
+		(circle (rect 31 12 39 20))
+	)
+)
+(symbol
+	(rect 576 128 624 160)
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst4" (rect 3 21 26 33)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 13 16))
+	)
+	(port
+		(pt 48 16)
+		(output)
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(line (pt 39 16)(pt 48 16))
+	)
+	(drawing
+		(line (pt 13 25)(pt 13 7))
+		(line (pt 13 7)(pt 31 16))
+		(line (pt 13 25)(pt 31 16))
+		(circle (rect 31 12 39 20))
+	)
+)
+(symbol
+	(rect 544 224 592 256)
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst9" (rect 3 21 26 33)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 13 16))
+	)
+	(port
+		(pt 48 16)
+		(output)
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(line (pt 39 16)(pt 48 16))
+	)
+	(drawing
+		(line (pt 13 25)(pt 13 7))
+		(line (pt 13 7)(pt 31 16))
+		(line (pt 13 25)(pt 31 16))
+		(circle (rect 31 12 39 20))
+	)
+)
+(symbol
+	(rect 544 256 592 288)
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst10" (rect 3 21 32 33)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 13 16))
+	)
+	(port
+		(pt 48 16)
+		(output)
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(line (pt 39 16)(pt 48 16))
+	)
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+	(pt 400 304)
+)
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+	(pt 824 296)
+)
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+	(pt 800 344)
+	(pt 592 344)
+)
+(connector
+	(pt 800 296)
+	(pt 800 344)
+)
+(connector
+	(text "DISPout[1]" (rect 898 272 952 284)(font "Arial" ))
+	(pt 888 288)
+	(pt 952 288)
+)
+(connector
+	(pt 592 416)
+	(pt 824 416)
+)
+(connector
+	(pt 400 432)
+	(pt 824 432)
+)
+(connector
+	(text "DISPout[2]" (rect 898 392 952 404)(font "Arial" ))
+	(pt 888 408)
+	(pt 952 408)
+)
+(connector
+	(pt 824 504)
+	(pt 608 504)
+)
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+	(pt 616 520)
+	(pt 632 520)
+)
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+	(pt 616 576)
+	(pt 616 520)
+)
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+	(pt 632 536)
+	(pt 624 536)
+)
+(connector
+	(pt 624 536)
+	(pt 624 584)
+)
+(connector
+	(pt 696 528)
+	(pt 704 528)
+)
+(connector
+	(pt 704 528)
+	(pt 704 520)
+)
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+	(pt 704 520)
+	(pt 824 520)
+)
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+	(pt 632 592)
+	(pt 632 568)
+)
+(connector
+	(pt 632 568)
+	(pt 656 568)
+)
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+	(pt 640 576)
+	(pt 656 576)
+)
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+	(pt 648 624)
+	(pt 648 584)
+)
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+	(pt 648 584)
+	(pt 656 584)
+)
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+	(pt 608 504)
+	(pt 608 544)
+)
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+	(pt 824 488)
+	(pt 608 488)
+)
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+	(pt 608 488)
+	(pt 608 496)
+)
+(connector
+	(pt 624 584)
+	(pt 536 584)
+)
+(connector
+	(pt 616 576)
+	(pt 528 576)
+)
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+	(pt 520 552)
+	(pt 536 552)
+)
+(connector
+	(pt 536 552)
+	(pt 544 552)
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+	(pt 520 504)
+	(pt 528 504)
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+	(pt 528 504)
+	(pt 544 504)
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+	(pt 400 504)
+	(pt 472 504)
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+	(pt 640 608)
+	(pt 520 608)
+)
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+	(pt 640 576)
+	(pt 640 608)
+)
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+	(pt 416 488)
+	(pt 544 488)
+)
+(connector
+	(pt 472 608)
+	(pt 416 608)
+)
+(connector
+	(pt 416 536)
+	(pt 544 536)
+)
+(connector
+	(pt 416 416)
+	(pt 544 416)
+)
+(connector
+	(pt 416 320)
+	(pt 632 320)
+)
+(connector
+	(pt 784 80)
+	(pt 416 80)
+)
+(connector
+	(pt 416 272)
+	(pt 544 272)
+)
+(connector
+	(pt 416 80)
+	(pt 416 272)
+)
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+	(pt 640 104)
+	(pt 432 104)
+)
+(connector
+	(pt 432 176)
+	(pt 576 176)
+)
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+	(pt 432 104)
+	(pt 432 176)
+)
+(connector
+	(pt 432 400)
+	(pt 824 400)
+)
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+	(pt 648 624)
+	(pt 432 624)
+)
+(connector
+	(pt 432 552)
+	(pt 472 552)
+)
+(connector
+	(pt 784 208)
+	(pt 448 208)
+)
+(connector
+	(pt 824 472)
+	(pt 448 472)
+)
+(connector
+	(pt 448 384)
+	(pt 824 384)
+)
+(connector
+	(pt 720 576)
+	(pt 736 576)
+)
+(connector
+	(pt 736 576)
+	(pt 736 536)
+)
+(connector
+	(pt 736 536)
+	(pt 824 536)
+)
+(connector
+	(text "DISPout[3]" (rect 898 496 952 508)(font "Arial" ))
+	(pt 888 512)
+	(pt 952 512)
+)
+(connector
+	(pt 632 592)
+	(pt 400 592)
+)
+(connector
+	(pt 528 504)
+	(pt 528 576)
+)
+(connector
+	(pt 528 576)
+	(pt 528 648)
+)
+(connector
+	(pt 528 648)
+	(pt 824 648)
+)
+(connector
+	(pt 536 552)
+	(pt 536 584)
+)
+(connector
+	(pt 536 584)
+	(pt 536 664)
+)
+(connector
+	(pt 616 664)
+	(pt 536 664)
+)
+(connector
+	(pt 680 672)
+	(pt 704 672)
+)
+(connector
+	(pt 704 672)
+	(pt 704 664)
+)
+(connector
+	(pt 704 664)
+	(pt 824 664)
+)
+(connector
+	(pt 416 680)
+	(pt 616 680)
+)
+(connector
+	(text "DISPout[4]" (rect 898 640 952 652)(font "Arial" ))
+	(pt 952 656)
+	(pt 888 656)
+)
+(connector
+	(pt 448 712)
+	(pt 824 712)
+)
+(connector
+	(pt 448 848)
+	(pt 824 848)
+)
+(connector
+	(pt 448 712)
+	(pt 448 848)
+)
+(connector
+	(pt 432 744)
+	(pt 576 744)
+)
+(connector
+	(pt 640 736)
+	(pt 656 736)
+)
+(connector
+	(pt 656 728)
+	(pt 824 728)
+)
+(connector
+	(pt 656 728)
+	(pt 656 736)
+)
+(connector
+	(pt 656 736)
+	(pt 656 864)
+)
+(connector
+	(pt 656 864)
+	(pt 824 864)
+)
+(connector
+	(pt 416 728)
+	(pt 456 728)
+)
+(connector
+	(pt 416 608)
+	(pt 416 680)
+)
+(connector
+	(pt 512 728)
+	(pt 512 760)
+)
+(connector
+	(pt 504 728)
+	(pt 512 728)
+)
+(connector
+	(pt 512 728)
+	(pt 576 728)
+)
+(connector
+	(pt 400 776)
+	(pt 456 776)
+)
+(connector
+	(pt 504 776)
+	(pt 512 776)
+)
+(connector
+	(pt 576 768)
+	(pt 672 768)
+)
+(connector
+	(pt 672 768)
+	(pt 672 744)
+)
+(connector
+	(pt 672 744)
+	(pt 824 744)
+)
+(connector
+	(pt 504 776)
+	(pt 504 792)
+)
+(connector
+	(pt 504 792)
+	(pt 584 792)
+)
+(connector
+	(pt 432 624)
+	(pt 432 744)
+)
+(connector
+	(pt 432 808)
+	(pt 584 808)
+)
+(connector
+	(pt 648 800)
+	(pt 688 800)
+)
+(connector
+	(pt 688 800)
+	(pt 688 760)
+)
+(connector
+	(pt 688 760)
+	(pt 824 760)
+)
+(connector
+	(text "DISPout[5]" (rect 897 712 951 724)(font "Arial" ))
+	(pt 888 736)
+	(pt 952 736)
+)
+(connector
+	(text "DISPout[6]" (rect 898 856 952 868)(font "Arial" ))
+	(pt 888 872)
+	(pt 952 872)
+)
+(connector
+	(pt 416 680)
+	(pt 416 728)
+)
+(connector
+	(pt 416 872)
+	(pt 512 872)
+)
+(connector
+	(pt 576 880)
+	(pt 824 880)
+)
+(connector
+	(pt 656 912)
+	(pt 672 912)
+)
+(connector
+	(pt 672 912)
+	(pt 672 896)
+)
+(connector
+	(pt 672 896)
+	(pt 824 896)
+)
+(connector
+	(pt 416 728)
+	(pt 416 872)
+)
+(connector
+	(pt 416 872)
+	(pt 416 904)
+)
+(connector
+	(pt 416 904)
+	(pt 592 904)
+)
+(connector
+	(pt 432 744)
+	(pt 432 808)
+)
+(connector
+	(pt 432 808)
+	(pt 432 920)
+)
+(connector
+	(pt 400 888)
+	(pt 464 888)
+)
+(connector
+	(pt 400 592)
+	(pt 400 776)
+)
+(connector
+	(pt 400 776)
+	(pt 400 888)
+)
+(connector
+	(pt 432 920)
+	(pt 464 920)
+)
+(connector
+	(pt 512 920)
+	(pt 592 920)
+)
+(connector
+	(text "BCDin[0]" (rect 250 512 294 524)(font "Arial" ))
+	(pt 400 528)
+	(pt 240 528)
+)
+(connector
+	(text "BCDin[1]" (rect 250 536 294 548)(font "Arial" ))
+	(pt 416 552)
+	(pt 240 552)
+)
+(connector
+	(text "BCDin[2]" (rect 250 560 294 572)(font "Arial" ))
+	(pt 432 576)
+	(pt 240 576)
+)
+(connector
+	(text "BCDin[3]" (rect 250 584 294 596)(font "Arial" ))
+	(pt 448 600)
+	(pt 240 600)
+)
+(connector
+	(pt 400 240)
+	(pt 400 304)
+)
+(connector
+	(pt 400 304)
+	(pt 400 432)
+)
+(connector
+	(pt 400 432)
+	(pt 400 504)
+)
+(connector
+	(pt 400 504)
+	(pt 400 528)
+)
+(connector
+	(pt 400 528)
+	(pt 400 592)
+)
+(connector
+	(pt 416 272)
+	(pt 416 320)
+)
+(connector
+	(pt 416 416)
+	(pt 416 488)
+)
+(connector
+	(pt 416 488)
+	(pt 416 536)
+)
+(connector
+	(pt 416 536)
+	(pt 416 552)
+)
+(connector
+	(pt 416 552)
+	(pt 416 608)
+)
+(connector
+	(pt 432 400)
+	(pt 432 552)
+)
+(connector
+	(pt 432 552)
+	(pt 432 576)
+)
+(connector
+	(pt 432 576)
+	(pt 432 624)
+)
+(connector
+	(pt 448 208)
+	(pt 448 384)
+)
+(connector
+	(pt 448 384)
+	(pt 448 472)
+)
+(connector
+	(pt 448 472)
+	(pt 448 600)
+)
+(connector
+	(pt 448 600)
+	(pt 448 712)
+)
+(connector
+	(text "BCDin[3..0]" (rect 174 544 231 556)(font "Arial" ))
+	(pt 168 560)
+	(pt 216 560)
+	(bus)
+)
+(connector
+	(text "DISPout[6..0]" (rect 1144 544 1211 556)(font "Arial" ))
+	(pt 1112 560)
+	(pt 1152 560)
+	(bus)
+)
+(connector
+	(pt 416 320)
+	(pt 416 416)
+)
+(connector
+	(pt 544 344)
+	(pt 432 344)
+)
+(connector
+	(pt 432 176)
+	(pt 432 344)
+)
+(connector
+	(pt 432 344)
+	(pt 432 400)
+)
+(junction (pt 400 144))
+(junction (pt 400 240))
+(junction (pt 400 304))
+(junction (pt 400 432))
+(junction (pt 400 504))
+(junction (pt 536 552))
+(junction (pt 528 504))
+(junction (pt 416 488))
+(junction (pt 416 536))
+(junction (pt 416 416))
+(junction (pt 416 320))
+(junction (pt 416 272))
+(junction (pt 432 176))
+(junction (pt 432 400))
+(junction (pt 432 552))
+(junction (pt 448 384))
+(junction (pt 528 576))
+(junction (pt 536 584))
+(junction (pt 416 608))
+(junction (pt 448 472))
+(junction (pt 448 712))
+(junction (pt 416 680))
+(junction (pt 432 624))
+(junction (pt 656 736))
+(junction (pt 512 728))
+(junction (pt 400 592))
+(junction (pt 504 776))
+(junction (pt 432 744))
+(junction (pt 416 728))
+(junction (pt 400 776))
+(junction (pt 416 872))
+(junction (pt 432 808))
+(junction (pt 400 528))
+(junction (pt 416 552))
+(junction (pt 432 576))
+(junction (pt 448 600))
+(junction (pt 432 344))
diff --git a/bcd_to_display/bcd_to_display.bsf b/bcd_to_display/bcd_to_display.bsf
new file mode 100644
index 0000000..1853043
--- /dev/null
+++ b/bcd_to_display/bcd_to_display.bsf
@@ -0,0 +1,43 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 200 112)
+	(text "bcd_to_display" (rect 5 0 91 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "BCDin[3..0]" (rect 0 0 62 14)(font "Arial" (font_size 8)))
+		(text "BCDin[3..0]" (rect 21 27 83 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 184 32)
+		(output)
+		(text "DISPout[6..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "DISPout[6..0]" (rect 92 27 163 41)(font "Arial" (font_size 8)))
+		(line (pt 184 32)(pt 168 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 168 80))
+	)
+)
diff --git a/bcd_to_display/bcd_to_display.qpf b/bcd_to_display/bcd_to_display.qpf
new file mode 100644
index 0000000..5c8d4eb
--- /dev/null
+++ b/bcd_to_display/bcd_to_display.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 12:03:56  February 20, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "12:03:56  February 20, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "bcd_to_display"
diff --git a/bcd_to_display/bcd_to_display.qsf b/bcd_to_display/bcd_to_display.qsf
new file mode 100644
index 0000000..4a40ec8
--- /dev/null
+++ b/bcd_to_display/bcd_to_display.qsf
@@ -0,0 +1,60 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 12:03:56  February 20, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		bcd_to_display_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY bcd_to_display
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:03:56  FEBRUARY 20, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name BDF_FILE bcd_to_display.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Git/bcd_to_display/Waveform.vwf"
+set_global_assignment -name SIMULATION_MODE FUNCTIONAL
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/bcd_to_display/bcd_to_display.qws b/bcd_to_display/bcd_to_display.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/bcd_to_display/bcd_to_display.qws
diff --git a/bcd_to_display/db/.cmp.kpt b/bcd_to_display/db/.cmp.kpt
new file mode 100644
index 0000000..f670c87
--- /dev/null
+++ b/bcd_to_display/db/.cmp.kpt
diff --git a/bcd_to_display/db/bcd_to_display.(0).cnf.cdb b/bcd_to_display/db/bcd_to_display.(0).cnf.cdb
new file mode 100644
index 0000000..5f4bf81
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.(0).cnf.cdb
diff --git a/bcd_to_display/db/bcd_to_display.(0).cnf.hdb b/bcd_to_display/db/bcd_to_display.(0).cnf.hdb
new file mode 100644
index 0000000..d3c23c0
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.(0).cnf.hdb
diff --git a/bcd_to_display/db/bcd_to_display.asm.qmsg b/bcd_to_display/db/bcd_to_display.asm.qmsg
new file mode 100644
index 0000000..0e030e4
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504621048 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504621049 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:00 2016 " "Processing started: Fri Feb 26 16:37:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504621049 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456504621049 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456504621049 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456504621646 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456504621664 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "419 " "Peak virtual memory: 419 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504621888 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:01 2016 " "Processing ended: Fri Feb 26 16:37:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504621888 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504621888 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504621888 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456504621888 ""}
diff --git a/bcd_to_display/db/bcd_to_display.asm.rdb b/bcd_to_display/db/bcd_to_display.asm.rdb
new file mode 100644
index 0000000..f4a6bb6
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.asm.rdb
diff --git a/bcd_to_display/db/bcd_to_display.asm_labs.ddb b/bcd_to_display/db/bcd_to_display.asm_labs.ddb
new file mode 100644
index 0000000..e0053dd
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.asm_labs.ddb
diff --git a/bcd_to_display/db/bcd_to_display.cbx.xml b/bcd_to_display/db/bcd_to_display.cbx.xml
new file mode 100644
index 0000000..446c3b9
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="bcd_to_display">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/bcd_to_display/db/bcd_to_display.cmp.bpm b/bcd_to_display/db/bcd_to_display.cmp.bpm
new file mode 100644
index 0000000..e6015cf
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.bpm
diff --git a/bcd_to_display/db/bcd_to_display.cmp.cdb b/bcd_to_display/db/bcd_to_display.cmp.cdb
new file mode 100644
index 0000000..652c281
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.cdb
diff --git a/bcd_to_display/db/bcd_to_display.cmp.hdb b/bcd_to_display/db/bcd_to_display.cmp.hdb
new file mode 100644
index 0000000..a900cf4
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.hdb
diff --git a/bcd_to_display/db/bcd_to_display.cmp.idb b/bcd_to_display/db/bcd_to_display.cmp.idb
new file mode 100644
index 0000000..d265b5f
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.idb
diff --git a/bcd_to_display/db/bcd_to_display.cmp.kpt b/bcd_to_display/db/bcd_to_display.cmp.kpt
new file mode 100644
index 0000000..ce6100e
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.kpt
diff --git a/bcd_to_display/db/bcd_to_display.cmp.logdb b/bcd_to_display/db/bcd_to_display.cmp.logdb
new file mode 100644
index 0000000..e106b45
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.logdb
@@ -0,0 +1,53 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;11;0;0;11;11;0;7;0;0;4;0;7;4;0;0;0;7;0;0;0;0;0;11;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,11;11;11;11;11;0;11;11;0;0;11;4;11;11;7;11;4;7;11;11;11;4;11;11;11;11;11;0;11;11,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,DISPout[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DISPout[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BCDin[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BCDin[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BCDin[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BCDin[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/bcd_to_display/db/bcd_to_display.cmp.rdb b/bcd_to_display/db/bcd_to_display.cmp.rdb
new file mode 100644
index 0000000..77180fd
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp.rdb
diff --git a/bcd_to_display/db/bcd_to_display.cmp_merge.kpt b/bcd_to_display/db/bcd_to_display.cmp_merge.kpt
new file mode 100644
index 0000000..e340e17
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cmp_merge.kpt
diff --git a/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..48e9c1b
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..e9cbe95
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/bcd_to_display/db/bcd_to_display.db_info b/bcd_to_display/db/bcd_to_display.db_info
new file mode 100644
index 0000000..bbc70e0
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 16:35:00 2016
diff --git a/bcd_to_display/db/bcd_to_display.eda.qmsg b/bcd_to_display/db/bcd_to_display.eda.qmsg
new file mode 100644
index 0000000..273c3f4
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.eda.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504626359 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504626361 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:05 2016 " "Processing started: Fri Feb 26 16:37:05 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504626361 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456504626361 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display " "Command: quartus_eda --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456504626361 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "bcd_to_display.vo C:/Git/bcd_to_display/simulation/modelsim/ simulation " "Generated file bcd_to_display.vo in folder \"C:/Git/bcd_to_display/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456504626613 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504626635 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:06 2016 " "Processing ended: Fri Feb 26 16:37:06 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504626635 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504626635 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504626635 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456504626635 ""}
diff --git a/bcd_to_display/db/bcd_to_display.fit.qmsg b/bcd_to_display/db/bcd_to_display.fit.qmsg
new file mode 100644
index 0000000..a435530
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.fit.qmsg
@@ -0,0 +1,47 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456504616062 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "bcd_to_display EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"bcd_to_display\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456504616286 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504616341 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504616341 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504616341 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456504616400 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504616579 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504616579 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504616579 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456504616579 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504616580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504616580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504616580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504616580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504616580 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456504616580 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456504616581 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[6\] " "Pin DISPout\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[6] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 5 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[5\] " "Pin DISPout\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[5] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 6 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[4\] " "Pin DISPout\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[4] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 7 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[3\] " "Pin DISPout\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[3] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 8 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[2\] " "Pin DISPout\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[2] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 9 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[1\] " "Pin DISPout\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[1] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 10 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "DISPout\[0\] " "Pin DISPout\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DISPout[0] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 1152 1328 568 "DISPout" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DISPout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 11 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BCDin\[3\] " "Pin BCDin\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BCDin[3] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 0 168 568 "BCDin" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BCDin[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 12 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BCDin\[1\] " "Pin BCDin\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BCDin[1] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 0 168 568 "BCDin" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BCDin[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 14 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BCDin\[2\] " "Pin BCDin\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BCDin[2] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 0 168 568 "BCDin" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BCDin[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 13 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BCDin\[0\] " "Pin BCDin\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BCDin[0] } } } { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { { 552 0 168 568 "BCDin" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BCDin[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/bcd_to_display/" { { 0 { 0 ""} 0 15 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456504617227 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456504617227 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "bcd_to_display.sdc " "Synopsys Design Constraints File file not found: 'bcd_to_display.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456504617322 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456504617322 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1456504617323 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1456504617323 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456504617323 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456504617323 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456504617323 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456504617324 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456504617324 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456504617325 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456504617326 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456504617326 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456504617326 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 2.5V 4 7 0 " "Number of I/O pins in group: 11 (unused VREF, 2.5V VCCIO, 4 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456504617327 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456504617327 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456504617327 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456504617328 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456504617328 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456504617328 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504617336 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456504617724 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504617765 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456504617772 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456504617892 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504617892 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456504618031 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" {  } { { "loc" "" { Generic "C:/Git/bcd_to_display/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456504618362 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456504618362 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504618398 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456504618400 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1456504618400 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456504618400 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.12 " "Total time spent on timing analysis during the Fitter is 0.12 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456504618404 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456504618431 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456504618645 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456504618670 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456504618913 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504619180 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Git/bcd_to_display/output_files/bcd_to_display.fit.smsg " "Generated suppressed messages file C:/Git/bcd_to_display/output_files/bcd_to_display.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456504619823 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1068 " "Peak virtual memory: 1068 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504619966 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:36:59 2016 " "Processing ended: Fri Feb 26 16:36:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504619966 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504619966 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504619966 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456504619966 ""}
diff --git a/bcd_to_display/db/bcd_to_display.hier_info b/bcd_to_display/db/bcd_to_display.hier_info
new file mode 100644
index 0000000..46739e9
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.hier_info
@@ -0,0 +1,44 @@
+|bcd_to_display
+DISPout[0] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[2] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[3] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[4] <= inst12.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[5] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[6] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+BCDin[0] => inst4.IN0
+BCDin[0] => inst16.IN1
+BCDin[0] => inst9.IN0
+BCDin[0] => inst19.IN0
+BCDin[0] => inst6.IN3
+BCDin[0] => inst14.IN0
+BCDin[0] => inst26.IN0
+BCDin[0] => inst36.IN0
+BCDin[0] => inst37.IN0
+BCDin[1] => inst8.IN0
+BCDin[1] => inst10.IN0
+BCDin[1] => inst19.IN1
+BCDin[1] => inst13.IN0
+BCDin[1] => inst25.IN0
+BCDin[1] => inst24.IN0
+BCDin[1] => inst28.IN0
+BCDin[1] => inst31.IN0
+BCDin[1] => inst34.IN0
+BCDin[1] => inst40.IN0
+BCDin[1] => inst41.IN0
+BCDin[2] => inst3.IN0
+BCDin[2] => inst16.IN0
+BCDin[2] => inst11.IN0
+BCDin[2] => inst6.IN2
+BCDin[2] => inst15.IN0
+BCDin[2] => inst26.IN2
+BCDin[2] => inst33.IN1
+BCDin[2] => inst39.IN1
+BCDin[2] => inst38.IN0
+BCDin[3] => inst8.IN3
+BCDin[3] => inst6.IN0
+BCDin[3] => inst5.IN0
+BCDin[3] => inst2.IN0
+BCDin[3] => inst1.IN0
+
+
diff --git a/bcd_to_display/db/bcd_to_display.hif b/bcd_to_display/db/bcd_to_display.hif
new file mode 100644
index 0000000..bdc3baa
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.hif
diff --git a/bcd_to_display/db/bcd_to_display.ipinfo b/bcd_to_display/db/bcd_to_display.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.ipinfo
diff --git a/bcd_to_display/db/bcd_to_display.lpc.html b/bcd_to_display/db/bcd_to_display.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/bcd_to_display/db/bcd_to_display.lpc.rdb b/bcd_to_display/db/bcd_to_display.lpc.rdb
new file mode 100644
index 0000000..da6029a
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.lpc.rdb
diff --git a/bcd_to_display/db/bcd_to_display.lpc.txt b/bcd_to_display/db/bcd_to_display.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/bcd_to_display/db/bcd_to_display.map.ammdb b/bcd_to_display/db/bcd_to_display.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.ammdb
diff --git a/bcd_to_display/db/bcd_to_display.map.bpm b/bcd_to_display/db/bcd_to_display.map.bpm
new file mode 100644
index 0000000..91516ab
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.bpm
diff --git a/bcd_to_display/db/bcd_to_display.map.cdb b/bcd_to_display/db/bcd_to_display.map.cdb
new file mode 100644
index 0000000..5342ef7
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.cdb
diff --git a/bcd_to_display/db/bcd_to_display.map.hdb b/bcd_to_display/db/bcd_to_display.map.hdb
new file mode 100644
index 0000000..676a72a
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.hdb
diff --git a/bcd_to_display/db/bcd_to_display.map.kpt b/bcd_to_display/db/bcd_to_display.map.kpt
new file mode 100644
index 0000000..070ee9c
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.kpt
diff --git a/bcd_to_display/db/bcd_to_display.map.logdb b/bcd_to_display/db/bcd_to_display.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/bcd_to_display/db/bcd_to_display.map.qmsg b/bcd_to_display/db/bcd_to_display.map.qmsg
new file mode 100644
index 0000000..f6bd11c
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504613924 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504613925 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:36:53 2016 " "Processing started: Fri Feb 26 16:36:53 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504613925 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456504613925 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bcd_to_display -c bcd_to_display " "Command: quartus_map --read_settings_files=on --write_settings_files=off bcd_to_display -c bcd_to_display" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456504613926 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456504614160 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd_to_display.bdf 1 1 " "Found 1 design units, including 1 entities, in source file bcd_to_display.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bcd_to_display " "Found entity 1: bcd_to_display" {  } { { "bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504614198 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504614198 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "bcd_to_display " "Elaborating entity \"bcd_to_display\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456504614215 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456504614603 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456504614753 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456504614753 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "18 " "Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456504614773 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456504614773 ""} { "Info" "ICUT_CUT_TM_LCELLS" "7 " "Implemented 7 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456504614773 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456504614773 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "464 " "Peak virtual memory: 464 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504614783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:36:54 2016 " "Processing ended: Fri Feb 26 16:36:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504614783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504614783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504614783 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456504614783 ""}
diff --git a/bcd_to_display/db/bcd_to_display.map.rdb b/bcd_to_display/db/bcd_to_display.map.rdb
new file mode 100644
index 0000000..4bb9b52
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map.rdb
diff --git a/bcd_to_display/db/bcd_to_display.map_bb.cdb b/bcd_to_display/db/bcd_to_display.map_bb.cdb
new file mode 100644
index 0000000..311b21c
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map_bb.cdb
diff --git a/bcd_to_display/db/bcd_to_display.map_bb.hdb b/bcd_to_display/db/bcd_to_display.map_bb.hdb
new file mode 100644
index 0000000..c6de791
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map_bb.hdb
diff --git a/bcd_to_display/db/bcd_to_display.map_bb.logdb b/bcd_to_display/db/bcd_to_display.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/bcd_to_display/db/bcd_to_display.pre_map.hdb b/bcd_to_display/db/bcd_to_display.pre_map.hdb
new file mode 100644
index 0000000..30c040f
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.pre_map.hdb
diff --git a/bcd_to_display/db/bcd_to_display.pti_db_list.ddb b/bcd_to_display/db/bcd_to_display.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.pti_db_list.ddb
diff --git a/bcd_to_display/db/bcd_to_display.root_partition.map.reg_db.cdb b/bcd_to_display/db/bcd_to_display.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..d86af0f
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.root_partition.map.reg_db.cdb
diff --git a/bcd_to_display/db/bcd_to_display.routing.rdb b/bcd_to_display/db/bcd_to_display.routing.rdb
new file mode 100644
index 0000000..6b38f4c
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.routing.rdb
diff --git a/bcd_to_display/db/bcd_to_display.rtlv.hdb b/bcd_to_display/db/bcd_to_display.rtlv.hdb
new file mode 100644
index 0000000..0a92a6b
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.rtlv.hdb
diff --git a/bcd_to_display/db/bcd_to_display.rtlv_sg.cdb b/bcd_to_display/db/bcd_to_display.rtlv_sg.cdb
new file mode 100644
index 0000000..942943a
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.rtlv_sg.cdb
diff --git a/bcd_to_display/db/bcd_to_display.rtlv_sg_swap.cdb b/bcd_to_display/db/bcd_to_display.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..c194c18
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.rtlv_sg_swap.cdb
diff --git a/bcd_to_display/db/bcd_to_display.sgdiff.cdb b/bcd_to_display/db/bcd_to_display.sgdiff.cdb
new file mode 100644
index 0000000..62820cf
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sgdiff.cdb
diff --git a/bcd_to_display/db/bcd_to_display.sgdiff.hdb b/bcd_to_display/db/bcd_to_display.sgdiff.hdb
new file mode 100644
index 0000000..fa363c3
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sgdiff.hdb
diff --git a/bcd_to_display/db/bcd_to_display.sld_design_entry.sci b/bcd_to_display/db/bcd_to_display.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sld_design_entry.sci
diff --git a/bcd_to_display/db/bcd_to_display.sld_design_entry_dsc.sci b/bcd_to_display/db/bcd_to_display.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sld_design_entry_dsc.sci
diff --git a/bcd_to_display/db/bcd_to_display.smart_action.txt b/bcd_to_display/db/bcd_to_display.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/bcd_to_display/db/bcd_to_display.sta.qmsg b/bcd_to_display/db/bcd_to_display.sta.qmsg
new file mode 100644
index 0000000..102fac4
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sta.qmsg
@@ -0,0 +1,49 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504623100 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504623100 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:02 2016 " "Processing started: Fri Feb 26 16:37:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504623100 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456504623100 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta bcd_to_display -c bcd_to_display " "Command: quartus_sta bcd_to_display -c bcd_to_display" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456504623101 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456504623159 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456504623244 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504623245 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504623288 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504623288 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "bcd_to_display.sdc " "Synopsys Design Constraints File file not found: 'bcd_to_display.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456504623408 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456504623408 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456504623409 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456504623409 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456504623409 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456504623409 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456504623410 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1456504623415 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456504623416 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623417 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623423 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623425 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623427 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623429 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623430 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456504623440 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456504623458 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456504623843 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456504623866 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456504623866 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456504623866 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456504623866 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623867 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623871 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623874 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623876 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623878 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623880 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456504623888 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456504623941 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456504623941 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456504623942 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456504623942 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623944 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623945 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623947 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623949 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456504623950 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456504625057 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456504625057 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "476 " "Peak virtual memory: 476 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504625114 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:05 2016 " "Processing ended: Fri Feb 26 16:37:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504625114 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504625114 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504625114 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456504625114 ""}
diff --git a/bcd_to_display/db/bcd_to_display.sta.rdb b/bcd_to_display/db/bcd_to_display.sta.rdb
new file mode 100644
index 0000000..f0106db
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sta.rdb
diff --git a/bcd_to_display/db/bcd_to_display.sta_cmp.6_slow_1200mv_85c.tdb b/bcd_to_display/db/bcd_to_display.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..37b3adf
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/bcd_to_display/db/bcd_to_display.syn_hier_info b/bcd_to_display/db/bcd_to_display.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.syn_hier_info
diff --git a/bcd_to_display/db/bcd_to_display.tis_db_list.ddb b/bcd_to_display/db/bcd_to_display.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.tis_db_list.ddb
diff --git a/bcd_to_display/db/bcd_to_display.tiscmp.fast_1200mv_0c.ddb b/bcd_to_display/db/bcd_to_display.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..a6f9360
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.tiscmp.fast_1200mv_0c.ddb
diff --git a/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_0c.ddb b/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..36e6bd1
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_0c.ddb
diff --git a/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_85c.ddb b/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..6bdfbab
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.tiscmp.slow_1200mv_85c.ddb
diff --git a/bcd_to_display/db/bcd_to_display.tmw_info b/bcd_to_display/db/bcd_to_display.tmw_info
new file mode 100644
index 0000000..d52716a
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:14
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:05-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/bcd_to_display/db/bcd_to_display.vpr.ammdb b/bcd_to_display/db/bcd_to_display.vpr.ammdb
new file mode 100644
index 0000000..3e42627
--- /dev/null
+++ b/bcd_to_display/db/bcd_to_display.vpr.ammdb
diff --git a/bcd_to_display/db/logic_util_heursitic.dat b/bcd_to_display/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..79765b7
--- /dev/null
+++ b/bcd_to_display/db/logic_util_heursitic.dat
diff --git a/bcd_to_display/incremental_db/README b/bcd_to_display/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/bcd_to_display/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.db_info b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.db_info
new file mode 100644
index 0000000..e7725f1
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 14:08:18 2016
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.ammdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.ammdb
new file mode 100644
index 0000000..1deeb1f
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.ammdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.cdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.cdb
new file mode 100644
index 0000000..82f6673
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.cdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.dfp b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.dfp
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.hdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.hdb
new file mode 100644
index 0000000..3ec4f79
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.hdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.kpt b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.kpt
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.logdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.rcfdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..95a25fb
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.cmp.rcfdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.cdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.cdb
new file mode 100644
index 0000000..9094ff4
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.cdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.dpi b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.dpi
new file mode 100644
index 0000000..029adfc
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.dpi
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.cdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..97cfdcc
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.cdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hb_info b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hb_info
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..ef792c8
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.hdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.sig b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hdb b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hdb
new file mode 100644
index 0000000..66d30cd
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.hdb
diff --git a/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.kpt b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.kpt
new file mode 100644
index 0000000..90fbb23
--- /dev/null
+++ b/bcd_to_display/incremental_db/compiled_partitions/bcd_to_display.root_partition.map.kpt
diff --git a/bcd_to_display/output_files/bcd_to_display.asm.rpt b/bcd_to_display/output_files/bcd_to_display.asm.rpt
new file mode 100644
index 0000000..cbb8556
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for bcd_to_display
+Fri Feb 26 16:37:01 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Git/bcd_to_display/output_files/bcd_to_display.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 26 16:37:01 2016 ;
+; Revision Name         ; bcd_to_display                        ;
+; Top-level Entity Name ; bcd_to_display                        ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------------------------+
+; Assembler Generated Files                             ;
++-------------------------------------------------------+
+; File Name                                             ;
++-------------------------------------------------------+
+; C:/Git/bcd_to_display/output_files/bcd_to_display.sof ;
++-------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Git/bcd_to_display/output_files/bcd_to_display.sof ;
++----------------+----------------------------------------------------------------+
+; Option         ; Setting                                                        ;
++----------------+----------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                   ;
+; JTAG usercode  ; 0x000C93D9                                                     ;
+; Checksum       ; 0x000C93D9                                                     ;
++----------------+----------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:00 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 419 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:01 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.done b/bcd_to_display/output_files/bcd_to_display.done
new file mode 100644
index 0000000..c4998ba
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.done
@@ -0,0 +1 @@
+Fri Feb 26 16:37:07 2016
diff --git a/bcd_to_display/output_files/bcd_to_display.eda.rpt b/bcd_to_display/output_files/bcd_to_display.eda.rpt
new file mode 100644
index 0000000..ca43667
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.eda.rpt
@@ -0,0 +1,92 @@
+EDA Netlist Writer report for bcd_to_display
+Fri Feb 26 16:37:06 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb 26 16:37:06 2016 ;
+; Revision Name             ; bcd_to_display                        ;
+; Top-level Entity Name     ; bcd_to_display                        ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate netlist for functional simulation only                                                   ; On                        ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++-------------------------------------------------------------+
+; Simulation Generated Files                                  ;
++-------------------------------------------------------------+
+; Generated Files                                             ;
++-------------------------------------------------------------+
+; C:/Git/bcd_to_display/simulation/modelsim/bcd_to_display.vo ;
++-------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:05 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display
+Info (204019): Generated file bcd_to_display.vo in folder "C:/Git/bcd_to_display/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 384 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:06 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.fit.rpt b/bcd_to_display/output_files/bcd_to_display.fit.rpt
new file mode 100644
index 0000000..23e9d1e
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.fit.rpt
@@ -0,0 +1,1270 @@
+Fitter report for bcd_to_display
+Fri Feb 26 16:36:59 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Other Routing Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. I/O Rules Summary
+ 27. I/O Rules Details
+ 28. I/O Rules Matrix
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 26 16:36:59 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; bcd_to_display                                   ;
+; Top-level Entity Name              ; bcd_to_display                                   ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 7 / 15,408 ( < 1 % )                             ;
+;     Total combinational functions  ; 7 / 15,408 ( < 1 % )                             ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                               ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 11 / 347 ( 3 % )                                 ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------+
+; I/O Assignment Warnings                    ;
++------------+-------------------------------+
+; Pin Name   ; Reason                        ;
++------------+-------------------------------+
+; DISPout[6] ; Incomplete set of assignments ;
+; DISPout[5] ; Incomplete set of assignments ;
+; DISPout[4] ; Incomplete set of assignments ;
+; DISPout[3] ; Incomplete set of assignments ;
+; DISPout[2] ; Incomplete set of assignments ;
+; DISPout[1] ; Incomplete set of assignments ;
+; DISPout[0] ; Incomplete set of assignments ;
+; BCDin[3]   ; Incomplete set of assignments ;
+; BCDin[1]   ; Incomplete set of assignments ;
+; BCDin[2]   ; Incomplete set of assignments ;
+; BCDin[0]   ; Incomplete set of assignments ;
++------------+-------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 40 ( 0.00 % )      ;
+;     -- Achieved     ; 0 / 40 ( 0.00 % )      ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 30      ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Git/bcd_to_display/output_files/bcd_to_display.pin.
+
+
++--------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                      ;
++---------------------------------------------+----------------------+
+; Resource                                    ; Usage                ;
++---------------------------------------------+----------------------+
+; Total logic elements                        ; 7 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 7                    ;
+;     -- Register only                        ; 0                    ;
+;     -- Combinational with a register        ; 0                    ;
+;                                             ;                      ;
+; Logic element usage by number of LUT inputs ;                      ;
+;     -- 4 input functions                    ; 5                    ;
+;     -- 3 input functions                    ; 2                    ;
+;     -- <=2 input functions                  ; 0                    ;
+;     -- Register only                        ; 0                    ;
+;                                             ;                      ;
+; Logic elements by mode                      ;                      ;
+;     -- normal mode                          ; 7                    ;
+;     -- arithmetic mode                      ; 0                    ;
+;                                             ;                      ;
+; Total registers*                            ; 0 / 17,068 ( 0 % )   ;
+;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )   ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )    ;
+;                                             ;                      ;
+; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ;
+; Virtual pins                                ; 0                    ;
+; I/O pins                                    ; 11 / 347 ( 3 % )     ;
+;     -- Clock pins                           ; 0 / 8 ( 0 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )        ;
+;                                             ;                      ;
+; Global signals                              ; 0                    ;
+; M9Ks                                        ; 0 / 56 ( 0 % )       ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
+; PLLs                                        ; 0 / 4 ( 0 % )        ;
+; Global clocks                               ; 0 / 20 ( 0 % )       ;
+; JTAGs                                       ; 0 / 1 ( 0 % )        ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
+; Maximum fan-out                             ; 7                    ;
+; Highest non-global fan-out                  ; 7                    ;
+; Total fan-out                               ; 49                   ;
+; Average fan-out                             ; 1.26                 ;
++---------------------------------------------+----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                        ;
++---------------------------------------------+---------------------+--------------------------------+
+; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
++---------------------------------------------+---------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                 ; Low                            ;
+;                                             ;                     ;                                ;
+; Total logic elements                        ; 7 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 7                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;     -- Combinational with a register        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic element usage by number of LUT inputs ;                     ;                                ;
+;     -- 4 input functions                    ; 5                   ; 0                              ;
+;     -- 3 input functions                    ; 2                   ; 0                              ;
+;     -- <=2 input functions                  ; 0                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic elements by mode                      ;                     ;                                ;
+;     -- normal mode                          ; 7                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Total registers                             ; 0                   ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )   ; 0 / 15408 ( 0 % )              ;
+;                                             ;                     ;                                ;
+; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )   ; 0 / 963 ( 0 % )                ;
+;                                             ;                     ;                                ;
+; Virtual pins                                ; 0                   ; 0                              ;
+; I/O pins                                    ; 11                  ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                   ; 0                              ;
+; Total RAM block bits                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Connections                                 ;                     ;                                ;
+;     -- Input Connections                    ; 0                   ; 0                              ;
+;     -- Registered Input Connections         ; 0                   ; 0                              ;
+;     -- Output Connections                   ; 0                   ; 0                              ;
+;     -- Registered Output Connections        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Internal Connections                        ;                     ;                                ;
+;     -- Total Connections                    ; 44                  ; 5                              ;
+;     -- Registered Connections               ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; External Connections                        ;                     ;                                ;
+;     -- Top                                  ; 0                   ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Partition Interface                         ;                     ;                                ;
+;     -- Input Ports                          ; 4                   ; 0                              ;
+;     -- Output Ports                         ; 7                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Registered Ports                            ;                     ;                                ;
+;     -- Registered Input Ports               ; 0                   ; 0                              ;
+;     -- Registered Output Ports              ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Port Connectivity                           ;                     ;                                ;
+;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
++---------------------------------------------+---------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                    ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; BCDin[0] ; V2    ; 2        ; 0            ; 9            ; 21           ; 7                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; BCDin[1] ; M7    ; 2        ; 0            ; 8            ; 21           ; 7                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; BCDin[2] ; V1    ; 2        ; 0            ; 8            ; 0            ; 7                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
+; BCDin[3] ; P7    ; 2        ; 0            ; 5            ; 0            ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DISPout[0] ; F1    ; 1        ; 0            ; 23           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[1] ; U2    ; 2        ; 0            ; 9            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[2] ; N7    ; 2        ; 0            ; 6            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[3] ; N6    ; 2        ; 0            ; 8            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[4] ; N5    ; 2        ; 0            ; 10           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[5] ; M4    ; 2        ; 0            ; 12           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; DISPout[6] ; P5    ; 2        ; 0            ; 8            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 5 / 33 ( 15 % )  ; 2.5V          ; --           ;
+; 2        ; 10 / 48 ( 21 % ) ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; DISPout[0]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; DISPout[5]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; BCDin[1]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; DISPout[4]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N6       ; 64         ; 2        ; DISPout[3]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N7       ; 73         ; 2        ; DISPout[2]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; DISPout[6]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; BCDin[3]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; DISPout[1]                                                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; BCDin[2]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; V2       ; 61         ; 2        ; BCDin[0]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |bcd_to_display            ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 11   ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |bcd_to_display     ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                        ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; DISPout[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DISPout[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; BCDin[3]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; BCDin[1]   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; BCDin[2]   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; BCDin[0]   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; BCDin[3]            ;                   ;         ;
+;      - inst1~0      ; 0                 ; 6       ;
+;      - inst2~0      ; 0                 ; 6       ;
+;      - inst5~0      ; 0                 ; 6       ;
+;      - inst6~0      ; 0                 ; 6       ;
+;      - inst8~0      ; 0                 ; 6       ;
+; BCDin[1]            ;                   ;         ;
+;      - inst1~0      ; 1                 ; 6       ;
+;      - inst2~0      ; 1                 ; 6       ;
+;      - inst12~0     ; 1                 ; 6       ;
+;      - inst5~0      ; 1                 ; 6       ;
+;      - inst6~0      ; 1                 ; 6       ;
+;      - inst7        ; 1                 ; 6       ;
+;      - inst8~0      ; 1                 ; 6       ;
+; BCDin[2]            ;                   ;         ;
+;      - inst1~0      ; 0                 ; 6       ;
+;      - inst2~0      ; 0                 ; 6       ;
+;      - inst12~0     ; 0                 ; 6       ;
+;      - inst5~0      ; 0                 ; 6       ;
+;      - inst6~0      ; 0                 ; 6       ;
+;      - inst7        ; 0                 ; 6       ;
+;      - inst8~0      ; 0                 ; 6       ;
+; BCDin[0]            ;                   ;         ;
+;      - inst1~0      ; 1                 ; 6       ;
+;      - inst2~0      ; 1                 ; 6       ;
+;      - inst12~0     ; 1                 ; 6       ;
+;      - inst5~0      ; 1                 ; 6       ;
+;      - inst6~0      ; 1                 ; 6       ;
+;      - inst7        ; 1                 ; 6       ;
+;      - inst8~0      ; 1                 ; 6       ;
++---------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++----------------+----------------+
+; Name           ; Fan-Out        ;
++----------------+----------------+
+; BCDin[0]~input ; 7              ;
+; BCDin[2]~input ; 7              ;
+; BCDin[1]~input ; 7              ;
+; BCDin[3]~input ; 5              ;
+; inst8~0        ; 1              ;
+; inst7          ; 1              ;
+; inst6~0        ; 1              ;
+; inst5~0        ; 1              ;
+; inst12~0       ; 1              ;
+; inst2~0        ; 1              ;
+; inst1~0        ; 1              ;
++----------------+----------------+
+
+
++-----------------------------------------------------+
+; Other Routing Usage Summary                         ;
++-----------------------------+-----------------------+
+; Other Routing Resource Type ; Usage                 ;
++-----------------------------+-----------------------+
+; Block interconnects         ; 11 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 1 / 1,804 ( < 1 % )   ;
+; C4 interconnects            ; 7 / 31,272 ( < 1 % )  ;
+; Direct links                ; 2 / 47,787 ( < 1 % )  ;
+; Global clocks               ; 0 / 20 ( 0 % )        ;
+; Local interconnects         ; 0 / 15,408 ( 0 % )    ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects            ; 1 / 41,310 ( < 1 % )  ;
++-----------------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements                                                       ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 7.00) ; Number of LABs  (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1                                          ; 0                           ;
+; 2                                          ; 0                           ;
+; 3                                          ; 0                           ;
+; 4                                          ; 0                           ;
+; 5                                          ; 0                           ;
+; 6                                          ; 0                           ;
+; 7                                          ; 1                           ;
+; 8                                          ; 0                           ;
+; 9                                          ; 0                           ;
+; 10                                         ; 0                           ;
+; 11                                         ; 0                           ;
+; 12                                         ; 0                           ;
+; 13                                         ; 0                           ;
+; 14                                         ; 0                           ;
+; 15                                         ; 0                           ;
+; 16                                         ; 0                           ;
++--------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Signals Sourced                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 7.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 7.00) ; Number of LABs  (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 4.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 11        ; 0            ; 0            ; 11        ; 11        ; 0            ; 7            ; 0            ; 0            ; 4            ; 0            ; 7            ; 4            ; 0            ; 0            ; 0            ; 7            ; 0            ; 0            ; 0            ; 0            ; 0            ; 11        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 11           ; 11           ; 11           ; 11           ; 11           ; 0         ; 11           ; 11           ; 0         ; 0         ; 11           ; 4            ; 11           ; 11           ; 7            ; 11           ; 4            ; 7            ; 11           ; 11           ; 11           ; 4            ; 11           ; 11           ; 11           ; 11           ; 11           ; 0         ; 11           ; 11           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DISPout[6]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[5]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[4]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[3]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[2]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[1]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DISPout[0]         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BCDin[3]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BCDin[1]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BCDin[2]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BCDin[0]           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "bcd_to_display"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 11 pins of 11 total pins
+    Info (169086): Pin DISPout[6] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[5] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[4] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[3] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[2] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[1] not assigned to an exact location on the device
+    Info (169086): Pin DISPout[0] not assigned to an exact location on the device
+    Info (169086): Pin BCDin[3] not assigned to an exact location on the device
+    Info (169086): Pin BCDin[1] not assigned to an exact location on the device
+    Info (169086): Pin BCDin[2] not assigned to an exact location on the device
+    Info (169086): Pin BCDin[0] not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'bcd_to_display.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 11 (unused VREF, 2.5V VCCIO, 4 input, 7 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  29 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.12 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Git/bcd_to_display/output_files/bcd_to_display.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 1068 megabytes
+    Info: Processing ended: Fri Feb 26 16:36:59 2016
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:05
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Git/bcd_to_display/output_files/bcd_to_display.fit.smsg.
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.fit.smsg b/bcd_to_display/output_files/bcd_to_display.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/bcd_to_display/output_files/bcd_to_display.fit.summary b/bcd_to_display/output_files/bcd_to_display.fit.summary
new file mode 100644
index 0000000..c923f36
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Fri Feb 26 16:36:59 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : bcd_to_display
+Top-level Entity Name : bcd_to_display
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 7 / 15,408 ( < 1 % )
+    Total combinational functions : 7 / 15,408 ( < 1 % )
+    Dedicated logic registers : 0 / 15,408 ( 0 % )
+Total registers : 0
+Total pins : 11 / 347 ( 3 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/bcd_to_display/output_files/bcd_to_display.flow.rpt b/bcd_to_display/output_files/bcd_to_display.flow.rpt
new file mode 100644
index 0000000..db23ecd
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for bcd_to_display
+Fri Feb 26 16:37:06 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 26 16:37:06 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; bcd_to_display                                   ;
+; Top-level Entity Name              ; bcd_to_display                                   ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 7 / 15,408 ( < 1 % )                             ;
+;     Total combinational functions  ; 7 / 15,408 ( < 1 % )                             ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                               ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 11 / 347 ( 3 % )                                 ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/26/2016 16:36:54 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; bcd_to_display      ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297093.145650461403352 ; --            ; --          ; --             ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; On                              ; --            ; --          ; eda_simulation ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                     ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)       ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 464 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:04     ; 1.0                     ; 1068 MB             ; 00:00:04                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 419 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 476 MB              ; 00:00:01                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 372 MB              ; 00:00:00                           ;
+; Total                     ; 00:00:10     ; --                      ; --                  ; 00:00:07                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off bcd_to_display -c bcd_to_display
+quartus_fit --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display
+quartus_asm --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display
+quartus_sta bcd_to_display -c bcd_to_display
+quartus_eda --read_settings_files=off --write_settings_files=off bcd_to_display -c bcd_to_display
+
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.jdi b/bcd_to_display/output_files/bcd_to_display.jdi
new file mode 100644
index 0000000..9d338b7
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="1e38f6c232c64bcab382"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="bcd_to_display.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/bcd_to_display/output_files/bcd_to_display.map.rpt b/bcd_to_display/output_files/bcd_to_display.map.rpt
new file mode 100644
index 0000000..d0a7598
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.map.rpt
@@ -0,0 +1,263 @@
+Analysis & Synthesis report for bcd_to_display
+Fri Feb 26 16:36:54 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 26 16:36:54 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; bcd_to_display                                   ;
+; Top-level Entity Name              ; bcd_to_display                                   ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 7                                                ;
+;     Total combinational functions  ; 7                                                ;
+;     Dedicated logic registers      ; 0                                                ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 11                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; bcd_to_display     ; bcd_to_display     ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                       ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path             ; Library ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------+---------+
+; bcd_to_display.bdf               ; yes             ; User Block Diagram/Schematic File  ; C:/Git/bcd_to_display/bcd_to_display.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimated Total logic elements              ; 7              ;
+;                                             ;                ;
+; Total combinational functions               ; 7              ;
+; Logic element usage by number of LUT inputs ;                ;
+;     -- 4 input functions                    ; 5              ;
+;     -- 3 input functions                    ; 2              ;
+;     -- <=2 input functions                  ; 0              ;
+;                                             ;                ;
+; Logic elements by mode                      ;                ;
+;     -- normal mode                          ; 7              ;
+;     -- arithmetic mode                      ; 0              ;
+;                                             ;                ;
+; Total registers                             ; 0              ;
+;     -- Dedicated logic registers            ; 0              ;
+;     -- I/O registers                        ; 0              ;
+;                                             ;                ;
+; I/O pins                                    ; 11             ;
+; Embedded Multiplier 9-bit elements          ; 0              ;
+; Maximum fan-out node                        ; BCDin[1]~input ;
+; Maximum fan-out                             ; 7              ;
+; Total fan-out                               ; 44             ;
+; Average fan-out                             ; 1.52           ;
++---------------------------------------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |bcd_to_display            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 11   ; 0            ; |bcd_to_display     ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:36:53 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bcd_to_display -c bcd_to_display
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file bcd_to_display.bdf
+    Info (12023): Found entity 1: bcd_to_display
+Info (12127): Elaborating entity "bcd_to_display" for the top level hierarchy
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 18 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 4 input pins
+    Info (21059): Implemented 7 output pins
+    Info (21061): Implemented 7 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 464 megabytes
+    Info: Processing ended: Fri Feb 26 16:36:54 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.map.summary b/bcd_to_display/output_files/bcd_to_display.map.summary
new file mode 100644
index 0000000..cf02d3b
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Fri Feb 26 16:36:54 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : bcd_to_display
+Top-level Entity Name : bcd_to_display
+Family : Cyclone III
+Total logic elements : 7
+    Total combinational functions : 7
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 11
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/bcd_to_display/output_files/bcd_to_display.pin b/bcd_to_display/output_files/bcd_to_display.pin
new file mode 100644
index 0000000..838e13f
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "bcd_to_display"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+DISPout[0]                   : F1        : output : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+DISPout[5]                   : M4        : output : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+BCDin[1]                     : M7        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+DISPout[4]                   : N5        : output : 2.5 V             :         : 2         : N              
+DISPout[3]                   : N6        : output : 2.5 V             :         : 2         : N              
+DISPout[2]                   : N7        : output : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+DISPout[6]                   : P5        : output : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+BCDin[3]                     : P7        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+DISPout[1]                   : U2        : output : 2.5 V             :         : 2         : N              
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+BCDin[2]                     : V1        : input  : 2.5 V             :         : 2         : N              
+BCDin[0]                     : V2        : input  : 2.5 V             :         : 2         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/bcd_to_display/output_files/bcd_to_display.sof b/bcd_to_display/output_files/bcd_to_display.sof
new file mode 100644
index 0000000..f7f51cb
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.sof
diff --git a/bcd_to_display/output_files/bcd_to_display.sta.rpt b/bcd_to_display/output_files/bcd_to_display.sta.rpt
new file mode 100644
index 0000000..f257f10
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.sta.rpt
@@ -0,0 +1,676 @@
+TimeQuest Timing Analyzer report for bcd_to_display
+Fri Feb 26 16:37:05 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Progagation Delay
+ 34. Minimum Progagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Slow Corner Signal Integrity Metrics
+ 38. Fast Corner Signal Integrity Metrics
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths
+ 43. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; bcd_to_display                                                     ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 7.077 ; 7.052 ; 7.481 ; 7.465 ;
+; BCDin[0]   ; DISPout[1]  ; 6.563 ; 6.586 ; 6.973 ; 7.005 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 6.563 ; 6.944 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 6.246 ; 6.261 ; 6.657 ; 6.681 ;
+; BCDin[0]   ; DISPout[4]  ; 6.408 ;       ;       ; 6.881 ;
+; BCDin[0]   ; DISPout[5]  ; 6.553 ;       ;       ; 6.963 ;
+; BCDin[0]   ; DISPout[6]  ; 6.139 ;       ;       ; 6.606 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 6.998 ; 7.482 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 6.555 ; 6.481 ; 6.913 ; 6.996 ;
+; BCDin[1]   ; DISPout[2]  ; 6.517 ;       ;       ; 6.940 ;
+; BCDin[1]   ; DISPout[3]  ; 6.184 ; 6.208 ; 6.658 ; 6.630 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 6.407 ; 6.819 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 6.531 ;       ;       ; 6.928 ;
+; BCDin[1]   ; DISPout[6]  ; 6.075 ; 6.144 ; 6.530 ; 6.556 ;
+; BCDin[2]   ; DISPout[0]  ; 7.093 ; 6.995 ; 7.436 ; 7.465 ;
+; BCDin[2]   ; DISPout[1]  ; 6.588 ;       ;       ; 7.019 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 6.544 ; 6.983 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 6.271 ; 6.213 ; 6.616 ; 6.685 ;
+; BCDin[2]   ; DISPout[4]  ; 6.432 ;       ;       ; 6.882 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 6.536 ; 7.005 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 6.119 ; 6.192 ; 6.572 ; 6.587 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 7.093 ; 7.569 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 6.606 ; 7.032 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 6.309 ; 6.747 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 6.596 ; 7.054 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 6.237 ; 6.640 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 6.909 ; 6.886 ; 7.302 ; 7.288 ;
+; BCDin[0]   ; DISPout[1]  ; 6.416 ; 6.439 ; 6.814 ; 6.846 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 6.415 ; 6.785 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 6.109 ; 6.125 ; 6.508 ; 6.533 ;
+; BCDin[0]   ; DISPout[4]  ; 6.261 ;       ;       ; 6.722 ;
+; BCDin[0]   ; DISPout[5]  ; 6.404 ;       ;       ; 6.804 ;
+; BCDin[0]   ; DISPout[6]  ; 6.003 ;       ;       ; 6.459 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 6.793 ; 7.221 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 6.400 ; 6.335 ; 6.749 ; 6.821 ;
+; BCDin[1]   ; DISPout[2]  ; 6.369 ;       ;       ; 6.780 ;
+; BCDin[1]   ; DISPout[3]  ; 6.048 ; 6.033 ; 6.428 ; 6.483 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 6.248 ; 6.633 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 6.340 ;       ;       ; 6.755 ;
+; BCDin[1]   ; DISPout[6]  ; 5.940 ; 5.958 ; 6.321 ; 6.409 ;
+; BCDin[2]   ; DISPout[0]  ; 6.924 ; 6.830 ; 7.259 ; 7.287 ;
+; BCDin[2]   ; DISPout[1]  ; 6.366 ;       ;       ; 6.792 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 6.396 ; 6.822 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 6.088 ; 6.078 ; 6.469 ; 6.512 ;
+; BCDin[2]   ; DISPout[4]  ; 6.256 ;       ;       ; 6.709 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 6.353 ; 6.765 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 5.983 ; 6.006 ; 6.364 ; 6.440 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 6.921 ; 7.383 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 6.454 ; 6.867 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 6.167 ; 6.592 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 6.441 ; 6.887 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 6.094 ; 6.486 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 6.545 ; 6.578 ; 6.884 ; 6.925 ;
+; BCDin[0]   ; DISPout[1]  ; 6.091 ; 6.133 ; 6.436 ; 6.486 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 6.110 ; 6.417 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 5.805 ; 5.834 ; 6.144 ; 6.181 ;
+; BCDin[0]   ; DISPout[4]  ; 5.951 ;       ;       ; 6.363 ;
+; BCDin[0]   ; DISPout[5]  ; 6.073 ;       ;       ; 6.445 ;
+; BCDin[0]   ; DISPout[6]  ; 5.697 ;       ;       ; 6.110 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 6.506 ; 6.872 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 6.062 ; 6.016 ; 6.365 ; 6.459 ;
+; BCDin[1]   ; DISPout[2]  ; 6.039 ;       ;       ; 6.410 ;
+; BCDin[1]   ; DISPout[3]  ; 5.725 ; 5.762 ; 6.133 ; 6.120 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 5.936 ; 6.279 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 6.035 ;       ;       ; 6.396 ;
+; BCDin[1]   ; DISPout[6]  ; 5.616 ; 5.698 ; 6.010 ; 6.046 ;
+; BCDin[2]   ; DISPout[0]  ; 6.530 ; 6.496 ; 6.832 ; 6.911 ;
+; BCDin[2]   ; DISPout[1]  ; 6.081 ;       ;       ; 6.483 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 6.058 ; 6.440 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 5.795 ; 5.757 ; 6.099 ; 6.174 ;
+; BCDin[2]   ; DISPout[4]  ; 5.941 ;       ;       ; 6.348 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 6.048 ; 6.445 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 5.643 ; 5.729 ; 6.052 ; 6.080 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 6.601 ; 6.948 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 6.135 ; 6.481 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 5.862 ; 6.214 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 6.124 ; 6.486 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 5.788 ; 6.109 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 6.401 ; 6.433 ; 6.732 ; 6.770 ;
+; BCDin[0]   ; DISPout[1]  ; 5.965 ; 6.006 ; 6.302 ; 6.349 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 5.984 ; 6.283 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 5.690 ; 5.718 ; 6.021 ; 6.055 ;
+; BCDin[0]   ; DISPout[4]  ; 5.825 ;       ;       ; 6.227 ;
+; BCDin[0]   ; DISPout[5]  ; 5.945 ;       ;       ; 6.308 ;
+; BCDin[0]   ; DISPout[6]  ; 5.580 ;       ;       ; 5.984 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 6.330 ; 6.647 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 5.933 ; 5.892 ; 6.229 ; 6.312 ;
+; BCDin[1]   ; DISPout[2]  ; 5.913 ;       ;       ; 6.274 ;
+; BCDin[1]   ; DISPout[3]  ; 5.612 ; 5.615 ; 5.937 ; 5.996 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 5.802 ; 6.122 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 5.868 ;       ;       ; 6.247 ;
+; BCDin[1]   ; DISPout[6]  ; 5.503 ; 5.539 ; 5.830 ; 5.922 ;
+; BCDin[2]   ; DISPout[0]  ; 6.387 ; 6.354 ; 6.680 ; 6.755 ;
+; BCDin[2]   ; DISPout[1]  ; 5.895 ;       ;       ; 6.286 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 5.934 ; 6.304 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 5.637 ; 5.644 ; 5.977 ; 6.028 ;
+; BCDin[2]   ; DISPout[4]  ; 5.793 ;       ;       ; 6.203 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 5.895 ; 6.238 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 5.530 ; 5.570 ; 5.872 ; 5.956 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 6.451 ; 6.789 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 6.005 ; 6.341 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 5.740 ; 6.085 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 5.992 ; 6.344 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 5.666 ; 5.978 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 4.294 ; 4.227 ; 4.864 ; 4.804 ;
+; BCDin[0]   ; DISPout[1]  ; 3.983 ; 3.961 ; 4.553 ; 4.538 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 3.942 ; 4.528 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 3.763 ; 3.760 ; 4.333 ; 4.337 ;
+; BCDin[0]   ; DISPout[4]  ; 3.874 ;       ;       ; 4.393 ;
+; BCDin[0]   ; DISPout[5]  ; 3.954 ;       ;       ; 4.511 ;
+; BCDin[0]   ; DISPout[6]  ; 3.695 ;       ;       ; 4.233 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 4.173 ; 4.819 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 3.951 ; 3.879 ; 4.478 ; 4.497 ;
+; BCDin[1]   ; DISPout[2]  ; 3.913 ;       ;       ; 4.454 ;
+; BCDin[1]   ; DISPout[3]  ; 3.698 ; 3.706 ; 4.288 ; 4.268 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 3.763 ; 4.399 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 3.912 ;       ;       ; 4.449 ;
+; BCDin[1]   ; DISPout[6]  ; 3.631 ; 3.610 ; 4.205 ; 4.165 ;
+; BCDin[2]   ; DISPout[0]  ; 4.269 ; 4.169 ; 4.800 ; 4.770 ;
+; BCDin[2]   ; DISPout[1]  ; 3.968 ;       ;       ; 4.517 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 3.908 ; 4.512 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 3.743 ; 3.707 ; 4.277 ; 4.311 ;
+; BCDin[2]   ; DISPout[4]  ; 3.852 ;       ;       ; 4.365 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 3.910 ; 4.519 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 3.657 ; 3.637 ; 4.247 ; 4.200 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 4.232 ; 4.880 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 3.948 ; 4.545 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 3.770 ; 4.354 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 3.951 ; 4.551 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 3.670 ; 4.290 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 4.194 ; 4.129 ; 4.758 ; 4.700 ;
+; BCDin[0]   ; DISPout[1]  ; 3.896 ; 3.874 ; 4.460 ; 4.445 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 3.855 ; 4.434 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 3.683 ; 3.679 ; 4.247 ; 4.250 ;
+; BCDin[0]   ; DISPout[4]  ; 3.786 ;       ;       ; 4.300 ;
+; BCDin[0]   ; DISPout[5]  ; 3.866 ;       ;       ; 4.417 ;
+; BCDin[0]   ; DISPout[6]  ; 3.615 ;       ;       ; 4.148 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 4.054 ; 4.666 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 3.859 ; 3.794 ; 4.384 ; 4.396 ;
+; BCDin[1]   ; DISPout[2]  ; 3.826 ;       ;       ; 4.363 ;
+; BCDin[1]   ; DISPout[3]  ; 3.619 ; 3.604 ; 4.155 ; 4.183 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 3.669 ; 4.292 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 3.804 ;       ;       ; 4.353 ;
+; BCDin[1]   ; DISPout[6]  ; 3.551 ; 3.502 ; 4.087 ; 4.081 ;
+; BCDin[2]   ; DISPout[0]  ; 4.170 ; 4.074 ; 4.696 ; 4.668 ;
+; BCDin[2]   ; DISPout[1]  ; 3.839 ;       ;       ; 4.383 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 3.823 ; 4.417 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 3.643 ; 3.629 ; 4.193 ; 4.214 ;
+; BCDin[2]   ; DISPout[4]  ; 3.753 ;       ;       ; 4.268 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 3.802 ; 4.381 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 3.578 ; 3.530 ; 4.128 ; 4.115 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 4.132 ; 4.771 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 3.859 ; 4.448 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 3.687 ; 4.265 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 3.861 ; 4.454 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 3.589 ; 4.201 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++----------------------------------------------------------+
+; Progagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 7.077 ; 7.052 ; 7.481 ; 7.465 ;
+; BCDin[0]   ; DISPout[1]  ; 6.563 ; 6.586 ; 6.973 ; 7.005 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 6.563 ; 6.944 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 6.246 ; 6.261 ; 6.657 ; 6.681 ;
+; BCDin[0]   ; DISPout[4]  ; 6.408 ;       ;       ; 6.881 ;
+; BCDin[0]   ; DISPout[5]  ; 6.553 ;       ;       ; 6.963 ;
+; BCDin[0]   ; DISPout[6]  ; 6.139 ;       ;       ; 6.606 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 6.998 ; 7.482 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 6.555 ; 6.481 ; 6.913 ; 6.996 ;
+; BCDin[1]   ; DISPout[2]  ; 6.517 ;       ;       ; 6.940 ;
+; BCDin[1]   ; DISPout[3]  ; 6.184 ; 6.208 ; 6.658 ; 6.630 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 6.407 ; 6.819 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 6.531 ;       ;       ; 6.928 ;
+; BCDin[1]   ; DISPout[6]  ; 6.075 ; 6.144 ; 6.530 ; 6.556 ;
+; BCDin[2]   ; DISPout[0]  ; 7.093 ; 6.995 ; 7.436 ; 7.465 ;
+; BCDin[2]   ; DISPout[1]  ; 6.588 ;       ;       ; 7.019 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 6.544 ; 6.983 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 6.271 ; 6.213 ; 6.616 ; 6.685 ;
+; BCDin[2]   ; DISPout[4]  ; 6.432 ;       ;       ; 6.882 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 6.536 ; 7.005 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 6.119 ; 6.192 ; 6.572 ; 6.587 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 7.093 ; 7.569 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 6.606 ; 7.032 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 6.309 ; 6.747 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 6.596 ; 7.054 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 6.237 ; 6.640 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Progagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; BCDin[0]   ; DISPout[0]  ; 4.194 ; 4.129 ; 4.758 ; 4.700 ;
+; BCDin[0]   ; DISPout[1]  ; 3.896 ; 3.874 ; 4.460 ; 4.445 ;
+; BCDin[0]   ; DISPout[2]  ;       ; 3.855 ; 4.434 ;       ;
+; BCDin[0]   ; DISPout[3]  ; 3.683 ; 3.679 ; 4.247 ; 4.250 ;
+; BCDin[0]   ; DISPout[4]  ; 3.786 ;       ;       ; 4.300 ;
+; BCDin[0]   ; DISPout[5]  ; 3.866 ;       ;       ; 4.417 ;
+; BCDin[0]   ; DISPout[6]  ; 3.615 ;       ;       ; 4.148 ;
+; BCDin[1]   ; DISPout[0]  ;       ; 4.054 ; 4.666 ;       ;
+; BCDin[1]   ; DISPout[1]  ; 3.859 ; 3.794 ; 4.384 ; 4.396 ;
+; BCDin[1]   ; DISPout[2]  ; 3.826 ;       ;       ; 4.363 ;
+; BCDin[1]   ; DISPout[3]  ; 3.619 ; 3.604 ; 4.155 ; 4.183 ;
+; BCDin[1]   ; DISPout[4]  ;       ; 3.669 ; 4.292 ;       ;
+; BCDin[1]   ; DISPout[5]  ; 3.804 ;       ;       ; 4.353 ;
+; BCDin[1]   ; DISPout[6]  ; 3.551 ; 3.502 ; 4.087 ; 4.081 ;
+; BCDin[2]   ; DISPout[0]  ; 4.170 ; 4.074 ; 4.696 ; 4.668 ;
+; BCDin[2]   ; DISPout[1]  ; 3.839 ;       ;       ; 4.383 ;
+; BCDin[2]   ; DISPout[2]  ;       ; 3.823 ; 4.417 ;       ;
+; BCDin[2]   ; DISPout[3]  ; 3.643 ; 3.629 ; 4.193 ; 4.214 ;
+; BCDin[2]   ; DISPout[4]  ; 3.753 ;       ;       ; 4.268 ;
+; BCDin[2]   ; DISPout[5]  ;       ; 3.802 ; 4.381 ;       ;
+; BCDin[2]   ; DISPout[6]  ; 3.578 ; 3.530 ; 4.128 ; 4.115 ;
+; BCDin[3]   ; DISPout[0]  ;       ; 4.132 ; 4.771 ;       ;
+; BCDin[3]   ; DISPout[2]  ;       ; 3.859 ; 4.448 ;       ;
+; BCDin[3]   ; DISPout[3]  ;       ; 3.687 ; 4.265 ;       ;
+; BCDin[3]   ; DISPout[5]  ;       ; 3.861 ; 4.454 ;       ;
+; BCDin[3]   ; DISPout[6]  ;       ; 3.589 ; 4.201 ;       ;
++------------+-------------+-------+-------+-------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DISPout[6]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[5]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[4]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[3]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[2]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[1]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DISPout[0]    ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; BCDin[3]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; BCDin[1]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; BCDin[2]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; BCDin[0]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DISPout[6]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
+; DISPout[5]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; DISPout[4]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.36 V              ; -0.00946 V          ; 0.111 V                              ; 0.027 V                              ; 6.46e-10 s                  ; 6.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.36 V             ; -0.00946 V         ; 0.111 V                             ; 0.027 V                             ; 6.46e-10 s                 ; 6.2e-10 s                  ; Yes                       ; Yes                       ;
+; DISPout[3]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; DISPout[2]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; DISPout[1]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; DISPout[0]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DISPout[6]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; DISPout[5]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; DISPout[4]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.72 V              ; -0.0408 V           ; 0.163 V                              ; 0.075 V                              ; 4.51e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.72 V             ; -0.0408 V          ; 0.163 V                             ; 0.075 V                             ; 4.51e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; DISPout[3]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; DISPout[2]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; DISPout[1]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; DISPout[0]    ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 4     ; 4    ;
+; Unconstrained Input Port Paths  ; 26    ; 26   ;
+; Unconstrained Output Ports      ; 7     ; 7    ;
+; Unconstrained Output Port Paths ; 26    ; 26   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:02 2016
+Info: Command: quartus_sta bcd_to_display -c bcd_to_display
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'bcd_to_display.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 476 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:05 2016
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/bcd_to_display/output_files/bcd_to_display.sta.summary b/bcd_to_display/output_files/bcd_to_display.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/bcd_to_display/output_files/bcd_to_display.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display.sft b/bcd_to_display/simulation/modelsim/bcd_to_display.sft
new file mode 100644
index 0000000..06a2ca4
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display.vho b/bcd_to_display/simulation/modelsim/bcd_to_display.vho
new file mode 100644
index 0000000..48e1fa7
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display.vho
@@ -0,0 +1,355 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 15:29:32"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	bcd_to_display IS
+    PORT (
+	DISPout : OUT std_logic_vector(6 DOWNTO 0);
+	BCDin : IN std_logic_vector(3 DOWNTO 0)
+	);
+END bcd_to_display;
+
+-- Design Ports Information
+-- DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF bcd_to_display IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_DISPout : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_BCDin : std_logic_vector(3 DOWNTO 0);
+SIGNAL \DISPout[6]~output_o\ : std_logic;
+SIGNAL \DISPout[5]~output_o\ : std_logic;
+SIGNAL \DISPout[4]~output_o\ : std_logic;
+SIGNAL \DISPout[3]~output_o\ : std_logic;
+SIGNAL \DISPout[2]~output_o\ : std_logic;
+SIGNAL \DISPout[1]~output_o\ : std_logic;
+SIGNAL \DISPout[0]~output_o\ : std_logic;
+SIGNAL \BCDin[2]~input_o\ : std_logic;
+SIGNAL \BCDin[1]~input_o\ : std_logic;
+SIGNAL \BCDin[3]~input_o\ : std_logic;
+SIGNAL \BCDin[0]~input_o\ : std_logic;
+SIGNAL \inst30~0_combout\ : std_logic;
+SIGNAL \inst29~0_combout\ : std_logic;
+SIGNAL \inst32~0_combout\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \inst21~0_combout\ : std_logic;
+SIGNAL \inst24~0_combout\ : std_logic;
+SIGNAL \inst20~0_combout\ : std_logic;
+SIGNAL \ALT_INV_inst24~0_combout\ : std_logic;
+
+BEGIN
+
+DISPout <= ww_DISPout;
+ww_BCDin <= BCDin;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\ALT_INV_inst24~0_combout\ <= NOT \inst24~0_combout\;
+
+-- Location: IOOBUF_X0_Y8_N9
+\DISPout[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst30~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y12_N2
+\DISPout[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst29~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y10_N16
+\DISPout[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y8_N16
+\DISPout[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y6_N23
+\DISPout[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y9_N9
+\DISPout[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \ALT_INV_inst24~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y23_N2
+\DISPout[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y8_N1
+\BCDin[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(2),
+	o => \BCDin[2]~input_o\);
+
+-- Location: IOIBUF_X0_Y8_N22
+\BCDin[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(1),
+	o => \BCDin[1]~input_o\);
+
+-- Location: IOIBUF_X0_Y5_N1
+\BCDin[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(3),
+	o => \BCDin[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y9_N22
+\BCDin[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(0),
+	o => \BCDin[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y8_N16
+\inst30~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (\BCDin[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst30~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N18
+\inst29~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst29~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (!\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001011111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst29~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N12
+\inst32~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst32~0_combout\ = (!\BCDin[0]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[2]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011011101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst32~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N14
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & (\BCDin[1]~input_o\ $ (\BCDin[0]~input_o\))) # (!\BCDin[2]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst23~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N8
+\inst21~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst21~0_combout\ = (\BCDin[2]~input_o\) # (((\BCDin[3]~input_o\) # (\BCDin[0]~input_o\)) # (!\BCDin[1]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst21~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N2
+\inst24~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst24~0_combout\ = (\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst24~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N4
+\inst20~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst20~0_combout\ = (\BCDin[1]~input_o\) # ((\BCDin[3]~input_o\) # (\BCDin[2]~input_o\ $ (!\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst20~0_combout\);
+
+ww_DISPout(6) <= \DISPout[6]~output_o\;
+
+ww_DISPout(5) <= \DISPout[5]~output_o\;
+
+ww_DISPout(4) <= \DISPout[4]~output_o\;
+
+ww_DISPout(3) <= \DISPout[3]~output_o\;
+
+ww_DISPout(2) <= \DISPout[2]~output_o\;
+
+ww_DISPout(1) <= \DISPout[1]~output_o\;
+
+ww_DISPout(0) <= \DISPout[0]~output_o\;
+END structure;
+
+
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display.vo b/bcd_to_display/simulation/modelsim/bcd_to_display.vo
new file mode 100644
index 0000000..dd92fc1
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display.vo
@@ -0,0 +1,346 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "02/26/2016 16:37:06"
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module bcd_to_display (
+	DISPout,
+	BCDin);
+output 	[6:0] DISPout;
+input 	[3:0] BCDin;
+
+// Design Ports Information
+// DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \DISPout[6]~output_o ;
+wire \DISPout[5]~output_o ;
+wire \DISPout[4]~output_o ;
+wire \DISPout[3]~output_o ;
+wire \DISPout[2]~output_o ;
+wire \DISPout[1]~output_o ;
+wire \DISPout[0]~output_o ;
+wire \BCDin[2]~input_o ;
+wire \BCDin[1]~input_o ;
+wire \BCDin[3]~input_o ;
+wire \BCDin[0]~input_o ;
+wire \inst1~0_combout ;
+wire \inst2~0_combout ;
+wire \inst12~0_combout ;
+wire \inst5~0_combout ;
+wire \inst6~0_combout ;
+wire \inst7~combout ;
+wire \inst8~0_combout ;
+
+
+// Location: IOOBUF_X0_Y8_N9
+cycloneiii_io_obuf \DISPout[6]~output (
+	.i(!\inst1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[6]~output .bus_hold = "false";
+defparam \DISPout[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y12_N2
+cycloneiii_io_obuf \DISPout[5]~output (
+	.i(!\inst2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[5]~output .bus_hold = "false";
+defparam \DISPout[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N16
+cycloneiii_io_obuf \DISPout[4]~output (
+	.i(!\inst12~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[4]~output .bus_hold = "false";
+defparam \DISPout[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y8_N16
+cycloneiii_io_obuf \DISPout[3]~output (
+	.i(!\inst5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[3]~output .bus_hold = "false";
+defparam \DISPout[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y6_N23
+cycloneiii_io_obuf \DISPout[2]~output (
+	.i(!\inst6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[2]~output .bus_hold = "false";
+defparam \DISPout[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N9
+cycloneiii_io_obuf \DISPout[1]~output (
+	.i(!\inst7~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[1]~output .bus_hold = "false";
+defparam \DISPout[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y23_N2
+cycloneiii_io_obuf \DISPout[0]~output (
+	.i(!\inst8~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[0]~output .bus_hold = "false";
+defparam \DISPout[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneiii_io_ibuf \BCDin[2]~input (
+	.i(BCDin[2]),
+	.ibar(gnd),
+	.o(\BCDin[2]~input_o ));
+// synopsys translate_off
+defparam \BCDin[2]~input .bus_hold = "false";
+defparam \BCDin[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N22
+cycloneiii_io_ibuf \BCDin[1]~input (
+	.i(BCDin[1]),
+	.ibar(gnd),
+	.o(\BCDin[1]~input_o ));
+// synopsys translate_off
+defparam \BCDin[1]~input .bus_hold = "false";
+defparam \BCDin[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y5_N1
+cycloneiii_io_ibuf \BCDin[3]~input (
+	.i(BCDin[3]),
+	.ibar(gnd),
+	.o(\BCDin[3]~input_o ));
+// synopsys translate_off
+defparam \BCDin[3]~input .bus_hold = "false";
+defparam \BCDin[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y9_N22
+cycloneiii_io_ibuf \BCDin[0]~input (
+	.i(BCDin[0]),
+	.ibar(gnd),
+	.o(\BCDin[0]~input_o ));
+// synopsys translate_off
+defparam \BCDin[0]~input .bus_hold = "false";
+defparam \BCDin[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N16
+cycloneiii_lcell_comb \inst1~0 (
+// Equation(s):
+// \inst1~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & ((!\BCDin[0]~input_o ) # (!\BCDin[1]~input_o ))) # (!\BCDin[2]~input_o  & (\BCDin[1]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst1~0 .lut_mask = 16'hF6FE;
+defparam \inst1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N18
+cycloneiii_lcell_comb \inst2~0 (
+// Equation(s):
+// \inst2~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & ((!\BCDin[0]~input_o ) # (!\BCDin[1]~input_o ))) # (!\BCDin[2]~input_o  & (!\BCDin[1]~input_o  & !\BCDin[0]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst2~0 .lut_mask = 16'hF2FB;
+defparam \inst2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N12
+cycloneiii_lcell_comb \inst12~0 (
+// Equation(s):
+// \inst12~0_combout  = (!\BCDin[0]~input_o  & ((\BCDin[1]~input_o ) # (!\BCDin[2]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(gnd),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst12~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst12~0 .lut_mask = 16'h00DD;
+defparam \inst12~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N14
+cycloneiii_lcell_comb \inst5~0 (
+// Equation(s):
+// \inst5~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & (\BCDin[1]~input_o  $ (\BCDin[0]~input_o ))) # (!\BCDin[2]~input_o  & ((\BCDin[1]~input_o ) # (!\BCDin[0]~input_o ))))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst5~0 .lut_mask = 16'hF6FD;
+defparam \inst5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N8
+cycloneiii_lcell_comb \inst6~0 (
+// Equation(s):
+// \inst6~0_combout  = (\BCDin[2]~input_o ) # (((\BCDin[3]~input_o ) # (\BCDin[0]~input_o )) # (!\BCDin[1]~input_o ))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst6~0 .lut_mask = 16'hFFFB;
+defparam \inst6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N2
+cycloneiii_lcell_comb inst7(
+// Equation(s):
+// \inst7~combout  = (\BCDin[1]~input_o  $ (!\BCDin[0]~input_o )) # (!\BCDin[2]~input_o )
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(gnd),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst7~combout ),
+	.cout());
+// synopsys translate_off
+defparam inst7.lut_mask = 16'hDD77;
+defparam inst7.sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N4
+cycloneiii_lcell_comb \inst8~0 (
+// Equation(s):
+// \inst8~0_combout  = (\BCDin[1]~input_o ) # ((\BCDin[3]~input_o ) # (\BCDin[2]~input_o  $ (!\BCDin[0]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst8~0 .lut_mask = 16'hFEFD;
+defparam \inst8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+assign DISPout[6] = \DISPout[6]~output_o ;
+
+assign DISPout[5] = \DISPout[5]~output_o ;
+
+assign DISPout[4] = \DISPout[4]~output_o ;
+
+assign DISPout[3] = \DISPout[3]~output_o ;
+
+assign DISPout[2] = \DISPout[2]~output_o ;
+
+assign DISPout[1] = \DISPout[1]~output_o ;
+
+assign DISPout[0] = \DISPout[0]~output_o ;
+
+endmodule
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_slow.vho b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..48e1fa7
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_slow.vho
@@ -0,0 +1,355 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 15:29:32"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	bcd_to_display IS
+    PORT (
+	DISPout : OUT std_logic_vector(6 DOWNTO 0);
+	BCDin : IN std_logic_vector(3 DOWNTO 0)
+	);
+END bcd_to_display;
+
+-- Design Ports Information
+-- DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF bcd_to_display IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_DISPout : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_BCDin : std_logic_vector(3 DOWNTO 0);
+SIGNAL \DISPout[6]~output_o\ : std_logic;
+SIGNAL \DISPout[5]~output_o\ : std_logic;
+SIGNAL \DISPout[4]~output_o\ : std_logic;
+SIGNAL \DISPout[3]~output_o\ : std_logic;
+SIGNAL \DISPout[2]~output_o\ : std_logic;
+SIGNAL \DISPout[1]~output_o\ : std_logic;
+SIGNAL \DISPout[0]~output_o\ : std_logic;
+SIGNAL \BCDin[2]~input_o\ : std_logic;
+SIGNAL \BCDin[1]~input_o\ : std_logic;
+SIGNAL \BCDin[3]~input_o\ : std_logic;
+SIGNAL \BCDin[0]~input_o\ : std_logic;
+SIGNAL \inst30~0_combout\ : std_logic;
+SIGNAL \inst29~0_combout\ : std_logic;
+SIGNAL \inst32~0_combout\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \inst21~0_combout\ : std_logic;
+SIGNAL \inst24~0_combout\ : std_logic;
+SIGNAL \inst20~0_combout\ : std_logic;
+SIGNAL \ALT_INV_inst24~0_combout\ : std_logic;
+
+BEGIN
+
+DISPout <= ww_DISPout;
+ww_BCDin <= BCDin;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\ALT_INV_inst24~0_combout\ <= NOT \inst24~0_combout\;
+
+-- Location: IOOBUF_X0_Y8_N9
+\DISPout[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst30~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y12_N2
+\DISPout[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst29~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y10_N16
+\DISPout[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y8_N16
+\DISPout[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y6_N23
+\DISPout[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y9_N9
+\DISPout[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \ALT_INV_inst24~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y23_N2
+\DISPout[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y8_N1
+\BCDin[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(2),
+	o => \BCDin[2]~input_o\);
+
+-- Location: IOIBUF_X0_Y8_N22
+\BCDin[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(1),
+	o => \BCDin[1]~input_o\);
+
+-- Location: IOIBUF_X0_Y5_N1
+\BCDin[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(3),
+	o => \BCDin[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y9_N22
+\BCDin[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(0),
+	o => \BCDin[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y8_N16
+\inst30~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (\BCDin[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst30~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N18
+\inst29~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst29~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (!\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001011111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst29~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N12
+\inst32~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst32~0_combout\ = (!\BCDin[0]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[2]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011011101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst32~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N14
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & (\BCDin[1]~input_o\ $ (\BCDin[0]~input_o\))) # (!\BCDin[2]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst23~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N8
+\inst21~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst21~0_combout\ = (\BCDin[2]~input_o\) # (((\BCDin[3]~input_o\) # (\BCDin[0]~input_o\)) # (!\BCDin[1]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst21~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N2
+\inst24~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst24~0_combout\ = (\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst24~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N4
+\inst20~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst20~0_combout\ = (\BCDin[1]~input_o\) # ((\BCDin[3]~input_o\) # (\BCDin[2]~input_o\ $ (!\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst20~0_combout\);
+
+ww_DISPout(6) <= \DISPout[6]~output_o\;
+
+ww_DISPout(5) <= \DISPout[5]~output_o\;
+
+ww_DISPout(4) <= \DISPout[4]~output_o\;
+
+ww_DISPout(3) <= \DISPout[3]~output_o\;
+
+ww_DISPout(2) <= \DISPout[2]~output_o\;
+
+ww_DISPout(1) <= \DISPout[1]~output_o\;
+
+ww_DISPout(0) <= \DISPout[0]~output_o\;
+END structure;
+
+
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_vhd_slow.sdo b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..cf3ab0f
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,251 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "bcd_to_display")
+  (DATE "02/26/2016 15:29:32")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (293:293:293) (287:287:287))
+        (IOPATH i o (2147:2147:2147) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (560:560:560) (565:565:565))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (552:552:552) (550:550:550))
+        (IOPATH i o (2137:2137:2137) (2095:2095:2095))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (299:299:299) (295:295:295))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (563:563:563) (555:555:555))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (537:537:537) (554:554:554))
+        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1010:1010:1010) (1002:1002:1002))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (765:765:765) (926:926:926))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2200:2200:2200) (2416:2416:2416))
+        (PORT datab (2204:2204:2204) (2415:2415:2415))
+        (PORT datac (2403:2403:2403) (2615:2615:2615))
+        (PORT datad (2424:2424:2424) (2618:2618:2618))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst29\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2200:2200:2200) (2416:2416:2416))
+        (PORT datab (2203:2203:2203) (2415:2415:2415))
+        (PORT datac (2403:2403:2403) (2615:2615:2615))
+        (PORT datad (2423:2423:2423) (2617:2617:2617))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst32\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2198:2198:2198) (2413:2413:2413))
+        (PORT datab (2206:2206:2206) (2414:2414:2414))
+        (PORT datad (2425:2425:2425) (2622:2622:2622))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2198:2198:2198) (2414:2414:2414))
+        (PORT datab (2206:2206:2206) (2414:2414:2414))
+        (PORT datac (2402:2402:2402) (2613:2613:2613))
+        (PORT datad (2425:2425:2425) (2614:2614:2614))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst21\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2197:2197:2197) (2412:2412:2412))
+        (PORT datab (2207:2207:2207) (2416:2416:2416))
+        (PORT datac (2401:2401:2401) (2611:2611:2611))
+        (PORT datad (2427:2427:2427) (2617:2617:2617))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst24\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2209:2209:2209) (2417:2417:2417))
+        (PORT datad (2429:2429:2429) (2624:2624:2624))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst20\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2197:2197:2197) (2409:2409:2409))
+        (PORT datab (2209:2209:2209) (2416:2416:2416))
+        (PORT datac (2400:2400:2400) (2610:2610:2610))
+        (PORT datad (2428:2428:2428) (2617:2617:2617))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_slow.vho b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..48e1fa7
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_slow.vho
@@ -0,0 +1,355 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 15:29:32"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	bcd_to_display IS
+    PORT (
+	DISPout : OUT std_logic_vector(6 DOWNTO 0);
+	BCDin : IN std_logic_vector(3 DOWNTO 0)
+	);
+END bcd_to_display;
+
+-- Design Ports Information
+-- DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF bcd_to_display IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_DISPout : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_BCDin : std_logic_vector(3 DOWNTO 0);
+SIGNAL \DISPout[6]~output_o\ : std_logic;
+SIGNAL \DISPout[5]~output_o\ : std_logic;
+SIGNAL \DISPout[4]~output_o\ : std_logic;
+SIGNAL \DISPout[3]~output_o\ : std_logic;
+SIGNAL \DISPout[2]~output_o\ : std_logic;
+SIGNAL \DISPout[1]~output_o\ : std_logic;
+SIGNAL \DISPout[0]~output_o\ : std_logic;
+SIGNAL \BCDin[2]~input_o\ : std_logic;
+SIGNAL \BCDin[1]~input_o\ : std_logic;
+SIGNAL \BCDin[3]~input_o\ : std_logic;
+SIGNAL \BCDin[0]~input_o\ : std_logic;
+SIGNAL \inst30~0_combout\ : std_logic;
+SIGNAL \inst29~0_combout\ : std_logic;
+SIGNAL \inst32~0_combout\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \inst21~0_combout\ : std_logic;
+SIGNAL \inst24~0_combout\ : std_logic;
+SIGNAL \inst20~0_combout\ : std_logic;
+SIGNAL \ALT_INV_inst24~0_combout\ : std_logic;
+
+BEGIN
+
+DISPout <= ww_DISPout;
+ww_BCDin <= BCDin;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\ALT_INV_inst24~0_combout\ <= NOT \inst24~0_combout\;
+
+-- Location: IOOBUF_X0_Y8_N9
+\DISPout[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst30~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y12_N2
+\DISPout[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst29~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y10_N16
+\DISPout[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y8_N16
+\DISPout[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y6_N23
+\DISPout[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y9_N9
+\DISPout[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \ALT_INV_inst24~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y23_N2
+\DISPout[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y8_N1
+\BCDin[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(2),
+	o => \BCDin[2]~input_o\);
+
+-- Location: IOIBUF_X0_Y8_N22
+\BCDin[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(1),
+	o => \BCDin[1]~input_o\);
+
+-- Location: IOIBUF_X0_Y5_N1
+\BCDin[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(3),
+	o => \BCDin[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y9_N22
+\BCDin[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(0),
+	o => \BCDin[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y8_N16
+\inst30~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (\BCDin[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst30~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N18
+\inst29~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst29~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (!\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001011111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst29~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N12
+\inst32~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst32~0_combout\ = (!\BCDin[0]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[2]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011011101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst32~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N14
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & (\BCDin[1]~input_o\ $ (\BCDin[0]~input_o\))) # (!\BCDin[2]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst23~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N8
+\inst21~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst21~0_combout\ = (\BCDin[2]~input_o\) # (((\BCDin[3]~input_o\) # (\BCDin[0]~input_o\)) # (!\BCDin[1]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst21~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N2
+\inst24~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst24~0_combout\ = (\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst24~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N4
+\inst20~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst20~0_combout\ = (\BCDin[1]~input_o\) # ((\BCDin[3]~input_o\) # (\BCDin[2]~input_o\ $ (!\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst20~0_combout\);
+
+ww_DISPout(6) <= \DISPout[6]~output_o\;
+
+ww_DISPout(5) <= \DISPout[5]~output_o\;
+
+ww_DISPout(4) <= \DISPout[4]~output_o\;
+
+ww_DISPout(3) <= \DISPout[3]~output_o\;
+
+ww_DISPout(2) <= \DISPout[2]~output_o\;
+
+ww_DISPout(1) <= \DISPout[1]~output_o\;
+
+ww_DISPout(0) <= \DISPout[0]~output_o\;
+END structure;
+
+
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_vhd_slow.sdo b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..c2a5c22
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,251 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "bcd_to_display")
+  (DATE "02/26/2016 15:29:32")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (321:321:321) (324:324:324))
+        (IOPATH i o (2147:2147:2147) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (639:639:639))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (603:603:603) (604:604:604))
+        (IOPATH i o (2137:2137:2137) (2095:2095:2095))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (326:326:326) (333:333:333))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (614:614:614) (612:612:612))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (605:605:605) (606:606:606))
+        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1082:1082:1082) (1129:1129:1129))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (765:765:765) (926:926:926))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2593:2593:2593) (2856:2856:2856))
+        (PORT datab (2586:2586:2586) (2856:2856:2856))
+        (PORT datac (2801:2801:2801) (3083:3083:3083))
+        (PORT datad (2815:2815:2815) (3073:3073:3073))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst29\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2593:2593:2593) (2856:2856:2856))
+        (PORT datab (2585:2585:2585) (2855:2855:2855))
+        (PORT datac (2801:2801:2801) (3083:3083:3083))
+        (PORT datad (2815:2815:2815) (3071:3071:3071))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst32\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2590:2590:2590) (2853:2853:2853))
+        (PORT datab (2588:2588:2588) (2855:2855:2855))
+        (PORT datad (2814:2814:2814) (3076:3076:3076))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2591:2591:2591) (2854:2854:2854))
+        (PORT datab (2587:2587:2587) (2856:2856:2856))
+        (PORT datac (2799:2799:2799) (3082:3082:3082))
+        (PORT datad (2814:2814:2814) (3074:3074:3074))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst21\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2588:2588:2588) (2850:2850:2850))
+        (PORT datab (2588:2588:2588) (2854:2854:2854))
+        (PORT datac (2798:2798:2798) (3079:3079:3079))
+        (PORT datad (2818:2818:2818) (3072:3072:3072))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst24\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2591:2591:2591) (2857:2857:2857))
+        (PORT datad (2819:2819:2819) (3078:3078:3078))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst20\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2587:2587:2587) (2848:2848:2848))
+        (PORT datab (2591:2591:2591) (2854:2854:2854))
+        (PORT datac (2797:2797:2797) (3078:3078:3078))
+        (PORT datad (2819:2819:2819) (3072:3072:3072))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_fast.vho b/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..48e1fa7
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_fast.vho
@@ -0,0 +1,355 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 15:29:32"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	bcd_to_display IS
+    PORT (
+	DISPout : OUT std_logic_vector(6 DOWNTO 0);
+	BCDin : IN std_logic_vector(3 DOWNTO 0)
+	);
+END bcd_to_display;
+
+-- Design Ports Information
+-- DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF bcd_to_display IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_DISPout : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_BCDin : std_logic_vector(3 DOWNTO 0);
+SIGNAL \DISPout[6]~output_o\ : std_logic;
+SIGNAL \DISPout[5]~output_o\ : std_logic;
+SIGNAL \DISPout[4]~output_o\ : std_logic;
+SIGNAL \DISPout[3]~output_o\ : std_logic;
+SIGNAL \DISPout[2]~output_o\ : std_logic;
+SIGNAL \DISPout[1]~output_o\ : std_logic;
+SIGNAL \DISPout[0]~output_o\ : std_logic;
+SIGNAL \BCDin[2]~input_o\ : std_logic;
+SIGNAL \BCDin[1]~input_o\ : std_logic;
+SIGNAL \BCDin[3]~input_o\ : std_logic;
+SIGNAL \BCDin[0]~input_o\ : std_logic;
+SIGNAL \inst30~0_combout\ : std_logic;
+SIGNAL \inst29~0_combout\ : std_logic;
+SIGNAL \inst32~0_combout\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \inst21~0_combout\ : std_logic;
+SIGNAL \inst24~0_combout\ : std_logic;
+SIGNAL \inst20~0_combout\ : std_logic;
+SIGNAL \ALT_INV_inst24~0_combout\ : std_logic;
+
+BEGIN
+
+DISPout <= ww_DISPout;
+ww_BCDin <= BCDin;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\ALT_INV_inst24~0_combout\ <= NOT \inst24~0_combout\;
+
+-- Location: IOOBUF_X0_Y8_N9
+\DISPout[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst30~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y12_N2
+\DISPout[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst29~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y10_N16
+\DISPout[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y8_N16
+\DISPout[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y6_N23
+\DISPout[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y9_N9
+\DISPout[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \ALT_INV_inst24~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y23_N2
+\DISPout[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~0_combout\,
+	devoe => ww_devoe,
+	o => \DISPout[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y8_N1
+\BCDin[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(2),
+	o => \BCDin[2]~input_o\);
+
+-- Location: IOIBUF_X0_Y8_N22
+\BCDin[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(1),
+	o => \BCDin[1]~input_o\);
+
+-- Location: IOIBUF_X0_Y5_N1
+\BCDin[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(3),
+	o => \BCDin[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y9_N22
+\BCDin[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_BCDin(0),
+	o => \BCDin[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y8_N16
+\inst30~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (\BCDin[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst30~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N18
+\inst29~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst29~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & ((!\BCDin[0]~input_o\) # (!\BCDin[1]~input_o\))) # (!\BCDin[2]~input_o\ & (!\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001011111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst29~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N12
+\inst32~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst32~0_combout\ = (!\BCDin[0]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[2]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011011101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst32~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N14
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (\BCDin[3]~input_o\) # ((\BCDin[2]~input_o\ & (\BCDin[1]~input_o\ $ (\BCDin[0]~input_o\))) # (!\BCDin[2]~input_o\ & ((\BCDin[1]~input_o\) # (!\BCDin[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst23~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N8
+\inst21~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst21~0_combout\ = (\BCDin[2]~input_o\) # (((\BCDin[3]~input_o\) # (\BCDin[0]~input_o\)) # (!\BCDin[1]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111111011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst21~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N2
+\inst24~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst24~0_combout\ = (\BCDin[1]~input_o\ & !\BCDin[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \BCDin[1]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst24~0_combout\);
+
+-- Location: LCCOMB_X1_Y8_N4
+\inst20~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst20~0_combout\ = (\BCDin[1]~input_o\) # ((\BCDin[3]~input_o\) # (\BCDin[2]~input_o\ $ (!\BCDin[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011111101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \BCDin[2]~input_o\,
+	datab => \BCDin[1]~input_o\,
+	datac => \BCDin[3]~input_o\,
+	datad => \BCDin[0]~input_o\,
+	combout => \inst20~0_combout\);
+
+ww_DISPout(6) <= \DISPout[6]~output_o\;
+
+ww_DISPout(5) <= \DISPout[5]~output_o\;
+
+ww_DISPout(4) <= \DISPout[4]~output_o\;
+
+ww_DISPout(3) <= \DISPout[3]~output_o\;
+
+ww_DISPout(2) <= \DISPout[2]~output_o\;
+
+ww_DISPout(1) <= \DISPout[1]~output_o\;
+
+ww_DISPout(0) <= \DISPout[0]~output_o\;
+END structure;
+
+
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_vhd_fast.sdo b/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..f7ea8e6
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,251 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16F484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "bcd_to_display")
+  (DATE "02/26/2016 15:29:32")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (161:161:161) (181:181:181))
+        (IOPATH i o (1358:1358:1358) (1378:1378:1378))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (343:343:343) (380:380:380))
+        (IOPATH i o (1456:1456:1456) (1440:1440:1440))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (327:327:327) (367:367:367))
+        (IOPATH i o (1348:1348:1348) (1368:1368:1368))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (164:164:164) (185:185:185))
+        (IOPATH i o (1456:1456:1456) (1440:1440:1440))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (334:334:334) (368:368:368))
+        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (362:362:362) (322:322:322))
+        (IOPATH i o (1480:1480:1480) (1496:1496:1496))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (599:599:599) (684:684:684))
+        (IOPATH i o (1486:1486:1486) (1470:1470:1470))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (421:421:421) (803:803:803))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (431:431:431) (813:813:813))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1497:1497:1497) (1684:1684:1684))
+        (PORT datab (1504:1504:1504) (1681:1681:1681))
+        (PORT datac (1640:1640:1640) (1835:1835:1835))
+        (PORT datad (1639:1639:1639) (1829:1829:1829))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst29\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1497:1497:1497) (1684:1684:1684))
+        (PORT datab (1504:1504:1504) (1681:1681:1681))
+        (PORT datac (1641:1641:1641) (1835:1835:1835))
+        (PORT datad (1637:1637:1637) (1827:1827:1827))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst32\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1496:1496:1496) (1681:1681:1681))
+        (PORT datab (1507:1507:1507) (1684:1684:1684))
+        (PORT datad (1642:1642:1642) (1833:1833:1833))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1496:1496:1496) (1682:1682:1682))
+        (PORT datab (1505:1505:1505) (1683:1683:1683))
+        (PORT datac (1639:1639:1639) (1833:1833:1833))
+        (PORT datad (1641:1641:1641) (1832:1832:1832))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst21\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1494:1494:1494) (1679:1679:1679))
+        (PORT datab (1507:1507:1507) (1685:1685:1685))
+        (PORT datac (1637:1637:1637) (1831:1831:1831))
+        (PORT datad (1643:1643:1643) (1834:1834:1834))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst24\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1509:1509:1509) (1687:1687:1687))
+        (PORT datad (1644:1644:1644) (1835:1835:1835))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst20\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1493:1493:1493) (1676:1676:1676))
+        (PORT datab (1507:1507:1507) (1685:1685:1685))
+        (PORT datac (1636:1636:1636) (1830:1830:1830))
+        (PORT datad (1643:1643:1643) (1834:1834:1834))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_modelsim.xrf b/bcd_to_display/simulation/modelsim/bcd_to_display_modelsim.xrf
new file mode 100644
index 0000000..6c4d221
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_modelsim.xrf
@@ -0,0 +1,22 @@
+vendor_name = ModelSim
+source_file = 1, C:/Git/bcd_to_display/bcd_to_display.bdf
+source_file = 1, C:/Git/bcd_to_display/Waveform.vwf
+source_file = 1, C:/Git/bcd_to_display/db/bcd_to_display.cbx.xml
+design_name = bcd_to_display
+instance = comp, \DISPout[6]~output , DISPout[6]~output, bcd_to_display, 1
+instance = comp, \DISPout[5]~output , DISPout[5]~output, bcd_to_display, 1
+instance = comp, \DISPout[4]~output , DISPout[4]~output, bcd_to_display, 1
+instance = comp, \DISPout[3]~output , DISPout[3]~output, bcd_to_display, 1
+instance = comp, \DISPout[2]~output , DISPout[2]~output, bcd_to_display, 1
+instance = comp, \DISPout[1]~output , DISPout[1]~output, bcd_to_display, 1
+instance = comp, \DISPout[0]~output , DISPout[0]~output, bcd_to_display, 1
+instance = comp, \BCDin[2]~input , BCDin[2]~input, bcd_to_display, 1
+instance = comp, \BCDin[1]~input , BCDin[1]~input, bcd_to_display, 1
+instance = comp, \BCDin[3]~input , BCDin[3]~input, bcd_to_display, 1
+instance = comp, \BCDin[0]~input , BCDin[0]~input, bcd_to_display, 1
+instance = comp, \inst1~0 , inst1~0, bcd_to_display, 1
+instance = comp, \inst2~0 , inst2~0, bcd_to_display, 1
+instance = comp, \inst12~0 , inst12~0, bcd_to_display, 1
+instance = comp, \inst5~0 , inst5~0, bcd_to_display, 1
+instance = comp, \inst6~0 , inst6~0, bcd_to_display, 1
+instance = comp, \inst8~0 , inst8~0, bcd_to_display, 1
diff --git a/bcd_to_display/simulation/modelsim/bcd_to_display_vhd.sdo b/bcd_to_display/simulation/modelsim/bcd_to_display_vhd.sdo
new file mode 100644
index 0000000..c2a5c22
--- /dev/null
+++ b/bcd_to_display/simulation/modelsim/bcd_to_display_vhd.sdo
@@ -0,0 +1,251 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "bcd_to_display")
+  (DATE "02/26/2016 15:29:32")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (321:321:321) (324:324:324))
+        (IOPATH i o (2147:2147:2147) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (639:639:639))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (603:603:603) (604:604:604))
+        (IOPATH i o (2137:2137:2137) (2095:2095:2095))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (326:326:326) (333:333:333))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (614:614:614) (612:612:612))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (605:605:605) (606:606:606))
+        (IOPATH i o (2244:2244:2244) (2256:2256:2256))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\DISPout\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1082:1082:1082) (1129:1129:1129))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (765:765:765) (926:926:926))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\BCDin\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2593:2593:2593) (2856:2856:2856))
+        (PORT datab (2586:2586:2586) (2856:2856:2856))
+        (PORT datac (2801:2801:2801) (3083:3083:3083))
+        (PORT datad (2815:2815:2815) (3073:3073:3073))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst29\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2593:2593:2593) (2856:2856:2856))
+        (PORT datab (2585:2585:2585) (2855:2855:2855))
+        (PORT datac (2801:2801:2801) (3083:3083:3083))
+        (PORT datad (2815:2815:2815) (3071:3071:3071))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst32\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2590:2590:2590) (2853:2853:2853))
+        (PORT datab (2588:2588:2588) (2855:2855:2855))
+        (PORT datad (2814:2814:2814) (3076:3076:3076))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2591:2591:2591) (2854:2854:2854))
+        (PORT datab (2587:2587:2587) (2856:2856:2856))
+        (PORT datac (2799:2799:2799) (3082:3082:3082))
+        (PORT datad (2814:2814:2814) (3074:3074:3074))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst21\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2588:2588:2588) (2850:2850:2850))
+        (PORT datab (2588:2588:2588) (2854:2854:2854))
+        (PORT datac (2798:2798:2798) (3079:3079:3079))
+        (PORT datad (2818:2818:2818) (3072:3072:3072))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst24\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2591:2591:2591) (2857:2857:2857))
+        (PORT datad (2819:2819:2819) (3078:3078:3078))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst20\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2587:2587:2587) (2848:2848:2848))
+        (PORT datab (2591:2591:2591) (2854:2854:2854))
+        (PORT datac (2797:2797:2797) (3078:3078:3078))
+        (PORT datad (2819:2819:2819) (3072:3072:3072))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.do b/bcd_to_display/simulation/qsim/bcd_to_display.do
new file mode 100644
index 0000000..171052d
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.do
@@ -0,0 +1,10 @@
+onerror {quit -f}
+vlib work
+vlog -work work bcd_to_display.vo
+vlog -work work bcd_to_display.vt
+vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.bcd_to_display_vlg_vec_tst
+vcd file -direction bcd_to_display.msim.vcd
+vcd add -internal bcd_to_display_vlg_vec_tst/*
+vcd add -internal bcd_to_display_vlg_vec_tst/i1/*
+add wave /*
+run -all
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.msim.vcd b/bcd_to_display/simulation/qsim/bcd_to_display.msim.vcd
new file mode 100644
index 0000000..8be9f68
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.msim.vcd
@@ -0,0 +1,88 @@
+$comment
+	File created using the following command:
+		vcd file bcd_to_display.msim.vcd -direction
+$end
+$date
+	Fri Feb 26 15:30:40 2016
+$end
+$version
+	ModelSim Version 10.1d
+$end
+$timescale
+	1ps
+$end
+$scope module bcd_to_display_vlg_vec_tst $end
+$var reg 4 ! BCDin [3:0] $end
+$var wire 1 " DISPout [6] $end
+$var wire 1 # DISPout [5] $end
+$var wire 1 $ DISPout [4] $end
+$var wire 1 % DISPout [3] $end
+$var wire 1 & DISPout [2] $end
+$var wire 1 ' DISPout [1] $end
+$var wire 1 ( DISPout [0] $end
+$var wire 1 ) sampler $end
+$scope module i1 $end
+$var wire 1 * gnd $end
+$var wire 1 + vcc $end
+$var wire 1 , unknown $end
+$var tri1 1 - devclrn $end
+$var tri1 1 . devpor $end
+$var tri1 1 / devoe $end
+$var wire 1 0 DISPout[6]~output_o $end
+$var wire 1 1 DISPout[5]~output_o $end
+$var wire 1 2 DISPout[4]~output_o $end
+$var wire 1 3 DISPout[3]~output_o $end
+$var wire 1 4 DISPout[2]~output_o $end
+$var wire 1 5 DISPout[1]~output_o $end
+$var wire 1 6 DISPout[0]~output_o $end
+$var wire 1 7 BCDin[2]~input_o $end
+$var wire 1 8 BCDin[1]~input_o $end
+$var wire 1 9 BCDin[3]~input_o $end
+$var wire 1 : BCDin[0]~input_o $end
+$var wire 1 ; inst30~0_combout $end
+$var wire 1 < inst29~0_combout $end
+$var wire 1 = inst32~0_combout $end
+$var wire 1 > inst23~0_combout $end
+$var wire 1 ? inst21~0_combout $end
+$var wire 1 @ inst24~0_combout $end
+$var wire 1 A inst20~0_combout $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b11 !
+1(
+1'
+1&
+1%
+0$
+0#
+1"
+x)
+0*
+1+
+x,
+1-
+1.
+1/
+10
+01
+02
+13
+14
+15
+16
+07
+18
+09
+1:
+1;
+0<
+0=
+1>
+1?
+0@
+1A
+$end
+#1000000
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.msim.vwf b/bcd_to_display/simulation/qsim/bcd_to_display.msim.vwf
new file mode 100644
index 0000000..607cc33
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.msim.vwf
@@ -0,0 +1,1066 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 0.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|BCDin")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 4;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|BCDin[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "bcd_to_display_vlg_vec_tst|BCDin";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|BCDin[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "bcd_to_display_vlg_vec_tst|BCDin";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|BCDin[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "bcd_to_display_vlg_vec_tst|BCDin";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|BCDin[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "bcd_to_display_vlg_vec_tst|BCDin";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|DISPout[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|sampler")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|gnd")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|vcc")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|unknown")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|devclrn")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|devpor")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|devoe")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[6]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[5]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[4]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[3]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[2]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[1]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|DISPout[0]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|BCDin[2]~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|BCDin[1]~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|BCDin[3]~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|BCDin[0]~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst30~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst29~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst32~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst23~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst21~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst24~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("bcd_to_display_vlg_vec_tst|i1|inst20~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|BCDin[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|BCDin[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|BCDin[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|BCDin[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|DISPout[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|sampler")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|gnd")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|vcc")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|unknown")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|devclrn")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|devpor")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|devoe")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[6]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[5]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[4]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[3]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[2]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[1]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|DISPout[0]~output_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|BCDin[2]~input_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|BCDin[1]~input_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|BCDin[3]~input_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|BCDin[0]~input_o")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst30~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst29~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst32~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst23~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst21~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst24~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("bcd_to_display_vlg_vec_tst|i1|inst20~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|BCDin";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2, 3, 4;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|BCDin[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|BCDin[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|BCDin[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|BCDin[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|DISPout[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 11;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|sampler";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 12;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|gnd";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 13;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|vcc";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 14;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|unknown";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 15;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|devclrn";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 16;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|devpor";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 17;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|devoe";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 18;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[6]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 19;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[5]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 20;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[4]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 21;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[3]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 22;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[2]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 23;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[1]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 24;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|DISPout[0]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 25;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|BCDin[2]~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 26;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|BCDin[1]~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 27;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|BCDin[3]~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 28;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|BCDin[0]~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 29;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst30~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 30;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst29~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 31;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst32~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 32;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst23~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 33;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst21~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 34;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst24~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 35;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "bcd_to_display_vlg_vec_tst|i1|inst20~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 36;
+	TREE_LEVEL = 0;
+}
+;
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.sim.vwf b/bcd_to_display/simulation/qsim/bcd_to_display.sim.vwf
new file mode 100644
index 0000000..057b629
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.sim.vwf
@@ -0,0 +1,392 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 0.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+
+
+
+SIGNAL("BCDin")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 4;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("BCDin[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("BCDin[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "BCDin";
+}
+
+SIGNAL("DISPout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 7;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("DISPout[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+SIGNAL("DISPout[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "DISPout";
+}
+
+TRANSITION_LIST("BCDin[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("BCDin[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("BCDin[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("BCDin[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("DISPout[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2, 3, 4;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "BCDin[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+	CHILDREN = 6, 7, 8, 9, 10, 11, 12;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 11;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "DISPout[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 12;
+	TREE_LEVEL = 1;
+	PARENT = 5;
+}
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.vo b/bcd_to_display/simulation/qsim/bcd_to_display.vo
new file mode 100644
index 0000000..5374202
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.vo
@@ -0,0 +1,346 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "02/26/2016 15:30:38"
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module bcd_to_display (
+	DISPout,
+	BCDin);
+output 	[6:0] DISPout;
+input 	[3:0] BCDin;
+
+// Design Ports Information
+// DISPout[6]	=>  Location: PIN_P5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[5]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[4]	=>  Location: PIN_N5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[3]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[2]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[1]	=>  Location: PIN_U2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// DISPout[0]	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[3]	=>  Location: PIN_P7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[1]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[2]	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// BCDin[0]	=>  Location: PIN_V2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \DISPout[6]~output_o ;
+wire \DISPout[5]~output_o ;
+wire \DISPout[4]~output_o ;
+wire \DISPout[3]~output_o ;
+wire \DISPout[2]~output_o ;
+wire \DISPout[1]~output_o ;
+wire \DISPout[0]~output_o ;
+wire \BCDin[2]~input_o ;
+wire \BCDin[1]~input_o ;
+wire \BCDin[3]~input_o ;
+wire \BCDin[0]~input_o ;
+wire \inst30~0_combout ;
+wire \inst29~0_combout ;
+wire \inst32~0_combout ;
+wire \inst23~0_combout ;
+wire \inst21~0_combout ;
+wire \inst24~0_combout ;
+wire \inst20~0_combout ;
+
+
+// Location: IOOBUF_X0_Y8_N9
+cycloneiii_io_obuf \DISPout[6]~output (
+	.i(\inst30~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[6]~output .bus_hold = "false";
+defparam \DISPout[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y12_N2
+cycloneiii_io_obuf \DISPout[5]~output (
+	.i(\inst29~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[5]~output .bus_hold = "false";
+defparam \DISPout[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N16
+cycloneiii_io_obuf \DISPout[4]~output (
+	.i(\inst32~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[4]~output .bus_hold = "false";
+defparam \DISPout[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y8_N16
+cycloneiii_io_obuf \DISPout[3]~output (
+	.i(\inst23~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[3]~output .bus_hold = "false";
+defparam \DISPout[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y6_N23
+cycloneiii_io_obuf \DISPout[2]~output (
+	.i(\inst21~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[2]~output .bus_hold = "false";
+defparam \DISPout[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y9_N9
+cycloneiii_io_obuf \DISPout[1]~output (
+	.i(!\inst24~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[1]~output .bus_hold = "false";
+defparam \DISPout[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y23_N2
+cycloneiii_io_obuf \DISPout[0]~output (
+	.i(\inst20~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DISPout[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DISPout[0]~output .bus_hold = "false";
+defparam \DISPout[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N1
+cycloneiii_io_ibuf \BCDin[2]~input (
+	.i(BCDin[2]),
+	.ibar(gnd),
+	.o(\BCDin[2]~input_o ));
+// synopsys translate_off
+defparam \BCDin[2]~input .bus_hold = "false";
+defparam \BCDin[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y8_N22
+cycloneiii_io_ibuf \BCDin[1]~input (
+	.i(BCDin[1]),
+	.ibar(gnd),
+	.o(\BCDin[1]~input_o ));
+// synopsys translate_off
+defparam \BCDin[1]~input .bus_hold = "false";
+defparam \BCDin[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y5_N1
+cycloneiii_io_ibuf \BCDin[3]~input (
+	.i(BCDin[3]),
+	.ibar(gnd),
+	.o(\BCDin[3]~input_o ));
+// synopsys translate_off
+defparam \BCDin[3]~input .bus_hold = "false";
+defparam \BCDin[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y9_N22
+cycloneiii_io_ibuf \BCDin[0]~input (
+	.i(BCDin[0]),
+	.ibar(gnd),
+	.o(\BCDin[0]~input_o ));
+// synopsys translate_off
+defparam \BCDin[0]~input .bus_hold = "false";
+defparam \BCDin[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N16
+cycloneiii_lcell_comb \inst30~0 (
+// Equation(s):
+// \inst30~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & ((!\BCDin[0]~input_o ) # (!\BCDin[1]~input_o ))) # (!\BCDin[2]~input_o  & (\BCDin[1]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst30~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst30~0 .lut_mask = 16'hF6FE;
+defparam \inst30~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N18
+cycloneiii_lcell_comb \inst29~0 (
+// Equation(s):
+// \inst29~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & ((!\BCDin[0]~input_o ) # (!\BCDin[1]~input_o ))) # (!\BCDin[2]~input_o  & (!\BCDin[1]~input_o  & !\BCDin[0]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst29~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst29~0 .lut_mask = 16'hF2FB;
+defparam \inst29~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N12
+cycloneiii_lcell_comb \inst32~0 (
+// Equation(s):
+// \inst32~0_combout  = (!\BCDin[0]~input_o  & ((\BCDin[1]~input_o ) # (!\BCDin[2]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(gnd),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst32~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst32~0 .lut_mask = 16'h00DD;
+defparam \inst32~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N14
+cycloneiii_lcell_comb \inst23~0 (
+// Equation(s):
+// \inst23~0_combout  = (\BCDin[3]~input_o ) # ((\BCDin[2]~input_o  & (\BCDin[1]~input_o  $ (\BCDin[0]~input_o ))) # (!\BCDin[2]~input_o  & ((\BCDin[1]~input_o ) # (!\BCDin[0]~input_o ))))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst23~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst23~0 .lut_mask = 16'hF6FD;
+defparam \inst23~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N8
+cycloneiii_lcell_comb \inst21~0 (
+// Equation(s):
+// \inst21~0_combout  = (\BCDin[2]~input_o ) # (((\BCDin[3]~input_o ) # (\BCDin[0]~input_o )) # (!\BCDin[1]~input_o ))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst21~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst21~0 .lut_mask = 16'hFFFB;
+defparam \inst21~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N2
+cycloneiii_lcell_comb \inst24~0 (
+// Equation(s):
+// \inst24~0_combout  = (\BCDin[1]~input_o  & !\BCDin[0]~input_o )
+
+	.dataa(gnd),
+	.datab(\BCDin[1]~input_o ),
+	.datac(gnd),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst24~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst24~0 .lut_mask = 16'h00CC;
+defparam \inst24~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y8_N4
+cycloneiii_lcell_comb \inst20~0 (
+// Equation(s):
+// \inst20~0_combout  = (\BCDin[1]~input_o ) # ((\BCDin[3]~input_o ) # (\BCDin[2]~input_o  $ (!\BCDin[0]~input_o )))
+
+	.dataa(\BCDin[2]~input_o ),
+	.datab(\BCDin[1]~input_o ),
+	.datac(\BCDin[3]~input_o ),
+	.datad(\BCDin[0]~input_o ),
+	.cin(gnd),
+	.combout(\inst20~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst20~0 .lut_mask = 16'hFEFD;
+defparam \inst20~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+assign DISPout[6] = \DISPout[6]~output_o ;
+
+assign DISPout[5] = \DISPout[5]~output_o ;
+
+assign DISPout[4] = \DISPout[4]~output_o ;
+
+assign DISPout[3] = \DISPout[3]~output_o ;
+
+assign DISPout[2] = \DISPout[2]~output_o ;
+
+assign DISPout[1] = \DISPout[1]~output_o ;
+
+assign DISPout[0] = \DISPout[0]~output_o ;
+
+endmodule
diff --git a/bcd_to_display/simulation/qsim/bcd_to_display.vt b/bcd_to_display/simulation/qsim/bcd_to_display.vt
new file mode 100644
index 0000000..1d1ee6a
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/bcd_to_display.vt
@@ -0,0 +1,305 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// *****************************************************************************
+// This file contains a Verilog test bench with test vectors .The test vectors  
+// are exported from a vector file in the Quartus Waveform Editor and apply to  
+// the top level entity of the current Quartus project .The user can use this   
+// testbench to simulate his design using a third-party simulation tool .       
+// *****************************************************************************
+// Generated on "02/26/2016 15:30:37"
+                                                                        
+// Verilog Self-Checking Test Bench (with test vectors) for design :    bcd_to_display
+// 
+// Simulation tool : 3rd Party
+// 
+
+`timescale 1 ps/ 1 ps
+module bcd_to_display_vlg_sample_tst(
+	BCDin,
+	sampler_tx
+);
+input [3:0] BCDin;
+output sampler_tx;
+
+reg sample;
+time current_time;
+always @(BCDin)
+                                                                                
+begin                                                 
+ if ($realtime > 0)                                   
+ begin                                                
+	if ($realtime == 0 || $realtime != current_time)  
+	begin									          
+		if (sample === 1'bx)                          
+			sample = 0;                               
+		else                                          
+			sample = ~sample;                         
+	end										          
+	current_time = $realtime;					      
+ end                                                  
+end                                                   
+
+assign sampler_tx = sample;
+endmodule
+
+module bcd_to_display_vlg_check_tst (
+	DISPout,
+	sampler_rx
+);
+input [6:0] DISPout;
+input sampler_rx;
+
+reg [6:0] DISPout_expected;
+
+reg [6:0] DISPout_prev;
+
+reg [6:0] DISPout_expected_prev;
+
+reg [6:0] last_DISPout_exp;
+
+reg trigger;
+
+integer i;
+integer nummismatches;
+
+reg [1:1] on_first_change ;
+
+
+initial
+begin
+trigger = 0;
+i = 0;
+nummismatches = 0;
+on_first_change = 1'b1;
+end
+
+// update real /o prevs
+
+always @(trigger)
+begin
+	DISPout_prev = DISPout;
+end
+
+// update expected /o prevs
+
+always @(trigger)
+begin
+	DISPout_expected_prev = DISPout_expected;
+end
+
+
+// expected DISPout[ 6 ]
+initial
+begin
+	DISPout_expected[6] = 1'bX;
+end 
+// expected DISPout[ 5 ]
+initial
+begin
+	DISPout_expected[5] = 1'bX;
+end 
+// expected DISPout[ 4 ]
+initial
+begin
+	DISPout_expected[4] = 1'bX;
+end 
+// expected DISPout[ 3 ]
+initial
+begin
+	DISPout_expected[3] = 1'bX;
+end 
+// expected DISPout[ 2 ]
+initial
+begin
+	DISPout_expected[2] = 1'bX;
+end 
+// expected DISPout[ 1 ]
+initial
+begin
+	DISPout_expected[1] = 1'bX;
+end 
+// expected DISPout[ 0 ]
+initial
+begin
+	DISPout_expected[0] = 1'bX;
+end 
+// generate trigger
+always @(DISPout_expected or DISPout)
+begin
+	trigger <= ~trigger;
+end
+
+always @(posedge sampler_rx or negedge sampler_rx)
+begin
+`ifdef debug_tbench
+	$display("Scanning pattern %d @time = %t",i,$realtime );
+	i = i + 1;
+	$display("| expected DISPout = %b | ",DISPout_expected_prev);
+	$display("| real DISPout = %b | ",DISPout_prev);
+`endif
+	if (
+		( DISPout_expected_prev[0] !== 1'bx ) && ( DISPout_prev[0] !== DISPout_expected_prev[0] )
+		&& ((DISPout_expected_prev[0] !== last_DISPout_exp[0]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[0] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[0] = DISPout_expected_prev[0];
+	end
+	if (
+		( DISPout_expected_prev[1] !== 1'bx ) && ( DISPout_prev[1] !== DISPout_expected_prev[1] )
+		&& ((DISPout_expected_prev[1] !== last_DISPout_exp[1]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[1] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[1] = DISPout_expected_prev[1];
+	end
+	if (
+		( DISPout_expected_prev[2] !== 1'bx ) && ( DISPout_prev[2] !== DISPout_expected_prev[2] )
+		&& ((DISPout_expected_prev[2] !== last_DISPout_exp[2]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[2] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[2] = DISPout_expected_prev[2];
+	end
+	if (
+		( DISPout_expected_prev[3] !== 1'bx ) && ( DISPout_prev[3] !== DISPout_expected_prev[3] )
+		&& ((DISPout_expected_prev[3] !== last_DISPout_exp[3]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[3] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[3] = DISPout_expected_prev[3];
+	end
+	if (
+		( DISPout_expected_prev[4] !== 1'bx ) && ( DISPout_prev[4] !== DISPout_expected_prev[4] )
+		&& ((DISPout_expected_prev[4] !== last_DISPout_exp[4]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[4] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[4] = DISPout_expected_prev[4];
+	end
+	if (
+		( DISPout_expected_prev[5] !== 1'bx ) && ( DISPout_prev[5] !== DISPout_expected_prev[5] )
+		&& ((DISPout_expected_prev[5] !== last_DISPout_exp[5]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[5] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[5] = DISPout_expected_prev[5];
+	end
+	if (
+		( DISPout_expected_prev[6] !== 1'bx ) && ( DISPout_prev[6] !== DISPout_expected_prev[6] )
+		&& ((DISPout_expected_prev[6] !== last_DISPout_exp[6]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port DISPout[6] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", DISPout_expected_prev);
+		$display ("     Real value = %b", DISPout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_DISPout_exp[6] = DISPout_expected_prev[6];
+	end
+
+	trigger <= ~trigger;
+end
+initial 
+
+begin 
+$timeformat(-12,3," ps",6);
+#1000000;
+if (nummismatches > 0)
+	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
+else
+	$display ("Simulation passed !");
+$finish;
+end 
+endmodule
+
+module bcd_to_display_vlg_vec_tst();
+// constants                                           
+// general purpose registers
+reg [3:0] BCDin;
+// wires                                               
+wire [6:0] DISPout;
+
+wire sampler;                             
+
+// assign statements (if any)                          
+bcd_to_display i1 (
+// port map - connection between master ports and signals/registers   
+	.BCDin(BCDin),
+	.DISPout(DISPout)
+);
+// BCDin[ 3 ]
+initial
+begin
+	BCDin[3] = 1'b0;
+end 
+// BCDin[ 2 ]
+initial
+begin
+	BCDin[2] = 1'b0;
+end 
+// BCDin[ 1 ]
+initial
+begin
+	BCDin[1] = 1'b1;
+end 
+// BCDin[ 0 ]
+initial
+begin
+	BCDin[0] = 1'b1;
+end 
+
+bcd_to_display_vlg_sample_tst tb_sample (
+	.BCDin(BCDin),
+	.sampler_tx(sampler)
+);
+
+bcd_to_display_vlg_check_tst tb_out(
+	.DISPout(DISPout),
+	.sampler_rx(sampler)
+);
+endmodule
+
diff --git a/bcd_to_display/simulation/qsim/transcript b/bcd_to_display/simulation/qsim/transcript
new file mode 100644
index 0000000..c156150
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/transcript
@@ -0,0 +1,24 @@
+# do bcd_to_display.do 
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module bcd_to_display
+# 
+# Top level modules:
+# 	bcd_to_display
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module bcd_to_display_vlg_sample_tst
+# -- Compiling module bcd_to_display_vlg_check_tst
+# -- Compiling module bcd_to_display_vlg_vec_tst
+# 
+# Top level modules:
+# 	bcd_to_display_vlg_vec_tst
+# vsim -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.bcd_to_display_vlg_vec_tst 
+# Loading work.bcd_to_display_vlg_vec_tst
+# Loading work.bcd_to_display
+# Loading cycloneiii_ver.cycloneiii_io_obuf
+# Loading cycloneiii_ver.cycloneiii_io_ibuf
+# Loading cycloneiii_ver.cycloneiii_lcell_comb
+# Loading work.bcd_to_display_vlg_sample_tst
+# Loading work.bcd_to_display_vlg_check_tst
+# Simulation passed !
+# ** Note: $finish    : bcd_to_display.vt(255)
+#    Time: 1 us  Iteration: 0  Instance: /bcd_to_display_vlg_vec_tst/tb_out
diff --git a/bcd_to_display/simulation/qsim/vsim.wlf b/bcd_to_display/simulation/qsim/vsim.wlf
new file mode 100644
index 0000000..7d3280f
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/vsim.wlf
diff --git a/bcd_to_display/simulation/qsim/work/_info b/bcd_to_display/simulation/qsim/work/_info
new file mode 100644
index 0000000..6db3272
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/_info
@@ -0,0 +1,81 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Git\bcd_to_display\simulation\qsim
+vbcd_to_display
+Z1 I2dJ>0W@HJDEJTHJE@=0bg3
+Z2 VJc=W1_NOQADa<S?Xb;b5B3
+Z3 dC:\Git\bcd_to_display\simulation\qsim
+Z4 w1456500638
+Z5 8bcd_to_display.vo
+Z6 Fbcd_to_display.vo
+L0 31
+Z7 OV;L;10.1d;51
+r1
+31
+Z8 o-work work -O0
+!i10b 1
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+!s85 0
+Z10 !s108 1456500639.509000
+Z11 !s107 bcd_to_display.vo|
+Z12 !s90 -work|work|bcd_to_display.vo|
+!s101 -O0
+vbcd_to_display_vlg_check_tst
+!i10b 1
+!s100 f_bg7b]0]_k@l`[2zcCNB1
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+Z16 !s108 1456500639.586000
+Z17 !s107 bcd_to_display.vt|
+Z18 !s90 -work|work|bcd_to_display.vt|
+!s101 -O0
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+vbcd_to_display_vlg_sample_tst
+!i10b 1
+!s100 Z^JoRB837FJ`HUJLHez2V1
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+!i10b 1
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diff --git a/bcd_to_display/simulation/qsim/work/_vmake b/bcd_to_display/simulation/qsim/work/_vmake
new file mode 100644
index 0000000..2f7e729
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dat b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dat
new file mode 100644
index 0000000..b430f1d
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dat
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dbs b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dbs
new file mode 100644
index 0000000..e5fca20
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.dbs
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.vhd b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.vhd
new file mode 100644
index 0000000..8a70392
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display/_primary.vhd
@@ -0,0 +1,8 @@
+library verilog;
+use verilog.vl_types.all;
+entity bcd_to_display is
+    port(
+        DISPout         : out    vl_logic_vector(6 downto 0);
+        BCDin           : in     vl_logic_vector(3 downto 0)
+    );
+end bcd_to_display;
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.prw b/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.prw
new file mode 100644
index 0000000..68eec58
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.prw
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.psm b/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.psm
new file mode 100644
index 0000000..eb40ede
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display/verilog.psm
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dat b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dat
new file mode 100644
index 0000000..f5f890c
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dat
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dbs b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dbs
new file mode 100644
index 0000000..f6e7817
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.dbs
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.vhd b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.vhd
new file mode 100644
index 0000000..f16303a
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/_primary.vhd
@@ -0,0 +1,8 @@
+library verilog;
+use verilog.vl_types.all;
+entity bcd_to_display_vlg_check_tst is
+    port(
+        DISPout         : in     vl_logic_vector(6 downto 0);
+        sampler_rx      : in     vl_logic
+    );
+end bcd_to_display_vlg_check_tst;
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.prw b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.prw
new file mode 100644
index 0000000..432b4cf
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.prw
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.psm b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.psm
new file mode 100644
index 0000000..f29b787
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_check_tst/verilog.psm
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dat b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dat
new file mode 100644
index 0000000..a45f88f
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dat
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dbs b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dbs
new file mode 100644
index 0000000..e279bfc
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.dbs
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd
new file mode 100644
index 0000000..61a9062
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd
@@ -0,0 +1,8 @@
+library verilog;
+use verilog.vl_types.all;
+entity bcd_to_display_vlg_sample_tst is
+    port(
+        BCDin           : in     vl_logic_vector(3 downto 0);
+        sampler_tx      : out    vl_logic
+    );
+end bcd_to_display_vlg_sample_tst;
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.prw b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.prw
new file mode 100644
index 0000000..faff3e4
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.prw
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.psm b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.psm
new file mode 100644
index 0000000..2e44951
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/verilog.psm
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dat b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dat
new file mode 100644
index 0000000..f2093d2
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dat
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dbs b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dbs
new file mode 100644
index 0000000..35dd024
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.dbs
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.vhd b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.vhd
new file mode 100644
index 0000000..5c361c0
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/_primary.vhd
@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity bcd_to_display_vlg_vec_tst is
+end bcd_to_display_vlg_vec_tst;
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.prw b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.prw
new file mode 100644
index 0000000..cadbaa9
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.prw
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.psm b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.psm
new file mode 100644
index 0000000..dfea9f4
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_vec_tst/verilog.psm
diff --git a/blinken_lights/altclkctrl0.bsf b/blinken_lights/altclkctrl0.bsf
new file mode 100644
index 0000000..b0b10f6
--- /dev/null
+++ b/blinken_lights/altclkctrl0.bsf
@@ -0,0 +1,51 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 160 64)
+	(text "altclkctrl0" (rect 4 -16 70 0)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 48 25 60)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inclk" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "inclk" (rect 4 18 23 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 72 32))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "outclk" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+		(text "outclk" (rect 129 18 155 31)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 91 32))
+	)
+	(drawing
+		(text "clk" (rect 74 26 158 63)(font "Arial" ))
+		(text "Global Clock" (rect 104 49 259 109)(font "Arial" ))
+		(line (pt 72 17)(pt 72 47))
+		(line (pt 72 17)(pt 92 33))
+		(line (pt 72 47)(pt 92 31))
+		(line (pt 0 0)(pt 162 0))
+		(line (pt 162 0)(pt 162 66))
+		(line (pt 0 66)(pt 162 66))
+		(line (pt 0 0)(pt 0 66))
+	)
+)
diff --git a/blinken_lights/altclkctrl0.cmp b/blinken_lights/altclkctrl0.cmp
new file mode 100644
index 0000000..f27da69
--- /dev/null
+++ b/blinken_lights/altclkctrl0.cmp
@@ -0,0 +1,22 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altclkctrl0
+	PORT
+	(
+		inclk		: IN STD_LOGIC ;
+		outclk		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/blinken_lights/altclkctrl0.qip b/blinken_lights/altclkctrl0.qip
new file mode 100644
index 0000000..5ba98ff
--- /dev/null
+++ b/blinken_lights/altclkctrl0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTCLKCTRL"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altclkctrl0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altclkctrl0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altclkctrl0.cmp"]
diff --git a/blinken_lights/altclkctrl0.vhd b/blinken_lights/altclkctrl0.vhd
new file mode 100644
index 0000000..4c9d20f
--- /dev/null
+++ b/blinken_lights/altclkctrl0.vhd
@@ -0,0 +1,175 @@
+-- megafunction wizard: %ALTCLKCTRL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altclkctrl 
+
+-- ============================================================
+-- File Name: altclkctrl0.vhd
+-- Megafunction Name(s):
+-- 			altclkctrl
+--
+-- Simulation Library Files(s):
+-- 			cycloneiii
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone III" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
+--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ  VERSION_END
+
+ LIBRARY cycloneiii;
+ USE cycloneiii.all;
+
+--synthesis_resources = clkctrl 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  altclkctrl0_altclkctrl_uhi IS 
+	 PORT 
+	 ( 
+		 clkselect	:	IN  STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
+		 ena	:	IN  STD_LOGIC := '1';
+		 inclk	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+		 outclk	:	OUT  STD_LOGIC
+	 ); 
+ END altclkctrl0_altclkctrl_uhi;
+
+ ARCHITECTURE RTL OF altclkctrl0_altclkctrl_uhi IS
+
+	 SIGNAL  wire_clkctrl1_outclk	:	STD_LOGIC;
+	 SIGNAL  clkselect_wire :	STD_LOGIC_VECTOR (1 DOWNTO 0);
+	 SIGNAL  inclk_wire :	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 COMPONENT  cycloneiii_clkctrl
+	 GENERIC 
+	 (
+		clock_type	:	STRING;
+		ena_register_mode	:	STRING := "falling edge";
+		lpm_type	:	STRING := "cycloneiii_clkctrl"
+	 );
+	 PORT
+	 ( 
+		clkselect	:	IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		ena	:	IN STD_LOGIC;
+		inclk	:	IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		outclk	:	OUT STD_LOGIC
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	clkselect_wire <= ( clkselect);
+	inclk_wire <= ( inclk);
+	outclk <= wire_clkctrl1_outclk;
+	clkctrl1 :  cycloneiii_clkctrl
+	  GENERIC MAP (
+		clock_type => "Global Clock",
+		ena_register_mode => "falling edge"
+	  )
+	  PORT MAP ( 
+		clkselect => clkselect_wire,
+		ena => ena,
+		inclk => inclk_wire,
+		outclk => wire_clkctrl1_outclk
+	  );
+
+ END RTL; --altclkctrl0_altclkctrl_uhi
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY altclkctrl0 IS
+	PORT
+	(
+		inclk		: IN STD_LOGIC ;
+		outclk		: OUT STD_LOGIC 
+	);
+END altclkctrl0;
+
+
+ARCHITECTURE RTL OF altclkctrl0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1_bv	: BIT_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (2 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+
+
+	COMPONENT altclkctrl0_altclkctrl_uhi
+	PORT (
+			clkselect	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			ena	: IN STD_LOGIC ;
+			inclk	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			outclk	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1_bv(1 DOWNTO 0) <= "00";
+	sub_wire1    <= To_stdlogicvector(sub_wire1_bv);
+	sub_wire2    <= '1';
+	sub_wire5_bv(2 DOWNTO 0) <= "000";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	outclk    <= sub_wire0;
+	sub_wire3    <= inclk;
+	sub_wire4    <= sub_wire5(2 DOWNTO 0) & sub_wire3;
+
+	altclkctrl0_altclkctrl_uhi_component : altclkctrl0_altclkctrl_uhi
+	PORT MAP (
+		clkselect => sub_wire1,
+		ena => sub_wire2,
+		inclk => sub_wire4,
+		outclk => sub_wire0
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
+-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "falling edge"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
+-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
+-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
+-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
+-- Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
+-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
+-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altclkctrl0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altclkctrl0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altclkctrl0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altclkctrl0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altclkctrl0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: cycloneiii
diff --git a/blinken_lights/blinken_Lights.bdf b/blinken_lights/blinken_Lights.bdf
new file mode 100644
index 0000000..ae8e85a
--- /dev/null
+++ b/blinken_lights/blinken_Lights.bdf
@@ -0,0 +1,3404 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
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+	(rect 504 256 680 272)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "pin_name1" (rect 9 0 62 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
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+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
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+)
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+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "LEDOUT[9..0]" (rect 90 0 159 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
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+		(line (pt 78 12)(pt 82 8))
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+	(port
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+		(line (pt 0 32)(pt 72 32))
+	)
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+		(output)
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+	)
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+(junction (pt 1824 384))
+(junction (pt 1824 520))
+(junction (pt 1800 768))
+(junction (pt 1264 392))
+(junction (pt 1424 392))
+(junction (pt 1272 528))
+(junction (pt 1432 528))
+(junction (pt 1256 656))
+(junction (pt 1416 656))
+(junction (pt 1600 384))
+(junction (pt 1760 384))
+(junction (pt 1608 520))
+(junction (pt 1768 520))
diff --git a/blinken_lights/blinken_Lights.qpf b/blinken_lights/blinken_Lights.qpf
new file mode 100644
index 0000000..d92b672
--- /dev/null
+++ b/blinken_lights/blinken_Lights.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 15:20:08  February 16, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "15:20:08  February 16, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "blinken_Lights"
diff --git a/blinken_lights/blinken_Lights.qsf b/blinken_lights/blinken_Lights.qsf
new file mode 100644
index 0000000..4fa6002
--- /dev/null
+++ b/blinken_lights/blinken_Lights.qsf
@@ -0,0 +1,68 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 15:20:08  February 16, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		blinken_Lights_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY blinken_Lights
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:20:08  FEBRUARY 16, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name QIP_FILE altclkctrl0.qip
+set_global_assignment -name BDF_FILE blinken_Lights.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_B1 -to LEDOUT[9]
+set_location_assignment PIN_B2 -to LEDOUT[8]
+set_location_assignment PIN_C2 -to LEDOUT[7]
+set_location_assignment PIN_C1 -to LEDOUT[6]
+set_location_assignment PIN_E1 -to LEDOUT[5]
+set_location_assignment PIN_F2 -to LEDOUT[4]
+set_location_assignment PIN_H1 -to LEDOUT[3]
+set_location_assignment PIN_J3 -to LEDOUT[2]
+set_location_assignment PIN_J2 -to LEDOUT[1]
+set_location_assignment PIN_J1 -to LEDOUT[0]
+set_location_assignment PIN_G21 -to pin_name1
+set_global_assignment -name CDF_FILE output_files/Chain3.cdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/blinken_lights/blinken_Lights.qws b/blinken_lights/blinken_Lights.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/blinken_lights/blinken_Lights.qws
diff --git a/blinken_lights/blinken_Lights_assignment_defaults.qdf b/blinken_lights/blinken_Lights_assignment_defaults.qdf
new file mode 100644
index 0000000..b37739b
--- /dev/null
+++ b/blinken_lights/blinken_Lights_assignment_defaults.qdf
@@ -0,0 +1,692 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 18:01:43  February 18, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN On
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name VREF_MODE EXTERNAL
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/blinken_lights/db/.cmp.kpt b/blinken_lights/db/.cmp.kpt
new file mode 100644
index 0000000..27b21c5
--- /dev/null
+++ b/blinken_lights/db/.cmp.kpt
diff --git a/blinken_lights/db/blinken_Lights.(0).cnf.cdb b/blinken_lights/db/blinken_Lights.(0).cnf.cdb
new file mode 100644
index 0000000..d552d59
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(0).cnf.cdb
diff --git a/blinken_lights/db/blinken_Lights.(0).cnf.hdb b/blinken_lights/db/blinken_Lights.(0).cnf.hdb
new file mode 100644
index 0000000..b6c8f61
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(0).cnf.hdb
diff --git a/blinken_lights/db/blinken_Lights.(1).cnf.cdb b/blinken_lights/db/blinken_Lights.(1).cnf.cdb
new file mode 100644
index 0000000..fbad725
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(1).cnf.cdb
diff --git a/blinken_lights/db/blinken_Lights.(1).cnf.hdb b/blinken_lights/db/blinken_Lights.(1).cnf.hdb
new file mode 100644
index 0000000..b258ccd
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(1).cnf.hdb
diff --git a/blinken_lights/db/blinken_Lights.(2).cnf.cdb b/blinken_lights/db/blinken_Lights.(2).cnf.cdb
new file mode 100644
index 0000000..709405e
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(2).cnf.cdb
diff --git a/blinken_lights/db/blinken_Lights.(2).cnf.hdb b/blinken_lights/db/blinken_Lights.(2).cnf.hdb
new file mode 100644
index 0000000..e2dd16d
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.(2).cnf.hdb
diff --git a/blinken_lights/db/blinken_Lights.asm.qmsg b/blinken_lights/db/blinken_Lights.asm.qmsg
new file mode 100644
index 0000000..2c9d6f4
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455829502426 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455829502426 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 21:05:02 2016 " "Processing started: Thu Feb 18 21:05:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455829502426 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455829502426 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455829502426 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455829503349 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455829503378 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "461 " "Peak virtual memory: 461 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455829503709 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 21:05:03 2016 " "Processing ended: Thu Feb 18 21:05:03 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455829503709 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455829503709 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455829503709 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455829503709 ""}
diff --git a/blinken_lights/db/blinken_Lights.asm.rdb b/blinken_lights/db/blinken_Lights.asm.rdb
new file mode 100644
index 0000000..4221d81
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.asm.rdb
diff --git a/blinken_lights/db/blinken_Lights.asm_labs.ddb b/blinken_lights/db/blinken_Lights.asm_labs.ddb
new file mode 100644
index 0000000..cc79825
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.asm_labs.ddb
diff --git a/blinken_lights/db/blinken_Lights.cbx.xml b/blinken_lights/db/blinken_Lights.cbx.xml
new file mode 100644
index 0000000..894bcba
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="blinken_Lights">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/blinken_lights/db/blinken_Lights.cmp.bpm b/blinken_lights/db/blinken_Lights.cmp.bpm
new file mode 100644
index 0000000..de60dd7
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.bpm
diff --git a/blinken_lights/db/blinken_Lights.cmp.cdb b/blinken_lights/db/blinken_Lights.cmp.cdb
new file mode 100644
index 0000000..c50cbd1
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.cdb
diff --git a/blinken_lights/db/blinken_Lights.cmp.hdb b/blinken_lights/db/blinken_Lights.cmp.hdb
new file mode 100644
index 0000000..e37bd67
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.hdb
diff --git a/blinken_lights/db/blinken_Lights.cmp.idb b/blinken_lights/db/blinken_Lights.cmp.idb
new file mode 100644
index 0000000..9ef8e67
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.idb
diff --git a/blinken_lights/db/blinken_Lights.cmp.logdb b/blinken_lights/db/blinken_Lights.cmp.logdb
new file mode 100644
index 0000000..f4f58a1
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.logdb
@@ -0,0 +1,53 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,11;0;11;0;0;11;11;0;11;11;0;10;0;0;1;0;10;1;0;0;0;10;0;0;0;0;0;11;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;11;0;11;11;0;0;11;0;0;11;1;11;11;10;11;1;10;11;11;11;1;11;11;11;11;11;0;11;11,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,LEDOUT[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDOUT[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,pin_name1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/blinken_lights/db/blinken_Lights.cmp.rdb b/blinken_lights/db/blinken_Lights.cmp.rdb
new file mode 100644
index 0000000..e2d583b
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp.rdb
diff --git a/blinken_lights/db/blinken_Lights.cmp_merge.kpt b/blinken_lights/db/blinken_Lights.cmp_merge.kpt
new file mode 100644
index 0000000..fae08c3
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cmp_merge.kpt
diff --git a/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..999f11c
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..4436436
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/blinken_lights/db/blinken_Lights.db_info b/blinken_lights/db/blinken_Lights.db_info
new file mode 100644
index 0000000..8426711
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 21:04:45 2016
diff --git a/blinken_lights/db/blinken_Lights.fit.qmsg b/blinken_lights/db/blinken_Lights.fit.qmsg
new file mode 100644
index 0000000..b83cd33
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455829494460 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "blinken_Lights EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"blinken_Lights\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455829494467 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455829494534 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455829494535 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455829494536 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455829494613 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455829494624 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455829494831 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455829494831 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455829494831 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455829494831 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 95 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455829494833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 97 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455829494833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 99 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455829494833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 101 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455829494833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 103 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455829494833 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455829494833 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455829494834 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "blinken_Lights.sdc " "Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455829495902 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455829495902 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455829495905 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1455829495905 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455829495906 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "pin_name1~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Promoted node pin_name1~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\|clkctrl1 Global Clock CLKCTRL_G9 " "Automatically promoted altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G9" {  } { { "altclkctrl0.vhd" "" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 81 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component|wire_clkctrl1_outclk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1455829495911 ""}  } { { "blinken_Lights.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/blinken_lights/blinken_Lights.bdf" { { 256 504 680 272 "pin_name1" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pin_name1~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 0 { 0 ""} 0 90 9662 10382 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1455829495911 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455829496059 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455829496059 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455829496060 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455829496060 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455829496061 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455829496061 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455829496062 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455829496062 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455829496075 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455829496076 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455829496076 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455829496087 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455829496910 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455829496974 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455829496981 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455829497338 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455829497338 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455829497494 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/blinken_lights/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455829498094 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455829498094 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455829498468 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455829498469 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455829498469 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455829498469 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.30 " "Total time spent on timing analysis during the Fitter is 0.30 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455829498479 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455829498515 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455829498782 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455829498811 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455829498915 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455829499259 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455829500202 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "850 " "Peak virtual memory: 850 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455829500416 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 21:05:00 2016 " "Processing ended: Thu Feb 18 21:05:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455829500416 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455829500416 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455829500416 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455829500416 ""}
diff --git a/blinken_lights/db/blinken_Lights.hier_info b/blinken_lights/db/blinken_Lights.hier_info
new file mode 100644
index 0000000..e640004
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.hier_info
@@ -0,0 +1,30 @@
+|blinken_Lights
+LEDOUT[0] <= inst63.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[1] <= inst64.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[2] <= inst67.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[3] <= inst68.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[4] <= inst71.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[5] <= inst72.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[6] <= inst75.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[7] <= inst76.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[8] <= inst79.DB_MAX_OUTPUT_PORT_TYPE
+LEDOUT[9] <= inst80.DB_MAX_OUTPUT_PORT_TYPE
+pin_name1 => altclkctrl0:inst.inclk
+
+
+|blinken_Lights|altclkctrl0:inst
+inclk => altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component.inclk[0]
+outclk <= altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component.outclk
+
+
+|blinken_Lights|altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component
+clkselect[0] => clkctrl1.CLKSELECT
+clkselect[1] => clkctrl1.CLKSELECT1
+ena => clkctrl1.ENA
+inclk[0] => clkctrl1.INCLK
+inclk[1] => clkctrl1.INCLK1
+inclk[2] => clkctrl1.INCLK2
+inclk[3] => clkctrl1.INCLK3
+outclk <= clkctrl1.CLK
+
+
diff --git a/blinken_lights/db/blinken_Lights.hif b/blinken_lights/db/blinken_Lights.hif
new file mode 100644
index 0000000..527624c
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.hif
diff --git a/blinken_lights/db/blinken_Lights.ipinfo b/blinken_lights/db/blinken_Lights.ipinfo
new file mode 100644
index 0000000..cc3edeb
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.ipinfo
diff --git a/blinken_lights/db/blinken_Lights.lpc.html b/blinken_lights/db/blinken_Lights.lpc.html
new file mode 100644
index 0000000..521ba8c
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.lpc.html
@@ -0,0 +1,50 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst|altclkctrl0_altclkctrl_uhi_component</TD>
+<TD >7</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >6</TD>
+<TD >1</TD>
+<TD >6</TD>
+<TD >6</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/blinken_lights/db/blinken_Lights.lpc.rdb b/blinken_lights/db/blinken_Lights.lpc.rdb
new file mode 100644
index 0000000..c492f34
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.lpc.rdb
diff --git a/blinken_lights/db/blinken_Lights.lpc.txt b/blinken_lights/db/blinken_Lights.lpc.txt
new file mode 100644
index 0000000..2e77753
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.lpc.txt
@@ -0,0 +1,8 @@
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                     ;
++-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                 ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst|altclkctrl0_altclkctrl_uhi_component ; 7     ; 6              ; 0            ; 6              ; 1      ; 6               ; 6             ; 6               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst                                      ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/blinken_lights/db/blinken_Lights.map.ammdb b/blinken_lights/db/blinken_Lights.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.ammdb
diff --git a/blinken_lights/db/blinken_Lights.map.bpm b/blinken_lights/db/blinken_Lights.map.bpm
new file mode 100644
index 0000000..bd6c622
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.bpm
diff --git a/blinken_lights/db/blinken_Lights.map.cdb b/blinken_lights/db/blinken_Lights.map.cdb
new file mode 100644
index 0000000..456ef83
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.cdb
diff --git a/blinken_lights/db/blinken_Lights.map.hdb b/blinken_lights/db/blinken_Lights.map.hdb
new file mode 100644
index 0000000..22f0ae2
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.hdb
diff --git a/blinken_lights/db/blinken_Lights.map.kpt b/blinken_lights/db/blinken_Lights.map.kpt
new file mode 100644
index 0000000..811a6a1
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.kpt
diff --git a/blinken_lights/db/blinken_Lights.map.logdb b/blinken_lights/db/blinken_Lights.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/blinken_lights/db/blinken_Lights.map.qmsg b/blinken_lights/db/blinken_Lights.map.qmsg
new file mode 100644
index 0000000..cb44932
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.qmsg
@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455829490522 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455829490522 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 21:04:50 2016 " "Processing started: Thu Feb 18 21:04:50 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455829490522 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455829490522 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455829490522 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455829490817 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altclkctrl0.vhd 4 2 " "Found 4 design units, including 2 entities, in source file altclkctrl0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altclkctrl0_altclkctrl_uhi-RTL " "Found design unit 1: altclkctrl0_altclkctrl_uhi-RTL" {  } { { "altclkctrl0.vhd" "" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 56 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455829491282 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 altclkctrl0-RTL " "Found design unit 2: altclkctrl0-RTL" {  } { { "altclkctrl0.vhd" "" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 109 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455829491282 ""} { "Info" "ISGN_ENTITY_NAME" "1 altclkctrl0_altclkctrl_uhi " "Found entity 1: altclkctrl0_altclkctrl_uhi" {  } { { "altclkctrl0.vhd" "" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455829491282 ""} { "Info" "ISGN_ENTITY_NAME" "2 altclkctrl0 " "Found entity 2: altclkctrl0" {  } { { "altclkctrl0.vhd" "" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 100 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455829491282 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455829491282 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "blinken_lights.bdf 1 1 " "Found 1 design units, including 1 entities, in source file blinken_lights.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 blinken_Lights " "Found entity 1: blinken_Lights" {  } { { "blinken_Lights.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/blinken_lights/blinken_Lights.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455829491285 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455829491285 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "blinken_Lights " "Elaborating entity \"blinken_Lights\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455829491317 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altclkctrl0 altclkctrl0:inst " "Elaborating entity \"altclkctrl0\" for hierarchy \"altclkctrl0:inst\"" {  } { { "blinken_Lights.bdf" "inst" { Schematic "C:/Users/Asus/Documents/GitHub/blinken_lights/blinken_Lights.bdf" { { 232 736 896 296 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455829491321 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altclkctrl0_altclkctrl_uhi altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component " "Elaborating entity \"altclkctrl0_altclkctrl_uhi\" for hierarchy \"altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\"" {  } { { "altclkctrl0.vhd" "altclkctrl0_altclkctrl_uhi_component" { Text "C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd" 141 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455829491323 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455829491925 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455829492154 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455829492154 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "42 " "Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455829492220 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455829492220 ""} { "Info" "ICUT_CUT_TM_LCELLS" "30 " "Implemented 30 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455829492220 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455829492220 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "542 " "Peak virtual memory: 542 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455829492240 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 21:04:52 2016 " "Processing ended: Thu Feb 18 21:04:52 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455829492240 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455829492240 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455829492240 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455829492240 ""}
diff --git a/blinken_lights/db/blinken_Lights.map.rdb b/blinken_lights/db/blinken_Lights.map.rdb
new file mode 100644
index 0000000..2a61c71
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map.rdb
diff --git a/blinken_lights/db/blinken_Lights.map_bb.cdb b/blinken_lights/db/blinken_Lights.map_bb.cdb
new file mode 100644
index 0000000..aaaddb5
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map_bb.cdb
diff --git a/blinken_lights/db/blinken_Lights.map_bb.hdb b/blinken_lights/db/blinken_Lights.map_bb.hdb
new file mode 100644
index 0000000..741c88a
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map_bb.hdb
diff --git a/blinken_lights/db/blinken_Lights.map_bb.logdb b/blinken_lights/db/blinken_Lights.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/blinken_lights/db/blinken_Lights.pre_map.hdb b/blinken_lights/db/blinken_Lights.pre_map.hdb
new file mode 100644
index 0000000..662b47f
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.pre_map.hdb
diff --git a/blinken_lights/db/blinken_Lights.pti_db_list.ddb b/blinken_lights/db/blinken_Lights.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.pti_db_list.ddb
diff --git a/blinken_lights/db/blinken_Lights.root_partition.map.reg_db.cdb b/blinken_lights/db/blinken_Lights.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..2dae3ba
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.root_partition.map.reg_db.cdb
diff --git a/blinken_lights/db/blinken_Lights.routing.rdb b/blinken_lights/db/blinken_Lights.routing.rdb
new file mode 100644
index 0000000..5096afa
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.routing.rdb
diff --git a/blinken_lights/db/blinken_Lights.rtlv.hdb b/blinken_lights/db/blinken_Lights.rtlv.hdb
new file mode 100644
index 0000000..b0b891a
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.rtlv.hdb
diff --git a/blinken_lights/db/blinken_Lights.rtlv_sg.cdb b/blinken_lights/db/blinken_Lights.rtlv_sg.cdb
new file mode 100644
index 0000000..be40e57
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.rtlv_sg.cdb
diff --git a/blinken_lights/db/blinken_Lights.rtlv_sg_swap.cdb b/blinken_lights/db/blinken_Lights.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..eb43921
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.rtlv_sg_swap.cdb
diff --git a/blinken_lights/db/blinken_Lights.sgdiff.cdb b/blinken_lights/db/blinken_Lights.sgdiff.cdb
new file mode 100644
index 0000000..cbbfb8e
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sgdiff.cdb
diff --git a/blinken_lights/db/blinken_Lights.sgdiff.hdb b/blinken_lights/db/blinken_Lights.sgdiff.hdb
new file mode 100644
index 0000000..cee7f59
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sgdiff.hdb
diff --git a/blinken_lights/db/blinken_Lights.sld_design_entry.sci b/blinken_lights/db/blinken_Lights.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sld_design_entry.sci
diff --git a/blinken_lights/db/blinken_Lights.sld_design_entry_dsc.sci b/blinken_lights/db/blinken_Lights.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sld_design_entry_dsc.sci
diff --git a/blinken_lights/db/blinken_Lights.smart_action.txt b/blinken_lights/db/blinken_Lights.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/blinken_lights/db/blinken_Lights.sta.qmsg b/blinken_lights/db/blinken_Lights.sta.qmsg
new file mode 100644
index 0000000..b8c4a36
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455829506482 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455829506482 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 21:05:06 2016 " "Processing started: Thu Feb 18 21:05:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455829506482 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455829506482 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta blinken_Lights -c blinken_Lights " "Command: quartus_sta blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455829506483 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455829506585 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455829506796 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455829506797 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455829506881 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455829506881 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "blinken_Lights.sdc " "Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455829507133 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455829507134 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst79 inst79 " "create_clock -period 1.000 -name inst79 inst79" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst76 inst76 " "create_clock -period 1.000 -name inst76 inst76" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst75 inst75 " "create_clock -period 1.000 -name inst75 inst75" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst72 inst72 " "create_clock -period 1.000 -name inst72 inst72" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst71 inst71 " "create_clock -period 1.000 -name inst71 inst71" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst68 inst68 " "create_clock -period 1.000 -name inst68 inst68" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst67 inst67 " "create_clock -period 1.000 -name inst67 inst67" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst64 inst64 " "create_clock -period 1.000 -name inst64 inst64" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst63 inst63 " "create_clock -period 1.000 -name inst63 inst63" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst60 inst60 " "create_clock -period 1.000 -name inst60 inst60" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst59 inst59 " "create_clock -period 1.000 -name inst59 inst59" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst56 inst56 " "create_clock -period 1.000 -name inst56 inst56" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst55 inst55 " "create_clock -period 1.000 -name inst55 inst55" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst52 inst52 " "create_clock -period 1.000 -name inst52 inst52" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst51 inst51 " "create_clock -period 1.000 -name inst51 inst51" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst48 inst48 " "create_clock -period 1.000 -name inst48 inst48" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst47 inst47 " "create_clock -period 1.000 -name inst47 inst47" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst44 inst44 " "create_clock -period 1.000 -name inst44 inst44" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst43 inst43 " "create_clock -period 1.000 -name inst43 inst43" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst40 inst40 " "create_clock -period 1.000 -name inst40 inst40" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst39 inst39 " "create_clock -period 1.000 -name inst39 inst39" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst36 inst36 " "create_clock -period 1.000 -name inst36 inst36" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst35 inst35 " "create_clock -period 1.000 -name inst35 inst35" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst32 inst32 " "create_clock -period 1.000 -name inst32 inst32" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst31 inst31 " "create_clock -period 1.000 -name inst31 inst31" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst28 inst28 " "create_clock -period 1.000 -name inst28 inst28" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst27 inst27 " "create_clock -period 1.000 -name inst27 inst27" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst24 inst24 " "create_clock -period 1.000 -name inst24 inst24" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst23 inst23 " "create_clock -period 1.000 -name inst23 inst23" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name pin_name1 pin_name1 " "create_clock -period 1.000 -name pin_name1 pin_name1" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507136 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455829507299 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507300 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455829507302 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455829507312 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455829507337 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455829507337 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.011 " "Worst-case setup slack is -0.011" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.011              -0.011 inst28  " "   -0.011              -0.011 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.010               0.000 inst43  " "    0.010               0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.030               0.000 pin_name1  " "    0.030               0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032               0.000 inst51  " "    0.032               0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.047               0.000 inst76  " "    0.047               0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.070               0.000 inst72  " "    0.070               0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.080               0.000 inst59  " "    0.080               0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.086               0.000 inst39  " "    0.086               0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.089               0.000 inst47  " "    0.089               0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.090               0.000 inst23  " "    0.090               0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 inst35  " "    0.094               0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.097               0.000 inst71  " "    0.097               0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.108               0.000 inst67  " "    0.108               0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.112               0.000 inst55  " "    0.112               0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.128               0.000 inst31  " "    0.128               0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.129               0.000 inst27  " "    0.129               0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.130               0.000 inst68  " "    0.130               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.134               0.000 inst32  " "    0.134               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.134               0.000 inst36  " "    0.134               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.139               0.000 inst48  " "    0.139               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.142               0.000 inst60  " "    0.142               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.143               0.000 inst44  " "    0.143               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.144               0.000 inst24  " "    0.144               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.144               0.000 inst56  " "    0.144               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.152               0.000 inst64  " "    0.152               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.154               0.000 inst75  " "    0.154               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.176               0.000 inst63  " "    0.176               0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298               0.000 inst40  " "    0.298               0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.317               0.000 inst79  " "    0.317               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.325               0.000 inst52  " "    0.325               0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829507343 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.088 " "Worst-case hold slack is -0.088" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.088              -0.088 inst63  " "   -0.088              -0.088 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.026              -0.026 inst52  " "   -0.026              -0.026 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.017              -0.017 inst31  " "   -0.017              -0.017 inst31 " { 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-1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.009               0.000 inst55  " "    0.009               0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013               0.000 pin_name1  " "    0.013               0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.019               0.000 inst35  " "    0.019               0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.028               0.000 inst39  " "    0.028               0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.029               0.000 inst47  " "    0.029               0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032               0.000 inst23  " "    0.032               0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.040               0.000 inst72  " "    0.040               0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.045               0.000 inst76  " "    0.045               0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.052               0.000 inst43  " "    0.052               0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.052               0.000 inst51  " "    0.052               0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.084               0.000 inst75  " "    0.084               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.086               0.000 inst24  " "    0.086               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.086               0.000 inst56  " "    0.086               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.088               0.000 inst64  " "    0.088               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.092               0.000 inst48  " "    0.092               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.097               0.000 inst44  " "    0.097               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.097               0.000 inst60  " "    0.097               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.101               0.000 inst68  " "    0.101               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.106               0.000 inst32  " "    0.106               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.106               0.000 inst36  " "    0.106               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.127               0.000 inst28  " "    0.127               0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 inst79  " "    0.384               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829507350 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829507359 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829507365 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -4.000 pin_name1  " "   -3.000              -4.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst23  " "   -1.000              -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst24  " "   -1.000              -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst27  " "   -1.000              -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst28  " "   -1.000              -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst31  " "   -1.000              -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst32  " "   -1.000              -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst35  " "   -1.000              -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst36  " "   -1.000              -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst39  " "   -1.000              -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst40  " "   -1.000              -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst43  " "   -1.000              -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst44  " "   -1.000              -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst47  " "   -1.000              -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst48  " "   -1.000              -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst51  " "   -1.000              -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst52  " "   -1.000              -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst55  " "   -1.000              -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst56  " "   -1.000              -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst59  " "   -1.000              -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst60  " "   -1.000              -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst63  " "   -1.000              -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst64  " "   -1.000              -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst67  " "   -1.000              -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst68  " "   -1.000              -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst71  " "   -1.000              -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst72  " "   -1.000              -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst75  " "   -1.000              -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst76  " "   -1.000              -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst79  " "   -1.000              -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829507374 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455829507985 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455829508016 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455829508498 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508546 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.051 " "Worst-case setup slack is 0.051" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.051               0.000 inst43  " "    0.051               0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.052               0.000 inst28  " "    0.052               0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.083               0.000 inst51  " "    0.083               0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.089               0.000 inst76  " "    0.089               0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.112               0.000 pin_name1  " "    0.112               0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.118               0.000 inst72  " "    0.118               0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.127               0.000 inst59  " "    0.127               0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.131               0.000 inst39  " "    0.131               0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 inst47  " "    0.135               0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.137               0.000 inst23  " "    0.137               0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.140               0.000 inst35  " "    0.140               0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.151               0.000 inst67  " "    0.151               0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.153               0.000 inst71  " "    0.153               0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.156               0.000 inst55  " "    0.156               0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.165               0.000 inst68  " "    0.165               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.170               0.000 inst31  " "    0.170               0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.171               0.000 inst32  " "    0.171               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.171               0.000 inst36  " "    0.171               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.173               0.000 inst27  " "    0.173               0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.173               0.000 inst48  " "    0.173               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178               0.000 inst24  " "    0.178               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178               0.000 inst56  " "    0.178               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178               0.000 inst60  " "    0.178               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 inst44  " "    0.179               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.186               0.000 inst64  " "    0.186               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188               0.000 inst75  " "    0.188               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.215               0.000 inst63  " "    0.215               0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.311               0.000 inst40  " "    0.311               0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.341               0.000 inst52  " "    0.341               0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.398               0.000 inst79  " "    0.398               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829508565 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455829508571 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455829508571 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.079 " "Worst-case hold slack is -0.079" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.079              -0.079 inst63  " "   -0.079              -0.079 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.022              -0.022 pin_name1  " "   -0.022              -0.022 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018              -0.018 inst52  " "   -0.018              -0.018 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.014              -0.014 inst71  " "   -0.014              -0.014 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.013              -0.013 inst31  " "   -0.013              -0.013 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.003              -0.003 inst27  " "   -0.003              -0.003 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.003              -0.003 inst59  " "   -0.003              -0.003 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.003               0.000 inst40  " "    0.003               0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.006               0.000 inst67  " "    0.006               0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.012               0.000 inst55  " "    0.012               0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.019               0.000 inst35  " "    0.019               0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.028               0.000 inst47  " "    0.028               0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.029               0.000 inst39  " "    0.029               0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032               0.000 inst23  " "    0.032               0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.040               0.000 inst72  " "    0.040               0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.045               0.000 inst76  " "    0.045               0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.047               0.000 inst51  " "    0.047               0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.063               0.000 inst43  " "    0.063               0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.073               0.000 inst75  " "    0.073               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.075               0.000 inst24  " "    0.075               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.075               0.000 inst56  " "    0.075               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077               0.000 inst64  " "    0.077               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.081               0.000 inst48  " "    0.081               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.085               0.000 inst60  " "    0.085               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.086               0.000 inst44  " "    0.086               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.089               0.000 inst68  " "    0.089               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 inst32  " "    0.094               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 inst36  " "    0.094               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.110               0.000 inst28  " "    0.110               0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.341               0.000 inst79  " "    0.341               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829508583 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829508594 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829508599 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -4.000 pin_name1  " "   -3.000              -4.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst23  " "   -1.000              -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst24  " "   -1.000              -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst27  " "   -1.000              -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst28  " "   -1.000              -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst31  " "   -1.000              -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst32  " "   -1.000              -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst35  " "   -1.000              -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst36  " "   -1.000              -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst39  " "   -1.000              -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst40  " "   -1.000              -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst43  " "   -1.000              -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst44  " "   -1.000              -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst47  " "   -1.000              -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst48  " "   -1.000              -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst51  " "   -1.000              -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst52  " "   -1.000              -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst55  " "   -1.000              -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst56  " "   -1.000              -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst59  " "   -1.000              -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst60  " "   -1.000              -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst63  " "   -1.000              -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst64  " "   -1.000              -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst67  " "   -1.000              -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst68  " "   -1.000              -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst71  " "   -1.000              -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst72  " "   -1.000              -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst75  " "   -1.000              -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst76  " "   -1.000              -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst79  " "   -1.000              -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829508612 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455829509475 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509574 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.237 " "Worst-case setup slack is 0.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.237               0.000 inst28  " "    0.237               0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.241               0.000 pin_name1  " "    0.241               0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.270               0.000 inst51  " "    0.270               0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.281               0.000 inst72  " "    0.281               0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.284               0.000 inst39  " "    0.284               0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.290               0.000 inst43  " "    0.290               0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.291               0.000 inst23  " "    0.291               0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.291               0.000 inst76  " "    0.291               0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.292               0.000 inst35  " "    0.292               0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.292               0.000 inst47  " "    0.292               0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.296               0.000 inst67  " "    0.296               0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.304               0.000 inst55  " "    0.304               0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.311               0.000 inst31  " "    0.311               0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.316               0.000 inst27  " "    0.316               0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.324               0.000 inst59  " "    0.324               0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.327               0.000 inst68  " "    0.327               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.328               0.000 inst71  " "    0.328               0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.330               0.000 inst32  " "    0.330               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.330               0.000 inst36  " "    0.330               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.331               0.000 inst48  " "    0.331               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.335               0.000 inst44  " "    0.335               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.335               0.000 inst60  " "    0.335               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.336               0.000 inst24  " "    0.336               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.336               0.000 inst56  " "    0.336               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.343               0.000 inst64  " "    0.343               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.344               0.000 inst75  " "    0.344               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.364               0.000 inst63  " "    0.364               0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.429               0.000 inst40  " "    0.429               0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.435               0.000 inst52  " "    0.435               0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.624               0.000 inst79  " "    0.624               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829509583 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455829509589 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455829509589 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.105 " "Worst-case hold slack is -0.105" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.105              -0.105 inst63  " "   -0.105              -0.105 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.066              -0.066 inst59  " "   -0.066              -0.066 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.060              -0.060 inst71  " "   -0.060              -0.060 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.049              -0.049 inst52  " "   -0.049              -0.049 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.041              -0.041 inst43  " "   -0.041              -0.041 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.033              -0.033 inst31  " "   -0.033              -0.033 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.029              -0.029 inst27  " "   -0.029              -0.029 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.027              -0.027 inst40  " "   -0.027              -0.027 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.027              -0.027 inst76  " "   -0.027              -0.027 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.021 pin_name1  " "   -0.021              -0.021 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018              -0.018 inst55  " "   -0.018              -0.018 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018              -0.018 inst67  " "   -0.018              -0.018 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.014              -0.014 inst35  " "   -0.014              -0.014 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.009              -0.009 inst51  " "   -0.009              -0.009 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.007              -0.007 inst47  " "   -0.007              -0.007 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.005              -0.005 inst23  " "   -0.005              -0.005 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.005              -0.005 inst39  " "   -0.005              -0.005 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.003              -0.003 inst72  " "   -0.003              -0.003 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.017               0.000 inst75  " "    0.017               0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.018               0.000 inst24  " "    0.018               0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.018               0.000 inst56  " "    0.018               0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.018               0.000 inst64  " "    0.018               0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 inst48  " "    0.024               0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.026               0.000 inst60  " "    0.026               0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.026               0.000 inst68  " "    0.026               0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.028               0.000 inst44  " "    0.028               0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.033               0.000 inst32  " "    0.033               0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.033               0.000 inst36  " "    0.033               0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.046               0.000 inst28  " "    0.046               0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.206               0.000 inst79  " "    0.206               0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829509595 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829509605 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455829509611 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -4.056 pin_name1  " "   -3.000              -4.056 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst23  " "   -1.000              -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst24  " "   -1.000              -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst27  " "   -1.000              -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst28  " "   -1.000              -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst31  " "   -1.000              -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst32  " "   -1.000              -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst35  " "   -1.000              -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst36  " "   -1.000              -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst39  " "   -1.000              -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst40  " "   -1.000              -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst43  " "   -1.000              -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst44  " "   -1.000              -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst47  " "   -1.000              -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst48  " "   -1.000              -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst51  " "   -1.000              -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst52  " "   -1.000              -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst55  " "   -1.000              -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst56  " "   -1.000              -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst59  " "   -1.000              -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst60  " "   -1.000              -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst63  " "   -1.000              -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst64  " "   -1.000              -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst67  " "   -1.000              -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst68  " "   -1.000              -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst71  " "   -1.000              -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst72  " "   -1.000              -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst75  " "   -1.000              -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst76  " "   -1.000              -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000              -1.000 inst79  " "   -1.000              -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455829509618 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455829510832 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455829510832 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "502 " "Peak virtual memory: 502 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455829510974 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 21:05:10 2016 " "Processing ended: Thu Feb 18 21:05:10 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455829510974 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455829510974 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455829510974 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455829510974 ""}
diff --git a/blinken_lights/db/blinken_Lights.sta.rdb b/blinken_lights/db/blinken_Lights.sta.rdb
new file mode 100644
index 0000000..cdeb800
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sta.rdb
diff --git a/blinken_lights/db/blinken_Lights.sta_cmp.6_slow_1200mv_85c.tdb b/blinken_lights/db/blinken_Lights.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..651eaad
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/blinken_lights/db/blinken_Lights.tis_db_list.ddb b/blinken_lights/db/blinken_Lights.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.tis_db_list.ddb
diff --git a/blinken_lights/db/blinken_Lights.tiscmp.fast_1200mv_0c.ddb b/blinken_lights/db/blinken_Lights.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..a2952f7
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.tiscmp.fast_1200mv_0c.ddb
diff --git a/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_0c.ddb b/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..ff48b0b
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_0c.ddb
diff --git a/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_85c.ddb b/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..05961b5
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.tiscmp.slow_1200mv_85c.ddb
diff --git a/blinken_lights/db/blinken_Lights.tmw_info b/blinken_lights/db/blinken_Lights.tmw_info
new file mode 100644
index 0000000..566752d
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:22
+start_analysis_synthesis:s:00:00:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:09-start_full_compilation
+start_assembler:s:00:00:03-start_full_compilation
+start_timing_analyzer:s:00:00:07-start_full_compilation
diff --git a/blinken_lights/db/blinken_Lights.vpr.ammdb b/blinken_lights/db/blinken_Lights.vpr.ammdb
new file mode 100644
index 0000000..af4b70a
--- /dev/null
+++ b/blinken_lights/db/blinken_Lights.vpr.ammdb
diff --git a/blinken_lights/db/logic_util_heursitic.dat b/blinken_lights/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..430bf4a
--- /dev/null
+++ b/blinken_lights/db/logic_util_heursitic.dat
diff --git a/blinken_lights/db/prev_cmp_blinken_Lights.qmsg b/blinken_lights/db/prev_cmp_blinken_Lights.qmsg
new file mode 100644
index 0000000..c003956
--- /dev/null
+++ b/blinken_lights/db/prev_cmp_blinken_Lights.qmsg
@@ -0,0 +1,115 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455638591471 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455638591479 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 16:03:11 2016 " "Processing started: Tue Feb 16 16:03:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455638591479 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455638591479 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455638591480 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455638592970 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "altclkctrl0.vhd 4 2 " "Found 4 design units, including 2 entities, in source file altclkctrl0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 altclkctrl0_altclkctrl_uhi-RTL " "Found design unit 1: altclkctrl0_altclkctrl_uhi-RTL" {  } { { "altclkctrl0.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 56 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455638594237 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 altclkctrl0-RTL " "Found design unit 2: altclkctrl0-RTL" {  } { { "altclkctrl0.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 109 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455638594237 ""} { "Info" "ISGN_ENTITY_NAME" "1 altclkctrl0_altclkctrl_uhi " "Found entity 1: altclkctrl0_altclkctrl_uhi" {  } { { "altclkctrl0.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 46 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455638594237 ""} { "Info" "ISGN_ENTITY_NAME" "2 altclkctrl0 " "Found entity 2: altclkctrl0" {  } { { "altclkctrl0.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 100 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455638594237 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455638594237 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "blinken_lights.bdf 1 1 " "Found 1 design units, including 1 entities, in source file blinken_lights.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 blinken_Lights " "Found entity 1: blinken_Lights" {  } { { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455638594289 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455638594289 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "blinken_Lights " "Elaborating entity \"blinken_Lights\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455638594432 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altclkctrl0 altclkctrl0:inst " "Elaborating entity \"altclkctrl0\" for hierarchy \"altclkctrl0:inst\"" {  } { { "blinken_Lights.bdf" "inst" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 232 736 896 296 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455638594535 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altclkctrl0_altclkctrl_uhi altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component " "Elaborating entity \"altclkctrl0_altclkctrl_uhi\" for hierarchy \"altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\"" {  } { { "altclkctrl0.vhd" "altclkctrl0_altclkctrl_uhi_component" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 141 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455638594590 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455638596155 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455638597364 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455638597364 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "42 " "Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455638597793 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455638597793 ""} { "Info" "ICUT_CUT_TM_LCELLS" "30 " "Implemented 30 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455638597793 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455638597793 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455638598574 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 16:03:18 2016 " "Processing ended: Tue Feb 16 16:03:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455638598574 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455638598574 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455638598574 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455638598574 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455638602915 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455638602970 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 16:03:19 2016 " "Processing started: Tue Feb 16 16:03:19 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455638602970 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455638602970 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights " "Command: quartus_fit --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455638602986 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455638603087 ""}
+{ "Info" "0" "" "Project  = blinken_Lights" {  } {  } 0 0 "Project  = blinken_Lights" 0 0 "Fitter" 0 0 1455638603087 ""}
+{ "Info" "0" "" "Revision = blinken_Lights" {  } {  } 0 0 "Revision = blinken_Lights" 0 0 "Fitter" 0 0 1455638603088 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1455638603495 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "blinken_Lights EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"blinken_Lights\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455638603950 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455638604017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455638604018 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455638604018 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455638604154 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455638604373 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455638604373 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455638604373 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455638604373 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 95 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455638604384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 97 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455638604384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 99 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455638604384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 101 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455638604384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 103 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455638604384 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455638604384 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455638604390 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "11 11 " "No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[9\] " "Pin LEDOUT\[9\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[9] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 6 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[8\] " "Pin LEDOUT\[8\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[8] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 7 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[7\] " "Pin LEDOUT\[7\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[7] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 8 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[6\] " "Pin LEDOUT\[6\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[6] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 9 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[5\] " "Pin LEDOUT\[5\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[5] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 10 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[4\] " "Pin LEDOUT\[4\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[4] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 11 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[3\] " "Pin LEDOUT\[3\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[3] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 12 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[2\] " "Pin LEDOUT\[2\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[2] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 13 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[1\] " "Pin LEDOUT\[1\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[1] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 14 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LEDOUT\[0\] " "Pin LEDOUT\[0\] not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDOUT[0] } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 184 1248 1424 200 "LEDOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDOUT[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 15 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_name1 " "Pin pin_name1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { pin_name1 } } } { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 256 504 680 272 "pin_name1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pin_name1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 16 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455638605046 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455638605046 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "blinken_Lights.sdc " "Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455638605304 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455638605311 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455638605323 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1455638605330 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455638605341 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "pin_name1~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Promoted node pin_name1~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\|clkctrl1 Global Clock CLKCTRL_G4 " "Automatically promoted altclkctrl0:inst\|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component\|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G4" {  } { { "altclkctrl0.vhd" "" { Text "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/altclkctrl0.vhd" 81 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component|wire_clkctrl1_outclk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 18 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1455638605364 ""}  } { { "blinken_Lights.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/blinken_Lights.bdf" { { 256 504 680 272 "pin_name1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pin_name1~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1455638605364 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455638605989 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455638605996 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455638606002 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455638606012 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455638606021 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455638606028 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455638606037 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455638606044 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455638606093 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455638606113 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455638606113 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "10 unused 2.5V 0 10 0 " "Number of I/O pins in group: 10 (unused VREF, 2.5V VCCIO, 0 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455638606143 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455638606143 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455638606143 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455638606161 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455638606161 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455638606161 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455638606202 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455638607032 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455638607107 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455638607119 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455638607440 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455638607446 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455638608006 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455638608593 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455638608593 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455638608952 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455638608967 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455638608967 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455638608967 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.41 " "Total time spent on timing analysis during the Fitter is 0.41 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455638608982 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455638609064 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455638609405 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455638609494 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455638609692 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455638610312 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/blinken_lights/output_files/blinken_Lights.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/blinken_lights/output_files/blinken_Lights.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455638611126 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1107 " "Peak virtual memory: 1107 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455638612589 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 16:03:32 2016 " "Processing ended: Tue Feb 16 16:03:32 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455638612589 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455638612589 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455638612589 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455638612589 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455638617095 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455638617102 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 16:03:36 2016 " "Processing started: Tue Feb 16 16:03:36 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455638617102 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455638617102 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455638617102 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455638618128 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455638618178 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455638618767 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 16:03:38 2016 " "Processing ended: Tue Feb 16 16:03:38 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455638618767 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455638618767 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455638618767 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455638618767 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455638619934 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455638620891 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455638620946 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 16:03:40 2016 " "Processing started: Tue Feb 16 16:03:40 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455638620946 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455638620946 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta blinken_Lights -c blinken_Lights " "Command: quartus_sta blinken_Lights -c blinken_Lights" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455638620960 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455638621071 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455638622015 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455638622045 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455638622135 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455638622135 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "blinken_Lights.sdc " "Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455638622787 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455638622802 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst79 inst79 " "create_clock -period 1.000 -name inst79 inst79" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst76 inst76 " "create_clock -period 1.000 -name inst76 inst76" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst75 inst75 " "create_clock -period 1.000 -name inst75 inst75" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst72 inst72 " "create_clock -period 1.000 -name inst72 inst72" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst71 inst71 " "create_clock -period 1.000 -name inst71 inst71" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst68 inst68 " "create_clock -period 1.000 -name inst68 inst68" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst67 inst67 " "create_clock -period 1.000 -name inst67 inst67" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst64 inst64 " "create_clock -period 1.000 -name inst64 inst64" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst63 inst63 " "create_clock -period 1.000 -name inst63 inst63" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst60 inst60 " "create_clock -period 1.000 -name inst60 inst60" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst59 inst59 " "create_clock -period 1.000 -name inst59 inst59" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst56 inst56 " "create_clock -period 1.000 -name inst56 inst56" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst55 inst55 " "create_clock -period 1.000 -name inst55 inst55" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst52 inst52 " "create_clock -period 1.000 -name inst52 inst52" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst51 inst51 " "create_clock -period 1.000 -name inst51 inst51" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst48 inst48 " "create_clock -period 1.000 -name inst48 inst48" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst47 inst47 " "create_clock -period 1.000 -name inst47 inst47" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst44 inst44 " "create_clock -period 1.000 -name inst44 inst44" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst43 inst43 " "create_clock -period 1.000 -name inst43 inst43" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst40 inst40 " "create_clock -period 1.000 -name inst40 inst40" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst39 inst39 " "create_clock -period 1.000 -name inst39 inst39" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst36 inst36 " "create_clock -period 1.000 -name inst36 inst36" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst35 inst35 " "create_clock -period 1.000 -name inst35 inst35" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst32 inst32 " "create_clock -period 1.000 -name inst32 inst32" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst31 inst31 " "create_clock -period 1.000 -name inst31 inst31" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst28 inst28 " "create_clock -period 1.000 -name inst28 inst28" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst27 inst27 " "create_clock -period 1.000 -name inst27 inst27" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst24 inst24 " "create_clock -period 1.000 -name inst24 inst24" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name inst23 inst23 " "create_clock -period 1.000 -name inst23 inst23" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name pin_name1 pin_name1 " "create_clock -period 1.000 -name pin_name1 pin_name1" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455638622821 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455638623004 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623016 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455638623080 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455638623193 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.008 " "Worst-case setup slack is 0.008" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.008         0.000 inst71  " "    0.008         0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.052         0.000 pin_name1  " "    0.052         0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.081         0.000 inst76  " "    0.081         0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.086         0.000 inst47  " "    0.086         0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.089         0.000 inst39  " "    0.089         0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.110         0.000 inst59  " "    0.110         0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.110         0.000 inst67  " "    0.110         0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.116         0.000 inst51  " "    0.116         0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.119         0.000 inst35  " "    0.119         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.119         0.000 inst43  " "    0.119         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123         0.000 inst75  " "    0.123         0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.131         0.000 inst24  " "    0.131         0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.133         0.000 inst31  " "    0.133         0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.138         0.000 inst36  " "    0.138         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.138         0.000 inst44  " "    0.138         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.141         0.000 inst28  " "    0.141         0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.141         0.000 inst55  " "    0.141         0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.143         0.000 inst23  " "    0.143         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.143         0.000 inst64  " "    0.143         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.147         0.000 inst60  " "    0.147         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.149         0.000 inst27  " "    0.149         0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.149         0.000 inst40  " "    0.149         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.155         0.000 inst63  " "    0.155         0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.157         0.000 inst32  " "    0.157         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.157         0.000 inst72  " "    0.157         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.288         0.000 inst52  " "    0.288         0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.317         0.000 inst48  " "    0.317         0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.317         0.000 inst79  " "    0.317         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.325         0.000 inst56  " "    0.325         0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.327         0.000 inst68  " "    0.327         0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638623346 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455638623385 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455638623385 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.062 " "Worst-case hold slack is -0.062" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.062        -0.062 inst55  " "   -0.062        -0.062 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.034        -0.034 inst28  " "   -0.034        -0.034 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.028        -0.028 inst68  " "   -0.028        -0.028 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.026        -0.026 inst56  " "   -0.026        -0.026 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018        -0.018 inst24  " "   -0.018        -0.018 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018        -0.018 inst48  " "   -0.018        -0.018 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.006        -0.006 inst75  " "   -0.006        -0.006 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.004        -0.004 inst51  " "   -0.004        -0.004 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.000         0.000 inst67  " "    0.000         0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.006         0.000 inst52  " "    0.006         0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013         0.000 inst59  " "    0.013         0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.017         0.000 pin_name1  " "    0.017         0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.028         0.000 inst27  " "    0.028         0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.033         0.000 inst39  " "    0.033         0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.033         0.000 inst47  " "    0.033         0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.039         0.000 inst76  " "    0.039         0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.057         0.000 inst63  " "    0.057         0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.067         0.000 inst31  " "    0.067         0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.080         0.000 inst71  " "    0.080         0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082         0.000 inst32  " "    0.082         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082         0.000 inst72  " "    0.082         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.087         0.000 inst23  " "    0.087         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.090         0.000 inst40  " "    0.090         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.091         0.000 inst60  " "    0.091         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.093         0.000 inst36  " "    0.093         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.093         0.000 inst44  " "    0.093         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.097         0.000 inst64  " "    0.097         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.130         0.000 inst35  " "    0.130         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.130         0.000 inst43  " "    0.130         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384         0.000 inst79  " "    0.384         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638623415 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638623462 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638623499 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -4.000 pin_name1  " "   -3.000        -4.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst23  " "   -1.000        -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst24  " "   -1.000        -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst27  " "   -1.000        -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst28  " "   -1.000        -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst31  " "   -1.000        -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst32  " "   -1.000        -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst35  " "   -1.000        -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst36  " "   -1.000        -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst39  " "   -1.000        -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst40  " "   -1.000        -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst43  " "   -1.000        -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst44  " "   -1.000        -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst47  " "   -1.000        -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst48  " "   -1.000        -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst51  " "   -1.000        -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst52  " "   -1.000        -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst55  " "   -1.000        -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst56  " "   -1.000        -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst59  " "   -1.000        -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst60  " "   -1.000        -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst63  " "   -1.000        -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst64  " "   -1.000        -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst67  " "   -1.000        -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst68  " "   -1.000        -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst71  " "   -1.000        -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst72  " "   -1.000        -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst75  " "   -1.000        -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst76  " "   -1.000        -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst79  " "   -1.000        -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638623535 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455638627858 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455638627912 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455638628453 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628560 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.077 " "Worst-case setup slack is 0.077" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077         0.000 inst71  " "    0.077         0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.093         0.000 pin_name1  " "    0.093         0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135         0.000 inst47  " "    0.135         0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135         0.000 inst76  " "    0.135         0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.139         0.000 inst39  " "    0.139         0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.152         0.000 inst67  " "    0.152         0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.154         0.000 inst59  " "    0.154         0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.158         0.000 inst35  " "    0.158         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.158         0.000 inst43  " "    0.158         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.159         0.000 inst51  " "    0.159         0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.160         0.000 inst31  " "    0.160         0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172         0.000 inst36  " "    0.172         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172         0.000 inst44  " "    0.172         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172         0.000 inst75  " "    0.172         0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.174         0.000 inst24  " "    0.174         0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177         0.000 inst23  " "    0.177         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178         0.000 inst64  " "    0.178         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180         0.000 inst28  " "    0.180         0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.183         0.000 inst55  " "    0.183         0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.183         0.000 inst60  " "    0.183         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184         0.000 inst40  " "    0.184         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184         0.000 inst63  " "    0.184         0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 inst27  " "    0.187         0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.191         0.000 inst32  " "    0.191         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.191         0.000 inst72  " "    0.191         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.296         0.000 inst52  " "    0.296         0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.334         0.000 inst48  " "    0.334         0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.341         0.000 inst56  " "    0.341         0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.343         0.000 inst68  " "    0.343         0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.398         0.000 inst79  " "    0.398         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638628614 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455638628620 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455638628620 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.058 " "Worst-case hold slack is -0.058" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.058        -0.058 inst55  " "   -0.058        -0.058 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.025        -0.025 inst28  " "   -0.025        -0.025 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021        -0.021 inst68  " "   -0.021        -0.021 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.018        -0.018 inst56  " "   -0.018        -0.018 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.014        -0.014 inst24  " "   -0.014        -0.014 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012        -0.012 inst48  " "   -0.012        -0.012 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.010        -0.010 pin_name1  " "   -0.010        -0.010 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.008        -0.008 inst75  " "   -0.008        -0.008 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.001        -0.001 inst51  " "   -0.001        -0.001 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.002         0.000 inst52  " "    0.002         0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.005         0.000 inst67  " "    0.005         0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.016         0.000 inst59  " "    0.016         0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.021         0.000 inst27  " "    0.021         0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.029         0.000 inst47  " "    0.029         0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.030         0.000 inst39  " "    0.030         0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032         0.000 inst76  " "    0.032         0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.049         0.000 inst63  " "    0.049         0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.053         0.000 inst71  " "    0.053         0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.061         0.000 inst31  " "    0.061         0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.072         0.000 inst32  " "    0.072         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.072         0.000 inst72  " "    0.072         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077         0.000 inst23  " "    0.077         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.078         0.000 inst40  " "    0.078         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.079         0.000 inst60  " "    0.079         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082         0.000 inst36  " "    0.082         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082         0.000 inst44  " "    0.082         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.085         0.000 inst64  " "    0.085         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.128         0.000 inst35  " "    0.128         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.128         0.000 inst43  " "    0.128         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.341         0.000 inst79  " "    0.341         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638628641 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638628668 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638628691 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -4.000 pin_name1  " "   -3.000        -4.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst23  " "   -1.000        -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst24  " "   -1.000        -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst27  " "   -1.000        -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst28  " "   -1.000        -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst31  " "   -1.000        -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst32  " "   -1.000        -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst35  " "   -1.000        -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst36  " "   -1.000        -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst39  " "   -1.000        -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst40  " "   -1.000        -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst43  " "   -1.000        -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst44  " "   -1.000        -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst47  " "   -1.000        -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst48  " "   -1.000        -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst51  " "   -1.000        -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst52  " "   -1.000        -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst55  " "   -1.000        -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst56  " "   -1.000        -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst59  " "   -1.000        -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst60  " "   -1.000        -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst63  " "   -1.000        -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst64  " "   -1.000        -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst67  " "   -1.000        -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst68  " "   -1.000        -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst71  " "   -1.000        -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst72  " "   -1.000        -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst75  " "   -1.000        -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst76  " "   -1.000        -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst79  " "   -1.000        -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638628713 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455638632712 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633316 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.273 " "Worst-case setup slack is 0.273" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.273         0.000 pin_name1  " "    0.273         0.000 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279         0.000 inst71  " "    0.279         0.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.286         0.000 inst76  " "    0.286         0.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.290         0.000 inst39  " "    0.290         0.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.292         0.000 inst47  " "    0.292         0.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.297         0.000 inst67  " "    0.297         0.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298         0.000 inst59  " "    0.298         0.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.305         0.000 inst51  " "    0.305         0.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 inst75  " "    0.312         0.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.319         0.000 inst35  " "    0.319         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.319         0.000 inst43  " "    0.319         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.320         0.000 inst24  " "    0.320         0.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.323         0.000 inst28  " "    0.323         0.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.332         0.000 inst27  " "    0.332         0.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.332         0.000 inst36  " "    0.332         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.332         0.000 inst44  " "    0.332         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.336         0.000 inst23  " "    0.336         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.338         0.000 inst64  " "    0.338         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.340         0.000 inst40  " "    0.340         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.342         0.000 inst60  " "    0.342         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.345         0.000 inst32  " "    0.345         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.345         0.000 inst72  " "    0.345         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.352         0.000 inst31  " "    0.352         0.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.353         0.000 inst63  " "    0.353         0.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.355         0.000 inst55  " "    0.355         0.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.422         0.000 inst52  " "    0.422         0.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.432         0.000 inst48  " "    0.432         0.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.435         0.000 inst56  " "    0.435         0.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.438         0.000 inst68  " "    0.438         0.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.624         0.000 inst79  " "    0.624         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638633360 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455638633371 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455638633371 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.098 " "Worst-case hold slack is -0.098" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.098        -0.098 inst55  " "   -0.098        -0.098 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.052        -0.052 inst68  " "   -0.052        -0.052 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.049        -0.049 inst56  " "   -0.049        -0.049 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.047        -0.047 inst28  " "   -0.047        -0.047 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.045        -0.045 inst48  " "   -0.045        -0.045 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.036        -0.036 inst24  " "   -0.036        -0.036 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.029        -0.029 inst75  " "   -0.029        -0.029 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.029        -0.029 pin_name1  " "   -0.029        -0.029 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.027        -0.027 inst51  " "   -0.027        -0.027 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.023        -0.023 inst52  " "   -0.023        -0.023 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021        -0.021 inst31  " "   -0.021        -0.021 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020        -0.020 inst67  " "   -0.020        -0.020 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.017        -0.017 inst71  " "   -0.017        -0.017 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.015        -0.015 inst63  " "   -0.015        -0.015 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012        -0.012 inst59  " "   -0.012        -0.012 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.008        -0.008 inst27  " "   -0.008        -0.008 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.007        -0.007 inst47  " "   -0.007        -0.007 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.005        -0.005 inst39  " "   -0.005        -0.005 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.001        -0.001 inst76  " "   -0.001        -0.001 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.016         0.000 inst32  " "    0.016         0.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.016         0.000 inst72  " "    0.016         0.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.018         0.000 inst23  " "    0.018         0.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.019         0.000 inst60  " "    0.019         0.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.021         0.000 inst40  " "    0.021         0.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023         0.000 inst36  " "    0.023         0.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.023         0.000 inst44  " "    0.023         0.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024         0.000 inst64  " "    0.024         0.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032         0.000 inst35  " "    0.032         0.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.032         0.000 inst43  " "    0.032         0.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.206         0.000 inst79  " "    0.206         0.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638633404 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638633447 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455638633809 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -4.057 pin_name1  " "   -3.000        -4.057 pin_name1 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst23  " "   -1.000        -1.000 inst23 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst24  " "   -1.000        -1.000 inst24 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst27  " "   -1.000        -1.000 inst27 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst28  " "   -1.000        -1.000 inst28 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst31  " "   -1.000        -1.000 inst31 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst32  " "   -1.000        -1.000 inst32 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst35  " "   -1.000        -1.000 inst35 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst36  " "   -1.000        -1.000 inst36 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst39  " "   -1.000        -1.000 inst39 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst40  " "   -1.000        -1.000 inst40 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst43  " "   -1.000        -1.000 inst43 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst44  " "   -1.000        -1.000 inst44 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst47  " "   -1.000        -1.000 inst47 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst48  " "   -1.000        -1.000 inst48 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst51  " "   -1.000        -1.000 inst51 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst52  " "   -1.000        -1.000 inst52 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst55  " "   -1.000        -1.000 inst55 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst56  " "   -1.000        -1.000 inst56 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst59  " "   -1.000        -1.000 inst59 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst60  " "   -1.000        -1.000 inst60 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst63  " "   -1.000        -1.000 inst63 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst64  " "   -1.000        -1.000 inst64 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst67  " "   -1.000        -1.000 inst67 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst68  " "   -1.000        -1.000 inst68 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst71  " "   -1.000        -1.000 inst71 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst72  " "   -1.000        -1.000 inst72 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst75  " "   -1.000        -1.000 inst75 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst76  " "   -1.000        -1.000 inst76 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -1.000 inst79  " "   -1.000        -1.000 inst79 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455638634009 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455638640030 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455638640031 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "500 " "Peak virtual memory: 500 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455638640607 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 16:04:00 2016 " "Processing ended: Tue Feb 16 16:04:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455638640607 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455638640607 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455638640607 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455638640607 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 7 s " "Quartus II Full Compilation was successful. 0 errors, 7 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455638652777 ""}
diff --git a/blinken_lights/greybox_tmp/cbx_args.txt b/blinken_lights/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..b6e510b
--- /dev/null
+++ b/blinken_lights/greybox_tmp/cbx_args.txt
@@ -0,0 +1,10 @@
+ENA_REGISTER_MODE="falling edge"
+INTENDED_DEVICE_FAMILY="Cyclone III"
+USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=OFF
+clock_type=AUTO
+DEVICE_FAMILY="Cyclone III"
+clkselect
+ena
+inclk
+inclk
+outclk
diff --git a/blinken_lights/incremental_db/README b/blinken_lights/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/blinken_lights/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.db_info b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.db_info
new file mode 100644
index 0000000..296c6b0
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 18:01:43 2016
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.ammdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.ammdb
new file mode 100644
index 0000000..8f8d5f6
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.ammdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.cdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.cdb
new file mode 100644
index 0000000..9152e4f
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.cdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.dfp b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.dfp
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.hdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.hdb
new file mode 100644
index 0000000..d370f68
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.hdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.kpt b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.kpt
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.logdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.rcfdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..8436474
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.cmp.rcfdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.cdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.cdb
new file mode 100644
index 0000000..a2d4709
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.cdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.dpi b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.dpi
new file mode 100644
index 0000000..58abac8
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.dpi
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.cdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..8b04353
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.cdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hb_info b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hb_info
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..cdf7cf0
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.hdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.sig b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hdb b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hdb
new file mode 100644
index 0000000..e54e808
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.hdb
diff --git a/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.kpt b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.kpt
new file mode 100644
index 0000000..b12d24b
--- /dev/null
+++ b/blinken_lights/incremental_db/compiled_partitions/blinken_Lights.root_partition.map.kpt
diff --git a/blinken_lights/output_files/Chain3.cdf b/blinken_lights/output_files/Chain3.cdf
new file mode 100644
index 0000000..32c0e8c
--- /dev/null
+++ b/blinken_lights/output_files/Chain3.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/blinken_lights/output_files/") File("blinken_Lights.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/blinken_lights/output_files/blinken_Lights.asm.rpt b/blinken_lights/output_files/blinken_Lights.asm.rpt
new file mode 100644
index 0000000..7082067
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for blinken_Lights
+Thu Feb 18 21:05:03 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Thu Feb 18 21:05:03 2016 ;
+; Revision Name         ; blinken_Lights                        ;
+; Top-level Entity Name ; blinken_Lights                        ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Generated Files                                                     ;
++-------------------------------------------------------------------------------+
+; File Name                                                                     ;
++-------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.sof ;
++-------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.sof ;
++----------------+----------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                ;
++----------------+----------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                           ;
+; JTAG usercode  ; 0x000CEA6F                                                                             ;
+; Checksum       ; 0x000CEA6F                                                                             ;
++----------------+----------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 21:05:02 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 461 megabytes
+    Info: Processing ended: Thu Feb 18 21:05:03 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/blinken_lights/output_files/blinken_Lights.done b/blinken_lights/output_files/blinken_Lights.done
new file mode 100644
index 0000000..81b38f6
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.done
@@ -0,0 +1 @@
+Thu Feb 18 21:05:11 2016
diff --git a/blinken_lights/output_files/blinken_Lights.fit.rpt b/blinken_lights/output_files/blinken_Lights.fit.rpt
new file mode 100644
index 0000000..152df1d
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.fit.rpt
@@ -0,0 +1,1364 @@
+Fitter report for blinken_Lights
+Thu Feb 18 21:05:00 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Estimated Delay Added for Hold Timing Summary
+ 35. Estimated Delay Added for Hold Timing Details
+ 36. Fitter Messages
+ 37. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Thu Feb 18 21:05:00 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; blinken_Lights                             ;
+; Top-level Entity Name              ; blinken_Lights                             ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 59 / 15,408 ( < 1 % )                      ;
+;     Total combinational functions  ; 30 / 15,408 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 30 / 15,408 ( < 1 % )                      ;
+; Total registers                    ; 30                                         ;
+; Total pins                         ; 11 / 347 ( 3 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; LEDOUT[9] ; Missing drive strength and slew rate ;
+; LEDOUT[8] ; Missing drive strength and slew rate ;
+; LEDOUT[7] ; Missing drive strength and slew rate ;
+; LEDOUT[6] ; Missing drive strength and slew rate ;
+; LEDOUT[5] ; Missing drive strength and slew rate ;
+; LEDOUT[4] ; Missing drive strength and slew rate ;
+; LEDOUT[3] ; Missing drive strength and slew rate ;
+; LEDOUT[2] ; Missing drive strength and slew rate ;
+; LEDOUT[1] ; Missing drive strength and slew rate ;
+; LEDOUT[0] ; Missing drive strength and slew rate ;
++-----------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 94 ) ; 0.00 % ( 0 / 94 )          ; 0.00 % ( 0 / 94 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 94 ) ; 0.00 % ( 0 / 94 )          ; 0.00 % ( 0 / 94 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 84 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 59 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 29                    ;
+;     -- Register only                        ; 29                    ;
+;     -- Combinational with a register        ; 1                     ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 0                     ;
+;     -- 3 input functions                    ; 0                     ;
+;     -- <=2 input functions                  ; 30                    ;
+;     -- Register only                        ; 29                    ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 30                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 30 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 30 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 16 / 963 ( 2 % )      ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 11 / 347 ( 3 % )      ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
+; Maximum fan-out                             ; 3                     ;
+; Highest non-global fan-out                  ; 3                     ;
+; Total fan-out                               ; 134                   ;
+; Average fan-out                             ; 1.22                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 59 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 29                   ; 0                              ;
+;     -- Register only                        ; 29                   ; 0                              ;
+;     -- Combinational with a register        ; 1                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 0                    ; 0                              ;
+;     -- 3 input functions                    ; 0                    ; 0                              ;
+;     -- <=2 input functions                  ; 30                   ; 0                              ;
+;     -- Register only                        ; 29                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 30                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 30                   ; 0                              ;
+;     -- Dedicated logic registers            ; 30 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 16 / 963 ( 2 % )     ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 11                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+; Clock control block                         ; 1 / 24 ( 4 % )       ; 0 / 24 ( 0 % )                 ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 129                  ; 5                              ;
+;     -- Registered Connections               ; 69                   ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 1                    ; 0                              ;
+;     -- Output Ports                         ; 10                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                     ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; pin_name1 ; G21   ; 6        ; 41           ; 15           ; 0            ; 1                     ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; LEDOUT[0] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[1] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[2] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[3] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[4] ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[5] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[6] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[7] ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[8] ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDOUT[9] ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 14 / 33 ( 42 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDOUT[9]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDOUT[8]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDOUT[6]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDOUT[7]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDOUT[5]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F2       ; 15         ; 1        ; LEDOUT[4]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; pin_name1                                                 ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDOUT[3]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; LEDOUT[0]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDOUT[1]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDOUT[2]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                     ;
++-------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                                              ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                              ; Library Name ;
++-------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------+--------------+
+; |blinken_Lights                                                         ; 59 (59)     ; 30 (30)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 11   ; 0            ; 29 (29)      ; 29 (29)           ; 1 (1)            ; |blinken_Lights                                                                                  ; work         ;
+;    |altclkctrl0:inst|                                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |blinken_Lights|altclkctrl0:inst                                                                 ; work         ;
+;       |altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component| ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |blinken_Lights|altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component ; work         ;
++-------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                       ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name      ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; LEDOUT[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; pin_name1 ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; pin_name1           ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                             ;
++-----------+----------------+---------+-------+--------+----------------------+------------------+---------------------------+
+; Name      ; Location       ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------+----------------+---------+-------+--------+----------------------+------------------+---------------------------+
+; inst23    ; FF_X31_Y21_N7  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst24    ; FF_X30_Y21_N11 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst27    ; FF_X30_Y21_N17 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst28    ; FF_X29_Y21_N27 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst31    ; FF_X29_Y21_N13 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst32    ; FF_X28_Y21_N5  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst35    ; FF_X28_Y21_N7  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst36    ; FF_X27_Y21_N5  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst39    ; FF_X27_Y21_N7  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst40    ; FF_X26_Y21_N29 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst43    ; FF_X26_Y21_N23 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst44    ; FF_X17_Y21_N5  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst47    ; FF_X17_Y21_N7  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst48    ; FF_X16_Y21_N11 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst51    ; FF_X16_Y21_N1  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst52    ; FF_X15_Y22_N11 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst55    ; FF_X15_Y22_N5  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst56    ; FF_X14_Y22_N11 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst59    ; FF_X14_Y22_N17 ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst60    ; FF_X10_Y22_N3  ; 2       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst63    ; FF_X10_Y22_N13 ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst64    ; FF_X2_Y22_N31  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst67    ; FF_X2_Y22_N13  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst68    ; FF_X1_Y22_N29  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst71    ; FF_X1_Y22_N3   ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst72    ; FF_X2_Y24_N17  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst75    ; FF_X1_Y24_N3   ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst76    ; FF_X1_Y24_N11  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; inst79    ; FF_X1_Y27_N15  ; 3       ; Clock ; no     ; --                   ; --               ; --                        ;
+; pin_name1 ; PIN_G21        ; 1       ; Clock ; yes    ; Global Clock         ; GCLK9            ; VCC                       ;
++-----------+----------------+---------+-------+--------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                 ;
++-----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name      ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; pin_name1 ; PIN_G21  ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; VCC                       ;
++-----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++----------+----------------------+
+; Name     ; Fan-Out              ;
++----------+----------------------+
+; inst63   ; 3                    ;
+; inst64   ; 3                    ;
+; inst67   ; 3                    ;
+; inst68   ; 3                    ;
+; inst71   ; 3                    ;
+; inst72   ; 3                    ;
+; inst75   ; 3                    ;
+; inst76   ; 3                    ;
+; inst79   ; 3                    ;
+; inst23   ; 2                    ;
+; inst24   ; 2                    ;
+; inst27   ; 2                    ;
+; inst28   ; 2                    ;
+; inst31   ; 2                    ;
+; inst32   ; 2                    ;
+; inst35   ; 2                    ;
+; inst36   ; 2                    ;
+; inst39   ; 2                    ;
+; inst40   ; 2                    ;
+; inst43   ; 2                    ;
+; inst44   ; 2                    ;
+; inst47   ; 2                    ;
+; inst48   ; 2                    ;
+; inst51   ; 2                    ;
+; inst52   ; 2                    ;
+; inst55   ; 2                    ;
+; inst56   ; 2                    ;
+; inst59   ; 2                    ;
+; inst60   ; 2                    ;
+; inst80   ; 2                    ;
+; inst23~0 ; 1                    ;
+; inst24~0 ; 1                    ;
+; inst27~0 ; 1                    ;
+; inst28~0 ; 1                    ;
+; inst31~0 ; 1                    ;
+; inst32~0 ; 1                    ;
+; inst35~0 ; 1                    ;
+; inst36~0 ; 1                    ;
+; inst39~0 ; 1                    ;
+; inst40~0 ; 1                    ;
+; inst43~0 ; 1                    ;
+; inst44~0 ; 1                    ;
+; inst47~0 ; 1                    ;
+; inst48~0 ; 1                    ;
+; inst51~0 ; 1                    ;
+; inst52~0 ; 1                    ;
+; inst55~0 ; 1                    ;
+; inst56~0 ; 1                    ;
+; inst59~0 ; 1                    ;
+; inst60~0 ; 1                    ;
+; inst63~0 ; 1                    ;
+; inst64~0 ; 1                    ;
+; inst67~0 ; 1                    ;
+; inst68~0 ; 1                    ;
+; inst71~0 ; 1                    ;
+; inst72~0 ; 1                    ;
+; inst75~0 ; 1                    ;
+; inst76~0 ; 1                    ;
+; inst79~0 ; 1                    ;
+; inst80~0 ; 1                    ;
++----------+----------------------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary                         ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage                 ;
++-----------------------+-----------------------+
+; Block interconnects   ; 40 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects      ; 12 / 31,272 ( < 1 % ) ;
+; Direct links          ; 22 / 47,787 ( < 1 % ) ;
+; Global clocks         ; 1 / 20 ( 5 % )        ;
+; Local interconnects   ; 48 / 15,408 ( < 1 % ) ;
+; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects      ; 14 / 41,310 ( < 1 % ) ;
++-----------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 3.69) ; Number of LABs  (Total = 16) ;
++--------------------------------------------+------------------------------+
+; 1                                          ; 0                            ;
+; 2                                          ; 2                            ;
+; 3                                          ; 1                            ;
+; 4                                          ; 13                           ;
+; 5                                          ; 0                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 0                            ;
+; 8                                          ; 0                            ;
+; 9                                          ; 0                            ;
+; 10                                         ; 0                            ;
+; 11                                         ; 0                            ;
+; 12                                         ; 0                            ;
+; 13                                         ; 0                            ;
+; 14                                         ; 0                            ;
+; 15                                         ; 0                            ;
+; 16                                         ; 0                            ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 16) ;
++------------------------------------+------------------------------+
+; 1 Clock                            ; 16                           ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 4.81) ; Number of LABs  (Total = 16) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 0                            ;
+; 3                                           ; 2                            ;
+; 4                                           ; 0                            ;
+; 5                                           ; 13                           ;
+; 6                                           ; 1                            ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 1.25) ; Number of LABs  (Total = 16) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 12                           ;
+; 2                                               ; 4                            ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 1.00) ; Number of LABs  (Total = 16) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 16                           ;
++---------------------------------------------+------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 11        ; 0            ; 11        ; 0            ; 0            ; 11        ; 11        ; 0            ; 11        ; 11        ; 0            ; 10           ; 0            ; 0            ; 1            ; 0            ; 10           ; 1            ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 11        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 11           ; 0         ; 11           ; 11           ; 0         ; 0         ; 11           ; 0         ; 0         ; 11           ; 1            ; 11           ; 11           ; 10           ; 11           ; 1            ; 10           ; 11           ; 11           ; 11           ; 1            ; 11           ; 11           ; 11           ; 11           ; 11           ; 0         ; 11           ; 11           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; LEDOUT[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDOUT[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; pin_name1          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; pin_name1       ; pin_name1            ; 2.1               ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details              ;
++-----------------+----------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; inst23          ; inst23               ; 2.102             ;
+; inst44          ; inst44               ; 0.999             ;
+; inst64          ; inst64               ; 0.869             ;
+; inst72          ; inst72               ; 0.869             ;
+; inst79          ; inst79               ; 0.756             ;
+; inst60          ; inst60               ; 0.735             ;
+; inst52          ; inst52               ; 0.699             ;
+; inst28          ; inst28               ; 0.465             ;
+; inst32          ; inst32               ; 0.457             ;
+; inst68          ; inst68               ; 0.457             ;
+; inst75          ; inst75               ; 0.455             ;
+; inst24          ; inst24               ; 0.451             ;
+; inst36          ; inst36               ; 0.451             ;
+; inst40          ; inst40               ; 0.451             ;
+; inst48          ; inst48               ; 0.451             ;
+; inst56          ; inst56               ; 0.451             ;
+; inst31          ; inst31               ; 0.323             ;
+; inst27          ; inst27               ; 0.245             ;
+; inst35          ; inst35               ; 0.245             ;
+; inst39          ; inst39               ; 0.245             ;
+; inst43          ; inst43               ; 0.245             ;
+; inst47          ; inst47               ; 0.245             ;
+; inst51          ; inst51               ; 0.245             ;
+; inst55          ; inst55               ; 0.245             ;
+; inst59          ; inst59               ; 0.245             ;
+; inst63          ; inst63               ; 0.245             ;
+; inst67          ; inst67               ; 0.245             ;
+; inst71          ; inst71               ; 0.245             ;
+; inst76          ; inst76               ; 0.245             ;
++-----------------+----------------------+-------------------+
+Note: This table only shows the top 29 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EP3C16F484C6 for design "blinken_Lights"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176352): Promoted node pin_name1~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component|clkctrl1 to use location or clock signal Global Clock CLKCTRL_G9
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.30 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 850 megabytes
+    Info: Processing ended: Thu Feb 18 21:05:00 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/blinken_lights/output_files/blinken_Lights.fit.smsg.
+
+
diff --git a/blinken_lights/output_files/blinken_Lights.fit.smsg b/blinken_lights/output_files/blinken_Lights.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/blinken_lights/output_files/blinken_Lights.fit.summary b/blinken_lights/output_files/blinken_Lights.fit.summary
new file mode 100644
index 0000000..a3e0145
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Thu Feb 18 21:05:00 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : blinken_Lights
+Top-level Entity Name : blinken_Lights
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 59 / 15,408 ( < 1 % )
+    Total combinational functions : 30 / 15,408 ( < 1 % )
+    Dedicated logic registers : 30 / 15,408 ( < 1 % )
+Total registers : 30
+Total pins : 11 / 347 ( 3 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/blinken_lights/output_files/blinken_Lights.flow.rpt b/blinken_lights/output_files/blinken_Lights.flow.rpt
new file mode 100644
index 0000000..baec2b5
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.flow.rpt
@@ -0,0 +1,127 @@
+Flow report for blinken_Lights
+Thu Feb 18 21:05:10 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Thu Feb 18 21:05:03 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; blinken_Lights                             ;
+; Top-level Entity Name              ; blinken_Lights                             ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 59 / 15,408 ( < 1 % )                      ;
+;     Total combinational functions  ; 30 / 15,408 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 30 / 15,408 ( < 1 % )                      ;
+; Total registers                    ; 30                                         ;
+; Total pins                         ; 11 / 347 ( 3 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/18/2016 21:04:50 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; blinken_Lights      ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                 ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145582949010492 ; --            ; --          ; --         ;
+; IP_TOOL_NAME                        ; ALTCLKCTRL                      ; --            ; --          ; --         ;
+; IP_TOOL_VERSION                     ; 13.0                            ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --         ;
+; MISC_FILE                           ; altclkctrl0.bsf                 ; --            ; --          ; --         ;
+; MISC_FILE                           ; altclkctrl0.cmp                 ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top        ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 534 MB              ; 00:00:02                           ;
+; Fitter                    ; 00:00:07     ; 1.0                     ; 850 MB              ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 453 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 502 MB              ; 00:00:04                           ;
+; Total                     ; 00:00:14     ; --                      ; --                  ; 00:00:13                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights
+quartus_fit --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights
+quartus_asm --read_settings_files=off --write_settings_files=off blinken_Lights -c blinken_Lights
+quartus_sta blinken_Lights -c blinken_Lights
+
+
+
diff --git a/blinken_lights/output_files/blinken_Lights.jdi b/blinken_lights/output_files/blinken_Lights.jdi
new file mode 100644
index 0000000..60ab0e3
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="35acc6b732097c18a5c5"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="blinken_Lights.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/blinken_lights/output_files/blinken_Lights.map.rpt b/blinken_lights/output_files/blinken_Lights.map.rpt
new file mode 100644
index 0000000..4a8c640
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.map.rpt
@@ -0,0 +1,277 @@
+Analysis & Synthesis report for blinken_Lights
+Thu Feb 18 21:04:52 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis IP Cores Summary
+  9. General Register Statistics
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Thu Feb 18 21:04:52 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; blinken_Lights                             ;
+; Top-level Entity Name              ; blinken_Lights                             ;
+; Family                             ; Cyclone III                                ;
+; Total logic elements               ; 30                                         ;
+;     Total combinational functions  ; 30                                         ;
+;     Dedicated logic registers      ; 30                                         ;
+; Total registers                    ; 30                                         ;
+; Total pins                         ; 11                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; blinken_Lights     ; blinken_Lights     ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                               ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                     ; Library ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+---------+
+; altclkctrl0.vhd                  ; yes             ; User Wizard-Generated File         ; C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd    ;         ;
+; blinken_Lights.bdf               ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/blinken_lights/blinken_Lights.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary          ;
++---------------------------------------------+--------+
+; Resource                                    ; Usage  ;
++---------------------------------------------+--------+
+; Estimated Total logic elements              ; 30     ;
+;                                             ;        ;
+; Total combinational functions               ; 30     ;
+; Logic element usage by number of LUT inputs ;        ;
+;     -- 4 input functions                    ; 0      ;
+;     -- 3 input functions                    ; 0      ;
+;     -- <=2 input functions                  ; 30     ;
+;                                             ;        ;
+; Logic elements by mode                      ;        ;
+;     -- normal mode                          ; 30     ;
+;     -- arithmetic mode                      ; 0      ;
+;                                             ;        ;
+; Total registers                             ; 30     ;
+;     -- Dedicated logic registers            ; 30     ;
+;     -- I/O registers                        ; 0      ;
+;                                             ;        ;
+; I/O pins                                    ; 11     ;
+; Embedded Multiplier 9-bit elements          ; 0      ;
+; Maximum fan-out node                        ; inst79 ;
+; Maximum fan-out                             ; 3      ;
+; Total fan-out                               ; 112    ;
+; Average fan-out                             ; 1.35   ;
++---------------------------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                   ;
++-------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                                              ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                              ; Library Name ;
++-------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------+--------------+
+; |blinken_Lights                                                         ; 30 (30)           ; 30 (30)      ; 0           ; 0            ; 0       ; 0         ; 11   ; 0            ; |blinken_Lights                                                                                  ; work         ;
+;    |altclkctrl0:inst|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |blinken_Lights|altclkctrl0:inst                                                                 ; work         ;
+;       |altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |blinken_Lights|altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component ; work         ;
++-------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                            ;
++--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                  ; IP Include File                                               ;
++--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------+
+; Altera ; ALTCLKCTRL   ; 13.0    ; N/A          ; N/A          ; |blinken_Lights|altclkctrl0:inst ; C:/Users/Asus/Documents/GitHub/blinken_lights/altclkctrl0.vhd ;
++--------+--------------+---------+--------------+--------------+----------------------------------+---------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 30    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 21:04:50 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off blinken_Lights -c blinken_Lights
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 4 design units, including 2 entities, in source file altclkctrl0.vhd
+    Info (12022): Found design unit 1: altclkctrl0_altclkctrl_uhi-RTL
+    Info (12022): Found design unit 2: altclkctrl0-RTL
+    Info (12023): Found entity 1: altclkctrl0_altclkctrl_uhi
+    Info (12023): Found entity 2: altclkctrl0
+Info (12021): Found 1 design units, including 1 entities, in source file blinken_lights.bdf
+    Info (12023): Found entity 1: blinken_Lights
+Info (12127): Elaborating entity "blinken_Lights" for the top level hierarchy
+Info (12128): Elaborating entity "altclkctrl0" for hierarchy "altclkctrl0:inst"
+Info (12128): Elaborating entity "altclkctrl0_altclkctrl_uhi" for hierarchy "altclkctrl0:inst|altclkctrl0_altclkctrl_uhi:altclkctrl0_altclkctrl_uhi_component"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 42 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 1 input pins
+    Info (21059): Implemented 10 output pins
+    Info (21061): Implemented 30 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 542 megabytes
+    Info: Processing ended: Thu Feb 18 21:04:52 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/blinken_lights/output_files/blinken_Lights.map.summary b/blinken_lights/output_files/blinken_Lights.map.summary
new file mode 100644
index 0000000..034d3c9
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Thu Feb 18 21:04:52 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : blinken_Lights
+Top-level Entity Name : blinken_Lights
+Family : Cyclone III
+Total logic elements : 30
+    Total combinational functions : 30
+    Dedicated logic registers : 30
+Total registers : 30
+Total pins : 11
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/blinken_lights/output_files/blinken_Lights.pin b/blinken_lights/output_files/blinken_Lights.pin
new file mode 100644
index 0000000..83d1878
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "blinken_Lights"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDOUT[9]                    : B1        : output : 2.5 V             :         : 1         : Y              
+LEDOUT[8]                    : B2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDOUT[6]                    : C1        : output : 2.5 V             :         : 1         : Y              
+LEDOUT[7]                    : C2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDOUT[5]                    : E1        : output : 2.5 V             :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+LEDOUT[4]                    : F2        : output : 2.5 V             :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+pin_name1                    : G21       : input  : 2.5 V             :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDOUT[3]                    : H1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+LEDOUT[0]                    : J1        : output : 2.5 V             :         : 1         : Y              
+LEDOUT[1]                    : J2        : output : 2.5 V             :         : 1         : Y              
+LEDOUT[2]                    : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/blinken_lights/output_files/blinken_Lights.sof b/blinken_lights/output_files/blinken_Lights.sof
new file mode 100644
index 0000000..b1761a7
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.sof
diff --git a/blinken_lights/output_files/blinken_Lights.sta.rpt b/blinken_lights/output_files/blinken_Lights.sta.rpt
new file mode 100644
index 0000000..a76070e
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.sta.rpt
@@ -0,0 +1,4973 @@
+TimeQuest Timing Analyzer report for blinken_Lights
+Thu Feb 18 21:05:10 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'inst28'
+ 13. Slow 1200mV 85C Model Setup: 'inst43'
+ 14. Slow 1200mV 85C Model Setup: 'pin_name1'
+ 15. Slow 1200mV 85C Model Setup: 'inst51'
+ 16. Slow 1200mV 85C Model Setup: 'inst76'
+ 17. Slow 1200mV 85C Model Setup: 'inst72'
+ 18. Slow 1200mV 85C Model Setup: 'inst59'
+ 19. Slow 1200mV 85C Model Setup: 'inst39'
+ 20. Slow 1200mV 85C Model Setup: 'inst47'
+ 21. Slow 1200mV 85C Model Setup: 'inst23'
+ 22. Slow 1200mV 85C Model Setup: 'inst35'
+ 23. Slow 1200mV 85C Model Setup: 'inst71'
+ 24. Slow 1200mV 85C Model Setup: 'inst67'
+ 25. Slow 1200mV 85C Model Setup: 'inst55'
+ 26. Slow 1200mV 85C Model Setup: 'inst31'
+ 27. Slow 1200mV 85C Model Setup: 'inst27'
+ 28. Slow 1200mV 85C Model Setup: 'inst68'
+ 29. Slow 1200mV 85C Model Setup: 'inst32'
+ 30. Slow 1200mV 85C Model Setup: 'inst36'
+ 31. Slow 1200mV 85C Model Setup: 'inst48'
+ 32. Slow 1200mV 85C Model Setup: 'inst60'
+ 33. Slow 1200mV 85C Model Setup: 'inst44'
+ 34. Slow 1200mV 85C Model Setup: 'inst24'
+ 35. Slow 1200mV 85C Model Setup: 'inst56'
+ 36. Slow 1200mV 85C Model Setup: 'inst64'
+ 37. Slow 1200mV 85C Model Setup: 'inst75'
+ 38. Slow 1200mV 85C Model Setup: 'inst63'
+ 39. Slow 1200mV 85C Model Setup: 'inst40'
+ 40. Slow 1200mV 85C Model Setup: 'inst79'
+ 41. Slow 1200mV 85C Model Setup: 'inst52'
+ 42. Slow 1200mV 85C Model Hold: 'inst63'
+ 43. Slow 1200mV 85C Model Hold: 'inst52'
+ 44. Slow 1200mV 85C Model Hold: 'inst31'
+ 45. Slow 1200mV 85C Model Hold: 'inst27'
+ 46. Slow 1200mV 85C Model Hold: 'inst71'
+ 47. Slow 1200mV 85C Model Hold: 'inst59'
+ 48. Slow 1200mV 85C Model Hold: 'inst67'
+ 49. Slow 1200mV 85C Model Hold: 'inst40'
+ 50. Slow 1200mV 85C Model Hold: 'inst55'
+ 51. Slow 1200mV 85C Model Hold: 'pin_name1'
+ 52. Slow 1200mV 85C Model Hold: 'inst35'
+ 53. Slow 1200mV 85C Model Hold: 'inst39'
+ 54. Slow 1200mV 85C Model Hold: 'inst47'
+ 55. Slow 1200mV 85C Model Hold: 'inst23'
+ 56. Slow 1200mV 85C Model Hold: 'inst72'
+ 57. Slow 1200mV 85C Model Hold: 'inst76'
+ 58. Slow 1200mV 85C Model Hold: 'inst43'
+ 59. Slow 1200mV 85C Model Hold: 'inst51'
+ 60. Slow 1200mV 85C Model Hold: 'inst75'
+ 61. Slow 1200mV 85C Model Hold: 'inst24'
+ 62. Slow 1200mV 85C Model Hold: 'inst56'
+ 63. Slow 1200mV 85C Model Hold: 'inst64'
+ 64. Slow 1200mV 85C Model Hold: 'inst48'
+ 65. Slow 1200mV 85C Model Hold: 'inst44'
+ 66. Slow 1200mV 85C Model Hold: 'inst60'
+ 67. Slow 1200mV 85C Model Hold: 'inst68'
+ 68. Slow 1200mV 85C Model Hold: 'inst32'
+ 69. Slow 1200mV 85C Model Hold: 'inst36'
+ 70. Slow 1200mV 85C Model Hold: 'inst28'
+ 71. Slow 1200mV 85C Model Hold: 'inst79'
+ 72. Slow 1200mV 85C Model Minimum Pulse Width: 'pin_name1'
+ 73. Slow 1200mV 85C Model Minimum Pulse Width: 'inst23'
+ 74. Slow 1200mV 85C Model Minimum Pulse Width: 'inst24'
+ 75. Slow 1200mV 85C Model Minimum Pulse Width: 'inst27'
+ 76. Slow 1200mV 85C Model Minimum Pulse Width: 'inst28'
+ 77. Slow 1200mV 85C Model Minimum Pulse Width: 'inst31'
+ 78. Slow 1200mV 85C Model Minimum Pulse Width: 'inst32'
+ 79. Slow 1200mV 85C Model Minimum Pulse Width: 'inst35'
+ 80. Slow 1200mV 85C Model Minimum Pulse Width: 'inst36'
+ 81. Slow 1200mV 85C Model Minimum Pulse Width: 'inst39'
+ 82. Slow 1200mV 85C Model Minimum Pulse Width: 'inst40'
+ 83. Slow 1200mV 85C Model Minimum Pulse Width: 'inst43'
+ 84. Slow 1200mV 85C Model Minimum Pulse Width: 'inst44'
+ 85. Slow 1200mV 85C Model Minimum Pulse Width: 'inst47'
+ 86. Slow 1200mV 85C Model Minimum Pulse Width: 'inst48'
+ 87. Slow 1200mV 85C Model Minimum Pulse Width: 'inst51'
+ 88. Slow 1200mV 85C Model Minimum Pulse Width: 'inst52'
+ 89. Slow 1200mV 85C Model Minimum Pulse Width: 'inst55'
+ 90. Slow 1200mV 85C Model Minimum Pulse Width: 'inst56'
+ 91. Slow 1200mV 85C Model Minimum Pulse Width: 'inst59'
+ 92. Slow 1200mV 85C Model Minimum Pulse Width: 'inst60'
+ 93. Slow 1200mV 85C Model Minimum Pulse Width: 'inst63'
+ 94. Slow 1200mV 85C Model Minimum Pulse Width: 'inst64'
+ 95. Slow 1200mV 85C Model Minimum Pulse Width: 'inst67'
+ 96. Slow 1200mV 85C Model Minimum Pulse Width: 'inst68'
+ 97. Slow 1200mV 85C Model Minimum Pulse Width: 'inst71'
+ 98. Slow 1200mV 85C Model Minimum Pulse Width: 'inst72'
+ 99. Slow 1200mV 85C Model Minimum Pulse Width: 'inst75'
+100. Slow 1200mV 85C Model Minimum Pulse Width: 'inst76'
+101. Slow 1200mV 85C Model Minimum Pulse Width: 'inst79'
+102. Clock to Output Times
+103. Minimum Clock to Output Times
+104. Slow 1200mV 85C Model Metastability Report
+105. Slow 1200mV 0C Model Fmax Summary
+106. Slow 1200mV 0C Model Setup Summary
+107. Slow 1200mV 0C Model Hold Summary
+108. Slow 1200mV 0C Model Recovery Summary
+109. Slow 1200mV 0C Model Removal Summary
+110. Slow 1200mV 0C Model Minimum Pulse Width Summary
+111. Slow 1200mV 0C Model Setup: 'inst43'
+112. Slow 1200mV 0C Model Setup: 'inst28'
+113. Slow 1200mV 0C Model Setup: 'inst51'
+114. Slow 1200mV 0C Model Setup: 'inst76'
+115. Slow 1200mV 0C Model Setup: 'pin_name1'
+116. Slow 1200mV 0C Model Setup: 'inst72'
+117. Slow 1200mV 0C Model Setup: 'inst59'
+118. Slow 1200mV 0C Model Setup: 'inst39'
+119. Slow 1200mV 0C Model Setup: 'inst47'
+120. Slow 1200mV 0C Model Setup: 'inst23'
+121. Slow 1200mV 0C Model Setup: 'inst35'
+122. Slow 1200mV 0C Model Setup: 'inst67'
+123. Slow 1200mV 0C Model Setup: 'inst71'
+124. Slow 1200mV 0C Model Setup: 'inst55'
+125. Slow 1200mV 0C Model Setup: 'inst68'
+126. Slow 1200mV 0C Model Setup: 'inst31'
+127. Slow 1200mV 0C Model Setup: 'inst32'
+128. Slow 1200mV 0C Model Setup: 'inst36'
+129. Slow 1200mV 0C Model Setup: 'inst27'
+130. Slow 1200mV 0C Model Setup: 'inst48'
+131. Slow 1200mV 0C Model Setup: 'inst24'
+132. Slow 1200mV 0C Model Setup: 'inst56'
+133. Slow 1200mV 0C Model Setup: 'inst60'
+134. Slow 1200mV 0C Model Setup: 'inst44'
+135. Slow 1200mV 0C Model Setup: 'inst64'
+136. Slow 1200mV 0C Model Setup: 'inst75'
+137. Slow 1200mV 0C Model Setup: 'inst63'
+138. Slow 1200mV 0C Model Setup: 'inst40'
+139. Slow 1200mV 0C Model Setup: 'inst52'
+140. Slow 1200mV 0C Model Setup: 'inst79'
+141. Slow 1200mV 0C Model Hold: 'inst63'
+142. Slow 1200mV 0C Model Hold: 'pin_name1'
+143. Slow 1200mV 0C Model Hold: 'inst52'
+144. Slow 1200mV 0C Model Hold: 'inst71'
+145. Slow 1200mV 0C Model Hold: 'inst31'
+146. Slow 1200mV 0C Model Hold: 'inst27'
+147. Slow 1200mV 0C Model Hold: 'inst59'
+148. Slow 1200mV 0C Model Hold: 'inst40'
+149. Slow 1200mV 0C Model Hold: 'inst67'
+150. Slow 1200mV 0C Model Hold: 'inst55'
+151. Slow 1200mV 0C Model Hold: 'inst35'
+152. Slow 1200mV 0C Model Hold: 'inst47'
+153. Slow 1200mV 0C Model Hold: 'inst39'
+154. Slow 1200mV 0C Model Hold: 'inst23'
+155. Slow 1200mV 0C Model Hold: 'inst72'
+156. Slow 1200mV 0C Model Hold: 'inst76'
+157. Slow 1200mV 0C Model Hold: 'inst51'
+158. Slow 1200mV 0C Model Hold: 'inst43'
+159. Slow 1200mV 0C Model Hold: 'inst75'
+160. Slow 1200mV 0C Model Hold: 'inst24'
+161. Slow 1200mV 0C Model Hold: 'inst56'
+162. Slow 1200mV 0C Model Hold: 'inst64'
+163. Slow 1200mV 0C Model Hold: 'inst48'
+164. Slow 1200mV 0C Model Hold: 'inst60'
+165. Slow 1200mV 0C Model Hold: 'inst44'
+166. Slow 1200mV 0C Model Hold: 'inst68'
+167. Slow 1200mV 0C Model Hold: 'inst32'
+168. Slow 1200mV 0C Model Hold: 'inst36'
+169. Slow 1200mV 0C Model Hold: 'inst28'
+170. Slow 1200mV 0C Model Hold: 'inst79'
+171. Slow 1200mV 0C Model Minimum Pulse Width: 'pin_name1'
+172. Slow 1200mV 0C Model Minimum Pulse Width: 'inst23'
+173. Slow 1200mV 0C Model Minimum Pulse Width: 'inst24'
+174. Slow 1200mV 0C Model Minimum Pulse Width: 'inst27'
+175. Slow 1200mV 0C Model Minimum Pulse Width: 'inst28'
+176. Slow 1200mV 0C Model Minimum Pulse Width: 'inst31'
+177. Slow 1200mV 0C Model Minimum Pulse Width: 'inst32'
+178. Slow 1200mV 0C Model Minimum Pulse Width: 'inst35'
+179. Slow 1200mV 0C Model Minimum Pulse Width: 'inst36'
+180. Slow 1200mV 0C Model Minimum Pulse Width: 'inst39'
+181. Slow 1200mV 0C Model Minimum Pulse Width: 'inst40'
+182. Slow 1200mV 0C Model Minimum Pulse Width: 'inst43'
+183. Slow 1200mV 0C Model Minimum Pulse Width: 'inst44'
+184. Slow 1200mV 0C Model Minimum Pulse Width: 'inst47'
+185. Slow 1200mV 0C Model Minimum Pulse Width: 'inst48'
+186. Slow 1200mV 0C Model Minimum Pulse Width: 'inst51'
+187. Slow 1200mV 0C Model Minimum Pulse Width: 'inst52'
+188. Slow 1200mV 0C Model Minimum Pulse Width: 'inst55'
+189. Slow 1200mV 0C Model Minimum Pulse Width: 'inst56'
+190. Slow 1200mV 0C Model Minimum Pulse Width: 'inst59'
+191. Slow 1200mV 0C Model Minimum Pulse Width: 'inst60'
+192. Slow 1200mV 0C Model Minimum Pulse Width: 'inst63'
+193. Slow 1200mV 0C Model Minimum Pulse Width: 'inst64'
+194. Slow 1200mV 0C Model Minimum Pulse Width: 'inst67'
+195. Slow 1200mV 0C Model Minimum Pulse Width: 'inst68'
+196. Slow 1200mV 0C Model Minimum Pulse Width: 'inst71'
+197. Slow 1200mV 0C Model Minimum Pulse Width: 'inst72'
+198. Slow 1200mV 0C Model Minimum Pulse Width: 'inst75'
+199. Slow 1200mV 0C Model Minimum Pulse Width: 'inst76'
+200. Slow 1200mV 0C Model Minimum Pulse Width: 'inst79'
+201. Clock to Output Times
+202. Minimum Clock to Output Times
+203. Slow 1200mV 0C Model Metastability Report
+204. Fast 1200mV 0C Model Setup Summary
+205. Fast 1200mV 0C Model Hold Summary
+206. Fast 1200mV 0C Model Recovery Summary
+207. Fast 1200mV 0C Model Removal Summary
+208. Fast 1200mV 0C Model Minimum Pulse Width Summary
+209. Fast 1200mV 0C Model Setup: 'inst28'
+210. Fast 1200mV 0C Model Setup: 'pin_name1'
+211. Fast 1200mV 0C Model Setup: 'inst51'
+212. Fast 1200mV 0C Model Setup: 'inst72'
+213. Fast 1200mV 0C Model Setup: 'inst39'
+214. Fast 1200mV 0C Model Setup: 'inst43'
+215. Fast 1200mV 0C Model Setup: 'inst23'
+216. Fast 1200mV 0C Model Setup: 'inst76'
+217. Fast 1200mV 0C Model Setup: 'inst35'
+218. Fast 1200mV 0C Model Setup: 'inst47'
+219. Fast 1200mV 0C Model Setup: 'inst67'
+220. Fast 1200mV 0C Model Setup: 'inst55'
+221. Fast 1200mV 0C Model Setup: 'inst31'
+222. Fast 1200mV 0C Model Setup: 'inst27'
+223. Fast 1200mV 0C Model Setup: 'inst59'
+224. Fast 1200mV 0C Model Setup: 'inst68'
+225. Fast 1200mV 0C Model Setup: 'inst71'
+226. Fast 1200mV 0C Model Setup: 'inst32'
+227. Fast 1200mV 0C Model Setup: 'inst36'
+228. Fast 1200mV 0C Model Setup: 'inst48'
+229. Fast 1200mV 0C Model Setup: 'inst44'
+230. Fast 1200mV 0C Model Setup: 'inst60'
+231. Fast 1200mV 0C Model Setup: 'inst24'
+232. Fast 1200mV 0C Model Setup: 'inst56'
+233. Fast 1200mV 0C Model Setup: 'inst64'
+234. Fast 1200mV 0C Model Setup: 'inst75'
+235. Fast 1200mV 0C Model Setup: 'inst63'
+236. Fast 1200mV 0C Model Setup: 'inst40'
+237. Fast 1200mV 0C Model Setup: 'inst52'
+238. Fast 1200mV 0C Model Setup: 'inst79'
+239. Fast 1200mV 0C Model Hold: 'inst63'
+240. Fast 1200mV 0C Model Hold: 'inst59'
+241. Fast 1200mV 0C Model Hold: 'inst71'
+242. Fast 1200mV 0C Model Hold: 'inst52'
+243. Fast 1200mV 0C Model Hold: 'inst43'
+244. Fast 1200mV 0C Model Hold: 'inst31'
+245. Fast 1200mV 0C Model Hold: 'inst27'
+246. Fast 1200mV 0C Model Hold: 'inst40'
+247. Fast 1200mV 0C Model Hold: 'inst76'
+248. Fast 1200mV 0C Model Hold: 'pin_name1'
+249. Fast 1200mV 0C Model Hold: 'inst55'
+250. Fast 1200mV 0C Model Hold: 'inst67'
+251. Fast 1200mV 0C Model Hold: 'inst35'
+252. Fast 1200mV 0C Model Hold: 'inst51'
+253. Fast 1200mV 0C Model Hold: 'inst47'
+254. Fast 1200mV 0C Model Hold: 'inst23'
+255. Fast 1200mV 0C Model Hold: 'inst39'
+256. Fast 1200mV 0C Model Hold: 'inst72'
+257. Fast 1200mV 0C Model Hold: 'inst75'
+258. Fast 1200mV 0C Model Hold: 'inst24'
+259. Fast 1200mV 0C Model Hold: 'inst56'
+260. Fast 1200mV 0C Model Hold: 'inst64'
+261. Fast 1200mV 0C Model Hold: 'inst48'
+262. Fast 1200mV 0C Model Hold: 'inst60'
+263. Fast 1200mV 0C Model Hold: 'inst68'
+264. Fast 1200mV 0C Model Hold: 'inst44'
+265. Fast 1200mV 0C Model Hold: 'inst32'
+266. Fast 1200mV 0C Model Hold: 'inst36'
+267. Fast 1200mV 0C Model Hold: 'inst28'
+268. Fast 1200mV 0C Model Hold: 'inst79'
+269. Fast 1200mV 0C Model Minimum Pulse Width: 'pin_name1'
+270. Fast 1200mV 0C Model Minimum Pulse Width: 'inst23'
+271. Fast 1200mV 0C Model Minimum Pulse Width: 'inst24'
+272. Fast 1200mV 0C Model Minimum Pulse Width: 'inst27'
+273. Fast 1200mV 0C Model Minimum Pulse Width: 'inst28'
+274. Fast 1200mV 0C Model Minimum Pulse Width: 'inst31'
+275. Fast 1200mV 0C Model Minimum Pulse Width: 'inst32'
+276. Fast 1200mV 0C Model Minimum Pulse Width: 'inst35'
+277. Fast 1200mV 0C Model Minimum Pulse Width: 'inst36'
+278. Fast 1200mV 0C Model Minimum Pulse Width: 'inst39'
+279. Fast 1200mV 0C Model Minimum Pulse Width: 'inst40'
+280. Fast 1200mV 0C Model Minimum Pulse Width: 'inst43'
+281. Fast 1200mV 0C Model Minimum Pulse Width: 'inst44'
+282. Fast 1200mV 0C Model Minimum Pulse Width: 'inst47'
+283. Fast 1200mV 0C Model Minimum Pulse Width: 'inst48'
+284. Fast 1200mV 0C Model Minimum Pulse Width: 'inst51'
+285. Fast 1200mV 0C Model Minimum Pulse Width: 'inst52'
+286. Fast 1200mV 0C Model Minimum Pulse Width: 'inst55'
+287. Fast 1200mV 0C Model Minimum Pulse Width: 'inst56'
+288. Fast 1200mV 0C Model Minimum Pulse Width: 'inst59'
+289. Fast 1200mV 0C Model Minimum Pulse Width: 'inst60'
+290. Fast 1200mV 0C Model Minimum Pulse Width: 'inst63'
+291. Fast 1200mV 0C Model Minimum Pulse Width: 'inst64'
+292. Fast 1200mV 0C Model Minimum Pulse Width: 'inst67'
+293. Fast 1200mV 0C Model Minimum Pulse Width: 'inst68'
+294. Fast 1200mV 0C Model Minimum Pulse Width: 'inst71'
+295. Fast 1200mV 0C Model Minimum Pulse Width: 'inst72'
+296. Fast 1200mV 0C Model Minimum Pulse Width: 'inst75'
+297. Fast 1200mV 0C Model Minimum Pulse Width: 'inst76'
+298. Fast 1200mV 0C Model Minimum Pulse Width: 'inst79'
+299. Clock to Output Times
+300. Minimum Clock to Output Times
+301. Fast 1200mV 0C Model Metastability Report
+302. Multicorner Timing Analysis Summary
+303. Clock to Output Times
+304. Minimum Clock to Output Times
+305. Board Trace Model Assignments
+306. Input Transition Times
+307. Slow Corner Signal Integrity Metrics
+308. Fast Corner Signal Integrity Metrics
+309. Setup Transfers
+310. Hold Transfers
+311. Report TCCS
+312. Report RSKM
+313. Unconstrained Paths
+314. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; blinken_Lights                                     ;
+; Device Family      ; Cyclone III                                        ;
+; Device Name        ; EP3C16F484C6                                       ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets       ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+; inst23     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst23 }    ;
+; inst24     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst24 }    ;
+; inst27     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst27 }    ;
+; inst28     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst28 }    ;
+; inst31     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst31 }    ;
+; inst32     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst32 }    ;
+; inst35     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst35 }    ;
+; inst36     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst36 }    ;
+; inst39     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst39 }    ;
+; inst40     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst40 }    ;
+; inst43     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst43 }    ;
+; inst44     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst44 }    ;
+; inst47     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst47 }    ;
+; inst48     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst48 }    ;
+; inst51     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst51 }    ;
+; inst52     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst52 }    ;
+; inst55     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst55 }    ;
+; inst56     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst56 }    ;
+; inst59     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst59 }    ;
+; inst60     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst60 }    ;
+; inst63     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst63 }    ;
+; inst64     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst64 }    ;
+; inst67     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst67 }    ;
+; inst68     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst68 }    ;
+; inst71     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst71 }    ;
+; inst72     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst72 }    ;
+; inst75     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst75 }    ;
+; inst76     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst76 }    ;
+; inst79     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { inst79 }    ;
+; pin_name1  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { pin_name1 } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                          ;
++-------------+-----------------+------------+------------------------------------------------+
+; Fmax        ; Restricted Fmax ; Clock Name ; Note                                           ;
++-------------+-----------------+------------+------------------------------------------------+
+; 1464.13 MHz ; 500.0 MHz       ; inst79     ; limit due to minimum period restriction (tmin) ;
++-------------+-----------------+------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-----------+--------+----------------+
+; Clock     ; Slack  ; End Point TNS  ;
++-----------+--------+----------------+
+; inst28    ; -0.011 ; -0.011         ;
+; inst43    ; 0.010  ; 0.000          ;
+; pin_name1 ; 0.030  ; 0.000          ;
+; inst51    ; 0.032  ; 0.000          ;
+; inst76    ; 0.047  ; 0.000          ;
+; inst72    ; 0.070  ; 0.000          ;
+; inst59    ; 0.080  ; 0.000          ;
+; inst39    ; 0.086  ; 0.000          ;
+; inst47    ; 0.089  ; 0.000          ;
+; inst23    ; 0.090  ; 0.000          ;
+; inst35    ; 0.094  ; 0.000          ;
+; inst71    ; 0.097  ; 0.000          ;
+; inst67    ; 0.108  ; 0.000          ;
+; inst55    ; 0.112  ; 0.000          ;
+; inst31    ; 0.128  ; 0.000          ;
+; inst27    ; 0.129  ; 0.000          ;
+; inst68    ; 0.130  ; 0.000          ;
+; inst32    ; 0.134  ; 0.000          ;
+; inst36    ; 0.134  ; 0.000          ;
+; inst48    ; 0.139  ; 0.000          ;
+; inst60    ; 0.142  ; 0.000          ;
+; inst44    ; 0.143  ; 0.000          ;
+; inst24    ; 0.144  ; 0.000          ;
+; inst56    ; 0.144  ; 0.000          ;
+; inst64    ; 0.152  ; 0.000          ;
+; inst75    ; 0.154  ; 0.000          ;
+; inst63    ; 0.176  ; 0.000          ;
+; inst40    ; 0.298  ; 0.000          ;
+; inst79    ; 0.317  ; 0.000          ;
+; inst52    ; 0.325  ; 0.000          ;
++-----------+--------+----------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-----------+--------+---------------+
+; Clock     ; Slack  ; End Point TNS ;
++-----------+--------+---------------+
+; inst63    ; -0.088 ; -0.088        ;
+; inst52    ; -0.026 ; -0.026        ;
+; inst31    ; -0.017 ; -0.017        ;
+; inst27    ; -0.006 ; -0.006        ;
+; inst71    ; -0.002 ; -0.002        ;
+; inst59    ; 0.001  ; 0.000         ;
+; inst67    ; 0.002  ; 0.000         ;
+; inst40    ; 0.006  ; 0.000         ;
+; inst55    ; 0.009  ; 0.000         ;
+; pin_name1 ; 0.013  ; 0.000         ;
+; inst35    ; 0.019  ; 0.000         ;
+; inst39    ; 0.028  ; 0.000         ;
+; inst47    ; 0.029  ; 0.000         ;
+; inst23    ; 0.032  ; 0.000         ;
+; inst72    ; 0.040  ; 0.000         ;
+; inst76    ; 0.045  ; 0.000         ;
+; inst43    ; 0.052  ; 0.000         ;
+; inst51    ; 0.052  ; 0.000         ;
+; inst75    ; 0.084  ; 0.000         ;
+; inst24    ; 0.086  ; 0.000         ;
+; inst56    ; 0.086  ; 0.000         ;
+; inst64    ; 0.088  ; 0.000         ;
+; inst48    ; 0.092  ; 0.000         ;
+; inst44    ; 0.097  ; 0.000         ;
+; inst60    ; 0.097  ; 0.000         ;
+; inst68    ; 0.101  ; 0.000         ;
+; inst32    ; 0.106  ; 0.000         ;
+; inst36    ; 0.106  ; 0.000         ;
+; inst28    ; 0.127  ; 0.000         ;
+; inst79    ; 0.384  ; 0.000         ;
++-----------+--------+---------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-----------+--------+------------------------------+
+; Clock     ; Slack  ; End Point TNS                ;
++-----------+--------+------------------------------+
+; pin_name1 ; -3.000 ; -4.000                       ;
+; inst23    ; -1.000 ; -1.000                       ;
+; inst24    ; -1.000 ; -1.000                       ;
+; inst27    ; -1.000 ; -1.000                       ;
+; inst28    ; -1.000 ; -1.000                       ;
+; inst31    ; -1.000 ; -1.000                       ;
+; inst32    ; -1.000 ; -1.000                       ;
+; inst35    ; -1.000 ; -1.000                       ;
+; inst36    ; -1.000 ; -1.000                       ;
+; inst39    ; -1.000 ; -1.000                       ;
+; inst40    ; -1.000 ; -1.000                       ;
+; inst43    ; -1.000 ; -1.000                       ;
+; inst44    ; -1.000 ; -1.000                       ;
+; inst47    ; -1.000 ; -1.000                       ;
+; inst48    ; -1.000 ; -1.000                       ;
+; inst51    ; -1.000 ; -1.000                       ;
+; inst52    ; -1.000 ; -1.000                       ;
+; inst55    ; -1.000 ; -1.000                       ;
+; inst56    ; -1.000 ; -1.000                       ;
+; inst59    ; -1.000 ; -1.000                       ;
+; inst60    ; -1.000 ; -1.000                       ;
+; inst63    ; -1.000 ; -1.000                       ;
+; inst64    ; -1.000 ; -1.000                       ;
+; inst67    ; -1.000 ; -1.000                       ;
+; inst68    ; -1.000 ; -1.000                       ;
+; inst71    ; -1.000 ; -1.000                       ;
+; inst72    ; -1.000 ; -1.000                       ;
+; inst75    ; -1.000 ; -1.000                       ;
+; inst76    ; -1.000 ; -1.000                       ;
+; inst79    ; -1.000 ; -1.000                       ;
++-----------+--------+------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst28'                                                              ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.011 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.500        ; 0.821      ; 1.546      ;
+; 0.481  ; inst31    ; inst31  ; inst31       ; inst28      ; 1.000        ; 0.821      ; 1.554      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst43'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.010 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.500        ; 1.442      ; 2.146      ;
+; 0.499 ; inst44    ; inst44  ; inst44       ; inst43      ; 1.000        ; 1.442      ; 2.157      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'pin_name1'                                                          ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.030 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.500        ; 2.314      ; 2.978      ;
+; 0.502 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 1.000        ; 2.314      ; 3.006      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst51'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.032 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.500        ; 1.138      ; 1.820      ;
+; 0.525 ; inst52    ; inst52  ; inst52       ; inst51      ; 1.000        ; 1.138      ; 1.827      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst76'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.047 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.500        ; 1.192      ; 1.859      ;
+; 0.535 ; inst79    ; inst79  ; inst79       ; inst76      ; 1.000        ; 1.192      ; 1.871      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst72'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.070 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.500        ; 0.905      ; 1.549      ;
+; 0.556 ; inst75    ; inst75  ; inst75       ; inst72      ; 1.000        ; 0.905      ; 1.563      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst59'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.080 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.500        ; 1.218      ; 1.852      ;
+; 0.568 ; inst60    ; inst60  ; inst60       ; inst59      ; 1.000        ; 1.218      ; 1.864      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst39'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.086 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.500        ; 0.909      ; 1.537      ;
+; 0.570 ; inst40    ; inst40  ; inst40       ; inst39      ; 1.000        ; 0.909      ; 1.553      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst47'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.089 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.500        ; 0.909      ; 1.534      ;
+; 0.576 ; inst48    ; inst48  ; inst48       ; inst47      ; 1.000        ; 0.909      ; 1.547      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst23'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.090 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.500        ; 0.909      ; 1.533      ;
+; 0.575 ; inst24    ; inst24  ; inst24       ; inst23      ; 1.000        ; 0.909      ; 1.548      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst35'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.094 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.500        ; 0.909      ; 1.529      ;
+; 0.580 ; inst36    ; inst36  ; inst36       ; inst35      ; 1.000        ; 0.909      ; 1.543      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst71'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.097 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.500        ; 1.228      ; 1.845      ;
+; 0.580 ; inst72    ; inst72  ; inst72       ; inst71      ; 1.000        ; 1.228      ; 1.862      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst67'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.108 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.500        ; 0.952      ; 1.558      ;
+; 0.593 ; inst68    ; inst68  ; inst68       ; inst67      ; 1.000        ; 0.952      ; 1.573      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst55'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.112 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.500        ; 0.931      ; 1.533      ;
+; 0.597 ; inst56    ; inst56  ; inst56       ; inst55      ; 1.000        ; 0.931      ; 1.548      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst31'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.128 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.500        ; 0.943      ; 1.529      ;
+; 0.614 ; inst32    ; inst32  ; inst32       ; inst31      ; 1.000        ; 0.943      ; 1.543      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst27'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.129 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.500        ; 0.943      ; 1.528      ;
+; 0.612 ; inst28    ; inst28  ; inst28       ; inst27      ; 1.000        ; 0.943      ; 1.545      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst68'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.130 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.500        ; 0.831      ; 1.415      ;
+; 0.576 ; inst71    ; inst71  ; inst71       ; inst68      ; 1.000        ; 0.831      ; 1.469      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst32'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.134 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.500        ; 0.811      ; 1.391      ;
+; 0.581 ; inst35    ; inst35  ; inst35       ; inst32      ; 1.000        ; 0.811      ; 1.444      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst36'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.134 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.500        ; 0.811      ; 1.391      ;
+; 0.581 ; inst39    ; inst39  ; inst39       ; inst36      ; 1.000        ; 0.811      ; 1.444      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst48'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.139 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.500        ; 0.821      ; 1.396      ;
+; 0.586 ; inst51    ; inst51  ; inst51       ; inst48      ; 1.000        ; 0.821      ; 1.449      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst60'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.142 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.500        ; 0.820      ; 1.392      ;
+; 0.591 ; inst63    ; inst63  ; inst63       ; inst60      ; 1.000        ; 0.820      ; 1.443      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst44'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.143 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.500        ; 0.820      ; 1.391      ;
+; 0.590 ; inst47    ; inst47  ; inst47       ; inst44      ; 1.000        ; 0.820      ; 1.444      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst24'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.144 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.500        ; 0.821      ; 1.391      ;
+; 0.592 ; inst27    ; inst27  ; inst27       ; inst24      ; 1.000        ; 0.821      ; 1.443      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst56'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.144 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.500        ; 0.821      ; 1.391      ;
+; 0.592 ; inst59    ; inst59  ; inst59       ; inst56      ; 1.000        ; 0.821      ; 1.443      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst64'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.152 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.500        ; 0.829      ; 1.391      ;
+; 0.600 ; inst67    ; inst67  ; inst67       ; inst64      ; 1.000        ; 0.829      ; 1.443      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst75'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.154 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.500        ; 0.831      ; 1.391      ;
+; 0.604 ; inst76    ; inst76  ; inst76       ; inst75      ; 1.000        ; 0.831      ; 1.441      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst63'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.176 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.500        ; 1.324      ; 1.862      ;
+; 0.652 ; inst64    ; inst64  ; inst64       ; inst63      ; 1.000        ; 1.324      ; 1.886      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst40'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.298 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.500        ; 0.811      ; 1.227      ;
+; 0.756 ; inst43    ; inst43  ; inst43       ; inst40      ; 1.000        ; 0.811      ; 1.269      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst79'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.317 ; inst80    ; inst80  ; inst79       ; inst79      ; 1.000        ; -0.039     ; 0.659      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst52'                                                             ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.325 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.500        ; 0.829      ; 1.218      ;
+; 0.788 ; inst55    ; inst55  ; inst55       ; inst52      ; 1.000        ; 0.829      ; 1.255      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst63'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.088 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.000        ; 1.398      ; 1.666      ;
+; 0.368  ; inst64    ; inst64  ; inst64       ; inst63      ; -0.500       ; 1.398      ; 1.622      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst52'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.026 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.000        ; 0.882      ; 1.212      ;
+; 0.436  ; inst55    ; inst55  ; inst55       ; inst52      ; -0.500       ; 0.882      ; 1.174      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst31'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.017 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.000        ; 1.001      ; 1.340      ;
+; 0.443  ; inst32    ; inst32  ; inst32       ; inst31      ; -0.500       ; 1.001      ; 1.300      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst27'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.006 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.000        ; 1.001      ; 1.351      ;
+; 0.438  ; inst28    ; inst28  ; inst28       ; inst27      ; -0.500       ; 1.001      ; 1.295      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst71'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.002 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.000        ; 1.298      ; 1.652      ;
+; 0.448  ; inst72    ; inst72  ; inst72       ; inst71      ; -0.500       ; 1.298      ; 1.602      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst59'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.001 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.000        ; 1.287      ; 1.644      ;
+; 0.468 ; inst60    ; inst60  ; inst60       ; inst59      ; -0.500       ; 1.287      ; 1.611      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst67'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.002 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.000        ; 1.011      ; 1.369      ;
+; 0.461 ; inst68    ; inst68  ; inst68       ; inst67      ; -0.500       ; 1.011      ; 1.328      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst40'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.006 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.000        ; 0.864      ; 1.226      ;
+; 0.466 ; inst43    ; inst43  ; inst43       ; inst40      ; -0.500       ; 0.864      ; 1.186      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst55'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.009 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.000        ; 0.988      ; 1.353      ;
+; 0.455 ; inst56    ; inst56  ; inst56       ; inst55      ; -0.500       ; 0.988      ; 1.299      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'pin_name1'                                                           ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.013 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.000        ; 2.397      ; 2.786      ;
+; 0.517 ; inst23    ; inst23  ; inst23       ; pin_name1   ; -0.500       ; 2.397      ; 2.790      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst35'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.019 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.000        ; 0.965      ; 1.340      ;
+; 0.479 ; inst36    ; inst36  ; inst36       ; inst35      ; -0.500       ; 0.965      ; 1.300      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst39'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.028 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.000        ; 0.965      ; 1.349      ;
+; 0.487 ; inst40    ; inst40  ; inst40       ; inst39      ; -0.500       ; 0.965      ; 1.308      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst47'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.029 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.000        ; 0.965      ; 1.350      ;
+; 0.482 ; inst48    ; inst48  ; inst48       ; inst47      ; -0.500       ; 0.965      ; 1.303      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst23'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.032 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.000        ; 0.965      ; 1.353      ;
+; 0.478 ; inst24    ; inst24  ; inst24       ; inst23      ; -0.500       ; 0.965      ; 1.299      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst72'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.040 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.000        ; 0.962      ; 1.358      ;
+; 0.500 ; inst75    ; inst75  ; inst75       ; inst72      ; -0.500       ; 0.962      ; 1.318      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst76'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.045 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.000        ; 1.260      ; 1.661      ;
+; 0.500 ; inst79    ; inst79  ; inst79       ; inst76      ; -0.500       ; 1.260      ; 1.616      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst43'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.052 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.000        ; 1.521      ; 1.929      ;
+; 0.515 ; inst44    ; inst44  ; inst44       ; inst43      ; -0.500       ; 1.521      ; 1.892      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst51'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.052 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.000        ; 1.204      ; 1.612      ;
+; 0.518 ; inst52    ; inst52  ; inst52       ; inst51      ; -0.500       ; 1.204      ; 1.578      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst75'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.084 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.000        ; 0.884      ; 1.324      ;
+; 0.530 ; inst76    ; inst76  ; inst76       ; inst75      ; -0.500       ; 0.884      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst24'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.086 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.000        ; 0.874      ; 1.316      ;
+; 0.543 ; inst27    ; inst27  ; inst27       ; inst24      ; -0.500       ; 0.874      ; 1.273      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst56'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.086 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.000        ; 0.874      ; 1.316      ;
+; 0.543 ; inst59    ; inst59  ; inst59       ; inst56      ; -0.500       ; 0.874      ; 1.273      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst64'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.088 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.000        ; 0.882      ; 1.326      ;
+; 0.532 ; inst67    ; inst67  ; inst67       ; inst64      ; -0.500       ; 0.882      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst48'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.092 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.000        ; 0.874      ; 1.322      ;
+; 0.548 ; inst51    ; inst51  ; inst51       ; inst48      ; -0.500       ; 0.874      ; 1.278      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst44'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.097 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.000        ; 0.873      ; 1.326      ;
+; 0.541 ; inst47    ; inst47  ; inst47       ; inst44      ; -0.500       ; 0.873      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst60'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.097 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.000        ; 0.873      ; 1.326      ;
+; 0.541 ; inst63    ; inst63  ; inst63       ; inst60      ; -0.500       ; 0.873      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst68'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.101 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.000        ; 0.884      ; 1.341      ;
+; 0.557 ; inst71    ; inst71  ; inst71       ; inst68      ; -0.500       ; 0.884      ; 1.297      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst32'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.106 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.000        ; 0.864      ; 1.326      ;
+; 0.550 ; inst35    ; inst35  ; inst35       ; inst32      ; -0.500       ; 0.864      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst36'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.106 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.000        ; 0.864      ; 1.326      ;
+; 0.550 ; inst39    ; inst39  ; inst39       ; inst36      ; -0.500       ; 0.864      ; 1.270      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst28'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.127 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.000        ; 0.874      ; 1.357      ;
+; 0.585 ; inst31    ; inst31  ; inst31       ; inst28      ; -0.500       ; 0.874      ; 1.315      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst79'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.384 ; inst80    ; inst80  ; inst79       ; inst79      ; 0.000        ; 0.039      ; 0.580      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'pin_name1'                                                                                           ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                      ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; pin_name1 ; Rise       ; pin_name1                                                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.188  ; 0.372        ; 0.184          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
+; 0.349  ; 0.349        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.411  ; 0.627        ; 0.216          ; High Pulse Width ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.650  ; 0.650        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst23'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst23 ; Fall       ; inst24     ;
+; 0.241  ; 0.457        ; 0.216          ; High Pulse Width ; inst23 ; Fall       ; inst24     ;
+; 0.358  ; 0.542        ; 0.184          ; Low Pulse Width  ; inst23 ; Fall       ; inst24     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst24|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst23|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst23|q   ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst24|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst24'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst24 ; Fall       ; inst27     ;
+; 0.208  ; 0.424        ; 0.216          ; High Pulse Width ; inst24 ; Fall       ; inst27     ;
+; 0.392  ; 0.576        ; 0.184          ; Low Pulse Width  ; inst24 ; Fall       ; inst27     ;
+; 0.415  ; 0.415        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst27|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst24|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst24|q   ;
+; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst27|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst27'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst27 ; Fall       ; inst28     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst27 ; Fall       ; inst28     ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; inst27 ; Fall       ; inst28     ;
+; 0.439  ; 0.439        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst28|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst27|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst27|q   ;
+; 0.559  ; 0.559        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst28|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst28'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst28 ; Fall       ; inst31     ;
+; 0.208  ; 0.424        ; 0.216          ; High Pulse Width ; inst28 ; Fall       ; inst31     ;
+; 0.392  ; 0.576        ; 0.184          ; Low Pulse Width  ; inst28 ; Fall       ; inst31     ;
+; 0.415  ; 0.415        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst31|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst28|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst28|q   ;
+; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst31|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst31'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst31 ; Fall       ; inst32     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst31 ; Fall       ; inst32     ;
+; 0.367  ; 0.551        ; 0.184          ; Low Pulse Width  ; inst31 ; Fall       ; inst32     ;
+; 0.440  ; 0.440        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst32|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst31|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst31|q   ;
+; 0.557  ; 0.557        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst32|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst32'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst32 ; Fall       ; inst35     ;
+; 0.216  ; 0.432        ; 0.216          ; High Pulse Width ; inst32 ; Fall       ; inst35     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst32 ; Fall       ; inst35     ;
+; 0.423  ; 0.423        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst35|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst32|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst32|q   ;
+; 0.573  ; 0.573        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst35|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst35'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst35 ; Fall       ; inst36     ;
+; 0.241  ; 0.457        ; 0.216          ; High Pulse Width ; inst35 ; Fall       ; inst36     ;
+; 0.358  ; 0.542        ; 0.184          ; Low Pulse Width  ; inst35 ; Fall       ; inst36     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst36|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst35|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst35|q   ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst36|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst36'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst36 ; Fall       ; inst39     ;
+; 0.216  ; 0.432        ; 0.216          ; High Pulse Width ; inst36 ; Fall       ; inst39     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst36 ; Fall       ; inst39     ;
+; 0.423  ; 0.423        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst39|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst36|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst36|q   ;
+; 0.573  ; 0.573        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst39|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst39'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst39 ; Fall       ; inst40     ;
+; 0.241  ; 0.457        ; 0.216          ; High Pulse Width ; inst39 ; Fall       ; inst40     ;
+; 0.358  ; 0.542        ; 0.184          ; Low Pulse Width  ; inst39 ; Fall       ; inst40     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst40|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst39|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst39|q   ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst40|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst40'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst40 ; Fall       ; inst43     ;
+; 0.216  ; 0.432        ; 0.216          ; High Pulse Width ; inst40 ; Fall       ; inst43     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst40 ; Fall       ; inst43     ;
+; 0.423  ; 0.423        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst43|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst40|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst40|q   ;
+; 0.573  ; 0.573        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst43|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst43'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst43 ; Fall       ; inst44     ;
+; 0.238  ; 0.454        ; 0.216          ; High Pulse Width ; inst43 ; Fall       ; inst44     ;
+; 0.361  ; 0.545        ; 0.184          ; Low Pulse Width  ; inst43 ; Fall       ; inst44     ;
+; 0.446  ; 0.446        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst44|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst43|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst43|q   ;
+; 0.552  ; 0.552        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst44|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst44'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst44 ; Fall       ; inst47     ;
+; 0.220  ; 0.436        ; 0.216          ; High Pulse Width ; inst44 ; Fall       ; inst47     ;
+; 0.380  ; 0.564        ; 0.184          ; Low Pulse Width  ; inst44 ; Fall       ; inst47     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst47|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst44|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst44|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst47|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst47'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst47 ; Fall       ; inst48     ;
+; 0.241  ; 0.457        ; 0.216          ; High Pulse Width ; inst47 ; Fall       ; inst48     ;
+; 0.358  ; 0.542        ; 0.184          ; Low Pulse Width  ; inst47 ; Fall       ; inst48     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst48|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst47|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst47|q   ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst48|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst48'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst48 ; Fall       ; inst51     ;
+; 0.208  ; 0.424        ; 0.216          ; High Pulse Width ; inst48 ; Fall       ; inst51     ;
+; 0.392  ; 0.576        ; 0.184          ; Low Pulse Width  ; inst48 ; Fall       ; inst51     ;
+; 0.415  ; 0.415        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst51|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst48|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst48|q   ;
+; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst51|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst51'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst51 ; Fall       ; inst52     ;
+; 0.251  ; 0.467        ; 0.216          ; High Pulse Width ; inst51 ; Fall       ; inst52     ;
+; 0.347  ; 0.531        ; 0.184          ; Low Pulse Width  ; inst51 ; Fall       ; inst52     ;
+; 0.460  ; 0.460        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst52|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst51|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst51|q   ;
+; 0.539  ; 0.539        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst52|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst52'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst52 ; Fall       ; inst55     ;
+; 0.212  ; 0.428        ; 0.216          ; High Pulse Width ; inst52 ; Fall       ; inst55     ;
+; 0.388  ; 0.572        ; 0.184          ; Low Pulse Width  ; inst52 ; Fall       ; inst55     ;
+; 0.419  ; 0.419        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst55|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst52|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst52|q   ;
+; 0.578  ; 0.578        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst55|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst55'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst55 ; Fall       ; inst56     ;
+; 0.239  ; 0.455        ; 0.216          ; High Pulse Width ; inst55 ; Fall       ; inst56     ;
+; 0.359  ; 0.543        ; 0.184          ; Low Pulse Width  ; inst55 ; Fall       ; inst56     ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst56|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst55|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst55|q   ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst56|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst56'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst56 ; Fall       ; inst59     ;
+; 0.208  ; 0.424        ; 0.216          ; High Pulse Width ; inst56 ; Fall       ; inst59     ;
+; 0.392  ; 0.576        ; 0.184          ; Low Pulse Width  ; inst56 ; Fall       ; inst59     ;
+; 0.415  ; 0.415        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst59|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst56|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst56|q   ;
+; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst59|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst59'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst59 ; Fall       ; inst60     ;
+; 0.229  ; 0.445        ; 0.216          ; High Pulse Width ; inst59 ; Fall       ; inst60     ;
+; 0.371  ; 0.555        ; 0.184          ; Low Pulse Width  ; inst59 ; Fall       ; inst60     ;
+; 0.436  ; 0.436        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst60|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst59|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst59|q   ;
+; 0.561  ; 0.561        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst60|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst60'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst60 ; Fall       ; inst63     ;
+; 0.220  ; 0.436        ; 0.216          ; High Pulse Width ; inst60 ; Fall       ; inst63     ;
+; 0.380  ; 0.564        ; 0.184          ; Low Pulse Width  ; inst60 ; Fall       ; inst63     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst63|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst60|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst60|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst63|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst63'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst63 ; Fall       ; inst64     ;
+; 0.250  ; 0.466        ; 0.216          ; High Pulse Width ; inst63 ; Fall       ; inst64     ;
+; 0.349  ; 0.533        ; 0.184          ; Low Pulse Width  ; inst63 ; Fall       ; inst64     ;
+; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst64|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst63|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst63|q   ;
+; 0.540  ; 0.540        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst64|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst64'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst64 ; Fall       ; inst67     ;
+; 0.212  ; 0.428        ; 0.216          ; High Pulse Width ; inst64 ; Fall       ; inst67     ;
+; 0.388  ; 0.572        ; 0.184          ; Low Pulse Width  ; inst64 ; Fall       ; inst67     ;
+; 0.419  ; 0.419        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst67|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst64|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst64|q   ;
+; 0.578  ; 0.578        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst67|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst67'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst67 ; Fall       ; inst68     ;
+; 0.230  ; 0.446        ; 0.216          ; High Pulse Width ; inst67 ; Fall       ; inst68     ;
+; 0.370  ; 0.554        ; 0.184          ; Low Pulse Width  ; inst67 ; Fall       ; inst68     ;
+; 0.437  ; 0.437        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst68|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst67|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst67|q   ;
+; 0.560  ; 0.560        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst68|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst68'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst68 ; Fall       ; inst71     ;
+; 0.216  ; 0.432        ; 0.216          ; High Pulse Width ; inst68 ; Fall       ; inst71     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst68 ; Fall       ; inst71     ;
+; 0.424  ; 0.424        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst71|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst68|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst68|q   ;
+; 0.574  ; 0.574        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst71|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst71'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst71 ; Fall       ; inst72     ;
+; 0.229  ; 0.445        ; 0.216          ; High Pulse Width ; inst71 ; Fall       ; inst72     ;
+; 0.371  ; 0.555        ; 0.184          ; Low Pulse Width  ; inst71 ; Fall       ; inst72     ;
+; 0.436  ; 0.436        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst72|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst71|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst71|q   ;
+; 0.561  ; 0.561        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst72|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst72'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst72 ; Fall       ; inst75     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst72 ; Fall       ; inst75     ;
+; 0.366  ; 0.550        ; 0.184          ; Low Pulse Width  ; inst72 ; Fall       ; inst75     ;
+; 0.441  ; 0.441        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst75|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst72|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst72|q   ;
+; 0.556  ; 0.556        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst75|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst75'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst75 ; Fall       ; inst76     ;
+; 0.216  ; 0.432        ; 0.216          ; High Pulse Width ; inst75 ; Fall       ; inst76     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst75 ; Fall       ; inst76     ;
+; 0.424  ; 0.424        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst76|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst75|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst75|q   ;
+; 0.574  ; 0.574        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst76|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst76'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst76 ; Fall       ; inst79     ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; inst76 ; Fall       ; inst79     ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; inst76 ; Fall       ; inst79     ;
+; 0.424  ; 0.424        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst79|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst76|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst76|q   ;
+; 0.573  ; 0.573        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst79|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst79'                                          ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst79 ; Fall       ; inst80     ;
+; 0.220  ; 0.436        ; 0.216          ; High Pulse Width ; inst79 ; Fall       ; inst80     ;
+; 0.380  ; 0.564        ; 0.184          ; Low Pulse Width  ; inst79 ; Fall       ; inst80     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst80|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst79|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst79|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst80|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 3.445 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 3.445 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 3.447 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 3.447 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 2.983 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 2.983 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 3.009 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 3.009 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 4.251 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 4.251 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 4.384 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 4.384 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 2.876 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 2.876 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 2.913 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 2.913 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 2.957 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 2.957 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 2.996 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 2.996 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 2.779 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 2.779 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 2.808 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 2.808 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 2.951 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 2.951 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 2.994 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 2.994 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 3.081 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 3.081 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 3.104 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 3.104 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 2.657 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 2.657 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 3.701 ; 3.735 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 2.692 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 3.701 ; 3.735 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 3.396 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 3.396 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 3.398 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 3.398 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 2.953 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 2.953 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 2.977 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 2.977 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 4.219 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 4.219 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 4.350 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 4.350 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 2.850 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 2.850 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 2.885 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 2.885 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 2.928 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 2.928 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 2.965 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 2.965 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 2.758 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 2.758 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 2.785 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 2.785 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 2.923 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 2.923 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 2.964 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 2.964 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 3.049 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 3.049 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 3.070 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 3.070 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 2.641 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 2.641 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 3.634 ; 2.675 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 2.675 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 3.634 ; 3.665 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                           ;
++-------------+-----------------+------------+------------------------------------------------+
+; Fmax        ; Restricted Fmax ; Clock Name ; Note                                           ;
++-------------+-----------------+------------+------------------------------------------------+
+; 1661.13 MHz ; 500.0 MHz       ; inst79     ; limit due to minimum period restriction (tmin) ;
++-------------+-----------------+------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-----------+-------+----------------+
+; Clock     ; Slack ; End Point TNS  ;
++-----------+-------+----------------+
+; inst43    ; 0.051 ; 0.000          ;
+; inst28    ; 0.052 ; 0.000          ;
+; inst51    ; 0.083 ; 0.000          ;
+; inst76    ; 0.089 ; 0.000          ;
+; pin_name1 ; 0.112 ; 0.000          ;
+; inst72    ; 0.118 ; 0.000          ;
+; inst59    ; 0.127 ; 0.000          ;
+; inst39    ; 0.131 ; 0.000          ;
+; inst47    ; 0.135 ; 0.000          ;
+; inst23    ; 0.137 ; 0.000          ;
+; inst35    ; 0.140 ; 0.000          ;
+; inst67    ; 0.151 ; 0.000          ;
+; inst71    ; 0.153 ; 0.000          ;
+; inst55    ; 0.156 ; 0.000          ;
+; inst68    ; 0.165 ; 0.000          ;
+; inst31    ; 0.170 ; 0.000          ;
+; inst32    ; 0.171 ; 0.000          ;
+; inst36    ; 0.171 ; 0.000          ;
+; inst27    ; 0.173 ; 0.000          ;
+; inst48    ; 0.173 ; 0.000          ;
+; inst24    ; 0.178 ; 0.000          ;
+; inst56    ; 0.178 ; 0.000          ;
+; inst60    ; 0.178 ; 0.000          ;
+; inst44    ; 0.179 ; 0.000          ;
+; inst64    ; 0.186 ; 0.000          ;
+; inst75    ; 0.188 ; 0.000          ;
+; inst63    ; 0.215 ; 0.000          ;
+; inst40    ; 0.311 ; 0.000          ;
+; inst52    ; 0.341 ; 0.000          ;
+; inst79    ; 0.398 ; 0.000          ;
++-----------+-------+----------------+
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Hold Summary  ;
++-----------+--------+---------------+
+; Clock     ; Slack  ; End Point TNS ;
++-----------+--------+---------------+
+; inst63    ; -0.079 ; -0.079        ;
+; pin_name1 ; -0.022 ; -0.022        ;
+; inst52    ; -0.018 ; -0.018        ;
+; inst71    ; -0.014 ; -0.014        ;
+; inst31    ; -0.013 ; -0.013        ;
+; inst27    ; -0.003 ; -0.003        ;
+; inst59    ; -0.003 ; -0.003        ;
+; inst40    ; 0.003  ; 0.000         ;
+; inst67    ; 0.006  ; 0.000         ;
+; inst55    ; 0.012  ; 0.000         ;
+; inst35    ; 0.019  ; 0.000         ;
+; inst47    ; 0.028  ; 0.000         ;
+; inst39    ; 0.029  ; 0.000         ;
+; inst23    ; 0.032  ; 0.000         ;
+; inst72    ; 0.040  ; 0.000         ;
+; inst76    ; 0.045  ; 0.000         ;
+; inst51    ; 0.047  ; 0.000         ;
+; inst43    ; 0.063  ; 0.000         ;
+; inst75    ; 0.073  ; 0.000         ;
+; inst24    ; 0.075  ; 0.000         ;
+; inst56    ; 0.075  ; 0.000         ;
+; inst64    ; 0.077  ; 0.000         ;
+; inst48    ; 0.081  ; 0.000         ;
+; inst60    ; 0.085  ; 0.000         ;
+; inst44    ; 0.086  ; 0.000         ;
+; inst68    ; 0.089  ; 0.000         ;
+; inst32    ; 0.094  ; 0.000         ;
+; inst36    ; 0.094  ; 0.000         ;
+; inst28    ; 0.110  ; 0.000         ;
+; inst79    ; 0.341  ; 0.000         ;
++-----------+--------+---------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-----------+--------+-----------------------------+
+; Clock     ; Slack  ; End Point TNS               ;
++-----------+--------+-----------------------------+
+; pin_name1 ; -3.000 ; -4.000                      ;
+; inst23    ; -1.000 ; -1.000                      ;
+; inst24    ; -1.000 ; -1.000                      ;
+; inst27    ; -1.000 ; -1.000                      ;
+; inst28    ; -1.000 ; -1.000                      ;
+; inst31    ; -1.000 ; -1.000                      ;
+; inst32    ; -1.000 ; -1.000                      ;
+; inst35    ; -1.000 ; -1.000                      ;
+; inst36    ; -1.000 ; -1.000                      ;
+; inst39    ; -1.000 ; -1.000                      ;
+; inst40    ; -1.000 ; -1.000                      ;
+; inst43    ; -1.000 ; -1.000                      ;
+; inst44    ; -1.000 ; -1.000                      ;
+; inst47    ; -1.000 ; -1.000                      ;
+; inst48    ; -1.000 ; -1.000                      ;
+; inst51    ; -1.000 ; -1.000                      ;
+; inst52    ; -1.000 ; -1.000                      ;
+; inst55    ; -1.000 ; -1.000                      ;
+; inst56    ; -1.000 ; -1.000                      ;
+; inst59    ; -1.000 ; -1.000                      ;
+; inst60    ; -1.000 ; -1.000                      ;
+; inst63    ; -1.000 ; -1.000                      ;
+; inst64    ; -1.000 ; -1.000                      ;
+; inst67    ; -1.000 ; -1.000                      ;
+; inst68    ; -1.000 ; -1.000                      ;
+; inst71    ; -1.000 ; -1.000                      ;
+; inst72    ; -1.000 ; -1.000                      ;
+; inst75    ; -1.000 ; -1.000                      ;
+; inst76    ; -1.000 ; -1.000                      ;
+; inst79    ; -1.000 ; -1.000                      ;
++-----------+--------+-----------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst43'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.051 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.500        ; 1.291      ; 1.935      ;
+; 0.534 ; inst44    ; inst44  ; inst44       ; inst43      ; 1.000        ; 1.291      ; 1.952      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst28'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.052 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.500        ; 0.735      ; 1.378      ;
+; 0.535 ; inst31    ; inst31  ; inst31       ; inst28      ; 1.000        ; 0.735      ; 1.395      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst51'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.083 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.500        ; 1.018      ; 1.630      ;
+; 0.572 ; inst52    ; inst52  ; inst52       ; inst51      ; 1.000        ; 1.018      ; 1.641      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst76'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.089 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.500        ; 1.060      ; 1.666      ;
+; 0.574 ; inst79    ; inst79  ; inst79       ; inst76      ; 1.000        ; 1.060      ; 1.681      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'pin_name1'                                                           ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.112 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.500        ; 2.136      ; 2.699      ;
+; 0.583 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 1.000        ; 2.136      ; 2.728      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst72'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.118 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.500        ; 0.804      ; 1.381      ;
+; 0.597 ; inst75    ; inst75  ; inst75       ; inst72      ; 1.000        ; 0.804      ; 1.402      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst59'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.127 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.500        ; 1.092      ; 1.660      ;
+; 0.615 ; inst60    ; inst60  ; inst60       ; inst59      ; 1.000        ; 1.092      ; 1.672      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst39'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.131 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.500        ; 0.808      ; 1.372      ;
+; 0.610 ; inst40    ; inst40  ; inst40       ; inst39      ; 1.000        ; 0.808      ; 1.393      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst47'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.135 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.500        ; 0.808      ; 1.368      ;
+; 0.614 ; inst48    ; inst48  ; inst48       ; inst47      ; 1.000        ; 0.808      ; 1.389      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst23'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.137 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.500        ; 0.808      ; 1.366      ;
+; 0.612 ; inst24    ; inst24  ; inst24       ; inst23      ; 1.000        ; 0.808      ; 1.391      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst35'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.140 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.500        ; 0.808      ; 1.363      ;
+; 0.620 ; inst36    ; inst36  ; inst36       ; inst35      ; 1.000        ; 0.808      ; 1.383      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst67'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.151 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.500        ; 0.846      ; 1.390      ;
+; 0.630 ; inst68    ; inst68  ; inst68       ; inst67      ; 1.000        ; 0.846      ; 1.411      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst71'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.153 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.500        ; 1.109      ; 1.651      ;
+; 0.632 ; inst72    ; inst72  ; inst72       ; inst71      ; 1.000        ; 1.109      ; 1.672      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst55'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.156 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.500        ; 0.827      ; 1.366      ;
+; 0.631 ; inst56    ; inst56  ; inst56       ; inst55      ; 1.000        ; 0.827      ; 1.391      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst68'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.165 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.500        ; 0.744      ; 1.274      ;
+; 0.622 ; inst71    ; inst71  ; inst71       ; inst68      ; 1.000        ; 0.744      ; 1.317      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst31'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.170 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.500        ; 0.838      ; 1.363      ;
+; 0.650 ; inst32    ; inst32  ; inst32       ; inst31      ; 1.000        ; 0.838      ; 1.383      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst32'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.171 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.500        ; 0.726      ; 1.250      ;
+; 0.625 ; inst35    ; inst35  ; inst35       ; inst32      ; 1.000        ; 0.726      ; 1.296      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst36'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.171 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.500        ; 0.726      ; 1.250      ;
+; 0.625 ; inst39    ; inst39  ; inst39       ; inst36      ; 1.000        ; 0.726      ; 1.296      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst27'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.173 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.500        ; 0.839      ; 1.361      ;
+; 0.647 ; inst28    ; inst28  ; inst28       ; inst27      ; 1.000        ; 0.839      ; 1.387      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst48'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.173 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.500        ; 0.735      ; 1.257      ;
+; 0.631 ; inst51    ; inst51  ; inst51       ; inst48      ; 1.000        ; 0.735      ; 1.299      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst24'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.178 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.500        ; 0.735      ; 1.252      ;
+; 0.636 ; inst27    ; inst27  ; inst27       ; inst24      ; 1.000        ; 0.735      ; 1.294      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst56'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.178 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.500        ; 0.735      ; 1.252      ;
+; 0.636 ; inst59    ; inst59  ; inst59       ; inst56      ; 1.000        ; 0.735      ; 1.294      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst60'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.178 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.500        ; 0.734      ; 1.251      ;
+; 0.633 ; inst63    ; inst63  ; inst63       ; inst60      ; 1.000        ; 0.734      ; 1.296      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst44'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.179 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.500        ; 0.734      ; 1.250      ;
+; 0.633 ; inst47    ; inst47  ; inst47       ; inst44      ; 1.000        ; 0.734      ; 1.296      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst64'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.186 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.500        ; 0.742      ; 1.251      ;
+; 0.642 ; inst67    ; inst67  ; inst67       ; inst64      ; 1.000        ; 0.742      ; 1.295      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst75'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.188 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.500        ; 0.744      ; 1.251      ;
+; 0.646 ; inst76    ; inst76  ; inst76       ; inst75      ; 1.000        ; 0.744      ; 1.293      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst63'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.215 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.500        ; 1.186      ; 1.666      ;
+; 0.685 ; inst64    ; inst64  ; inst64       ; inst63      ; 1.000        ; 1.186      ; 1.696      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst40'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.311 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.500        ; 0.726      ; 1.110      ;
+; 0.783 ; inst43    ; inst43  ; inst43       ; inst40      ; 1.000        ; 0.726      ; 1.138      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst52'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.341 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.500        ; 0.742      ; 1.096      ;
+; 0.802 ; inst55    ; inst55  ; inst55       ; inst52      ; 1.000        ; 0.742      ; 1.135      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst79'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.398 ; inst80    ; inst80  ; inst79       ; inst79      ; 1.000        ; -0.034     ; 0.583      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst63'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.079 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.000        ; 1.251      ; 1.496      ;
+; 0.379  ; inst64    ; inst64  ; inst64       ; inst63      ; -0.500       ; 1.251      ; 1.454      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'pin_name1'                                                             ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.022 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.000        ; 2.208      ; 2.530      ;
+; 0.475  ; inst23    ; inst23  ; inst23       ; pin_name1   ; -0.500       ; 2.208      ; 2.527      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst52'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.018 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.000        ; 0.788      ; 1.094      ;
+; 0.444  ; inst55    ; inst55  ; inst55       ; inst52      ; -0.500       ; 0.788      ; 1.056      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst71'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.014 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.000        ; 1.171      ; 1.481      ;
+; 0.443  ; inst72    ; inst72  ; inst72       ; inst71      ; -0.500       ; 1.171      ; 1.438      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst31'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.013 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.000        ; 0.889      ; 1.200      ;
+; 0.451  ; inst32    ; inst32  ; inst32       ; inst31      ; -0.500       ; 0.889      ; 1.164      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst27'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.003 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.000        ; 0.890      ; 1.211      ;
+; 0.446  ; inst28    ; inst28  ; inst28       ; inst27      ; -0.500       ; 0.890      ; 1.160      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst59'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.003 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.000        ; 1.154      ; 1.475      ;
+; 0.471  ; inst60    ; inst60  ; inst60       ; inst59      ; -0.500       ; 1.154      ; 1.449      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst40'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.003 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.000        ; 0.772      ; 1.099      ;
+; 0.476 ; inst43    ; inst43  ; inst43       ; inst40      ; -0.500       ; 0.772      ; 1.072      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst67'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.006 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.000        ; 0.897      ; 1.227      ;
+; 0.468 ; inst68    ; inst68  ; inst68       ; inst67      ; -0.500       ; 0.897      ; 1.189      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst55'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.012 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.000        ; 0.877      ; 1.213      ;
+; 0.463 ; inst56    ; inst56  ; inst56       ; inst55      ; -0.500       ; 0.877      ; 1.164      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst35'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.019 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.000        ; 0.857      ; 1.200      ;
+; 0.483 ; inst36    ; inst36  ; inst36       ; inst35      ; -0.500       ; 0.857      ; 1.164      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst47'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.028 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.000        ; 0.857      ; 1.209      ;
+; 0.485 ; inst48    ; inst48  ; inst48       ; inst47      ; -0.500       ; 0.857      ; 1.166      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst39'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.029 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.000        ; 0.857      ; 1.210      ;
+; 0.490 ; inst40    ; inst40  ; inst40       ; inst39      ; -0.500       ; 0.857      ; 1.171      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst23'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.032 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.000        ; 0.857      ; 1.213      ;
+; 0.483 ; inst24    ; inst24  ; inst24       ; inst23      ; -0.500       ; 0.857      ; 1.164      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst72'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.040 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.000        ; 0.854      ; 1.218      ;
+; 0.502 ; inst75    ; inst75  ; inst75       ; inst72      ; -0.500       ; 0.854      ; 1.180      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst76'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.045 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.000        ; 1.120      ; 1.489      ;
+; 0.508 ; inst79    ; inst79  ; inst79       ; inst76      ; -0.500       ; 1.120      ; 1.452      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst51'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.047 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.000        ; 1.076      ; 1.447      ;
+; 0.520 ; inst52    ; inst52  ; inst52       ; inst51      ; -0.500       ; 1.076      ; 1.420      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst43'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.063 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.000        ; 1.360      ; 1.747      ;
+; 0.528 ; inst44    ; inst44  ; inst44       ; inst43      ; -0.500       ; 1.360      ; 1.712      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst75'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.073 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.000        ; 0.791      ; 1.188      ;
+; 0.531 ; inst76    ; inst76  ; inst76       ; inst75      ; -0.500       ; 0.791      ; 1.146      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst24'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.075 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.000        ; 0.782      ; 1.181      ;
+; 0.543 ; inst27    ; inst27  ; inst27       ; inst24      ; -0.500       ; 0.782      ; 1.149      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst56'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.075 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.000        ; 0.782      ; 1.181      ;
+; 0.543 ; inst59    ; inst59  ; inst59       ; inst56      ; -0.500       ; 0.782      ; 1.149      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst64'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.077 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.000        ; 0.788      ; 1.189      ;
+; 0.534 ; inst67    ; inst67  ; inst67       ; inst64      ; -0.500       ; 0.788      ; 1.146      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst48'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.081 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.000        ; 0.782      ; 1.187      ;
+; 0.547 ; inst51    ; inst51  ; inst51       ; inst48      ; -0.500       ; 0.782      ; 1.153      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst60'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.085 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.000        ; 0.780      ; 1.189      ;
+; 0.542 ; inst63    ; inst63  ; inst63       ; inst60      ; -0.500       ; 0.780      ; 1.146      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst44'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.086 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.000        ; 0.780      ; 1.190      ;
+; 0.543 ; inst47    ; inst47  ; inst47       ; inst44      ; -0.500       ; 0.780      ; 1.147      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst68'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.089 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.000        ; 0.791      ; 1.204      ;
+; 0.555 ; inst71    ; inst71  ; inst71       ; inst68      ; -0.500       ; 0.791      ; 1.170      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst32'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.094 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.000        ; 0.772      ; 1.190      ;
+; 0.551 ; inst35    ; inst35  ; inst35       ; inst32      ; -0.500       ; 0.772      ; 1.147      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst36'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.094 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.000        ; 0.772      ; 1.190      ;
+; 0.551 ; inst39    ; inst39  ; inst39       ; inst36      ; -0.500       ; 0.772      ; 1.147      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst28'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.110 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.000        ; 0.782      ; 1.216      ;
+; 0.571 ; inst31    ; inst31  ; inst31       ; inst28      ; -0.500       ; 0.782      ; 1.177      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst79'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.341 ; inst80    ; inst80  ; inst79       ; inst79      ; 0.000        ; 0.034      ; 0.519      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'pin_name1'                                                                                            ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                      ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; pin_name1 ; Rise       ; pin_name1                                                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
+; 0.347  ; 0.347        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.653  ; 0.653        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst23'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst23 ; Fall       ; inst24     ;
+; 0.273  ; 0.489        ; 0.216          ; High Pulse Width ; inst23 ; Fall       ; inst24     ;
+; 0.326  ; 0.510        ; 0.184          ; Low Pulse Width  ; inst23 ; Fall       ; inst24     ;
+; 0.475  ; 0.475        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst24|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst23|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst23|q   ;
+; 0.525  ; 0.525        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst24|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst24'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst24 ; Fall       ; inst27     ;
+; 0.226  ; 0.442        ; 0.216          ; High Pulse Width ; inst24 ; Fall       ; inst27     ;
+; 0.372  ; 0.556        ; 0.184          ; Low Pulse Width  ; inst24 ; Fall       ; inst27     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst27|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst24|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst24|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst27|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst27'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst27 ; Fall       ; inst28     ;
+; 0.263  ; 0.479        ; 0.216          ; High Pulse Width ; inst27 ; Fall       ; inst28     ;
+; 0.336  ; 0.520        ; 0.184          ; Low Pulse Width  ; inst27 ; Fall       ; inst28     ;
+; 0.464  ; 0.464        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst28|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst27|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst27|q   ;
+; 0.534  ; 0.534        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst28|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst28'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst28 ; Fall       ; inst31     ;
+; 0.226  ; 0.442        ; 0.216          ; High Pulse Width ; inst28 ; Fall       ; inst31     ;
+; 0.372  ; 0.556        ; 0.184          ; Low Pulse Width  ; inst28 ; Fall       ; inst31     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst31|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst28|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst28|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst31|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst31'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst31 ; Fall       ; inst32     ;
+; 0.268  ; 0.484        ; 0.216          ; High Pulse Width ; inst31 ; Fall       ; inst32     ;
+; 0.332  ; 0.516        ; 0.184          ; Low Pulse Width  ; inst31 ; Fall       ; inst32     ;
+; 0.469  ; 0.469        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst32|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst31|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst31|q   ;
+; 0.530  ; 0.530        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst32|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst32'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst32 ; Fall       ; inst35     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst32 ; Fall       ; inst35     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst32 ; Fall       ; inst35     ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst35|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst32|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst32|q   ;
+; 0.563  ; 0.563        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst35|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst35'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst35 ; Fall       ; inst36     ;
+; 0.273  ; 0.489        ; 0.216          ; High Pulse Width ; inst35 ; Fall       ; inst36     ;
+; 0.326  ; 0.510        ; 0.184          ; Low Pulse Width  ; inst35 ; Fall       ; inst36     ;
+; 0.475  ; 0.475        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst36|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst35|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst35|q   ;
+; 0.525  ; 0.525        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst36|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst36'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst36 ; Fall       ; inst39     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst36 ; Fall       ; inst39     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst36 ; Fall       ; inst39     ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst39|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst36|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst36|q   ;
+; 0.563  ; 0.563        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst39|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst39'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst39 ; Fall       ; inst40     ;
+; 0.273  ; 0.489        ; 0.216          ; High Pulse Width ; inst39 ; Fall       ; inst40     ;
+; 0.326  ; 0.510        ; 0.184          ; Low Pulse Width  ; inst39 ; Fall       ; inst40     ;
+; 0.475  ; 0.475        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst40|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst39|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst39|q   ;
+; 0.525  ; 0.525        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst40|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst40'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst40 ; Fall       ; inst43     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst40 ; Fall       ; inst43     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst40 ; Fall       ; inst43     ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst43|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst40|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst40|q   ;
+; 0.563  ; 0.563        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst43|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst43'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst43 ; Fall       ; inst44     ;
+; 0.286  ; 0.502        ; 0.216          ; High Pulse Width ; inst43 ; Fall       ; inst44     ;
+; 0.313  ; 0.497        ; 0.184          ; Low Pulse Width  ; inst43 ; Fall       ; inst44     ;
+; 0.488  ; 0.488        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst44|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst43|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst43|q   ;
+; 0.512  ; 0.512        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst44|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst44'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst44 ; Fall       ; inst47     ;
+; 0.238  ; 0.454        ; 0.216          ; High Pulse Width ; inst44 ; Fall       ; inst47     ;
+; 0.361  ; 0.545        ; 0.184          ; Low Pulse Width  ; inst44 ; Fall       ; inst47     ;
+; 0.439  ; 0.439        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst47|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst44|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst44|q   ;
+; 0.559  ; 0.559        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst47|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst47'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst47 ; Fall       ; inst48     ;
+; 0.273  ; 0.489        ; 0.216          ; High Pulse Width ; inst47 ; Fall       ; inst48     ;
+; 0.326  ; 0.510        ; 0.184          ; Low Pulse Width  ; inst47 ; Fall       ; inst48     ;
+; 0.475  ; 0.475        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst48|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst47|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst47|q   ;
+; 0.525  ; 0.525        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst48|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst48'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst48 ; Fall       ; inst51     ;
+; 0.226  ; 0.442        ; 0.216          ; High Pulse Width ; inst48 ; Fall       ; inst51     ;
+; 0.372  ; 0.556        ; 0.184          ; Low Pulse Width  ; inst48 ; Fall       ; inst51     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst51|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst48|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst48|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst51|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst51'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst51 ; Fall       ; inst52     ;
+; 0.281  ; 0.497        ; 0.216          ; High Pulse Width ; inst51 ; Fall       ; inst52     ;
+; 0.318  ; 0.502        ; 0.184          ; Low Pulse Width  ; inst51 ; Fall       ; inst52     ;
+; 0.483  ; 0.483        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst52|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst51|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst51|q   ;
+; 0.517  ; 0.517        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst52|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst52'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst52 ; Fall       ; inst55     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst52 ; Fall       ; inst55     ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; inst52 ; Fall       ; inst55     ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst55|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst52|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst52|q   ;
+; 0.566  ; 0.566        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst55|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst55'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst55 ; Fall       ; inst56     ;
+; 0.273  ; 0.489        ; 0.216          ; High Pulse Width ; inst55 ; Fall       ; inst56     ;
+; 0.326  ; 0.510        ; 0.184          ; Low Pulse Width  ; inst55 ; Fall       ; inst56     ;
+; 0.475  ; 0.475        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst56|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst55|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst55|q   ;
+; 0.525  ; 0.525        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst56|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst56'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst56 ; Fall       ; inst59     ;
+; 0.226  ; 0.442        ; 0.216          ; High Pulse Width ; inst56 ; Fall       ; inst59     ;
+; 0.372  ; 0.556        ; 0.184          ; Low Pulse Width  ; inst56 ; Fall       ; inst59     ;
+; 0.427  ; 0.427        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst59|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst56|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst56|q   ;
+; 0.570  ; 0.570        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst59|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst59'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst59 ; Fall       ; inst60     ;
+; 0.272  ; 0.488        ; 0.216          ; High Pulse Width ; inst59 ; Fall       ; inst60     ;
+; 0.328  ; 0.512        ; 0.184          ; Low Pulse Width  ; inst59 ; Fall       ; inst60     ;
+; 0.473  ; 0.473        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst60|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst59|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst59|q   ;
+; 0.526  ; 0.526        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst60|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst60'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst60 ; Fall       ; inst63     ;
+; 0.238  ; 0.454        ; 0.216          ; High Pulse Width ; inst60 ; Fall       ; inst63     ;
+; 0.361  ; 0.545        ; 0.184          ; Low Pulse Width  ; inst60 ; Fall       ; inst63     ;
+; 0.439  ; 0.439        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst63|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst60|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst60|q   ;
+; 0.559  ; 0.559        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst63|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst63'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst63 ; Fall       ; inst64     ;
+; 0.298  ; 0.514        ; 0.216          ; High Pulse Width ; inst63 ; Fall       ; inst64     ;
+; 0.301  ; 0.485        ; 0.184          ; Low Pulse Width  ; inst63 ; Fall       ; inst64     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst63|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst63|q   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst64|clk ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst64|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst64'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst64 ; Fall       ; inst67     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst64 ; Fall       ; inst67     ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; inst64 ; Fall       ; inst67     ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst67|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst64|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst64|q   ;
+; 0.566  ; 0.566        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst67|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst67'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst67 ; Fall       ; inst68     ;
+; 0.265  ; 0.481        ; 0.216          ; High Pulse Width ; inst67 ; Fall       ; inst68     ;
+; 0.335  ; 0.519        ; 0.184          ; Low Pulse Width  ; inst67 ; Fall       ; inst68     ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst68|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst67|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst67|q   ;
+; 0.533  ; 0.533        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst68|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst68'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst68 ; Fall       ; inst71     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst68 ; Fall       ; inst71     ;
+; 0.366  ; 0.550        ; 0.184          ; Low Pulse Width  ; inst68 ; Fall       ; inst71     ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst71|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst68|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst68|q   ;
+; 0.564  ; 0.564        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst71|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst71'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst71 ; Fall       ; inst72     ;
+; 0.255  ; 0.471        ; 0.216          ; High Pulse Width ; inst71 ; Fall       ; inst72     ;
+; 0.345  ; 0.529        ; 0.184          ; Low Pulse Width  ; inst71 ; Fall       ; inst72     ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst72|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst71|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst71|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst72|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst72'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst72 ; Fall       ; inst75     ;
+; 0.264  ; 0.480        ; 0.216          ; High Pulse Width ; inst72 ; Fall       ; inst75     ;
+; 0.335  ; 0.519        ; 0.184          ; Low Pulse Width  ; inst72 ; Fall       ; inst75     ;
+; 0.465  ; 0.465        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst75|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst72|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst72|q   ;
+; 0.533  ; 0.533        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst75|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst75'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst75 ; Fall       ; inst76     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst75 ; Fall       ; inst76     ;
+; 0.366  ; 0.550        ; 0.184          ; Low Pulse Width  ; inst75 ; Fall       ; inst76     ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst76|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst75|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst75|q   ;
+; 0.564  ; 0.564        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst76|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst76'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst76 ; Fall       ; inst79     ;
+; 0.262  ; 0.478        ; 0.216          ; High Pulse Width ; inst76 ; Fall       ; inst79     ;
+; 0.338  ; 0.522        ; 0.184          ; Low Pulse Width  ; inst76 ; Fall       ; inst79     ;
+; 0.463  ; 0.463        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst79|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst76|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst76|q   ;
+; 0.536  ; 0.536        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst79|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst79'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst79 ; Fall       ; inst80     ;
+; 0.238  ; 0.454        ; 0.216          ; High Pulse Width ; inst79 ; Fall       ; inst80     ;
+; 0.361  ; 0.545        ; 0.184          ; Low Pulse Width  ; inst79 ; Fall       ; inst80     ;
+; 0.439  ; 0.439        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst80|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst79|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst79|q   ;
+; 0.559  ; 0.559        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst80|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 3.365 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 3.365 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 3.332 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 3.332 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 2.932 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 2.932 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 2.926 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 2.926 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 4.195 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 4.195 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 4.285 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 4.285 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 2.825 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 2.825 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 2.842 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 2.842 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 2.895 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 2.895 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 2.923 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 2.923 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 2.743 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 2.743 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 2.739 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 2.739 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 2.891 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 2.891 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 2.921 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 2.921 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 3.023 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 3.023 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 3.026 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 3.026 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 2.624 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 2.624 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 3.557 ; 3.574 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 2.640 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 3.557 ; 3.574 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 3.319 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 3.319 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 3.288 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 3.288 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 2.904 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 2.904 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 2.897 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 2.897 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 4.165 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 4.165 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 4.255 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 4.255 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 2.801 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 2.801 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 2.817 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 2.817 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 2.869 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 2.869 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 2.896 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 2.896 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 2.723 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 2.723 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 2.719 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 2.719 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 2.866 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 2.866 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 2.893 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 2.893 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 2.993 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 2.993 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 2.995 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 2.995 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 2.610 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 2.610 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 3.498 ; 2.625 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 2.625 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 3.498 ; 3.514 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-----------+-------+----------------+
+; Clock     ; Slack ; End Point TNS  ;
++-----------+-------+----------------+
+; inst28    ; 0.237 ; 0.000          ;
+; pin_name1 ; 0.241 ; 0.000          ;
+; inst51    ; 0.270 ; 0.000          ;
+; inst72    ; 0.281 ; 0.000          ;
+; inst39    ; 0.284 ; 0.000          ;
+; inst43    ; 0.290 ; 0.000          ;
+; inst23    ; 0.291 ; 0.000          ;
+; inst76    ; 0.291 ; 0.000          ;
+; inst35    ; 0.292 ; 0.000          ;
+; inst47    ; 0.292 ; 0.000          ;
+; inst67    ; 0.296 ; 0.000          ;
+; inst55    ; 0.304 ; 0.000          ;
+; inst31    ; 0.311 ; 0.000          ;
+; inst27    ; 0.316 ; 0.000          ;
+; inst59    ; 0.324 ; 0.000          ;
+; inst68    ; 0.327 ; 0.000          ;
+; inst71    ; 0.328 ; 0.000          ;
+; inst32    ; 0.330 ; 0.000          ;
+; inst36    ; 0.330 ; 0.000          ;
+; inst48    ; 0.331 ; 0.000          ;
+; inst44    ; 0.335 ; 0.000          ;
+; inst60    ; 0.335 ; 0.000          ;
+; inst24    ; 0.336 ; 0.000          ;
+; inst56    ; 0.336 ; 0.000          ;
+; inst64    ; 0.343 ; 0.000          ;
+; inst75    ; 0.344 ; 0.000          ;
+; inst63    ; 0.364 ; 0.000          ;
+; inst40    ; 0.429 ; 0.000          ;
+; inst52    ; 0.435 ; 0.000          ;
+; inst79    ; 0.624 ; 0.000          ;
++-----------+-------+----------------+
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Hold Summary  ;
++-----------+--------+---------------+
+; Clock     ; Slack  ; End Point TNS ;
++-----------+--------+---------------+
+; inst63    ; -0.105 ; -0.105        ;
+; inst59    ; -0.066 ; -0.066        ;
+; inst71    ; -0.060 ; -0.060        ;
+; inst52    ; -0.049 ; -0.049        ;
+; inst43    ; -0.041 ; -0.041        ;
+; inst31    ; -0.033 ; -0.033        ;
+; inst27    ; -0.029 ; -0.029        ;
+; inst40    ; -0.027 ; -0.027        ;
+; inst76    ; -0.027 ; -0.027        ;
+; pin_name1 ; -0.021 ; -0.021        ;
+; inst55    ; -0.018 ; -0.018        ;
+; inst67    ; -0.018 ; -0.018        ;
+; inst35    ; -0.014 ; -0.014        ;
+; inst51    ; -0.009 ; -0.009        ;
+; inst47    ; -0.007 ; -0.007        ;
+; inst23    ; -0.005 ; -0.005        ;
+; inst39    ; -0.005 ; -0.005        ;
+; inst72    ; -0.003 ; -0.003        ;
+; inst75    ; 0.017  ; 0.000         ;
+; inst24    ; 0.018  ; 0.000         ;
+; inst56    ; 0.018  ; 0.000         ;
+; inst64    ; 0.018  ; 0.000         ;
+; inst48    ; 0.024  ; 0.000         ;
+; inst60    ; 0.026  ; 0.000         ;
+; inst68    ; 0.026  ; 0.000         ;
+; inst44    ; 0.028  ; 0.000         ;
+; inst32    ; 0.033  ; 0.000         ;
+; inst36    ; 0.033  ; 0.000         ;
+; inst28    ; 0.046  ; 0.000         ;
+; inst79    ; 0.206  ; 0.000         ;
++-----------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-----------+--------+-----------------------------+
+; Clock     ; Slack  ; End Point TNS               ;
++-----------+--------+-----------------------------+
+; pin_name1 ; -3.000 ; -4.056                      ;
+; inst23    ; -1.000 ; -1.000                      ;
+; inst24    ; -1.000 ; -1.000                      ;
+; inst27    ; -1.000 ; -1.000                      ;
+; inst28    ; -1.000 ; -1.000                      ;
+; inst31    ; -1.000 ; -1.000                      ;
+; inst32    ; -1.000 ; -1.000                      ;
+; inst35    ; -1.000 ; -1.000                      ;
+; inst36    ; -1.000 ; -1.000                      ;
+; inst39    ; -1.000 ; -1.000                      ;
+; inst40    ; -1.000 ; -1.000                      ;
+; inst43    ; -1.000 ; -1.000                      ;
+; inst44    ; -1.000 ; -1.000                      ;
+; inst47    ; -1.000 ; -1.000                      ;
+; inst48    ; -1.000 ; -1.000                      ;
+; inst51    ; -1.000 ; -1.000                      ;
+; inst52    ; -1.000 ; -1.000                      ;
+; inst55    ; -1.000 ; -1.000                      ;
+; inst56    ; -1.000 ; -1.000                      ;
+; inst59    ; -1.000 ; -1.000                      ;
+; inst60    ; -1.000 ; -1.000                      ;
+; inst63    ; -1.000 ; -1.000                      ;
+; inst64    ; -1.000 ; -1.000                      ;
+; inst67    ; -1.000 ; -1.000                      ;
+; inst68    ; -1.000 ; -1.000                      ;
+; inst71    ; -1.000 ; -1.000                      ;
+; inst72    ; -1.000 ; -1.000                      ;
+; inst75    ; -1.000 ; -1.000                      ;
+; inst76    ; -1.000 ; -1.000                      ;
+; inst79    ; -1.000 ; -1.000                      ;
++-----------+--------+-----------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst28'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.237 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.500        ; 0.470      ; 0.845      ;
+; 0.734 ; inst31    ; inst31  ; inst31       ; inst28      ; 1.000        ; 0.470      ; 0.848      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'pin_name1'                                                           ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.241 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.500        ; 1.342      ; 1.693      ;
+; 0.734 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 1.000        ; 1.342      ; 1.700      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst51'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.270 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.500        ; 0.654      ; 0.996      ;
+; 0.769 ; inst52    ; inst52  ; inst52       ; inst51      ; 1.000        ; 0.654      ; 0.997      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst72'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.281 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.500        ; 0.518      ; 0.849      ;
+; 0.774 ; inst75    ; inst75  ; inst75       ; inst72      ; 1.000        ; 0.518      ; 0.856      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst39'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.284 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.500        ; 0.518      ; 0.846      ;
+; 0.776 ; inst40    ; inst40  ; inst40       ; inst39      ; 1.000        ; 0.518      ; 0.854      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst43'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.290 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.500        ; 0.858      ; 1.180      ;
+; 0.785 ; inst44    ; inst44  ; inst44       ; inst43      ; 1.000        ; 0.858      ; 1.185      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst23'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.291 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.500        ; 0.518      ; 0.839      ;
+; 0.784 ; inst24    ; inst24  ; inst24       ; inst23      ; 1.000        ; 0.518      ; 0.846      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst76'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.291 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.500        ; 0.697      ; 1.018      ;
+; 0.790 ; inst79    ; inst79  ; inst79       ; inst76      ; 1.000        ; 0.697      ; 1.019      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst35'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.292 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.500        ; 0.518      ; 0.838      ;
+; 0.786 ; inst36    ; inst36  ; inst36       ; inst35      ; 1.000        ; 0.518      ; 0.844      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst47'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.292 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.500        ; 0.518      ; 0.838      ;
+; 0.785 ; inst48    ; inst48  ; inst48       ; inst47      ; 1.000        ; 0.518      ; 0.845      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst67'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.296 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.500        ; 0.542      ; 0.858      ;
+; 0.788 ; inst68    ; inst68  ; inst68       ; inst67      ; 1.000        ; 0.542      ; 0.866      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst55'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.304 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.500        ; 0.531      ; 0.839      ;
+; 0.797 ; inst56    ; inst56  ; inst56       ; inst55      ; 1.000        ; 0.531      ; 0.846      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst31'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.311 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.500        ; 0.537      ; 0.838      ;
+; 0.805 ; inst32    ; inst32  ; inst32       ; inst31      ; 1.000        ; 0.537      ; 0.844      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst27'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.316 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.500        ; 0.541      ; 0.837      ;
+; 0.807 ; inst28    ; inst28  ; inst28       ; inst27      ; 1.000        ; 0.541      ; 0.846      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst59'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.324 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.500        ; 0.723      ; 1.011      ;
+; 0.821 ; inst60    ; inst60  ; inst60       ; inst59      ; 1.000        ; 0.723      ; 1.014      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst68'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.327 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.500        ; 0.476      ; 0.761      ;
+; 0.788 ; inst71    ; inst71  ; inst71       ; inst68      ; 1.000        ; 0.476      ; 0.800      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst71'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.328 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.500        ; 0.727      ; 1.011      ;
+; 0.823 ; inst72    ; inst72  ; inst72       ; inst71      ; 1.000        ; 0.727      ; 1.016      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst32'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.330 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.500        ; 0.463      ; 0.745      ;
+; 0.791 ; inst35    ; inst35  ; inst35       ; inst32      ; 1.000        ; 0.463      ; 0.784      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst36'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.330 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.500        ; 0.463      ; 0.745      ;
+; 0.791 ; inst39    ; inst39  ; inst39       ; inst36      ; 1.000        ; 0.463      ; 0.784      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst48'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.331 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.500        ; 0.468      ; 0.749      ;
+; 0.791 ; inst51    ; inst51  ; inst51       ; inst48      ; 1.000        ; 0.468      ; 0.789      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst44'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.335 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.500        ; 0.468      ; 0.745      ;
+; 0.796 ; inst47    ; inst47  ; inst47       ; inst44      ; 1.000        ; 0.468      ; 0.784      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst60'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.335 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.500        ; 0.468      ; 0.745      ;
+; 0.797 ; inst63    ; inst63  ; inst63       ; inst60      ; 1.000        ; 0.468      ; 0.783      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst24'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.336 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.500        ; 0.468      ; 0.744      ;
+; 0.797 ; inst27    ; inst27  ; inst27       ; inst24      ; 1.000        ; 0.468      ; 0.783      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst56'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.336 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.500        ; 0.468      ; 0.744      ;
+; 0.797 ; inst59    ; inst59  ; inst59       ; inst56      ; 1.000        ; 0.468      ; 0.783      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst64'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.343 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.500        ; 0.474      ; 0.743      ;
+; 0.804 ; inst67    ; inst67  ; inst67       ; inst64      ; 1.000        ; 0.474      ; 0.782      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst75'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.344 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.500        ; 0.475      ; 0.743      ;
+; 0.806 ; inst76    ; inst76  ; inst76       ; inst75      ; 1.000        ; 0.475      ; 0.781      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst63'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.364 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.500        ; 0.776      ; 1.024      ;
+; 0.857 ; inst64    ; inst64  ; inst64       ; inst63      ; 1.000        ; 0.776      ; 1.031      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst40'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.429 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.500        ; 0.464      ; 0.647      ;
+; 0.896 ; inst43    ; inst43  ; inst43       ; inst40      ; 1.000        ; 0.464      ; 0.680      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst52'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.435 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.500        ; 0.472      ; 0.649      ;
+; 0.916 ; inst55    ; inst55  ; inst55       ; inst52      ; 1.000        ; 0.472      ; 0.668      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst79'                                                              ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.624 ; inst80    ; inst80  ; inst79       ; inst79      ; 1.000        ; -0.024     ; 0.359      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst63'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.105 ; inst64    ; inst64  ; inst64       ; inst63      ; 0.000        ; 0.821      ; 0.905      ;
+; 0.380  ; inst64    ; inst64  ; inst64       ; inst63      ; -0.500       ; 0.821      ; 0.890      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst59'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.066 ; inst60    ; inst60  ; inst60       ; inst59      ; 0.000        ; 0.765      ; 0.888      ;
+; 0.425  ; inst60    ; inst60  ; inst60       ; inst59      ; -0.500       ; 0.765      ; 0.879      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst71'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.060 ; inst72    ; inst72  ; inst72       ; inst71      ; 0.000        ; 0.769      ; 0.898      ;
+; 0.418  ; inst72    ; inst72  ; inst72       ; inst71      ; -0.500       ; 0.769      ; 0.876      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst52'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.049 ; inst55    ; inst55  ; inst55       ; inst52      ; 0.000        ; 0.504      ; 0.644      ;
+; 0.434  ; inst55    ; inst55  ; inst55       ; inst52      ; -0.500       ; 0.504      ; 0.627      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst43'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.041 ; inst44    ; inst44  ; inst44       ; inst43      ; 0.000        ; 0.906      ; 1.054      ;
+; 0.442  ; inst44    ; inst44  ; inst44       ; inst43      ; -0.500       ; 0.906      ; 1.037      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst31'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.033 ; inst32    ; inst32  ; inst32       ; inst31      ; 0.000        ; 0.571      ; 0.727      ;
+; 0.448  ; inst32    ; inst32  ; inst32       ; inst31      ; -0.500       ; 0.571      ; 0.708      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst27'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.029 ; inst28    ; inst28  ; inst28       ; inst27      ; 0.000        ; 0.576      ; 0.736      ;
+; 0.441  ; inst28    ; inst28  ; inst28       ; inst27      ; -0.500       ; 0.576      ; 0.706      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst40'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.027 ; inst43    ; inst43  ; inst43       ; inst40      ; 0.000        ; 0.496      ; 0.658      ;
+; 0.440  ; inst43    ; inst43  ; inst43       ; inst40      ; -0.500       ; 0.496      ; 0.625      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst76'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.027 ; inst79    ; inst79  ; inst79       ; inst76      ; 0.000        ; 0.739      ; 0.901      ;
+; 0.454  ; inst79    ; inst79  ; inst79       ; inst76      ; -0.500       ; 0.739      ; 0.882      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'pin_name1'                                                             ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.021 ; inst23    ; inst23  ; inst23       ; pin_name1   ; 0.000        ; 1.391      ; 1.579      ;
+; 0.489  ; inst23    ; inst23  ; inst23       ; pin_name1   ; -0.500       ; 1.391      ; 1.589      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst55'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.018 ; inst56    ; inst56  ; inst56       ; inst55      ; 0.000        ; 0.565      ; 0.736      ;
+; 0.453  ; inst56    ; inst56  ; inst56       ; inst55      ; -0.500       ; 0.565      ; 0.707      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst67'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.018 ; inst68    ; inst68  ; inst68       ; inst67      ; 0.000        ; 0.577      ; 0.748      ;
+; 0.462  ; inst68    ; inst68  ; inst68       ; inst67      ; -0.500       ; 0.577      ; 0.728      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst35'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.014 ; inst36    ; inst36  ; inst36       ; inst35      ; 0.000        ; 0.552      ; 0.727      ;
+; 0.467  ; inst36    ; inst36  ; inst36       ; inst35      ; -0.500       ; 0.552      ; 0.708      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst51'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.009 ; inst52    ; inst52  ; inst52       ; inst51      ; 0.000        ; 0.693      ; 0.873      ;
+; 0.478  ; inst52    ; inst52  ; inst52       ; inst51      ; -0.500       ; 0.693      ; 0.860      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst47'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.007 ; inst48    ; inst48  ; inst48       ; inst47      ; 0.000        ; 0.552      ; 0.734      ;
+; 0.469  ; inst48    ; inst48  ; inst48       ; inst47      ; -0.500       ; 0.552      ; 0.710      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst23'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.005 ; inst24    ; inst24  ; inst24       ; inst23      ; 0.000        ; 0.552      ; 0.736      ;
+; 0.466  ; inst24    ; inst24  ; inst24       ; inst23      ; -0.500       ; 0.552      ; 0.707      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst39'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.005 ; inst40    ; inst40  ; inst40       ; inst39      ; 0.000        ; 0.552      ; 0.736      ;
+; 0.476  ; inst40    ; inst40  ; inst40       ; inst39      ; -0.500       ; 0.552      ; 0.717      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst72'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.003 ; inst75    ; inst75  ; inst75       ; inst72      ; 0.000        ; 0.551      ; 0.737      ;
+; 0.479  ; inst75    ; inst75  ; inst75       ; inst72      ; -0.500       ; 0.551      ; 0.719      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst75'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.017 ; inst76    ; inst76  ; inst76       ; inst75      ; 0.000        ; 0.507      ; 0.713      ;
+; 0.481 ; inst76    ; inst76  ; inst76       ; inst75      ; -0.500       ; 0.507      ; 0.677      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst24'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.018 ; inst27    ; inst27  ; inst27       ; inst24      ; 0.000        ; 0.499      ; 0.706      ;
+; 0.490 ; inst27    ; inst27  ; inst27       ; inst24      ; -0.500       ; 0.499      ; 0.678      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst56'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.018 ; inst59    ; inst59  ; inst59       ; inst56      ; 0.000        ; 0.499      ; 0.706      ;
+; 0.490 ; inst59    ; inst59  ; inst59       ; inst56      ; -0.500       ; 0.499      ; 0.678      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst64'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.018 ; inst67    ; inst67  ; inst67       ; inst64      ; 0.000        ; 0.506      ; 0.713      ;
+; 0.482 ; inst67    ; inst67  ; inst67       ; inst64      ; -0.500       ; 0.506      ; 0.677      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst48'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.024 ; inst51    ; inst51  ; inst51       ; inst48      ; 0.000        ; 0.499      ; 0.712      ;
+; 0.496 ; inst51    ; inst51  ; inst51       ; inst48      ; -0.500       ; 0.499      ; 0.684      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst60'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.026 ; inst63    ; inst63  ; inst63       ; inst60      ; 0.000        ; 0.500      ; 0.715      ;
+; 0.488 ; inst63    ; inst63  ; inst63       ; inst60      ; -0.500       ; 0.500      ; 0.677      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst68'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.026 ; inst71    ; inst71  ; inst71       ; inst68      ; 0.000        ; 0.508      ; 0.723      ;
+; 0.498 ; inst71    ; inst71  ; inst71       ; inst68      ; -0.500       ; 0.508      ; 0.695      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst44'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.028 ; inst47    ; inst47  ; inst47       ; inst44      ; 0.000        ; 0.499      ; 0.716      ;
+; 0.491 ; inst47    ; inst47  ; inst47       ; inst44      ; -0.500       ; 0.499      ; 0.679      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst32'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.033 ; inst35    ; inst35  ; inst35       ; inst32      ; 0.000        ; 0.494      ; 0.716      ;
+; 0.496 ; inst35    ; inst35  ; inst35       ; inst32      ; -0.500       ; 0.494      ; 0.679      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst36'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.033 ; inst39    ; inst39  ; inst39       ; inst36      ; 0.000        ; 0.494      ; 0.716      ;
+; 0.496 ; inst39    ; inst39  ; inst39       ; inst36      ; -0.500       ; 0.494      ; 0.679      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst28'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.046 ; inst31    ; inst31  ; inst31       ; inst28      ; 0.000        ; 0.502      ; 0.737      ;
+; 0.526 ; inst31    ; inst31  ; inst31       ; inst28      ; -0.500       ; 0.502      ; 0.717      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst79'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.206 ; inst80    ; inst80  ; inst79       ; inst79      ; 0.000        ; 0.024      ; 0.314      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'pin_name1'                                                                                            ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                      ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; pin_name1 ; Rise       ; pin_name1                                                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; pin_name1 ; Rise       ; inst23                                                      ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; pin_name1 ; Rise       ; pin_name1~input|i                                           ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; pin_name1 ; Rise       ; inst23                                                      ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|inclk[0] ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst|altclkctrl0_altclkctrl_uhi_component|clkctrl1|outclk   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; inst23|clk                                                  ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; pin_name1 ; Rise       ; pin_name1~input|o                                           ;
++--------+--------------+----------------+------------------+-----------+------------+-------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst23'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst23 ; Fall       ; inst24     ;
+; 0.240  ; 0.456        ; 0.216          ; High Pulse Width ; inst23 ; Fall       ; inst24     ;
+; 0.359  ; 0.543        ; 0.184          ; Low Pulse Width  ; inst23 ; Fall       ; inst24     ;
+; 0.461  ; 0.461        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst24|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst23|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst23 ; Rise       ; inst23|q   ;
+; 0.537  ; 0.537        ; 0.000          ; High Pulse Width ; inst23 ; Rise       ; inst24|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst24'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst24 ; Fall       ; inst27     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst24 ; Fall       ; inst27     ;
+; 0.369  ; 0.553        ; 0.184          ; Low Pulse Width  ; inst24 ; Fall       ; inst27     ;
+; 0.452  ; 0.452        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst27|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst24|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst24 ; Rise       ; inst24|q   ;
+; 0.547  ; 0.547        ; 0.000          ; High Pulse Width ; inst24 ; Rise       ; inst27|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst27'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst27 ; Fall       ; inst28     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst27 ; Fall       ; inst28     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst27 ; Fall       ; inst28     ;
+; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst28|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst27|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst27 ; Rise       ; inst27|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst27 ; Rise       ; inst28|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst28'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst28 ; Fall       ; inst31     ;
+; 0.230  ; 0.446        ; 0.216          ; High Pulse Width ; inst28 ; Fall       ; inst31     ;
+; 0.369  ; 0.553        ; 0.184          ; Low Pulse Width  ; inst28 ; Fall       ; inst31     ;
+; 0.451  ; 0.451        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst31|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst28|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst28 ; Rise       ; inst28|q   ;
+; 0.547  ; 0.547        ; 0.000          ; High Pulse Width ; inst28 ; Rise       ; inst31|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst31'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst31 ; Fall       ; inst32     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst31 ; Fall       ; inst32     ;
+; 0.366  ; 0.550        ; 0.184          ; Low Pulse Width  ; inst31 ; Fall       ; inst32     ;
+; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst32|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst31|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst31 ; Rise       ; inst31|q   ;
+; 0.544  ; 0.544        ; 0.000          ; High Pulse Width ; inst31 ; Rise       ; inst32|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst32'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst32 ; Fall       ; inst35     ;
+; 0.235  ; 0.451        ; 0.216          ; High Pulse Width ; inst32 ; Fall       ; inst35     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst32 ; Fall       ; inst35     ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst35|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst32|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst32 ; Rise       ; inst32|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst32 ; Rise       ; inst35|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst35'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst35 ; Fall       ; inst36     ;
+; 0.240  ; 0.456        ; 0.216          ; High Pulse Width ; inst35 ; Fall       ; inst36     ;
+; 0.359  ; 0.543        ; 0.184          ; Low Pulse Width  ; inst35 ; Fall       ; inst36     ;
+; 0.461  ; 0.461        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst36|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst35|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst35 ; Rise       ; inst35|q   ;
+; 0.537  ; 0.537        ; 0.000          ; High Pulse Width ; inst35 ; Rise       ; inst36|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst36'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst36 ; Fall       ; inst39     ;
+; 0.235  ; 0.451        ; 0.216          ; High Pulse Width ; inst36 ; Fall       ; inst39     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst36 ; Fall       ; inst39     ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst39|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst36|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst36 ; Rise       ; inst36|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst36 ; Rise       ; inst39|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst39'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst39 ; Fall       ; inst40     ;
+; 0.240  ; 0.456        ; 0.216          ; High Pulse Width ; inst39 ; Fall       ; inst40     ;
+; 0.359  ; 0.543        ; 0.184          ; Low Pulse Width  ; inst39 ; Fall       ; inst40     ;
+; 0.461  ; 0.461        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst40|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst39|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst39 ; Rise       ; inst39|q   ;
+; 0.537  ; 0.537        ; 0.000          ; High Pulse Width ; inst39 ; Rise       ; inst40|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst40'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst40 ; Fall       ; inst43     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst40 ; Fall       ; inst43     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst40 ; Fall       ; inst43     ;
+; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst43|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst40|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst40 ; Rise       ; inst40|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst40 ; Rise       ; inst43|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst43'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst43 ; Fall       ; inst44     ;
+; 0.193  ; 0.409        ; 0.216          ; High Pulse Width ; inst43 ; Fall       ; inst44     ;
+; 0.405  ; 0.589        ; 0.184          ; Low Pulse Width  ; inst43 ; Fall       ; inst44     ;
+; 0.414  ; 0.414        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst44|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst43|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst43 ; Rise       ; inst43|q   ;
+; 0.583  ; 0.583        ; 0.000          ; High Pulse Width ; inst43 ; Rise       ; inst44|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst44'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst44 ; Fall       ; inst47     ;
+; 0.237  ; 0.453        ; 0.216          ; High Pulse Width ; inst44 ; Fall       ; inst47     ;
+; 0.363  ; 0.547        ; 0.184          ; Low Pulse Width  ; inst44 ; Fall       ; inst47     ;
+; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst47|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst44|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst44 ; Rise       ; inst44|q   ;
+; 0.541  ; 0.541        ; 0.000          ; High Pulse Width ; inst44 ; Rise       ; inst47|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst47'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst47 ; Fall       ; inst48     ;
+; 0.240  ; 0.456        ; 0.216          ; High Pulse Width ; inst47 ; Fall       ; inst48     ;
+; 0.359  ; 0.543        ; 0.184          ; Low Pulse Width  ; inst47 ; Fall       ; inst48     ;
+; 0.461  ; 0.461        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst48|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst47|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst47 ; Rise       ; inst47|q   ;
+; 0.537  ; 0.537        ; 0.000          ; High Pulse Width ; inst47 ; Rise       ; inst48|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst48'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst48 ; Fall       ; inst51     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst48 ; Fall       ; inst51     ;
+; 0.369  ; 0.553        ; 0.184          ; Low Pulse Width  ; inst48 ; Fall       ; inst51     ;
+; 0.452  ; 0.452        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst51|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst48|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst48 ; Rise       ; inst48|q   ;
+; 0.547  ; 0.547        ; 0.000          ; High Pulse Width ; inst48 ; Rise       ; inst51|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst51'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst51 ; Fall       ; inst52     ;
+; 0.228  ; 0.444        ; 0.216          ; High Pulse Width ; inst51 ; Fall       ; inst52     ;
+; 0.372  ; 0.556        ; 0.184          ; Low Pulse Width  ; inst51 ; Fall       ; inst52     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst52|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst51|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst51 ; Rise       ; inst51|q   ;
+; 0.550  ; 0.550        ; 0.000          ; High Pulse Width ; inst51 ; Rise       ; inst52|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst52'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst52 ; Fall       ; inst55     ;
+; 0.233  ; 0.449        ; 0.216          ; High Pulse Width ; inst52 ; Fall       ; inst55     ;
+; 0.366  ; 0.550        ; 0.184          ; Low Pulse Width  ; inst52 ; Fall       ; inst55     ;
+; 0.454  ; 0.454        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst55|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst52|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst52 ; Rise       ; inst52|q   ;
+; 0.544  ; 0.544        ; 0.000          ; High Pulse Width ; inst52 ; Rise       ; inst55|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst55'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst55 ; Fall       ; inst56     ;
+; 0.237  ; 0.453        ; 0.216          ; High Pulse Width ; inst55 ; Fall       ; inst56     ;
+; 0.362  ; 0.546        ; 0.184          ; Low Pulse Width  ; inst55 ; Fall       ; inst56     ;
+; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst56|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst55|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst55 ; Rise       ; inst55|q   ;
+; 0.540  ; 0.540        ; 0.000          ; High Pulse Width ; inst55 ; Rise       ; inst56|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst56'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst56 ; Fall       ; inst59     ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; inst56 ; Fall       ; inst59     ;
+; 0.369  ; 0.553        ; 0.184          ; Low Pulse Width  ; inst56 ; Fall       ; inst59     ;
+; 0.452  ; 0.452        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst59|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst56|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst56 ; Rise       ; inst56|q   ;
+; 0.547  ; 0.547        ; 0.000          ; High Pulse Width ; inst56 ; Rise       ; inst59|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst59'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst59 ; Fall       ; inst60     ;
+; 0.212  ; 0.428        ; 0.216          ; High Pulse Width ; inst59 ; Fall       ; inst60     ;
+; 0.387  ; 0.571        ; 0.184          ; Low Pulse Width  ; inst59 ; Fall       ; inst60     ;
+; 0.433  ; 0.433        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst60|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst59|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst59 ; Rise       ; inst59|q   ;
+; 0.565  ; 0.565        ; 0.000          ; High Pulse Width ; inst59 ; Rise       ; inst60|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst60'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst60 ; Fall       ; inst63     ;
+; 0.237  ; 0.453        ; 0.216          ; High Pulse Width ; inst60 ; Fall       ; inst63     ;
+; 0.362  ; 0.546        ; 0.184          ; Low Pulse Width  ; inst60 ; Fall       ; inst63     ;
+; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst63|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst60|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst60 ; Rise       ; inst60|q   ;
+; 0.540  ; 0.540        ; 0.000          ; High Pulse Width ; inst60 ; Rise       ; inst63|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst63'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst63 ; Fall       ; inst64     ;
+; 0.208  ; 0.424        ; 0.216          ; High Pulse Width ; inst63 ; Fall       ; inst64     ;
+; 0.389  ; 0.573        ; 0.184          ; Low Pulse Width  ; inst63 ; Fall       ; inst64     ;
+; 0.429  ; 0.429        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst64|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst63|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst63 ; Rise       ; inst63|q   ;
+; 0.567  ; 0.567        ; 0.000          ; High Pulse Width ; inst63 ; Rise       ; inst64|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst64'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst64 ; Fall       ; inst67     ;
+; 0.232  ; 0.448        ; 0.216          ; High Pulse Width ; inst64 ; Fall       ; inst67     ;
+; 0.367  ; 0.551        ; 0.184          ; Low Pulse Width  ; inst64 ; Fall       ; inst67     ;
+; 0.453  ; 0.453        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst67|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst64|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst64 ; Rise       ; inst64|q   ;
+; 0.545  ; 0.545        ; 0.000          ; High Pulse Width ; inst64 ; Rise       ; inst67|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst67'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst67 ; Fall       ; inst68     ;
+; 0.232  ; 0.448        ; 0.216          ; High Pulse Width ; inst67 ; Fall       ; inst68     ;
+; 0.367  ; 0.551        ; 0.184          ; Low Pulse Width  ; inst67 ; Fall       ; inst68     ;
+; 0.453  ; 0.453        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst68|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst67|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst67 ; Rise       ; inst67|q   ;
+; 0.545  ; 0.545        ; 0.000          ; High Pulse Width ; inst67 ; Rise       ; inst68|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst68'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst68 ; Fall       ; inst71     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst68 ; Fall       ; inst71     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst68 ; Fall       ; inst71     ;
+; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst71|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst68|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst68 ; Rise       ; inst68|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst68 ; Rise       ; inst71|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst71'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst71 ; Fall       ; inst72     ;
+; 0.207  ; 0.423        ; 0.216          ; High Pulse Width ; inst71 ; Fall       ; inst72     ;
+; 0.391  ; 0.575        ; 0.184          ; Low Pulse Width  ; inst71 ; Fall       ; inst72     ;
+; 0.428  ; 0.428        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst72|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst71|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst71 ; Rise       ; inst71|q   ;
+; 0.569  ; 0.569        ; 0.000          ; High Pulse Width ; inst71 ; Rise       ; inst72|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst72'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst72 ; Fall       ; inst75     ;
+; 0.235  ; 0.451        ; 0.216          ; High Pulse Width ; inst72 ; Fall       ; inst75     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst72 ; Fall       ; inst75     ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst75|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst72|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst72 ; Rise       ; inst72|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst72 ; Rise       ; inst75|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst75'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst75 ; Fall       ; inst76     ;
+; 0.234  ; 0.450        ; 0.216          ; High Pulse Width ; inst75 ; Fall       ; inst76     ;
+; 0.365  ; 0.549        ; 0.184          ; Low Pulse Width  ; inst75 ; Fall       ; inst76     ;
+; 0.455  ; 0.455        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst76|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst75|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst75 ; Rise       ; inst75|q   ;
+; 0.543  ; 0.543        ; 0.000          ; High Pulse Width ; inst75 ; Rise       ; inst76|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst76'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst76 ; Fall       ; inst79     ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; inst76 ; Fall       ; inst79     ;
+; 0.381  ; 0.565        ; 0.184          ; Low Pulse Width  ; inst76 ; Fall       ; inst79     ;
+; 0.438  ; 0.438        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst79|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst76|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst76 ; Rise       ; inst76|q   ;
+; 0.559  ; 0.559        ; 0.000          ; High Pulse Width ; inst76 ; Rise       ; inst79|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst79'                                           ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target     ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; inst79 ; Fall       ; inst80     ;
+; 0.237  ; 0.453        ; 0.216          ; High Pulse Width ; inst79 ; Fall       ; inst80     ;
+; 0.362  ; 0.546        ; 0.184          ; Low Pulse Width  ; inst79 ; Fall       ; inst80     ;
+; 0.458  ; 0.458        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst80|clk ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst79|q   ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; inst79 ; Rise       ; inst79|q   ;
+; 0.540  ; 0.540        ; 0.000          ; High Pulse Width ; inst79 ; Rise       ; inst80|clk ;
++--------+--------------+----------------+------------------+--------+------------+------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 2.117 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 2.117 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 2.194 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 2.194 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 1.870 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 1.870 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 1.922 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 1.922 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 2.713 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 2.713 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 2.914 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 2.914 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 1.817 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 1.817 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 1.865 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 1.865 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 1.877 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 1.877 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 1.924 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 1.924 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 1.761 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 1.761 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 1.795 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 1.795 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 1.878 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 1.878 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 1.926 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 1.926 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 1.944 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 1.944 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 1.996 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 1.996 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 1.709 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 1.709 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 2.296 ; 2.319 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 1.733 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 2.296 ; 2.319 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 2.091 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 2.091 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 2.164 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 2.164 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 1.854 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 1.854 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 1.903 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 1.903 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 2.696 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 2.696 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 2.894 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 2.894 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 1.803 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 1.803 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 1.849 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 1.849 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 1.861 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 1.861 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 1.906 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 1.906 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 1.750 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 1.750 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 1.782 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 1.782 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 1.862 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 1.862 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 1.908 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 1.908 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 1.927 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 1.927 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 1.975 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 1.975 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 1.701 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 1.701 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 2.256 ; 1.723 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 1.723 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 2.256 ; 2.278 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+--------+--------+----------+---------+---------------------+
+; Clock            ; Setup  ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+--------+--------+----------+---------+---------------------+
+; Worst-case Slack ; -0.011 ; -0.105 ; N/A      ; N/A     ; -3.000              ;
+;  inst23          ; 0.090  ; -0.005 ; N/A      ; N/A     ; -1.000              ;
+;  inst24          ; 0.144  ; 0.018  ; N/A      ; N/A     ; -1.000              ;
+;  inst27          ; 0.129  ; -0.029 ; N/A      ; N/A     ; -1.000              ;
+;  inst28          ; -0.011 ; 0.046  ; N/A      ; N/A     ; -1.000              ;
+;  inst31          ; 0.128  ; -0.033 ; N/A      ; N/A     ; -1.000              ;
+;  inst32          ; 0.134  ; 0.033  ; N/A      ; N/A     ; -1.000              ;
+;  inst35          ; 0.094  ; -0.014 ; N/A      ; N/A     ; -1.000              ;
+;  inst36          ; 0.134  ; 0.033  ; N/A      ; N/A     ; -1.000              ;
+;  inst39          ; 0.086  ; -0.005 ; N/A      ; N/A     ; -1.000              ;
+;  inst40          ; 0.298  ; -0.027 ; N/A      ; N/A     ; -1.000              ;
+;  inst43          ; 0.010  ; -0.041 ; N/A      ; N/A     ; -1.000              ;
+;  inst44          ; 0.143  ; 0.028  ; N/A      ; N/A     ; -1.000              ;
+;  inst47          ; 0.089  ; -0.007 ; N/A      ; N/A     ; -1.000              ;
+;  inst48          ; 0.139  ; 0.024  ; N/A      ; N/A     ; -1.000              ;
+;  inst51          ; 0.032  ; -0.009 ; N/A      ; N/A     ; -1.000              ;
+;  inst52          ; 0.325  ; -0.049 ; N/A      ; N/A     ; -1.000              ;
+;  inst55          ; 0.112  ; -0.018 ; N/A      ; N/A     ; -1.000              ;
+;  inst56          ; 0.144  ; 0.018  ; N/A      ; N/A     ; -1.000              ;
+;  inst59          ; 0.080  ; -0.066 ; N/A      ; N/A     ; -1.000              ;
+;  inst60          ; 0.142  ; 0.026  ; N/A      ; N/A     ; -1.000              ;
+;  inst63          ; 0.176  ; -0.105 ; N/A      ; N/A     ; -1.000              ;
+;  inst64          ; 0.152  ; 0.018  ; N/A      ; N/A     ; -1.000              ;
+;  inst67          ; 0.108  ; -0.018 ; N/A      ; N/A     ; -1.000              ;
+;  inst68          ; 0.130  ; 0.026  ; N/A      ; N/A     ; -1.000              ;
+;  inst71          ; 0.097  ; -0.060 ; N/A      ; N/A     ; -1.000              ;
+;  inst72          ; 0.070  ; -0.003 ; N/A      ; N/A     ; -1.000              ;
+;  inst75          ; 0.154  ; 0.017  ; N/A      ; N/A     ; -1.000              ;
+;  inst76          ; 0.047  ; -0.027 ; N/A      ; N/A     ; -1.000              ;
+;  inst79          ; 0.317  ; 0.206  ; N/A      ; N/A     ; -1.000              ;
+;  pin_name1       ; 0.030  ; -0.022 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -0.011 ; -0.537 ; 0.0      ; 0.0     ; -33.056             ;
+;  inst23          ; 0.000  ; -0.005 ; N/A      ; N/A     ; -1.000              ;
+;  inst24          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst27          ; 0.000  ; -0.029 ; N/A      ; N/A     ; -1.000              ;
+;  inst28          ; -0.011 ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst31          ; 0.000  ; -0.033 ; N/A      ; N/A     ; -1.000              ;
+;  inst32          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst35          ; 0.000  ; -0.014 ; N/A      ; N/A     ; -1.000              ;
+;  inst36          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst39          ; 0.000  ; -0.005 ; N/A      ; N/A     ; -1.000              ;
+;  inst40          ; 0.000  ; -0.027 ; N/A      ; N/A     ; -1.000              ;
+;  inst43          ; 0.000  ; -0.041 ; N/A      ; N/A     ; -1.000              ;
+;  inst44          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst47          ; 0.000  ; -0.007 ; N/A      ; N/A     ; -1.000              ;
+;  inst48          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst51          ; 0.000  ; -0.009 ; N/A      ; N/A     ; -1.000              ;
+;  inst52          ; 0.000  ; -0.049 ; N/A      ; N/A     ; -1.000              ;
+;  inst55          ; 0.000  ; -0.018 ; N/A      ; N/A     ; -1.000              ;
+;  inst56          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst59          ; 0.000  ; -0.066 ; N/A      ; N/A     ; -1.000              ;
+;  inst60          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst63          ; 0.000  ; -0.105 ; N/A      ; N/A     ; -1.000              ;
+;  inst64          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst67          ; 0.000  ; -0.018 ; N/A      ; N/A     ; -1.000              ;
+;  inst68          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst71          ; 0.000  ; -0.060 ; N/A      ; N/A     ; -1.000              ;
+;  inst72          ; 0.000  ; -0.003 ; N/A      ; N/A     ; -1.000              ;
+;  inst75          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  inst76          ; 0.000  ; -0.027 ; N/A      ; N/A     ; -1.000              ;
+;  inst79          ; 0.000  ; 0.000  ; N/A      ; N/A     ; -1.000              ;
+;  pin_name1       ; 0.000  ; -0.022 ; N/A      ; N/A     ; -4.056              ;
++------------------+--------+--------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 3.445 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 3.445 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 3.447 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 3.447 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 2.983 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 2.983 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 3.009 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 3.009 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 4.251 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 4.251 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 4.384 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 4.384 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 2.876 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 2.876 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 2.913 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 2.913 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 2.957 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 2.957 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 2.996 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 2.996 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 2.779 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 2.779 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 2.808 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 2.808 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 2.951 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 2.951 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 2.994 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 2.994 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 3.081 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 3.081 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 3.104 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 3.104 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 2.657 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 2.657 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 3.701 ; 3.735 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 2.692 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 3.701 ; 3.735 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; LEDOUT[*]  ; inst63     ; 2.091 ;       ; Rise       ; inst63          ;
+;  LEDOUT[0] ; inst63     ; 2.091 ;       ; Rise       ; inst63          ;
+; LEDOUT[*]  ; inst63     ;       ; 2.164 ; Fall       ; inst63          ;
+;  LEDOUT[0] ; inst63     ;       ; 2.164 ; Fall       ; inst63          ;
+; LEDOUT[*]  ; inst64     ; 1.854 ;       ; Rise       ; inst64          ;
+;  LEDOUT[1] ; inst64     ; 1.854 ;       ; Rise       ; inst64          ;
+; LEDOUT[*]  ; inst64     ;       ; 1.903 ; Fall       ; inst64          ;
+;  LEDOUT[1] ; inst64     ;       ; 1.903 ; Fall       ; inst64          ;
+; LEDOUT[*]  ; inst67     ; 2.696 ;       ; Rise       ; inst67          ;
+;  LEDOUT[2] ; inst67     ; 2.696 ;       ; Rise       ; inst67          ;
+; LEDOUT[*]  ; inst67     ;       ; 2.894 ; Fall       ; inst67          ;
+;  LEDOUT[2] ; inst67     ;       ; 2.894 ; Fall       ; inst67          ;
+; LEDOUT[*]  ; inst68     ; 1.803 ;       ; Rise       ; inst68          ;
+;  LEDOUT[3] ; inst68     ; 1.803 ;       ; Rise       ; inst68          ;
+; LEDOUT[*]  ; inst68     ;       ; 1.849 ; Fall       ; inst68          ;
+;  LEDOUT[3] ; inst68     ;       ; 1.849 ; Fall       ; inst68          ;
+; LEDOUT[*]  ; inst71     ; 1.861 ;       ; Rise       ; inst71          ;
+;  LEDOUT[4] ; inst71     ; 1.861 ;       ; Rise       ; inst71          ;
+; LEDOUT[*]  ; inst71     ;       ; 1.906 ; Fall       ; inst71          ;
+;  LEDOUT[4] ; inst71     ;       ; 1.906 ; Fall       ; inst71          ;
+; LEDOUT[*]  ; inst72     ; 1.750 ;       ; Rise       ; inst72          ;
+;  LEDOUT[5] ; inst72     ; 1.750 ;       ; Rise       ; inst72          ;
+; LEDOUT[*]  ; inst72     ;       ; 1.782 ; Fall       ; inst72          ;
+;  LEDOUT[5] ; inst72     ;       ; 1.782 ; Fall       ; inst72          ;
+; LEDOUT[*]  ; inst75     ; 1.862 ;       ; Rise       ; inst75          ;
+;  LEDOUT[6] ; inst75     ; 1.862 ;       ; Rise       ; inst75          ;
+; LEDOUT[*]  ; inst75     ;       ; 1.908 ; Fall       ; inst75          ;
+;  LEDOUT[6] ; inst75     ;       ; 1.908 ; Fall       ; inst75          ;
+; LEDOUT[*]  ; inst76     ; 1.927 ;       ; Rise       ; inst76          ;
+;  LEDOUT[7] ; inst76     ; 1.927 ;       ; Rise       ; inst76          ;
+; LEDOUT[*]  ; inst76     ;       ; 1.975 ; Fall       ; inst76          ;
+;  LEDOUT[7] ; inst76     ;       ; 1.975 ; Fall       ; inst76          ;
+; LEDOUT[*]  ; inst79     ; 1.701 ;       ; Rise       ; inst79          ;
+;  LEDOUT[8] ; inst79     ; 1.701 ;       ; Rise       ; inst79          ;
+; LEDOUT[*]  ; inst79     ; 2.256 ; 1.723 ; Fall       ; inst79          ;
+;  LEDOUT[8] ; inst79     ;       ; 1.723 ; Fall       ; inst79          ;
+;  LEDOUT[9] ; inst79     ; 2.256 ; 2.278 ; Fall       ; inst79          ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; LEDOUT[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDOUT[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; pin_name1               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; LEDOUT[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; LEDOUT[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; LEDOUT[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; LEDOUT[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; LEDOUT[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------+
+; Setup Transfers                                                    ;
++------------+-----------+----------+----------+----------+----------+
+; From Clock ; To Clock  ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------+----------+----------+----------+----------+
+; inst24     ; inst23    ; 0        ; 0        ; 1        ; 1        ;
+; inst27     ; inst24    ; 0        ; 0        ; 1        ; 1        ;
+; inst28     ; inst27    ; 0        ; 0        ; 1        ; 1        ;
+; inst31     ; inst28    ; 0        ; 0        ; 1        ; 1        ;
+; inst32     ; inst31    ; 0        ; 0        ; 1        ; 1        ;
+; inst35     ; inst32    ; 0        ; 0        ; 1        ; 1        ;
+; inst36     ; inst35    ; 0        ; 0        ; 1        ; 1        ;
+; inst39     ; inst36    ; 0        ; 0        ; 1        ; 1        ;
+; inst40     ; inst39    ; 0        ; 0        ; 1        ; 1        ;
+; inst43     ; inst40    ; 0        ; 0        ; 1        ; 1        ;
+; inst44     ; inst43    ; 0        ; 0        ; 1        ; 1        ;
+; inst47     ; inst44    ; 0        ; 0        ; 1        ; 1        ;
+; inst48     ; inst47    ; 0        ; 0        ; 1        ; 1        ;
+; inst51     ; inst48    ; 0        ; 0        ; 1        ; 1        ;
+; inst52     ; inst51    ; 0        ; 0        ; 1        ; 1        ;
+; inst55     ; inst52    ; 0        ; 0        ; 1        ; 1        ;
+; inst56     ; inst55    ; 0        ; 0        ; 1        ; 1        ;
+; inst59     ; inst56    ; 0        ; 0        ; 1        ; 1        ;
+; inst60     ; inst59    ; 0        ; 0        ; 1        ; 1        ;
+; inst63     ; inst60    ; 0        ; 0        ; 1        ; 1        ;
+; inst64     ; inst63    ; 0        ; 0        ; 1        ; 1        ;
+; inst67     ; inst64    ; 0        ; 0        ; 1        ; 1        ;
+; inst68     ; inst67    ; 0        ; 0        ; 1        ; 1        ;
+; inst71     ; inst68    ; 0        ; 0        ; 1        ; 1        ;
+; inst72     ; inst71    ; 0        ; 0        ; 1        ; 1        ;
+; inst75     ; inst72    ; 0        ; 0        ; 1        ; 1        ;
+; inst76     ; inst75    ; 0        ; 0        ; 1        ; 1        ;
+; inst79     ; inst76    ; 0        ; 0        ; 1        ; 1        ;
+; inst79     ; inst79    ; 0        ; 0        ; 0        ; 1        ;
+; inst23     ; pin_name1 ; 1        ; 1        ; 0        ; 0        ;
++------------+-----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------+
+; Hold Transfers                                                     ;
++------------+-----------+----------+----------+----------+----------+
+; From Clock ; To Clock  ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------+----------+----------+----------+----------+
+; inst24     ; inst23    ; 0        ; 0        ; 1        ; 1        ;
+; inst27     ; inst24    ; 0        ; 0        ; 1        ; 1        ;
+; inst28     ; inst27    ; 0        ; 0        ; 1        ; 1        ;
+; inst31     ; inst28    ; 0        ; 0        ; 1        ; 1        ;
+; inst32     ; inst31    ; 0        ; 0        ; 1        ; 1        ;
+; inst35     ; inst32    ; 0        ; 0        ; 1        ; 1        ;
+; inst36     ; inst35    ; 0        ; 0        ; 1        ; 1        ;
+; inst39     ; inst36    ; 0        ; 0        ; 1        ; 1        ;
+; inst40     ; inst39    ; 0        ; 0        ; 1        ; 1        ;
+; inst43     ; inst40    ; 0        ; 0        ; 1        ; 1        ;
+; inst44     ; inst43    ; 0        ; 0        ; 1        ; 1        ;
+; inst47     ; inst44    ; 0        ; 0        ; 1        ; 1        ;
+; inst48     ; inst47    ; 0        ; 0        ; 1        ; 1        ;
+; inst51     ; inst48    ; 0        ; 0        ; 1        ; 1        ;
+; inst52     ; inst51    ; 0        ; 0        ; 1        ; 1        ;
+; inst55     ; inst52    ; 0        ; 0        ; 1        ; 1        ;
+; inst56     ; inst55    ; 0        ; 0        ; 1        ; 1        ;
+; inst59     ; inst56    ; 0        ; 0        ; 1        ; 1        ;
+; inst60     ; inst59    ; 0        ; 0        ; 1        ; 1        ;
+; inst63     ; inst60    ; 0        ; 0        ; 1        ; 1        ;
+; inst64     ; inst63    ; 0        ; 0        ; 1        ; 1        ;
+; inst67     ; inst64    ; 0        ; 0        ; 1        ; 1        ;
+; inst68     ; inst67    ; 0        ; 0        ; 1        ; 1        ;
+; inst71     ; inst68    ; 0        ; 0        ; 1        ; 1        ;
+; inst72     ; inst71    ; 0        ; 0        ; 1        ; 1        ;
+; inst75     ; inst72    ; 0        ; 0        ; 1        ; 1        ;
+; inst76     ; inst75    ; 0        ; 0        ; 1        ; 1        ;
+; inst79     ; inst76    ; 0        ; 0        ; 1        ; 1        ;
+; inst79     ; inst79    ; 0        ; 0        ; 0        ; 1        ;
+; inst23     ; pin_name1 ; 1        ; 1        ; 0        ; 0        ;
++------------+-----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 0     ; 0    ;
+; Unconstrained Input Port Paths  ; 0     ; 0    ;
+; Unconstrained Output Ports      ; 10    ; 10   ;
+; Unconstrained Output Port Paths ; 10    ; 10   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 21:05:06 2016
+Info: Command: quartus_sta blinken_Lights -c blinken_Lights
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'blinken_Lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name inst79 inst79
+    Info (332105): create_clock -period 1.000 -name inst76 inst76
+    Info (332105): create_clock -period 1.000 -name inst75 inst75
+    Info (332105): create_clock -period 1.000 -name inst72 inst72
+    Info (332105): create_clock -period 1.000 -name inst71 inst71
+    Info (332105): create_clock -period 1.000 -name inst68 inst68
+    Info (332105): create_clock -period 1.000 -name inst67 inst67
+    Info (332105): create_clock -period 1.000 -name inst64 inst64
+    Info (332105): create_clock -period 1.000 -name inst63 inst63
+    Info (332105): create_clock -period 1.000 -name inst60 inst60
+    Info (332105): create_clock -period 1.000 -name inst59 inst59
+    Info (332105): create_clock -period 1.000 -name inst56 inst56
+    Info (332105): create_clock -period 1.000 -name inst55 inst55
+    Info (332105): create_clock -period 1.000 -name inst52 inst52
+    Info (332105): create_clock -period 1.000 -name inst51 inst51
+    Info (332105): create_clock -period 1.000 -name inst48 inst48
+    Info (332105): create_clock -period 1.000 -name inst47 inst47
+    Info (332105): create_clock -period 1.000 -name inst44 inst44
+    Info (332105): create_clock -period 1.000 -name inst43 inst43
+    Info (332105): create_clock -period 1.000 -name inst40 inst40
+    Info (332105): create_clock -period 1.000 -name inst39 inst39
+    Info (332105): create_clock -period 1.000 -name inst36 inst36
+    Info (332105): create_clock -period 1.000 -name inst35 inst35
+    Info (332105): create_clock -period 1.000 -name inst32 inst32
+    Info (332105): create_clock -period 1.000 -name inst31 inst31
+    Info (332105): create_clock -period 1.000 -name inst28 inst28
+    Info (332105): create_clock -period 1.000 -name inst27 inst27
+    Info (332105): create_clock -period 1.000 -name inst24 inst24
+    Info (332105): create_clock -period 1.000 -name inst23 inst23
+    Info (332105): create_clock -period 1.000 -name pin_name1 pin_name1
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.011
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.011              -0.011 inst28 
+    Info (332119):     0.010               0.000 inst43 
+    Info (332119):     0.030               0.000 pin_name1 
+    Info (332119):     0.032               0.000 inst51 
+    Info (332119):     0.047               0.000 inst76 
+    Info (332119):     0.070               0.000 inst72 
+    Info (332119):     0.080               0.000 inst59 
+    Info (332119):     0.086               0.000 inst39 
+    Info (332119):     0.089               0.000 inst47 
+    Info (332119):     0.090               0.000 inst23 
+    Info (332119):     0.094               0.000 inst35 
+    Info (332119):     0.097               0.000 inst71 
+    Info (332119):     0.108               0.000 inst67 
+    Info (332119):     0.112               0.000 inst55 
+    Info (332119):     0.128               0.000 inst31 
+    Info (332119):     0.129               0.000 inst27 
+    Info (332119):     0.130               0.000 inst68 
+    Info (332119):     0.134               0.000 inst32 
+    Info (332119):     0.134               0.000 inst36 
+    Info (332119):     0.139               0.000 inst48 
+    Info (332119):     0.142               0.000 inst60 
+    Info (332119):     0.143               0.000 inst44 
+    Info (332119):     0.144               0.000 inst24 
+    Info (332119):     0.144               0.000 inst56 
+    Info (332119):     0.152               0.000 inst64 
+    Info (332119):     0.154               0.000 inst75 
+    Info (332119):     0.176               0.000 inst63 
+    Info (332119):     0.298               0.000 inst40 
+    Info (332119):     0.317               0.000 inst79 
+    Info (332119):     0.325               0.000 inst52 
+Info (332146): Worst-case hold slack is -0.088
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.088              -0.088 inst63 
+    Info (332119):    -0.026              -0.026 inst52 
+    Info (332119):    -0.017              -0.017 inst31 
+    Info (332119):    -0.006              -0.006 inst27 
+    Info (332119):    -0.002              -0.002 inst71 
+    Info (332119):     0.001               0.000 inst59 
+    Info (332119):     0.002               0.000 inst67 
+    Info (332119):     0.006               0.000 inst40 
+    Info (332119):     0.009               0.000 inst55 
+    Info (332119):     0.013               0.000 pin_name1 
+    Info (332119):     0.019               0.000 inst35 
+    Info (332119):     0.028               0.000 inst39 
+    Info (332119):     0.029               0.000 inst47 
+    Info (332119):     0.032               0.000 inst23 
+    Info (332119):     0.040               0.000 inst72 
+    Info (332119):     0.045               0.000 inst76 
+    Info (332119):     0.052               0.000 inst43 
+    Info (332119):     0.052               0.000 inst51 
+    Info (332119):     0.084               0.000 inst75 
+    Info (332119):     0.086               0.000 inst24 
+    Info (332119):     0.086               0.000 inst56 
+    Info (332119):     0.088               0.000 inst64 
+    Info (332119):     0.092               0.000 inst48 
+    Info (332119):     0.097               0.000 inst44 
+    Info (332119):     0.097               0.000 inst60 
+    Info (332119):     0.101               0.000 inst68 
+    Info (332119):     0.106               0.000 inst32 
+    Info (332119):     0.106               0.000 inst36 
+    Info (332119):     0.127               0.000 inst28 
+    Info (332119):     0.384               0.000 inst79 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000              -4.000 pin_name1 
+    Info (332119):    -1.000              -1.000 inst23 
+    Info (332119):    -1.000              -1.000 inst24 
+    Info (332119):    -1.000              -1.000 inst27 
+    Info (332119):    -1.000              -1.000 inst28 
+    Info (332119):    -1.000              -1.000 inst31 
+    Info (332119):    -1.000              -1.000 inst32 
+    Info (332119):    -1.000              -1.000 inst35 
+    Info (332119):    -1.000              -1.000 inst36 
+    Info (332119):    -1.000              -1.000 inst39 
+    Info (332119):    -1.000              -1.000 inst40 
+    Info (332119):    -1.000              -1.000 inst43 
+    Info (332119):    -1.000              -1.000 inst44 
+    Info (332119):    -1.000              -1.000 inst47 
+    Info (332119):    -1.000              -1.000 inst48 
+    Info (332119):    -1.000              -1.000 inst51 
+    Info (332119):    -1.000              -1.000 inst52 
+    Info (332119):    -1.000              -1.000 inst55 
+    Info (332119):    -1.000              -1.000 inst56 
+    Info (332119):    -1.000              -1.000 inst59 
+    Info (332119):    -1.000              -1.000 inst60 
+    Info (332119):    -1.000              -1.000 inst63 
+    Info (332119):    -1.000              -1.000 inst64 
+    Info (332119):    -1.000              -1.000 inst67 
+    Info (332119):    -1.000              -1.000 inst68 
+    Info (332119):    -1.000              -1.000 inst71 
+    Info (332119):    -1.000              -1.000 inst72 
+    Info (332119):    -1.000              -1.000 inst75 
+    Info (332119):    -1.000              -1.000 inst76 
+    Info (332119):    -1.000              -1.000 inst79 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 0.051
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.051               0.000 inst43 
+    Info (332119):     0.052               0.000 inst28 
+    Info (332119):     0.083               0.000 inst51 
+    Info (332119):     0.089               0.000 inst76 
+    Info (332119):     0.112               0.000 pin_name1 
+    Info (332119):     0.118               0.000 inst72 
+    Info (332119):     0.127               0.000 inst59 
+    Info (332119):     0.131               0.000 inst39 
+    Info (332119):     0.135               0.000 inst47 
+    Info (332119):     0.137               0.000 inst23 
+    Info (332119):     0.140               0.000 inst35 
+    Info (332119):     0.151               0.000 inst67 
+    Info (332119):     0.153               0.000 inst71 
+    Info (332119):     0.156               0.000 inst55 
+    Info (332119):     0.165               0.000 inst68 
+    Info (332119):     0.170               0.000 inst31 
+    Info (332119):     0.171               0.000 inst32 
+    Info (332119):     0.171               0.000 inst36 
+    Info (332119):     0.173               0.000 inst27 
+    Info (332119):     0.173               0.000 inst48 
+    Info (332119):     0.178               0.000 inst24 
+    Info (332119):     0.178               0.000 inst56 
+    Info (332119):     0.178               0.000 inst60 
+    Info (332119):     0.179               0.000 inst44 
+    Info (332119):     0.186               0.000 inst64 
+    Info (332119):     0.188               0.000 inst75 
+    Info (332119):     0.215               0.000 inst63 
+    Info (332119):     0.311               0.000 inst40 
+    Info (332119):     0.341               0.000 inst52 
+    Info (332119):     0.398               0.000 inst79 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case hold slack is -0.079
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.079              -0.079 inst63 
+    Info (332119):    -0.022              -0.022 pin_name1 
+    Info (332119):    -0.018              -0.018 inst52 
+    Info (332119):    -0.014              -0.014 inst71 
+    Info (332119):    -0.013              -0.013 inst31 
+    Info (332119):    -0.003              -0.003 inst27 
+    Info (332119):    -0.003              -0.003 inst59 
+    Info (332119):     0.003               0.000 inst40 
+    Info (332119):     0.006               0.000 inst67 
+    Info (332119):     0.012               0.000 inst55 
+    Info (332119):     0.019               0.000 inst35 
+    Info (332119):     0.028               0.000 inst47 
+    Info (332119):     0.029               0.000 inst39 
+    Info (332119):     0.032               0.000 inst23 
+    Info (332119):     0.040               0.000 inst72 
+    Info (332119):     0.045               0.000 inst76 
+    Info (332119):     0.047               0.000 inst51 
+    Info (332119):     0.063               0.000 inst43 
+    Info (332119):     0.073               0.000 inst75 
+    Info (332119):     0.075               0.000 inst24 
+    Info (332119):     0.075               0.000 inst56 
+    Info (332119):     0.077               0.000 inst64 
+    Info (332119):     0.081               0.000 inst48 
+    Info (332119):     0.085               0.000 inst60 
+    Info (332119):     0.086               0.000 inst44 
+    Info (332119):     0.089               0.000 inst68 
+    Info (332119):     0.094               0.000 inst32 
+    Info (332119):     0.094               0.000 inst36 
+    Info (332119):     0.110               0.000 inst28 
+    Info (332119):     0.341               0.000 inst79 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000              -4.000 pin_name1 
+    Info (332119):    -1.000              -1.000 inst23 
+    Info (332119):    -1.000              -1.000 inst24 
+    Info (332119):    -1.000              -1.000 inst27 
+    Info (332119):    -1.000              -1.000 inst28 
+    Info (332119):    -1.000              -1.000 inst31 
+    Info (332119):    -1.000              -1.000 inst32 
+    Info (332119):    -1.000              -1.000 inst35 
+    Info (332119):    -1.000              -1.000 inst36 
+    Info (332119):    -1.000              -1.000 inst39 
+    Info (332119):    -1.000              -1.000 inst40 
+    Info (332119):    -1.000              -1.000 inst43 
+    Info (332119):    -1.000              -1.000 inst44 
+    Info (332119):    -1.000              -1.000 inst47 
+    Info (332119):    -1.000              -1.000 inst48 
+    Info (332119):    -1.000              -1.000 inst51 
+    Info (332119):    -1.000              -1.000 inst52 
+    Info (332119):    -1.000              -1.000 inst55 
+    Info (332119):    -1.000              -1.000 inst56 
+    Info (332119):    -1.000              -1.000 inst59 
+    Info (332119):    -1.000              -1.000 inst60 
+    Info (332119):    -1.000              -1.000 inst63 
+    Info (332119):    -1.000              -1.000 inst64 
+    Info (332119):    -1.000              -1.000 inst67 
+    Info (332119):    -1.000              -1.000 inst68 
+    Info (332119):    -1.000              -1.000 inst71 
+    Info (332119):    -1.000              -1.000 inst72 
+    Info (332119):    -1.000              -1.000 inst75 
+    Info (332119):    -1.000              -1.000 inst76 
+    Info (332119):    -1.000              -1.000 inst79 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 0.237
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.237               0.000 inst28 
+    Info (332119):     0.241               0.000 pin_name1 
+    Info (332119):     0.270               0.000 inst51 
+    Info (332119):     0.281               0.000 inst72 
+    Info (332119):     0.284               0.000 inst39 
+    Info (332119):     0.290               0.000 inst43 
+    Info (332119):     0.291               0.000 inst23 
+    Info (332119):     0.291               0.000 inst76 
+    Info (332119):     0.292               0.000 inst35 
+    Info (332119):     0.292               0.000 inst47 
+    Info (332119):     0.296               0.000 inst67 
+    Info (332119):     0.304               0.000 inst55 
+    Info (332119):     0.311               0.000 inst31 
+    Info (332119):     0.316               0.000 inst27 
+    Info (332119):     0.324               0.000 inst59 
+    Info (332119):     0.327               0.000 inst68 
+    Info (332119):     0.328               0.000 inst71 
+    Info (332119):     0.330               0.000 inst32 
+    Info (332119):     0.330               0.000 inst36 
+    Info (332119):     0.331               0.000 inst48 
+    Info (332119):     0.335               0.000 inst44 
+    Info (332119):     0.335               0.000 inst60 
+    Info (332119):     0.336               0.000 inst24 
+    Info (332119):     0.336               0.000 inst56 
+    Info (332119):     0.343               0.000 inst64 
+    Info (332119):     0.344               0.000 inst75 
+    Info (332119):     0.364               0.000 inst63 
+    Info (332119):     0.429               0.000 inst40 
+    Info (332119):     0.435               0.000 inst52 
+    Info (332119):     0.624               0.000 inst79 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case hold slack is -0.105
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.105              -0.105 inst63 
+    Info (332119):    -0.066              -0.066 inst59 
+    Info (332119):    -0.060              -0.060 inst71 
+    Info (332119):    -0.049              -0.049 inst52 
+    Info (332119):    -0.041              -0.041 inst43 
+    Info (332119):    -0.033              -0.033 inst31 
+    Info (332119):    -0.029              -0.029 inst27 
+    Info (332119):    -0.027              -0.027 inst40 
+    Info (332119):    -0.027              -0.027 inst76 
+    Info (332119):    -0.021              -0.021 pin_name1 
+    Info (332119):    -0.018              -0.018 inst55 
+    Info (332119):    -0.018              -0.018 inst67 
+    Info (332119):    -0.014              -0.014 inst35 
+    Info (332119):    -0.009              -0.009 inst51 
+    Info (332119):    -0.007              -0.007 inst47 
+    Info (332119):    -0.005              -0.005 inst23 
+    Info (332119):    -0.005              -0.005 inst39 
+    Info (332119):    -0.003              -0.003 inst72 
+    Info (332119):     0.017               0.000 inst75 
+    Info (332119):     0.018               0.000 inst24 
+    Info (332119):     0.018               0.000 inst56 
+    Info (332119):     0.018               0.000 inst64 
+    Info (332119):     0.024               0.000 inst48 
+    Info (332119):     0.026               0.000 inst60 
+    Info (332119):     0.026               0.000 inst68 
+    Info (332119):     0.028               0.000 inst44 
+    Info (332119):     0.033               0.000 inst32 
+    Info (332119):     0.033               0.000 inst36 
+    Info (332119):     0.046               0.000 inst28 
+    Info (332119):     0.206               0.000 inst79 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000              -4.056 pin_name1 
+    Info (332119):    -1.000              -1.000 inst23 
+    Info (332119):    -1.000              -1.000 inst24 
+    Info (332119):    -1.000              -1.000 inst27 
+    Info (332119):    -1.000              -1.000 inst28 
+    Info (332119):    -1.000              -1.000 inst31 
+    Info (332119):    -1.000              -1.000 inst32 
+    Info (332119):    -1.000              -1.000 inst35 
+    Info (332119):    -1.000              -1.000 inst36 
+    Info (332119):    -1.000              -1.000 inst39 
+    Info (332119):    -1.000              -1.000 inst40 
+    Info (332119):    -1.000              -1.000 inst43 
+    Info (332119):    -1.000              -1.000 inst44 
+    Info (332119):    -1.000              -1.000 inst47 
+    Info (332119):    -1.000              -1.000 inst48 
+    Info (332119):    -1.000              -1.000 inst51 
+    Info (332119):    -1.000              -1.000 inst52 
+    Info (332119):    -1.000              -1.000 inst55 
+    Info (332119):    -1.000              -1.000 inst56 
+    Info (332119):    -1.000              -1.000 inst59 
+    Info (332119):    -1.000              -1.000 inst60 
+    Info (332119):    -1.000              -1.000 inst63 
+    Info (332119):    -1.000              -1.000 inst64 
+    Info (332119):    -1.000              -1.000 inst67 
+    Info (332119):    -1.000              -1.000 inst68 
+    Info (332119):    -1.000              -1.000 inst71 
+    Info (332119):    -1.000              -1.000 inst72 
+    Info (332119):    -1.000              -1.000 inst75 
+    Info (332119):    -1.000              -1.000 inst76 
+    Info (332119):    -1.000              -1.000 inst79 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 502 megabytes
+    Info: Processing ended: Thu Feb 18 21:05:10 2016
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:04
+
+
diff --git a/blinken_lights/output_files/blinken_Lights.sta.summary b/blinken_lights/output_files/blinken_Lights.sta.summary
new file mode 100644
index 0000000..b3121ac
--- /dev/null
+++ b/blinken_lights/output_files/blinken_Lights.sta.summary
@@ -0,0 +1,1085 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst28'
+Slack : -0.011
+TNS   : -0.011
+
+Type  : Slow 1200mV 85C Model Setup 'inst43'
+Slack : 0.010
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'pin_name1'
+Slack : 0.030
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst51'
+Slack : 0.032
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst76'
+Slack : 0.047
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst72'
+Slack : 0.070
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst59'
+Slack : 0.080
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst39'
+Slack : 0.086
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst47'
+Slack : 0.089
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst23'
+Slack : 0.090
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst35'
+Slack : 0.094
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst71'
+Slack : 0.097
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst67'
+Slack : 0.108
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst55'
+Slack : 0.112
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst31'
+Slack : 0.128
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst27'
+Slack : 0.129
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst68'
+Slack : 0.130
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst32'
+Slack : 0.134
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst36'
+Slack : 0.134
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst48'
+Slack : 0.139
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst60'
+Slack : 0.142
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst44'
+Slack : 0.143
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst24'
+Slack : 0.144
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst56'
+Slack : 0.144
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst64'
+Slack : 0.152
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst75'
+Slack : 0.154
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst63'
+Slack : 0.176
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst40'
+Slack : 0.298
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst79'
+Slack : 0.317
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst52'
+Slack : 0.325
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst63'
+Slack : -0.088
+TNS   : -0.088
+
+Type  : Slow 1200mV 85C Model Hold 'inst52'
+Slack : -0.026
+TNS   : -0.026
+
+Type  : Slow 1200mV 85C Model Hold 'inst31'
+Slack : -0.017
+TNS   : -0.017
+
+Type  : Slow 1200mV 85C Model Hold 'inst27'
+Slack : -0.006
+TNS   : -0.006
+
+Type  : Slow 1200mV 85C Model Hold 'inst71'
+Slack : -0.002
+TNS   : -0.002
+
+Type  : Slow 1200mV 85C Model Hold 'inst59'
+Slack : 0.001
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst67'
+Slack : 0.002
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst40'
+Slack : 0.006
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst55'
+Slack : 0.009
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'pin_name1'
+Slack : 0.013
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst35'
+Slack : 0.019
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst39'
+Slack : 0.028
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst47'
+Slack : 0.029
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst23'
+Slack : 0.032
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst72'
+Slack : 0.040
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst76'
+Slack : 0.045
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst43'
+Slack : 0.052
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst51'
+Slack : 0.052
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst75'
+Slack : 0.084
+TNS   : 0.000
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+TNS   : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst39'
+Slack : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst40'
+Slack : -1.000
+TNS   : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst43'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst44'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst47'
+Slack : -1.000
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+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst51'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst52'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst55'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst56'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst59'
+Slack : -1.000
+TNS   : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst60'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst63'
+Slack : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst64'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst67'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst68'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst71'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst72'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst75'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst76'
+Slack : -1.000
+TNS   : -1.000
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+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst79'
+Slack : -1.000
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+
+------------------------------------------------------------
diff --git a/blinken_lights/test.txt b/blinken_lights/test.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/blinken_lights/test.txt
diff --git a/comb_multiply/Comb_multiply.bdf b/comb_multiply/Comb_multiply.bdf
new file mode 100644
index 0000000..7ae9791
--- /dev/null
+++ b/comb_multiply/Comb_multiply.bdf
@@ -0,0 +1,1977 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
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+	(pt 1656 280)
+)
+(connector
+	(text "M[3]" (rect 1648 280 1669 292)(font "Arial" ))
+	(pt 1632 296)
+	(pt 1656 296)
+)
+(connector
+	(text "M[4]" (rect 1644 296 1665 308)(font "Arial" ))
+	(pt 1632 312)
+	(pt 1656 312)
+)
+(connector
+	(text "M[5]" (rect 1640 312 1661 324)(font "Arial" ))
+	(pt 1632 328)
+	(pt 1656 328)
+)
+(connector
+	(text "M[6]" (rect 1644 328 1665 340)(font "Arial" ))
+	(pt 1632 344)
+	(pt 1656 344)
+)
+(connector
+	(text "M[7]" (rect 1645 344 1666 356)(font "Arial" ))
+	(pt 1632 360)
+	(pt 1656 360)
+)
+(connector
+	(text "M[8]" (rect 1647 360 1668 372)(font "Arial" ))
+	(pt 1632 376)
+	(pt 1656 376)
+)
+(connector
+	(text "M[9]" (rect 1642 376 1663 388)(font "Arial" ))
+	(pt 1632 392)
+	(pt 1656 392)
+)
+(connector
+	(pt 1672 408)
+	(pt 1632 408)
+)
+(connector
+	(text "Y[4]" (rect 1504 232 1525 244)(font "Arial" ))
+	(pt 1504 248)
+	(pt 1536 248)
+)
+(connector
+	(pt 1392 264)
+	(pt 1536 264)
+)
+(connector
+	(pt 1536 280)
+	(pt 1392 280)
+)
+(connector
+	(pt 1392 296)
+	(pt 1536 296)
+)
+(connector
+	(pt 1536 312)
+	(pt 1392 312)
+)
+(connector
+	(pt 1392 328)
+	(pt 1536 328)
+)
+(connector
+	(pt 1536 344)
+	(pt 1392 344)
+)
+(connector
+	(pt 1392 360)
+	(pt 1536 360)
+)
+(connector
+	(pt 1536 376)
+	(pt 1392 376)
+)
+(connector
+	(pt 1536 392)
+	(pt 1392 392)
+)
+(connector
+	(text "X[0]" (rect 1505 472 1523 484)(font "Arial" ))
+	(pt 1507 488)
+	(pt 1536 488)
+)
+(connector
+	(text "X[1]" (rect 1507 488 1525 500)(font "Arial" ))
+	(pt 1507 504)
+	(pt 1536 504)
+)
+(connector
+	(text "X[2]" (rect 1515 504 1533 516)(font "Arial" ))
+	(pt 1536 520)
+	(pt 1504 520)
+)
+(connector
+	(text "X[3]" (rect 1512 520 1530 532)(font "Arial" ))
+	(pt 1536 536)
+	(pt 1504 536)
+)
+(connector
+	(text "X[4]" (rect 1513 536 1531 548)(font "Arial" ))
+	(pt 1536 552)
+	(pt 1504 552)
+)
+(connector
+	(pt 1536 424)
+	(pt 1536 440)
+)
+(connector
+	(pt 1536 456)
+	(pt 1536 472)
+)
+(connector
+	(pt 1536 408)
+	(pt 1392 408)
+)
+(connector
+	(pt 816 472)
+	(pt 776 472)
+)
+(connector
+	(pt 1056 584)
+	(pt 1048 584)
+)
+(connector
+	(pt 1056 568)
+	(pt 1056 584)
+)
+(connector
+	(pt 1056 584)
+	(pt 1056 600)
+)
+(connector
+	(pt 1152 440)
+	(pt 1160 440)
+)
+(connector
+	(pt 1160 440)
+	(pt 1160 632)
+)
+(connector
+	(pt 912 456)
+	(pt 920 456)
+)
+(connector
+	(pt 920 456)
+	(pt 920 640)
+)
+(connector
+	(pt 1392 424)
+	(pt 1400 424)
+)
+(connector
+	(pt 1400 424)
+	(pt 1400 616)
+)
+(connector
+	(pt 1536 448)
+	(pt 1520 448)
+)
+(connector
+	(pt 1536 440)
+	(pt 1536 448)
+)
+(connector
+	(pt 1536 448)
+	(pt 1536 456)
+)
+(connector
+	(pt 1536 568)
+	(pt 1528 568)
+)
+(junction (pt 448 448))
+(junction (pt 520 448))
+(junction (pt 376 448))
+(junction (pt 280 448))
+(junction (pt 808 592))
+(junction (pt 808 584))
+(junction (pt 808 600))
+(junction (pt 792 408))
+(junction (pt 792 424))
+(junction (pt 792 440))
+(junction (pt 1056 456))
+(junction (pt 1056 584))
+(junction (pt 1296 456))
+(junction (pt 1296 568))
+(junction (pt 1296 440))
+(junction (pt 1536 440))
+(junction (pt 1536 456))
+(junction (pt 1536 448))
+(text "X[0]" (rect 778 472 796 484)(font "Arial" ))
+(text "X[0]" (rect 778 472 796 484)(font "Arial" ))
diff --git a/comb_multiply/Comb_multiply.qpf b/comb_multiply/Comb_multiply.qpf
new file mode 100644
index 0000000..95fa7e0
--- /dev/null
+++ b/comb_multiply/Comb_multiply.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:19:27  February 17, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:19:27  February 17, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "Comb_multiply"
diff --git a/comb_multiply/Comb_multiply.qsf b/comb_multiply/Comb_multiply.qsf
new file mode 100644
index 0000000..cd935d1
--- /dev/null
+++ b/comb_multiply/Comb_multiply.qsf
@@ -0,0 +1,82 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:19:27  February 17, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Comb_multiply_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY Comb_multiply
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:19:27  FEBRUARY 17, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BSF_FILE ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bsf
+set_global_assignment -name BDF_FILE ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name BDF_FILE Comb_multiply.bdf
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_J7 -to Y[0]
+set_location_assignment PIN_G5 -to X[4]
+set_location_assignment PIN_G4 -to X[3]
+set_location_assignment PIN_H6 -to X[2]
+set_location_assignment PIN_H5 -to X[1]
+set_location_assignment PIN_J6 -to X[0]
+set_location_assignment PIN_D2 -to Y[4]
+set_location_assignment PIN_E4 -to Y[3]
+set_location_assignment PIN_E3 -to Y[2]
+set_location_assignment PIN_H7 -to Y[1]
+set_location_assignment PIN_B1 -to Output[9]
+set_location_assignment PIN_B2 -to Output[8]
+set_location_assignment PIN_C2 -to Output[7]
+set_location_assignment PIN_C1 -to Output[6]
+set_location_assignment PIN_E1 -to Output[5]
+set_location_assignment PIN_F2 -to Output[4]
+set_location_assignment PIN_H1 -to Output[3]
+set_location_assignment PIN_J3 -to Output[2]
+set_location_assignment PIN_J2 -to Output[1]
+set_location_assignment PIN_J1 -to Output[0]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/comb_multiply/Comb_multiply.qws b/comb_multiply/Comb_multiply.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/comb_multiply/Comb_multiply.qws
diff --git a/comb_multiply/Lab 3.cpp b/comb_multiply/Lab 3.cpp
new file mode 100644
index 0000000..e728d46
--- /dev/null
+++ b/comb_multiply/Lab 3.cpp
@@ -0,0 +1,59 @@
+#include <iostream>
+
+unsigned multiply(unsigned op1, unsigned op2);
+
+int main()
+{
+	unsigned int a = 31;
+	unsigned int b = 3;
+
+	unsigned int c = multiply(a, b);
+
+	std::cout << "a: " << a << std::endl
+			<< "b: " << b << std::endl
+			<< "a*b: " << c << std::endl;
+	return 0;
+}
+
+// a and b are 5-bit numbers
+unsigned multiply(unsigned a, unsigned b)
+{
+  unsigned r=0;
+  // for(unsigned i=0; i<5; i++){ // Loop over 5 bits of a
+  //   r=r*2; // Shift r left by one bit
+  //   if(a&0x10){ // Test whether a[4] (the MSB) is 1 using bit mask (10000)
+  //     r=r+b;
+  //   }
+  //   a=a*2;  // Shift a left by one bit
+  // }
+  if (a & 0x10)
+  {
+  	r += b;
+  }
+  a *= 2;
+  r *= 2;
+  if (a & 0x10)
+  {
+  	r += b;
+  }
+  a *= 2;
+  r *= 2;
+  if (a & 0x10)
+  {
+  	r += b;
+  }
+  a *= 2;
+  r *= 2;
+  if (a & 0x10)
+  {
+  	r += b;
+  }
+  a *= 2;
+  r *= 2;
+  if (a & 0x10)
+  {
+  	r += b;
+  }
+  a *= 2;
+  return r;
+}
diff --git a/comb_multiply/Lab 3.exe b/comb_multiply/Lab 3.exe
new file mode 100644
index 0000000..b7005aa
--- /dev/null
+++ b/comb_multiply/Lab 3.exe
diff --git a/comb_multiply/db/.cmp.kpt b/comb_multiply/db/.cmp.kpt
new file mode 100644
index 0000000..1e14dbc
--- /dev/null
+++ b/comb_multiply/db/.cmp.kpt
diff --git a/comb_multiply/db/Comb_multiply.(0).cnf.cdb b/comb_multiply/db/Comb_multiply.(0).cnf.cdb
new file mode 100644
index 0000000..92af7fc
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(0).cnf.cdb
diff --git a/comb_multiply/db/Comb_multiply.(0).cnf.hdb b/comb_multiply/db/Comb_multiply.(0).cnf.hdb
new file mode 100644
index 0000000..dbe5a47
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(0).cnf.hdb
diff --git a/comb_multiply/db/Comb_multiply.(1).cnf.cdb b/comb_multiply/db/Comb_multiply.(1).cnf.cdb
new file mode 100644
index 0000000..e7c09c8
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(1).cnf.cdb
diff --git a/comb_multiply/db/Comb_multiply.(1).cnf.hdb b/comb_multiply/db/Comb_multiply.(1).cnf.hdb
new file mode 100644
index 0000000..a6215c0
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(1).cnf.hdb
diff --git a/comb_multiply/db/Comb_multiply.(2).cnf.cdb b/comb_multiply/db/Comb_multiply.(2).cnf.cdb
new file mode 100644
index 0000000..b9ba284
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(2).cnf.cdb
diff --git a/comb_multiply/db/Comb_multiply.(2).cnf.hdb b/comb_multiply/db/Comb_multiply.(2).cnf.hdb
new file mode 100644
index 0000000..f8ed515
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.(2).cnf.hdb
diff --git a/comb_multiply/db/Comb_multiply.asm.qmsg b/comb_multiply/db/Comb_multiply.asm.qmsg
new file mode 100644
index 0000000..c7e5ad0
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895087152 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895087153 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:18:07 2016 " "Processing started: Fri Feb 19 15:18:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895087153 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455895087153 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455895087153 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455895087918 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455895087943 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "471 " "Peak virtual memory: 471 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895088239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:18:08 2016 " "Processing ended: Fri Feb 19 15:18:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895088239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895088239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895088239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455895088239 ""}
diff --git a/comb_multiply/db/Comb_multiply.asm.rdb b/comb_multiply/db/Comb_multiply.asm.rdb
new file mode 100644
index 0000000..0689bcb
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.asm.rdb
diff --git a/comb_multiply/db/Comb_multiply.asm_labs.ddb b/comb_multiply/db/Comb_multiply.asm_labs.ddb
new file mode 100644
index 0000000..6046309
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.asm_labs.ddb
diff --git a/comb_multiply/db/Comb_multiply.cbx.xml b/comb_multiply/db/Comb_multiply.cbx.xml
new file mode 100644
index 0000000..a027846
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="Comb_multiply">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/comb_multiply/db/Comb_multiply.cmp.bpm b/comb_multiply/db/Comb_multiply.cmp.bpm
new file mode 100644
index 0000000..4980b21
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.bpm
diff --git a/comb_multiply/db/Comb_multiply.cmp.cdb b/comb_multiply/db/Comb_multiply.cmp.cdb
new file mode 100644
index 0000000..b7259b5
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.cdb
diff --git a/comb_multiply/db/Comb_multiply.cmp.hdb b/comb_multiply/db/Comb_multiply.cmp.hdb
new file mode 100644
index 0000000..1f93da1
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.hdb
diff --git a/comb_multiply/db/Comb_multiply.cmp.idb b/comb_multiply/db/Comb_multiply.cmp.idb
new file mode 100644
index 0000000..59a6c48
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.idb
diff --git a/comb_multiply/db/Comb_multiply.cmp.logdb b/comb_multiply/db/Comb_multiply.cmp.logdb
new file mode 100644
index 0000000..83c13a4
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.logdb
@@ -0,0 +1,62 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,20;0;20;0;0;20;20;0;20;20;0;10;0;0;10;0;10;10;0;0;0;10;0;0;0;0;0;20;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;20;0;20;20;0;0;20;0;0;20;10;20;20;10;20;10;10;20;20;20;10;20;20;20;20;20;0;20;20,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Output[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Output[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/comb_multiply/db/Comb_multiply.cmp.rdb b/comb_multiply/db/Comb_multiply.cmp.rdb
new file mode 100644
index 0000000..c5936ed
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp.rdb
diff --git a/comb_multiply/db/Comb_multiply.cmp_merge.kpt b/comb_multiply/db/Comb_multiply.cmp_merge.kpt
new file mode 100644
index 0000000..c91ddce
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cmp_merge.kpt
diff --git a/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..68a603e
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..ff83748
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/comb_multiply/db/Comb_multiply.db_info b/comb_multiply/db/Comb_multiply.db_info
new file mode 100644
index 0000000..d5c3d65
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 17:04:28 2016
diff --git a/comb_multiply/db/Comb_multiply.eda.qmsg b/comb_multiply/db/Comb_multiply.eda.qmsg
new file mode 100644
index 0000000..8b2b506
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895093139 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895093140 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:18:13 2016 " "Processing started: Fri Feb 19 15:18:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895093140 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895093140 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895093140 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093523 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093547 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093572 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093596 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093617 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093642 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093674 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_vhd.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895093697 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895093741 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:18:13 2016 " "Processing ended: Fri Feb 19 15:18:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895093741 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895093741 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895093741 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895093741 ""}
diff --git a/comb_multiply/db/Comb_multiply.fit.qmsg b/comb_multiply/db/Comb_multiply.fit.qmsg
new file mode 100644
index 0000000..378c576
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455895079909 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "Comb_multiply EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"Comb_multiply\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455895079914 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895079974 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895079975 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895079975 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455895080055 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455895080068 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895080290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895080290 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895080290 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455895080290 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 160 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895080292 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 162 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895080292 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 164 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895080292 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 166 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895080292 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 168 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895080292 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455895080292 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455895080293 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Comb_multiply.sdc " "Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455895081418 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455895081419 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455895081419 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455895081420 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455895081420 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455895081421 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455895081421 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455895081422 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455895081423 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455895081423 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455895081423 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455895081423 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455895081424 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455895081424 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455895081424 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455895081424 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455895081424 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455895081424 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895081442 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455895082283 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895082335 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455895082341 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455895082518 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895082518 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455895082678 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455895083182 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455895083182 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895083237 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455895083238 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455895083238 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455895083238 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455895083248 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455895083290 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455895083579 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455895083611 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455895083920 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895084266 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455895085230 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "835 " "Peak virtual memory: 835 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895085459 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:18:05 2016 " "Processing ended: Fri Feb 19 15:18:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895085459 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895085459 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895085459 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455895085459 ""}
diff --git a/comb_multiply/db/Comb_multiply.hier_info b/comb_multiply/db/Comb_multiply.hier_info
new file mode 100644
index 0000000..7942b49
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.hier_info
@@ -0,0 +1,783 @@
+|Comb_multiply
+Output[0] <= M[0].DB_MAX_OUTPUT_PORT_TYPE
+Output[1] <= M[1].DB_MAX_OUTPUT_PORT_TYPE
+Output[2] <= M[2].DB_MAX_OUTPUT_PORT_TYPE
+Output[3] <= M[3].DB_MAX_OUTPUT_PORT_TYPE
+Output[4] <= M[4].DB_MAX_OUTPUT_PORT_TYPE
+Output[5] <= M[5].DB_MAX_OUTPUT_PORT_TYPE
+Output[6] <= M[6].DB_MAX_OUTPUT_PORT_TYPE
+Output[7] <= M[7].DB_MAX_OUTPUT_PORT_TYPE
+Output[8] <= M[8].DB_MAX_OUTPUT_PORT_TYPE
+Output[9] <= M[9].DB_MAX_OUTPUT_PORT_TYPE
+Y[0] => inst5.IN1
+Y[0] => inst6.IN1
+Y[0] => inst7.IN1
+Y[0] => inst8.IN1
+Y[0] => inst9.IN1
+Y[1] => ten_bit_adder_NO_BUS:inst.ENY
+Y[2] => ten_bit_adder_NO_BUS:inst1.ENY
+Y[3] => ten_bit_adder_NO_BUS:inst2.ENY
+Y[4] => ten_bit_adder_NO_BUS:inst3.ENY
+X[0] => inst5.IN0
+X[0] => ten_bit_adder_NO_BUS:inst.Y1
+X[0] => ten_bit_adder_NO_BUS:inst1.Y2
+X[0] => ten_bit_adder_NO_BUS:inst2.Y3
+X[0] => ten_bit_adder_NO_BUS:inst3.Y4
+X[1] => inst6.IN0
+X[1] => ten_bit_adder_NO_BUS:inst.Y2
+X[1] => ten_bit_adder_NO_BUS:inst1.Y3
+X[1] => ten_bit_adder_NO_BUS:inst2.Y4
+X[1] => ten_bit_adder_NO_BUS:inst3.Y5
+X[2] => inst7.IN0
+X[2] => ten_bit_adder_NO_BUS:inst.Y3
+X[2] => ten_bit_adder_NO_BUS:inst1.Y4
+X[2] => ten_bit_adder_NO_BUS:inst2.Y5
+X[2] => ten_bit_adder_NO_BUS:inst3.Y6
+X[3] => inst8.IN0
+X[3] => ten_bit_adder_NO_BUS:inst.Y4
+X[3] => ten_bit_adder_NO_BUS:inst1.Y5
+X[3] => ten_bit_adder_NO_BUS:inst2.Y6
+X[3] => ten_bit_adder_NO_BUS:inst3.Y7
+X[4] => inst9.IN0
+X[4] => ten_bit_adder_NO_BUS:inst.Y5
+X[4] => ten_bit_adder_NO_BUS:inst1.Y6
+X[4] => ten_bit_adder_NO_BUS:inst2.Y7
+X[4] => ten_bit_adder_NO_BUS:inst3.Y8
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/comb_multiply/db/Comb_multiply.hif b/comb_multiply/db/Comb_multiply.hif
new file mode 100644
index 0000000..10d6e18
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.hif
diff --git a/comb_multiply/db/Comb_multiply.ipinfo b/comb_multiply/db/Comb_multiply.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.ipinfo
diff --git a/comb_multiply/db/Comb_multiply.lpc.html b/comb_multiply/db/Comb_multiply.lpc.html
new file mode 100644
index 0000000..2f64a91
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.lpc.html
@@ -0,0 +1,722 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst|inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst9</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst10</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
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diff --git a/comb_multiply/db/Comb_multiply.lpc.rdb b/comb_multiply/db/Comb_multiply.lpc.rdb
new file mode 100644
index 0000000..0092a24
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.lpc.rdb
diff --git a/comb_multiply/db/Comb_multiply.lpc.txt b/comb_multiply/db/Comb_multiply.lpc.txt
new file mode 100644
index 0000000..93b9c91
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.lpc.txt
@@ -0,0 +1,50 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                        ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy    ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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+; inst2|inst12 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2|inst13 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2|inst14 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2|inst15 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2|inst16 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2|inst17 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2        ; 21    ; 6              ; 0            ; 6              ; 11     ; 6               ; 6             ; 6               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst8  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst9  ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst10 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst11 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst12 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst13 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst14 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst15 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst16 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3|inst17 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3        ; 21    ; 6              ; 0            ; 6              ; 11     ; 6               ; 6             ; 6               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/comb_multiply/db/Comb_multiply.map.ammdb b/comb_multiply/db/Comb_multiply.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.ammdb
diff --git a/comb_multiply/db/Comb_multiply.map.bpm b/comb_multiply/db/Comb_multiply.map.bpm
new file mode 100644
index 0000000..a9d1916
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.bpm
diff --git a/comb_multiply/db/Comb_multiply.map.cdb b/comb_multiply/db/Comb_multiply.map.cdb
new file mode 100644
index 0000000..352ed09
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.cdb
diff --git a/comb_multiply/db/Comb_multiply.map.hdb b/comb_multiply/db/Comb_multiply.map.hdb
new file mode 100644
index 0000000..720dc7f
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.hdb
diff --git a/comb_multiply/db/Comb_multiply.map.kpt b/comb_multiply/db/Comb_multiply.map.kpt
new file mode 100644
index 0000000..ad6cadb
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.kpt
diff --git a/comb_multiply/db/Comb_multiply.map.logdb b/comb_multiply/db/Comb_multiply.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/comb_multiply/db/Comb_multiply.map.qmsg b/comb_multiply/db/Comb_multiply.map.qmsg
new file mode 100644
index 0000000..cf0a5dc
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.qmsg
@@ -0,0 +1,19 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895076332 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895076332 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:17:56 2016 " "Processing started: Fri Feb 19 15:17:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895076332 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895076332 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895076332 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455895076612 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895076656 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895076656 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895076657 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895076657 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "comb_multiply.bdf 1 1 " "Found 1 design units, including 1 entities, in source file comb_multiply.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Comb_multiply " "Found entity 1: Comb_multiply" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895076659 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895076659 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Comb_multiply " "Elaborating entity \"Comb_multiply\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455895076687 ""}
+{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "GND inst21 " "Block or symbol \"GND\" of instance \"inst21\" overlaps another block or symbol" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 640 904 936 672 "inst21" "" } } } }  } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Quartus II" 0 -1 1455895076688 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst21 " "Primitive \"GND\" of instance \"inst21\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 640 904 936 672 "inst21" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895076688 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst22 " "Primitive \"GND\" of instance \"inst22\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 632 1144 1176 664 "inst22" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895076688 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst23 " "Primitive \"GND\" of instance \"inst23\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 616 1384 1416 648 "inst23" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895076688 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst24 " "Primitive \"GND\" of instance \"inst24\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 392 1672 1704 424 "inst24" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895076688 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_bit_adder_NO_BUS ten_bit_adder_NO_BUS:inst3 " "Elaborating entity \"ten_bit_adder_NO_BUS\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\"" {  } { { "Comb_multiply.bdf" "inst3" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 216 1536 1632 600 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455895076690 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder ten_bit_adder_NO_BUS:inst3\|full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\|full_adder:inst17\"" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1424 888 984 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455895076691 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455895077597 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455895077862 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455895077862 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "68 " "Implemented 68 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455895077925 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455895077925 ""} { "Info" "ICUT_CUT_TM_LCELLS" "48 " "Implemented 48 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455895077925 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455895077925 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895077943 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:17:57 2016 " "Processing ended: Fri Feb 19 15:17:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895077943 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895077943 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895077943 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895077943 ""}
diff --git a/comb_multiply/db/Comb_multiply.map.rdb b/comb_multiply/db/Comb_multiply.map.rdb
new file mode 100644
index 0000000..ca6f880
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map.rdb
diff --git a/comb_multiply/db/Comb_multiply.map_bb.cdb b/comb_multiply/db/Comb_multiply.map_bb.cdb
new file mode 100644
index 0000000..285454a
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map_bb.cdb
diff --git a/comb_multiply/db/Comb_multiply.map_bb.hdb b/comb_multiply/db/Comb_multiply.map_bb.hdb
new file mode 100644
index 0000000..8791e14
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map_bb.hdb
diff --git a/comb_multiply/db/Comb_multiply.map_bb.logdb b/comb_multiply/db/Comb_multiply.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/comb_multiply/db/Comb_multiply.pplq.rdb b/comb_multiply/db/Comb_multiply.pplq.rdb
new file mode 100644
index 0000000..2765321
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.pplq.rdb
diff --git a/comb_multiply/db/Comb_multiply.pre_map.hdb b/comb_multiply/db/Comb_multiply.pre_map.hdb
new file mode 100644
index 0000000..7fe5397
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.pre_map.hdb
diff --git a/comb_multiply/db/Comb_multiply.pti_db_list.ddb b/comb_multiply/db/Comb_multiply.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.pti_db_list.ddb
diff --git a/comb_multiply/db/Comb_multiply.root_partition.map.reg_db.cdb b/comb_multiply/db/Comb_multiply.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..8f746f7
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.root_partition.map.reg_db.cdb
diff --git a/comb_multiply/db/Comb_multiply.routing.rdb b/comb_multiply/db/Comb_multiply.routing.rdb
new file mode 100644
index 0000000..e5fe1ab
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.routing.rdb
diff --git a/comb_multiply/db/Comb_multiply.rtlv.hdb b/comb_multiply/db/Comb_multiply.rtlv.hdb
new file mode 100644
index 0000000..9b78095
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.rtlv.hdb
diff --git a/comb_multiply/db/Comb_multiply.rtlv_sg.cdb b/comb_multiply/db/Comb_multiply.rtlv_sg.cdb
new file mode 100644
index 0000000..a868de4
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.rtlv_sg.cdb
diff --git a/comb_multiply/db/Comb_multiply.rtlv_sg_swap.cdb b/comb_multiply/db/Comb_multiply.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..28550fe
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.rtlv_sg_swap.cdb
diff --git a/comb_multiply/db/Comb_multiply.sgdiff.cdb b/comb_multiply/db/Comb_multiply.sgdiff.cdb
new file mode 100644
index 0000000..000d82e
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sgdiff.cdb
diff --git a/comb_multiply/db/Comb_multiply.sgdiff.hdb b/comb_multiply/db/Comb_multiply.sgdiff.hdb
new file mode 100644
index 0000000..2dbc619
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sgdiff.hdb
diff --git a/comb_multiply/db/Comb_multiply.sld_design_entry.sci b/comb_multiply/db/Comb_multiply.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sld_design_entry.sci
diff --git a/comb_multiply/db/Comb_multiply.sld_design_entry_dsc.sci b/comb_multiply/db/Comb_multiply.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sld_design_entry_dsc.sci
diff --git a/comb_multiply/db/Comb_multiply.smart_action.txt b/comb_multiply/db/Comb_multiply.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/comb_multiply/db/Comb_multiply.sta.qmsg b/comb_multiply/db/Comb_multiply.sta.qmsg
new file mode 100644
index 0000000..799ae7f
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sta.qmsg
@@ -0,0 +1,49 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895090019 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895090019 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:18:09 2016 " "Processing started: Fri Feb 19 15:18:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895090019 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895090019 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Comb_multiply -c Comb_multiply " "Command: quartus_sta Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895090020 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455895090086 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455895090222 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895090223 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895090296 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895090296 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Comb_multiply.sdc " "Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455895090483 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895090483 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895090486 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895090486 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455895090486 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895090487 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455895090487 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455895090493 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455895090496 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090497 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090506 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090510 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090514 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090518 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895090521 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455895090536 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455895090558 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455895091046 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895091077 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895091077 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895091077 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895091077 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091078 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091085 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091090 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091094 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091097 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091101 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455895091122 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895091209 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895091210 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895091210 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895091210 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091214 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091221 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091226 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091231 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895091237 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455895091390 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455895091390 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895091452 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:18:11 2016 " "Processing ended: Fri Feb 19 15:18:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895091452 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895091452 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895091452 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895091452 ""}
diff --git a/comb_multiply/db/Comb_multiply.sta.rdb b/comb_multiply/db/Comb_multiply.sta.rdb
new file mode 100644
index 0000000..010e3dc
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sta.rdb
diff --git a/comb_multiply/db/Comb_multiply.sta_cmp.6_slow_1200mv_85c.tdb b/comb_multiply/db/Comb_multiply.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..6f7cf9d
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/comb_multiply/db/Comb_multiply.tis_db_list.ddb b/comb_multiply/db/Comb_multiply.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.tis_db_list.ddb
diff --git a/comb_multiply/db/Comb_multiply.tiscmp.fast_1200mv_0c.ddb b/comb_multiply/db/Comb_multiply.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..60d9f97
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.tiscmp.fast_1200mv_0c.ddb
diff --git a/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_0c.ddb b/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..1e6065f
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_0c.ddb
diff --git a/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_85c.ddb b/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..424db39
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.tiscmp.slow_1200mv_85c.ddb
diff --git a/comb_multiply/db/Comb_multiply.tmw_info b/comb_multiply/db/Comb_multiply.tmw_info
new file mode 100644
index 0000000..ac40973
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s
+start_analysis_synthesis:s-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s-start_full_compilation
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation
diff --git a/comb_multiply/db/Comb_multiply.vpr.ammdb b/comb_multiply/db/Comb_multiply.vpr.ammdb
new file mode 100644
index 0000000..9042437
--- /dev/null
+++ b/comb_multiply/db/Comb_multiply.vpr.ammdb
diff --git a/comb_multiply/db/logic_util_heursitic.dat b/comb_multiply/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..6e0b005
--- /dev/null
+++ b/comb_multiply/db/logic_util_heursitic.dat
diff --git a/comb_multiply/db/prev_cmp_Comb_multiply.qmsg b/comb_multiply/db/prev_cmp_Comb_multiply.qmsg
new file mode 100644
index 0000000..a0735f2
--- /dev/null
+++ b/comb_multiply/db/prev_cmp_Comb_multiply.qmsg
@@ -0,0 +1,139 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895004664 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895004664 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:16:44 2016 " "Processing started: Fri Feb 19 15:16:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895004664 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895004664 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895004665 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455895004944 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895004986 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895004986 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895004988 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895004988 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "comb_multiply.bdf 1 1 " "Found 1 design units, including 1 entities, in source file comb_multiply.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Comb_multiply " "Found entity 1: Comb_multiply" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455895004990 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455895004990 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "Comb_multiply " "Elaborating entity \"Comb_multiply\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455895005016 ""}
+{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "GND inst21 " "Block or symbol \"GND\" of instance \"inst21\" overlaps another block or symbol" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 640 904 936 672 "inst21" "" } } } }  } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Quartus II" 0 -1 1455895005019 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst21 " "Primitive \"GND\" of instance \"inst21\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 640 904 936 672 "inst21" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895005020 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst22 " "Primitive \"GND\" of instance \"inst22\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 632 1144 1176 664 "inst22" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895005021 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst23 " "Primitive \"GND\" of instance \"inst23\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 616 1384 1416 648 "inst23" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895005021 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst24 " "Primitive \"GND\" of instance \"inst24\" not used" {  } { { "Comb_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 392 1672 1704 424 "inst24" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455895005021 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_bit_adder_NO_BUS ten_bit_adder_NO_BUS:inst3 " "Elaborating entity \"ten_bit_adder_NO_BUS\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\"" {  } { { "Comb_multiply.bdf" "inst3" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf" { { 216 1536 1632 600 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455895005030 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder ten_bit_adder_NO_BUS:inst3\|full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\|full_adder:inst17\"" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1424 888 984 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455895005032 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455895005903 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455895006183 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455895006183 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "68 " "Implemented 68 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455895006236 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455895006236 ""} { "Info" "ICUT_CUT_TM_LCELLS" "48 " "Implemented 48 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455895006236 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455895006236 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895006259 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:16:46 2016 " "Processing ended: Fri Feb 19 15:16:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895006259 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895006259 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895006259 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895006259 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895008073 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895008074 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:16:47 2016 " "Processing started: Fri Feb 19 15:16:47 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895008074 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455895008074 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_fit --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455895008074 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455895008148 ""}
+{ "Info" "0" "" "Project  = Comb_multiply" {  } {  } 0 0 "Project  = Comb_multiply" 0 0 "Fitter" 0 0 1455895008148 ""}
+{ "Info" "0" "" "Revision = Comb_multiply" {  } {  } 0 0 "Revision = Comb_multiply" 0 0 "Fitter" 0 0 1455895008148 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455895008210 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "Comb_multiply EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"Comb_multiply\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455895008216 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895008278 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895008279 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455895008280 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455895008360 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455895008373 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895008577 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895008577 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455895008577 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455895008577 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 160 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895008578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 162 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895008578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 164 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895008578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 166 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895008578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 0 { 0 ""} 0 168 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455895008578 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455895008578 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455895008580 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Comb_multiply.sdc " "Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455895009734 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455895009735 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455895009735 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455895009736 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455895009736 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455895009737 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455895009737 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455895009738 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455895009739 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455895009739 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455895009739 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455895009740 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455895009740 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895009758 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455895010657 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895010708 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455895010716 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455895010892 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895010892 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455895011048 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/comb_multiply/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455895011585 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455895011585 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895011635 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455895011636 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455895011636 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455895011636 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455895011645 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455895011685 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455895011973 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455895012009 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455895012323 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455895012666 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455895013679 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "835 " "Peak virtual memory: 835 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895013907 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:16:53 2016 " "Processing ended: Fri Feb 19 15:16:53 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895013907 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895013907 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895013907 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455895013907 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455895015639 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895015640 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:16:55 2016 " "Processing started: Fri Feb 19 15:16:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895015640 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455895015640 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455895015640 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455895016421 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455895016445 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "471 " "Peak virtual memory: 471 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895016741 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:16:56 2016 " "Processing ended: Fri Feb 19 15:16:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895016741 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895016741 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895016741 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455895016741 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455895017325 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455895018547 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895018548 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:16:58 2016 " "Processing started: Fri Feb 19 15:16:58 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895018548 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895018548 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Comb_multiply -c Comb_multiply " "Command: quartus_sta Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895018548 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455895018616 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455895018740 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895018740 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895018801 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455895018801 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "Comb_multiply.sdc " "Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455895018989 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895018990 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895018990 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895018991 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455895018991 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895018991 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455895018992 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455895018997 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455895019001 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019001 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019011 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019015 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019018 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019022 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019026 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455895019046 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455895019082 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455895019582 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895019616 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895019616 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895019616 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895019616 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019617 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019626 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019630 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019634 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019639 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019643 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455895019657 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455895019747 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455895019747 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455895019748 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455895019748 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019753 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019757 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019763 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019767 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455895019771 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455895019920 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455895019921 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "509 " "Peak virtual memory: 509 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895019976 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:16:59 2016 " "Processing ended: Fri Feb 19 15:16:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895019976 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895019976 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895019976 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895019976 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455895021689 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455895021690 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 15:17:01 2016 " "Processing started: Fri Feb 19 15:17:01 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455895021690 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455895021690 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455895021690 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022066 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022094 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022126 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply.vho C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply.vho in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022153 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022174 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022194 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022222 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "Comb_multiply_vhd.sdo C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/ simulation " "Generated file Comb_multiply_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455895022244 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455895022287 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 15:17:02 2016 " "Processing ended: Fri Feb 19 15:17:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455895022287 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455895022287 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455895022287 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895022287 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 16 s " "Quartus II Full Compilation was successful. 0 errors, 16 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455895022905 ""}
diff --git a/comb_multiply/incremental_db/README b/comb_multiply/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/comb_multiply/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.db_info b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.db_info
new file mode 100644
index 0000000..925b227
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 22:58:27 2016
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.ammdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.ammdb
new file mode 100644
index 0000000..7856e5a
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.ammdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.cdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.cdb
new file mode 100644
index 0000000..c35b123
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.cdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.dfp b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.dfp
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.hdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.hdb
new file mode 100644
index 0000000..ff833d5
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.hdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.logdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.rcfdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..3111e27
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.cmp.rcfdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.cdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.cdb
new file mode 100644
index 0000000..4d7cf97
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.cdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.dpi b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.dpi
new file mode 100644
index 0000000..de3fc87
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.dpi
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.cdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..2d0bfa3
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.cdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hb_info b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hb_info
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..7dd3662
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.hdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.sig b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hdb b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hdb
new file mode 100644
index 0000000..05ebe3e
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.hdb
diff --git a/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.kpt b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.kpt
new file mode 100644
index 0000000..98122ea
--- /dev/null
+++ b/comb_multiply/incremental_db/compiled_partitions/Comb_multiply.root_partition.map.kpt
diff --git a/comb_multiply/output_files/Comb_multiply.asm.rpt b/comb_multiply/output_files/Comb_multiply.asm.rpt
new file mode 100644
index 0000000..382da64
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for Comb_multiply
+Fri Feb 19 15:18:08 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 19 15:18:08 2016 ;
+; Revision Name         ; Comb_multiply                         ;
+; Top-level Entity Name ; Comb_multiply                         ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Assembler Generated Files                                                   ;
++-----------------------------------------------------------------------------+
+; File Name                                                                   ;
++-----------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.sof ;
++-----------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.sof ;
++----------------+--------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                              ;
++----------------+--------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                         ;
+; JTAG usercode  ; 0x000CEC10                                                                           ;
+; Checksum       ; 0x000CEC10                                                                           ;
++----------------+--------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 15:18:07 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 471 megabytes
+    Info: Processing ended: Fri Feb 19 15:18:08 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.cdf b/comb_multiply/output_files/Comb_multiply.cdf
new file mode 100644
index 0000000..f5a31b8
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/") File("Comb_multiply.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/comb_multiply/output_files/Comb_multiply.done b/comb_multiply/output_files/Comb_multiply.done
new file mode 100644
index 0000000..2dc82d1
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.done
@@ -0,0 +1 @@
+Fri Feb 19 15:18:14 2016
diff --git a/comb_multiply/output_files/Comb_multiply.eda.rpt b/comb_multiply/output_files/Comb_multiply.eda.rpt
new file mode 100644
index 0000000..6b19783
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for Comb_multiply
+Fri Feb 19 15:18:13 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb 19 15:18:13 2016 ;
+; Revision Name             ; Comb_multiply                         ;
+; Top-level Entity Name     ; Comb_multiply                         ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                ;
++-----------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                           ;
++-----------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply.vho                        ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/Comb_multiply_vhd.sdo                    ;
++-----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 15:18:13 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply
+Info (204019): Generated file Comb_multiply_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply.vho in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file Comb_multiply_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/comb_multiply/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 427 megabytes
+    Info: Processing ended: Fri Feb 19 15:18:13 2016
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.fit.rpt b/comb_multiply/output_files/Comb_multiply.fit.rpt
new file mode 100644
index 0000000..b226517
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.fit.rpt
@@ -0,0 +1,1431 @@
+Fitter report for Comb_multiply
+Fri Feb 19 15:18:05 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Routing Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. I/O Rules Summary
+ 27. I/O Rules Details
+ 28. I/O Rules Matrix
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 19 15:18:05 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; Comb_multiply                              ;
+; Top-level Entity Name              ; Comb_multiply                              ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 48 / 15,408 ( < 1 % )                      ;
+;     Total combinational functions  ; 48 / 15,408 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 20 / 347 ( 6 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; Output[9] ; Missing drive strength and slew rate ;
+; Output[8] ; Missing drive strength and slew rate ;
+; Output[7] ; Missing drive strength and slew rate ;
+; Output[6] ; Missing drive strength and slew rate ;
+; Output[5] ; Missing drive strength and slew rate ;
+; Output[4] ; Missing drive strength and slew rate ;
+; Output[3] ; Missing drive strength and slew rate ;
+; Output[2] ; Missing drive strength and slew rate ;
+; Output[1] ; Missing drive strength and slew rate ;
+; Output[0] ; Missing drive strength and slew rate ;
++-----------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 99 ) ; 0.00 % ( 0 / 99 )          ; 0.00 % ( 0 / 99 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 99 ) ; 0.00 % ( 0 / 99 )          ; 0.00 % ( 0 / 99 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 89 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 48 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 48                    ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 0                     ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 33                    ;
+;     -- 3 input functions                    ; 5                     ;
+;     -- <=2 input functions                  ; 10                    ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 48                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 0 / 17,068 ( 0 % )    ;
+;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )    ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 3 / 963 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 20 / 347 ( 6 % )      ;
+;     -- Clock pins                           ; 0 / 8 ( 0 % )         ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 0                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 0 / 20 ( 0 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 1%          ;
+; Maximum fan-out                             ; 13                    ;
+; Highest non-global fan-out                  ; 13                    ;
+; Total fan-out                               ; 202                   ;
+; Average fan-out                             ; 2.06                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 48 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 48                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 33                   ; 0                              ;
+;     -- 3 input functions                    ; 5                    ; 0                              ;
+;     -- <=2 input functions                  ; 10                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 48                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 0                    ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % )    ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 3 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 20                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 197                  ; 5                              ;
+;     -- Registered Connections               ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 10                   ; 0                              ;
+;     -- Output Ports                         ; 10                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; X[0] ; J6    ; 1        ; 0            ; 24           ; 0            ; 13                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; X[1] ; H5    ; 1        ; 0            ; 27           ; 0            ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; X[2] ; H6    ; 1        ; 0            ; 25           ; 21           ; 9                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; X[3] ; G4    ; 1        ; 0            ; 23           ; 7            ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; X[4] ; G5    ; 1        ; 0            ; 27           ; 21           ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Y[0] ; J7    ; 1        ; 0            ; 22           ; 14           ; 9                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Y[1] ; H7    ; 1        ; 0            ; 25           ; 14           ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Y[2] ; E3    ; 1        ; 0            ; 26           ; 7            ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Y[3] ; E4    ; 1        ; 0            ; 26           ; 0            ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Y[4] ; D2    ; 1        ; 0            ; 25           ; 0            ; 9                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Output[0] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[1] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[2] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[3] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[4] ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[5] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[6] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[7] ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[8] ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[9] ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; Y[3]                    ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 24 / 33 ( 73 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; Output[9]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; Output[8]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; Output[6]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; Output[7]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; Y[4]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; Output[5]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; Y[2]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; Y[3]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F2       ; 15         ; 1        ; Output[4]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; X[3]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; X[4]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; Output[3]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; X[1]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; X[2]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; Y[1]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; Output[0]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; Output[1]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; Output[2]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; X[0]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; Y[0]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                        ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                         ; Library Name ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+--------------+
+; |Comb_multiply                  ; 48 (1)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 20   ; 0            ; 48 (1)       ; 0 (0)             ; 0 (0)            ; |Comb_multiply                                              ; work         ;
+;    |ten_bit_adder_NO_BUS:inst1| ; 13 (2)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (2)       ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1                   ; work         ;
+;       |full_adder:inst10|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10 ; work         ;
+;       |full_adder:inst11|       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst2| ; 11 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (0)       ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2                   ; work         ;
+;       |full_adder:inst11|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst3| ; 11 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 11 (0)       ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3                   ; work         ;
+;       |full_adder:inst12|       ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15 ; work         ;
+;       |full_adder:inst16|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst|  ; 12 (4)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (4)       ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst                    ; work         ;
+;       |full_adder:inst10|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10  ; work         ;
+;       |full_adder:inst11|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11  ; work         ;
+;       |full_adder:inst12|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12  ; work         ;
+;       |full_adder:inst9|        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9   ; work         ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                       ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name      ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Output[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Y[4]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; X[4]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X[1]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; X[2]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Y[3]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; X[3]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Y[0]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Y[1]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X[0]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Y[2]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++-------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                            ;
++-------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                         ; Pad To Core Index ; Setting ;
++-------------------------------------------------------------+-------------------+---------+
+; Y[4]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~1 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst2~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst2~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst12|inst    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~0 ; 1                 ; 6       ;
+; X[4]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst2    ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst21                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst3~0  ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|inst22                    ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst2   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst2   ; 0                 ; 6       ;
+; X[1]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|inst18                     ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst6     ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~1 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~1 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~1 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~1 ; 1                 ; 6       ;
+; X[2]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst3~0  ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst19                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst2    ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst2   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst2   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst2~0 ; 0                 ; 6       ;
+; Y[3]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~1 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst6   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst    ; 1                 ; 6       ;
+; X[3]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst2    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst3~0  ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst20                     ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|inst21                    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst2   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst2~0 ; 1                 ; 6       ;
+; Y[0]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst6     ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst3~0  ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst2    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst2    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst3~0  ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst2    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst3~0  ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 1                 ; 6       ;
+;      - inst5                                                ; 1                 ; 6       ;
+; Y[1]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|inst18                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst6     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst19                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst20                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|inst21                     ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 0                 ; 6       ;
+; X[0]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst6     ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst6   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst6   ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 1                 ; 6       ;
+;      - inst5                                                ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst12|inst    ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~0 ; 1                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~1 ; 1                 ; 6       ;
+; Y[2]                                                        ;                   ;         ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~1 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst3~0 ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|inst21                    ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst2   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst6   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst2   ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|inst22                    ; 0                 ; 6       ;
+;      - ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst    ; 0                 ; 6       ;
++-------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                ;
++------------------------------------------------------+---------+
+; Name                                                 ; Fan-Out ;
++------------------------------------------------------+---------+
+; X[0]~input                                           ; 13      ;
+; Y[3]~input                                           ; 10      ;
+; X[1]~input                                           ; 10      ;
+; Y[0]~input                                           ; 9       ;
+; X[2]~input                                           ; 9       ;
+; Y[4]~input                                           ; 9       ;
+; Y[2]~input                                           ; 8       ;
+; X[3]~input                                           ; 8       ;
+; X[4]~input                                           ; 8       ;
+; Y[1]~input                                           ; 6       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst3~0  ; 4       ;
+; ten_bit_adder_NO_BUS:inst|inst21                     ; 4       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst2   ; 3       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst2   ; 3       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst2    ; 3       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst14|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst22                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst13|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~1 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~1 ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst13|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst21                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst2    ; 2       ;
+; ten_bit_adder_NO_BUS:inst|inst20                     ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst3~0  ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~1 ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst2    ; 2       ;
+; ten_bit_adder_NO_BUS:inst|inst19                     ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst3~0  ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst6     ; 2       ;
+; ten_bit_adder_NO_BUS:inst|inst18                     ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~1 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst12|inst    ; 1       ;
+; inst5                                                ; 1       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst    ; 1       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst    ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst2~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst2~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst2   ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst3~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst6   ; 1       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst6   ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~0 ; 1       ;
++------------------------------------------------------+---------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary                         ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage                 ;
++-----------------------+-----------------------+
+; Block interconnects   ; 49 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects      ; 41 / 31,272 ( < 1 % ) ;
+; Direct links          ; 1 / 47,787 ( < 1 % )  ;
+; Global clocks         ; 0 / 20 ( 0 % )        ;
+; Local interconnects   ; 25 / 15,408 ( < 1 % ) ;
+; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects      ; 3 / 41,310 ( < 1 % )  ;
++-----------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 16.00) ; Number of LABs  (Total = 3) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 0                           ;
+; 16                                          ; 3                           ;
++---------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 16.00) ; Number of LABs  (Total = 3) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 3                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 8.00) ; Number of LABs  (Total = 3) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 1                           ;
+; 7                                               ; 0                           ;
+; 8                                               ; 1                           ;
+; 9                                               ; 0                           ;
+; 10                                              ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 12.33) ; Number of LABs  (Total = 3) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 1                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 1                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 20        ; 0            ; 20        ; 0            ; 0            ; 20        ; 20        ; 0            ; 20        ; 20        ; 0            ; 10           ; 0            ; 0            ; 10           ; 0            ; 10           ; 10           ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 20        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 20           ; 0         ; 20           ; 20           ; 0         ; 0         ; 20           ; 0         ; 0         ; 20           ; 10           ; 20           ; 20           ; 10           ; 20           ; 10           ; 10           ; 20           ; 20           ; 20           ; 10           ; 20           ; 20           ; 20           ; 20           ; 20           ; 0         ; 20           ; 20           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Output[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[4]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[4]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[1]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[2]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[3]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[3]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[0]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[1]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[0]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[2]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EP3C16F484C6 for design "Comb_multiply"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.11 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 835 megabytes
+    Info: Processing ended: Fri Feb 19 15:18:05 2016
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/comb_multiply/output_files/Comb_multiply.fit.smsg.
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.fit.smsg b/comb_multiply/output_files/Comb_multiply.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/comb_multiply/output_files/Comb_multiply.fit.summary b/comb_multiply/output_files/Comb_multiply.fit.summary
new file mode 100644
index 0000000..e16d713
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Fri Feb 19 15:18:05 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : Comb_multiply
+Top-level Entity Name : Comb_multiply
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 48 / 15,408 ( < 1 % )
+    Total combinational functions : 48 / 15,408 ( < 1 % )
+    Dedicated logic registers : 0 / 15,408 ( 0 % )
+Total registers : 0
+Total pins : 20 / 347 ( 6 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/comb_multiply/output_files/Comb_multiply.flow.rpt b/comb_multiply/output_files/Comb_multiply.flow.rpt
new file mode 100644
index 0000000..3910af6
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.flow.rpt
@@ -0,0 +1,130 @@
+Flow report for Comb_multiply
+Fri Feb 19 15:18:13 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 19 15:18:13 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; Comb_multiply                              ;
+; Top-level Entity Name              ; Comb_multiply                              ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 48 / 15,408 ( < 1 % )                      ;
+;     Total combinational functions  ; 48 / 15,408 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 20 / 347 ( 6 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/19/2016 15:17:56 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; Comb_multiply       ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                           ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145589507613180       ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                                  ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)                ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top            ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --             ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --             ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 495 MB              ; 00:00:02                           ;
+; Fitter                    ; 00:00:06     ; 1.0                     ; 835 MB              ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 463 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 509 MB              ; 00:00:02                           ;
+; EDA Netlist Writer        ; 00:00:00     ; 1.0                     ; 415 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:10     ; --                      ; --                  ; 00:00:12                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply
+quartus_fit --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply
+quartus_asm --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply
+quartus_sta Comb_multiply -c Comb_multiply
+quartus_eda --read_settings_files=off --write_settings_files=off Comb_multiply -c Comb_multiply
+
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.jdi b/comb_multiply/output_files/Comb_multiply.jdi
new file mode 100644
index 0000000..5929854
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="442c38a65341cd675c57"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="Comb_multiply.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/comb_multiply/output_files/Comb_multiply.map.rpt b/comb_multiply/output_files/Comb_multiply.map.rpt
new file mode 100644
index 0000000..365025f
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.map.rpt
@@ -0,0 +1,293 @@
+Analysis & Synthesis report for Comb_multiply
+Fri Feb 19 15:17:57 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 19 15:17:57 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; Comb_multiply                              ;
+; Top-level Entity Name              ; Comb_multiply                              ;
+; Family                             ; Cyclone III                                ;
+; Total logic elements               ; 48                                         ;
+;     Total combinational functions  ; 48                                         ;
+;     Dedicated logic registers      ; 0                                          ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 20                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; Comb_multiply      ; Comb_multiply      ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                           ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path                 ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                 ; Library ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf ;         ;
+; ../adder/full_adder.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf                          ;         ;
+; Comb_multiply.bdf                                ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf               ;         ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary              ;
++---------------------------------------------+------------+
+; Resource                                    ; Usage      ;
++---------------------------------------------+------------+
+; Estimated Total logic elements              ; 48         ;
+;                                             ;            ;
+; Total combinational functions               ; 48         ;
+; Logic element usage by number of LUT inputs ;            ;
+;     -- 4 input functions                    ; 33         ;
+;     -- 3 input functions                    ; 5          ;
+;     -- <=2 input functions                  ; 10         ;
+;                                             ;            ;
+; Logic elements by mode                      ;            ;
+;     -- normal mode                          ; 48         ;
+;     -- arithmetic mode                      ; 0          ;
+;                                             ;            ;
+; Total registers                             ; 0          ;
+;     -- Dedicated logic registers            ; 0          ;
+;     -- I/O registers                        ; 0          ;
+;                                             ;            ;
+; I/O pins                                    ; 20         ;
+; Embedded Multiplier 9-bit elements          ; 0          ;
+; Maximum fan-out node                        ; X[0]~input ;
+; Maximum fan-out                             ; 13         ;
+; Total fan-out                               ; 197        ;
+; Average fan-out                             ; 2.24       ;
++---------------------------------------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                      ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                         ; Library Name ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------+--------------+
+; |Comb_multiply                  ; 48 (1)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |Comb_multiply                                              ; work         ;
+;    |ten_bit_adder_NO_BUS:inst1| ; 13 (2)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1                   ; work         ;
+;       |full_adder:inst10|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10 ; work         ;
+;       |full_adder:inst11|       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst2| ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2                   ; work         ;
+;       |full_adder:inst11|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst3| ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3                   ; work         ;
+;       |full_adder:inst12|       ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15 ; work         ;
+;       |full_adder:inst16|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst|  ; 12 (4)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst                    ; work         ;
+;       |full_adder:inst10|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10  ; work         ;
+;       |full_adder:inst11|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11  ; work         ;
+;       |full_adder:inst12|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12  ; work         ;
+;       |full_adder:inst9|        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Comb_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9   ; work         ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 15:17:56 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Comb_multiply -c Comb_multiply
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf
+    Info (12023): Found entity 1: ten_bit_adder_NO_BUS
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file comb_multiply.bdf
+    Info (12023): Found entity 1: Comb_multiply
+Info (12127): Elaborating entity "Comb_multiply" for the top level hierarchy
+Warning (275011): Block or symbol "GND" of instance "inst21" overlaps another block or symbol
+Warning (275008): Primitive "GND" of instance "inst21" not used
+Warning (275008): Primitive "GND" of instance "inst22" not used
+Warning (275008): Primitive "GND" of instance "inst23" not used
+Warning (275008): Primitive "GND" of instance "inst24" not used
+Info (12128): Elaborating entity "ten_bit_adder_NO_BUS" for hierarchy "ten_bit_adder_NO_BUS:inst3"
+Info (12128): Elaborating entity "full_adder" for hierarchy "ten_bit_adder_NO_BUS:inst3|full_adder:inst17"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 68 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 10 input pins
+    Info (21059): Implemented 10 output pins
+    Info (21061): Implemented 48 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 506 megabytes
+    Info: Processing ended: Fri Feb 19 15:17:57 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.map.summary b/comb_multiply/output_files/Comb_multiply.map.summary
new file mode 100644
index 0000000..9c71653
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Fri Feb 19 15:17:57 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : Comb_multiply
+Top-level Entity Name : Comb_multiply
+Family : Cyclone III
+Total logic elements : 48
+    Total combinational functions : 48
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 20
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/comb_multiply/output_files/Comb_multiply.pin b/comb_multiply/output_files/Comb_multiply.pin
new file mode 100644
index 0000000..1c0f7ad
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "Comb_multiply"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+Output[9]                    : B1        : output : 2.5 V             :         : 1         : Y              
+Output[8]                    : B2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+Output[6]                    : C1        : output : 2.5 V             :         : 1         : Y              
+Output[7]                    : C2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+Y[4]                         : D2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+Output[5]                    : E1        : output : 2.5 V             :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+Y[2]                         : E3        : input  : 2.5 V             :         : 1         : Y              
+Y[3]                         : E4        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+Output[4]                    : F2        : output : 2.5 V             :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+X[3]                         : G4        : input  : 2.5 V             :         : 1         : Y              
+X[4]                         : G5        : input  : 2.5 V             :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+Output[3]                    : H1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+X[1]                         : H5        : input  : 2.5 V             :         : 1         : Y              
+X[2]                         : H6        : input  : 2.5 V             :         : 1         : Y              
+Y[1]                         : H7        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+Output[0]                    : J1        : output : 2.5 V             :         : 1         : Y              
+Output[1]                    : J2        : output : 2.5 V             :         : 1         : Y              
+Output[2]                    : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+X[0]                         : J6        : input  : 2.5 V             :         : 1         : Y              
+Y[0]                         : J7        : input  : 2.5 V             :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/comb_multiply/output_files/Comb_multiply.sof b/comb_multiply/output_files/Comb_multiply.sof
new file mode 100644
index 0000000..fbd2687
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.sof
diff --git a/comb_multiply/output_files/Comb_multiply.sta.rpt b/comb_multiply/output_files/Comb_multiply.sta.rpt
new file mode 100644
index 0000000..a5122c4
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.sta.rpt
@@ -0,0 +1,1116 @@
+TimeQuest Timing Analyzer report for Comb_multiply
+Fri Feb 19 15:18:11 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Propagation Delay
+ 34. Minimum Propagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Slow Corner Signal Integrity Metrics
+ 38. Fast Corner Signal Integrity Metrics
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths
+ 43. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; Comb_multiply                                      ;
+; Device Family      ; Cyclone III                                        ;
+; Device Name        ; EP3C16F484C6                                       ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; X[0]       ; Output[0]   ; 6.667  ;        ;        ; 7.128  ;
+; X[0]       ; Output[1]   ; 6.889  ; 6.849  ; 7.290  ; 7.298  ;
+; X[0]       ; Output[2]   ; 9.015  ; 9.130  ; 9.464  ; 9.584  ;
+; X[0]       ; Output[3]   ; 8.936  ; 8.909  ; 9.381  ; 9.354  ;
+; X[0]       ; Output[4]   ; 10.800 ; 10.822 ; 11.245 ; 11.267 ;
+; X[0]       ; Output[5]   ; 11.521 ; 11.553 ; 11.966 ; 11.998 ;
+; X[0]       ; Output[6]   ; 12.272 ; 12.287 ; 12.717 ; 12.732 ;
+; X[0]       ; Output[7]   ; 12.499 ; 12.505 ; 12.944 ; 12.950 ;
+; X[0]       ; Output[8]   ; 13.102 ; 13.131 ; 13.547 ; 13.576 ;
+; X[0]       ; Output[9]   ; 12.944 ; 13.060 ; 13.389 ; 13.505 ;
+; X[1]       ; Output[1]   ; 6.727  ; 6.689  ; 7.149  ; 7.142  ;
+; X[1]       ; Output[2]   ; 9.187  ; 9.298  ; 9.666  ; 9.777  ;
+; X[1]       ; Output[3]   ; 9.108  ; 9.081  ; 9.587  ; 9.560  ;
+; X[1]       ; Output[4]   ; 10.972 ; 10.994 ; 11.451 ; 11.473 ;
+; X[1]       ; Output[5]   ; 11.693 ; 11.725 ; 12.172 ; 12.204 ;
+; X[1]       ; Output[6]   ; 12.444 ; 12.459 ; 12.923 ; 12.938 ;
+; X[1]       ; Output[7]   ; 12.671 ; 12.677 ; 13.150 ; 13.156 ;
+; X[1]       ; Output[8]   ; 13.274 ; 13.303 ; 13.753 ; 13.782 ;
+; X[1]       ; Output[9]   ; 13.116 ; 13.232 ; 13.595 ; 13.711 ;
+; X[2]       ; Output[2]   ; 8.348  ; 8.465  ; 8.788  ; 8.899  ;
+; X[2]       ; Output[3]   ; 8.269  ; 8.242  ; 8.709  ; 8.682  ;
+; X[2]       ; Output[4]   ; 10.133 ; 10.155 ; 10.573 ; 10.595 ;
+; X[2]       ; Output[5]   ; 10.854 ; 10.886 ; 11.294 ; 11.326 ;
+; X[2]       ; Output[6]   ; 11.605 ; 11.620 ; 12.045 ; 12.060 ;
+; X[2]       ; Output[7]   ; 11.832 ; 11.838 ; 12.272 ; 12.278 ;
+; X[2]       ; Output[8]   ; 12.435 ; 12.464 ; 12.875 ; 12.904 ;
+; X[2]       ; Output[9]   ; 12.277 ; 12.393 ; 12.717 ; 12.833 ;
+; X[3]       ; Output[3]   ; 8.081  ; 8.054  ; 8.507  ; 8.480  ;
+; X[3]       ; Output[4]   ; 9.892  ; 9.914  ; 10.318 ; 10.340 ;
+; X[3]       ; Output[5]   ; 10.588 ; 10.620 ; 11.014 ; 11.046 ;
+; X[3]       ; Output[6]   ; 11.339 ; 11.354 ; 11.765 ; 11.780 ;
+; X[3]       ; Output[7]   ; 11.566 ; 11.572 ; 11.992 ; 11.998 ;
+; X[3]       ; Output[8]   ; 12.169 ; 12.198 ; 12.595 ; 12.624 ;
+; X[3]       ; Output[9]   ; 12.011 ; 12.127 ; 12.437 ; 12.553 ;
+; X[4]       ; Output[4]   ; 8.892  ; 8.914  ; 9.343  ; 9.365  ;
+; X[4]       ; Output[5]   ; 9.613  ; 9.645  ; 10.064 ; 10.096 ;
+; X[4]       ; Output[6]   ; 10.364 ; 10.379 ; 10.815 ; 10.830 ;
+; X[4]       ; Output[7]   ; 10.591 ; 10.597 ; 11.042 ; 11.048 ;
+; X[4]       ; Output[8]   ; 11.194 ; 11.223 ; 11.645 ; 11.674 ;
+; X[4]       ; Output[9]   ; 11.036 ; 11.152 ; 11.487 ; 11.603 ;
+; Y[0]       ; Output[0]   ; 6.786  ;        ;        ; 7.225  ;
+; Y[0]       ; Output[1]   ; 6.657  ; 6.619  ; 7.098  ; 7.051  ;
+; Y[0]       ; Output[2]   ; 8.834  ; 8.949  ; 9.280  ; 9.400  ;
+; Y[0]       ; Output[3]   ; 8.755  ; 8.728  ; 9.197  ; 9.170  ;
+; Y[0]       ; Output[4]   ; 10.619 ; 10.641 ; 11.061 ; 11.083 ;
+; Y[0]       ; Output[5]   ; 11.340 ; 11.372 ; 11.782 ; 11.814 ;
+; Y[0]       ; Output[6]   ; 12.091 ; 12.106 ; 12.533 ; 12.548 ;
+; Y[0]       ; Output[7]   ; 12.318 ; 12.324 ; 12.760 ; 12.766 ;
+; Y[0]       ; Output[8]   ; 12.921 ; 12.950 ; 13.363 ; 13.392 ;
+; Y[0]       ; Output[9]   ; 12.763 ; 12.879 ; 13.205 ; 13.321 ;
+; Y[1]       ; Output[1]   ; 6.597  ; 6.558  ; 7.020  ; 7.035  ;
+; Y[1]       ; Output[2]   ; 9.057  ; 9.168  ; 9.536  ; 9.647  ;
+; Y[1]       ; Output[3]   ; 8.978  ; 8.951  ; 9.457  ; 9.430  ;
+; Y[1]       ; Output[4]   ; 10.842 ; 10.864 ; 11.321 ; 11.343 ;
+; Y[1]       ; Output[5]   ; 11.563 ; 11.595 ; 12.042 ; 12.074 ;
+; Y[1]       ; Output[6]   ; 12.314 ; 12.329 ; 12.793 ; 12.808 ;
+; Y[1]       ; Output[7]   ; 12.541 ; 12.547 ; 13.020 ; 13.026 ;
+; Y[1]       ; Output[8]   ; 13.144 ; 13.173 ; 13.623 ; 13.652 ;
+; Y[1]       ; Output[9]   ; 12.986 ; 13.102 ; 13.465 ; 13.581 ;
+; Y[2]       ; Output[2]   ; 8.162  ; 8.282  ; 8.599  ; 8.738  ;
+; Y[2]       ; Output[3]   ; 8.026  ; 7.999  ; 8.503  ; 8.476  ;
+; Y[2]       ; Output[4]   ; 9.837  ; 9.859  ; 10.314 ; 10.336 ;
+; Y[2]       ; Output[5]   ; 10.533 ; 10.565 ; 11.010 ; 11.042 ;
+; Y[2]       ; Output[6]   ; 11.284 ; 11.299 ; 11.761 ; 11.776 ;
+; Y[2]       ; Output[7]   ; 11.511 ; 11.517 ; 11.988 ; 11.994 ;
+; Y[2]       ; Output[8]   ; 12.114 ; 12.143 ; 12.591 ; 12.620 ;
+; Y[2]       ; Output[9]   ; 11.956 ; 12.072 ; 12.433 ; 12.549 ;
+; Y[3]       ; Output[3]   ; 6.619  ; 6.599  ; 7.041  ; 7.053  ;
+; Y[3]       ; Output[4]   ; 8.401  ; 8.423  ; 8.887  ; 8.909  ;
+; Y[3]       ; Output[5]   ; 8.736  ; 8.716  ; 9.222  ; 9.202  ;
+; Y[3]       ; Output[6]   ; 9.489  ; 9.474  ; 9.975  ; 9.960  ;
+; Y[3]       ; Output[7]   ; 9.705  ; 9.711  ; 10.191 ; 10.197 ;
+; Y[3]       ; Output[8]   ; 10.308 ; 10.337 ; 10.794 ; 10.823 ;
+; Y[3]       ; Output[9]   ; 10.071 ; 10.266 ; 10.571 ; 10.752 ;
+; Y[4]       ; Output[4]   ; 6.784  ; 6.810  ; 7.246  ; 7.231  ;
+; Y[4]       ; Output[5]   ; 7.107  ; 7.096  ; 7.597  ; 7.577  ;
+; Y[4]       ; Output[6]   ; 7.265  ; 7.259  ; 7.758  ; 7.743  ;
+; Y[4]       ; Output[7]   ; 7.473  ; 7.488  ; 7.974  ; 7.980  ;
+; Y[4]       ; Output[8]   ; 8.044  ; 8.087  ; 8.577  ; 8.606  ;
+; Y[4]       ; Output[9]   ; 7.985  ;        ;        ; 8.535  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; X[0]       ; Output[0]   ; 6.510 ;       ;       ; 6.958 ;
+; X[0]       ; Output[1]   ; 6.676 ; 6.687 ; 7.117 ; 7.067 ;
+; X[0]       ; Output[2]   ; 7.686 ; 7.803 ; 8.085 ; 8.232 ;
+; X[0]       ; Output[3]   ; 6.319 ; 6.285 ; 6.738 ; 6.746 ;
+; X[0]       ; Output[4]   ; 6.345 ; 6.335 ; 6.748 ; 6.729 ;
+; X[0]       ; Output[5]   ; 6.474 ; 6.463 ; 6.874 ; 6.891 ;
+; X[0]       ; Output[6]   ; 7.312 ; 7.305 ; 7.796 ; 7.780 ;
+; X[0]       ; Output[7]   ; 7.513 ; 7.526 ; 8.005 ; 8.009 ;
+; X[0]       ; Output[8]   ; 8.001 ; 8.038 ; 8.521 ; 8.548 ;
+; X[0]       ; Output[9]   ; 7.967 ; 9.613 ; 9.942 ; 8.483 ;
+; X[1]       ; Output[1]   ; 6.571 ; 6.534 ; 6.981 ; 6.973 ;
+; X[1]       ; Output[2]   ; 8.705 ; 8.818 ; 9.158 ; 9.267 ;
+; X[1]       ; Output[3]   ; 7.049 ; 7.031 ; 7.502 ; 7.484 ;
+; X[1]       ; Output[4]   ; 7.674 ; 7.665 ; 8.133 ; 8.124 ;
+; X[1]       ; Output[5]   ; 6.595 ; 6.609 ; 7.053 ; 7.014 ;
+; X[1]       ; Output[6]   ; 6.828 ; 6.821 ; 7.266 ; 7.250 ;
+; X[1]       ; Output[7]   ; 7.029 ; 7.042 ; 7.475 ; 7.479 ;
+; X[1]       ; Output[8]   ; 7.517 ; 7.554 ; 7.991 ; 8.018 ;
+; X[1]       ; Output[9]   ; 7.483 ; 9.370 ; 9.686 ; 7.953 ;
+; X[2]       ; Output[2]   ; 8.170 ; 8.281 ; 8.568 ; 8.686 ;
+; X[2]       ; Output[3]   ; 7.708 ; 7.690 ; 8.140 ; 8.122 ;
+; X[2]       ; Output[4]   ; 7.879 ; 7.870 ; 8.308 ; 8.299 ;
+; X[2]       ; Output[5]   ; 7.473 ; 7.475 ; 7.911 ; 7.913 ;
+; X[2]       ; Output[6]   ; 6.645 ; 6.661 ; 7.060 ; 7.066 ;
+; X[2]       ; Output[7]   ; 6.857 ; 6.870 ; 7.268 ; 7.272 ;
+; X[2]       ; Output[8]   ; 7.345 ; 7.382 ; 7.784 ; 7.811 ;
+; X[2]       ; Output[9]   ; 7.311 ; 8.662 ; 8.994 ; 7.746 ;
+; X[3]       ; Output[3]   ; 7.755 ; 7.737 ; 8.201 ; 8.183 ;
+; X[3]       ; Output[4]   ; 8.759 ; 8.750 ; 9.209 ; 9.200 ;
+; X[3]       ; Output[5]   ; 8.427 ; 8.417 ; 8.879 ; 8.868 ;
+; X[3]       ; Output[6]   ; 7.628 ; 7.642 ; 8.074 ; 8.088 ;
+; X[3]       ; Output[7]   ; 6.248 ; 6.259 ; 6.636 ; 6.678 ;
+; X[3]       ; Output[8]   ; 6.735 ; 6.772 ; 7.189 ; 7.216 ;
+; X[3]       ; Output[9]   ; 6.701 ; 8.338 ; 8.728 ; 7.151 ;
+; X[4]       ; Output[4]   ; 8.503 ; 8.494 ; 8.911 ; 8.902 ;
+; X[4]       ; Output[5]   ; 8.552 ; 8.542 ; 9.050 ; 9.038 ;
+; X[4]       ; Output[6]   ; 8.508 ; 8.522 ; 8.972 ; 8.986 ;
+; X[4]       ; Output[7]   ; 7.771 ; 7.807 ; 8.222 ; 8.258 ;
+; X[4]       ; Output[8]   ; 6.586 ; 6.621 ; 7.036 ; 7.064 ;
+; X[4]       ; Output[9]   ; 6.568 ; 8.289 ; 8.679 ; 6.999 ;
+; Y[0]       ; Output[0]   ; 6.580 ;       ;       ; 6.993 ;
+; Y[0]       ; Output[1]   ; 6.504 ; 6.466 ; 6.932 ; 6.885 ;
+; Y[0]       ; Output[2]   ; 8.487 ; 8.605 ; 8.937 ; 9.055 ;
+; Y[0]       ; Output[3]   ; 7.767 ; 7.749 ; 8.224 ; 8.206 ;
+; Y[0]       ; Output[4]   ; 8.639 ; 8.630 ; 9.082 ; 9.073 ;
+; Y[0]       ; Output[5]   ; 8.741 ; 8.731 ; 9.208 ; 9.196 ;
+; Y[0]       ; Output[6]   ; 8.654 ; 8.668 ; 9.099 ; 9.113 ;
+; Y[0]       ; Output[7]   ; 8.742 ; 8.778 ; 9.212 ; 9.248 ;
+; Y[0]       ; Output[8]   ; 8.567 ; 8.581 ; 9.031 ; 9.036 ;
+; Y[0]       ; Output[9]   ; 8.535 ; 8.663 ; 9.096 ; 8.995 ;
+; Y[1]       ; Output[1]   ; 6.397 ; 6.408 ; 6.858 ; 6.814 ;
+; Y[1]       ; Output[2]   ; 8.526 ; 8.639 ; 8.987 ; 9.096 ;
+; Y[1]       ; Output[3]   ; 7.869 ; 7.851 ; 8.305 ; 8.287 ;
+; Y[1]       ; Output[4]   ; 8.455 ; 8.446 ; 8.869 ; 8.860 ;
+; Y[1]       ; Output[5]   ; 8.386 ; 8.376 ; 8.875 ; 8.863 ;
+; Y[1]       ; Output[6]   ; 8.460 ; 8.474 ; 8.893 ; 8.907 ;
+; Y[1]       ; Output[7]   ; 8.548 ; 8.584 ; 9.006 ; 9.042 ;
+; Y[1]       ; Output[8]   ; 8.373 ; 8.387 ; 8.825 ; 8.830 ;
+; Y[1]       ; Output[9]   ; 8.341 ; 8.469 ; 8.890 ; 8.789 ;
+; Y[2]       ; Output[2]   ; 7.987 ; 8.092 ; 8.391 ; 8.535 ;
+; Y[2]       ; Output[3]   ; 7.124 ; 7.106 ; 7.539 ; 7.521 ;
+; Y[2]       ; Output[4]   ; 8.531 ; 8.522 ; 8.936 ; 8.927 ;
+; Y[2]       ; Output[5]   ; 8.808 ; 8.796 ; 9.213 ; 9.201 ;
+; Y[2]       ; Output[6]   ; 8.397 ; 8.411 ; 8.827 ; 8.841 ;
+; Y[2]       ; Output[7]   ; 8.483 ; 8.519 ; 8.978 ; 9.014 ;
+; Y[2]       ; Output[8]   ; 8.308 ; 8.322 ; 8.797 ; 8.802 ;
+; Y[2]       ; Output[9]   ; 8.276 ; 8.404 ; 8.824 ; 8.761 ;
+; Y[3]       ; Output[3]   ; 6.467 ; 6.448 ; 6.877 ; 6.888 ;
+; Y[3]       ; Output[4]   ; 7.608 ; 7.599 ; 8.019 ; 8.010 ;
+; Y[3]       ; Output[5]   ; 7.672 ; 7.660 ; 8.083 ; 8.085 ;
+; Y[3]       ; Output[6]   ; 7.785 ; 7.799 ; 8.201 ; 8.215 ;
+; Y[3]       ; Output[7]   ; 7.688 ; 7.724 ; 8.102 ; 8.138 ;
+; Y[3]       ; Output[8]   ; 7.513 ; 7.527 ; 7.956 ; 7.961 ;
+; Y[3]       ; Output[9]   ; 7.481 ; 8.183 ; 8.559 ; 7.920 ;
+; Y[4]       ; Output[4]   ; 6.613 ; 6.625 ; 7.056 ; 7.041 ;
+; Y[4]       ; Output[5]   ; 6.900 ; 6.888 ; 7.351 ; 7.330 ;
+; Y[4]       ; Output[6]   ; 6.662 ; 6.653 ; 7.067 ; 7.089 ;
+; Y[4]       ; Output[7]   ; 6.646 ; 6.680 ; 7.086 ; 7.113 ;
+; Y[4]       ; Output[8]   ; 6.577 ; 6.589 ; 6.985 ; 7.028 ;
+; Y[4]       ; Output[9]   ; 6.546 ;       ;       ; 6.987 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; X[0]       ; Output[0]   ; 6.192  ;        ;        ; 6.570  ;
+; X[0]       ; Output[1]   ; 6.404  ; 6.349  ; 6.740  ; 6.726  ;
+; X[0]       ; Output[2]   ; 8.443  ; 8.543  ; 8.818  ; 8.918  ;
+; X[0]       ; Output[3]   ; 8.228  ; 8.192  ; 8.603  ; 8.567  ;
+; X[0]       ; Output[4]   ; 9.931  ; 9.915  ; 10.306 ; 10.290 ;
+; X[0]       ; Output[5]   ; 10.552 ; 10.562 ; 10.927 ; 10.937 ;
+; X[0]       ; Output[6]   ; 11.243 ; 11.220 ; 11.618 ; 11.595 ;
+; X[0]       ; Output[7]   ; 11.432 ; 11.419 ; 11.807 ; 11.794 ;
+; X[0]       ; Output[8]   ; 11.967 ; 11.969 ; 12.342 ; 12.344 ;
+; X[0]       ; Output[9]   ; 11.844 ; 11.906 ; 12.219 ; 12.281 ;
+; X[1]       ; Output[1]   ; 6.267  ; 6.211  ; 6.622  ; 6.595  ;
+; X[1]       ; Output[2]   ; 8.594  ; 8.686  ; 8.992  ; 9.087  ;
+; X[1]       ; Output[3]   ; 8.386  ; 8.350  ; 8.784  ; 8.748  ;
+; X[1]       ; Output[4]   ; 10.087 ; 10.071 ; 10.485 ; 10.469 ;
+; X[1]       ; Output[5]   ; 10.708 ; 10.718 ; 11.106 ; 11.116 ;
+; X[1]       ; Output[6]   ; 11.391 ; 11.368 ; 11.789 ; 11.766 ;
+; X[1]       ; Output[7]   ; 11.580 ; 11.567 ; 11.978 ; 11.965 ;
+; X[1]       ; Output[8]   ; 12.115 ; 12.117 ; 12.513 ; 12.515 ;
+; X[1]       ; Output[9]   ; 11.992 ; 12.054 ; 12.390 ; 12.452 ;
+; X[2]       ; Output[2]   ; 7.829  ; 7.929  ; 8.209  ; 8.301  ;
+; X[2]       ; Output[3]   ; 7.614  ; 7.578  ; 8.001  ; 7.965  ;
+; X[2]       ; Output[4]   ; 9.317  ; 9.301  ; 9.702  ; 9.686  ;
+; X[2]       ; Output[5]   ; 9.938  ; 9.948  ; 10.323 ; 10.333 ;
+; X[2]       ; Output[6]   ; 10.629 ; 10.606 ; 11.006 ; 10.983 ;
+; X[2]       ; Output[7]   ; 10.818 ; 10.805 ; 11.195 ; 11.182 ;
+; X[2]       ; Output[8]   ; 11.353 ; 11.355 ; 11.730 ; 11.732 ;
+; X[2]       ; Output[9]   ; 11.230 ; 11.292 ; 11.607 ; 11.669 ;
+; X[3]       ; Output[3]   ; 7.460  ; 7.432  ; 7.837  ; 7.807  ;
+; X[3]       ; Output[4]   ; 9.074  ; 9.070  ; 9.454  ; 9.450  ;
+; X[3]       ; Output[5]   ; 9.704  ; 9.714  ; 10.084 ; 10.094 ;
+; X[3]       ; Output[6]   ; 10.395 ; 10.372 ; 10.775 ; 10.752 ;
+; X[3]       ; Output[7]   ; 10.584 ; 10.571 ; 10.964 ; 10.951 ;
+; X[3]       ; Output[8]   ; 11.119 ; 11.121 ; 11.499 ; 11.501 ;
+; X[3]       ; Output[9]   ; 10.996 ; 11.058 ; 11.376 ; 11.438 ;
+; X[4]       ; Output[4]   ; 8.185  ; 8.167  ; 8.565  ; 8.547  ;
+; X[4]       ; Output[5]   ; 8.816  ; 8.826  ; 9.196  ; 9.206  ;
+; X[4]       ; Output[6]   ; 9.507  ; 9.484  ; 9.887  ; 9.864  ;
+; X[4]       ; Output[7]   ; 9.696  ; 9.683  ; 10.076 ; 10.063 ;
+; X[4]       ; Output[8]   ; 10.231 ; 10.233 ; 10.611 ; 10.613 ;
+; X[4]       ; Output[9]   ; 10.108 ; 10.170 ; 10.488 ; 10.550 ;
+; Y[0]       ; Output[0]   ; 6.301  ;        ;        ; 6.651  ;
+; Y[0]       ; Output[1]   ; 6.199  ; 6.143  ; 6.569  ; 6.505  ;
+; Y[0]       ; Output[2]   ; 8.282  ; 8.382  ; 8.653  ; 8.753  ;
+; Y[0]       ; Output[3]   ; 8.067  ; 8.031  ; 8.438  ; 8.402  ;
+; Y[0]       ; Output[4]   ; 9.770  ; 9.754  ; 10.141 ; 10.125 ;
+; Y[0]       ; Output[5]   ; 10.391 ; 10.401 ; 10.762 ; 10.772 ;
+; Y[0]       ; Output[6]   ; 11.082 ; 11.059 ; 11.453 ; 11.430 ;
+; Y[0]       ; Output[7]   ; 11.271 ; 11.258 ; 11.642 ; 11.629 ;
+; Y[0]       ; Output[8]   ; 11.806 ; 11.808 ; 12.177 ; 12.179 ;
+; Y[0]       ; Output[9]   ; 11.683 ; 11.745 ; 12.054 ; 12.116 ;
+; Y[1]       ; Output[1]   ; 6.137  ; 6.083  ; 6.507  ; 6.500  ;
+; Y[1]       ; Output[2]   ; 8.469  ; 8.561  ; 8.876  ; 8.971  ;
+; Y[1]       ; Output[3]   ; 8.261  ; 8.225  ; 8.668  ; 8.632  ;
+; Y[1]       ; Output[4]   ; 9.962  ; 9.946  ; 10.369 ; 10.353 ;
+; Y[1]       ; Output[5]   ; 10.583 ; 10.593 ; 10.990 ; 11.000 ;
+; Y[1]       ; Output[6]   ; 11.266 ; 11.243 ; 11.673 ; 11.650 ;
+; Y[1]       ; Output[7]   ; 11.455 ; 11.442 ; 11.862 ; 11.849 ;
+; Y[1]       ; Output[8]   ; 11.990 ; 11.992 ; 12.397 ; 12.399 ;
+; Y[1]       ; Output[9]   ; 11.867 ; 11.929 ; 12.274 ; 12.336 ;
+; Y[2]       ; Output[2]   ; 7.670  ; 7.769  ; 8.010  ; 8.128  ;
+; Y[2]       ; Output[3]   ; 7.420  ; 7.384  ; 7.787  ; 7.751  ;
+; Y[2]       ; Output[4]   ; 9.037  ; 9.033  ; 9.404  ; 9.400  ;
+; Y[2]       ; Output[5]   ; 9.667  ; 9.677  ; 10.034 ; 10.044 ;
+; Y[2]       ; Output[6]   ; 10.358 ; 10.335 ; 10.725 ; 10.702 ;
+; Y[2]       ; Output[7]   ; 10.547 ; 10.534 ; 10.914 ; 10.901 ;
+; Y[2]       ; Output[8]   ; 11.082 ; 11.084 ; 11.449 ; 11.451 ;
+; Y[2]       ; Output[9]   ; 10.959 ; 11.021 ; 11.326 ; 11.388 ;
+; Y[3]       ; Output[3]   ; 6.146  ; 6.116  ; 6.498  ; 6.498  ;
+; Y[3]       ; Output[4]   ; 7.739  ; 7.737  ; 8.148  ; 8.144  ;
+; Y[3]       ; Output[5]   ; 8.039  ; 7.999  ; 8.446  ; 8.406  ;
+; Y[3]       ; Output[6]   ; 8.722  ; 8.673  ; 9.129  ; 9.080  ;
+; Y[3]       ; Output[7]   ; 8.902  ; 8.881  ; 9.309  ; 9.288  ;
+; Y[3]       ; Output[8]   ; 9.437  ; 9.439  ; 9.844  ; 9.846  ;
+; Y[3]       ; Output[9]   ; 9.275  ; 9.376  ; 9.696  ; 9.783  ;
+; Y[4]       ; Output[4]   ; 6.302  ; 6.301  ; 6.706  ; 6.670  ;
+; Y[4]       ; Output[5]   ; 6.594  ; 6.562  ; 7.019  ; 6.979  ;
+; Y[4]       ; Output[6]   ; 6.752  ; 6.711  ; 7.181  ; 7.132  ;
+; Y[4]       ; Output[7]   ; 6.932  ; 6.919  ; 7.361  ; 7.340  ;
+; Y[4]       ; Output[8]   ; 7.446  ; 7.462  ; 7.896  ; 7.898  ;
+; Y[4]       ; Output[9]   ; 7.389  ;        ;        ; 7.835  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; X[0]       ; Output[0]   ; 6.059 ;       ;       ; 6.425 ;
+; X[0]       ; Output[1]   ; 6.219 ; 6.211 ; 6.591 ; 6.526 ;
+; X[0]       ; Output[2]   ; 7.237 ; 7.334 ; 7.575 ; 7.700 ;
+; X[0]       ; Output[3]   ; 5.874 ; 5.838 ; 6.228 ; 6.225 ;
+; X[0]       ; Output[4]   ; 5.909 ; 5.879 ; 6.250 ; 6.214 ;
+; X[0]       ; Output[5]   ; 6.025 ; 5.993 ; 6.365 ; 6.359 ;
+; X[0]       ; Output[6]   ; 6.799 ; 6.759 ; 7.205 ; 7.159 ;
+; X[0]       ; Output[7]   ; 6.972 ; 6.959 ; 7.379 ; 7.360 ;
+; X[0]       ; Output[8]   ; 7.411 ; 7.426 ; 7.836 ; 7.841 ;
+; X[0]       ; Output[9]   ; 7.377 ; 8.801 ; 9.127 ; 7.783 ;
+; X[1]       ; Output[1]   ; 6.131 ; 6.077 ; 6.478 ; 6.451 ;
+; X[1]       ; Output[2]   ; 8.171 ; 8.264 ; 8.548 ; 8.641 ;
+; X[1]       ; Output[3]   ; 6.559 ; 6.531 ; 6.940 ; 6.912 ;
+; X[1]       ; Output[4]   ; 7.119 ; 7.089 ; 7.490 ; 7.460 ;
+; X[1]       ; Output[5]   ; 6.136 ; 6.125 ; 6.518 ; 6.463 ;
+; X[1]       ; Output[6]   ; 6.359 ; 6.319 ; 6.726 ; 6.680 ;
+; X[1]       ; Output[7]   ; 6.532 ; 6.519 ; 6.900 ; 6.881 ;
+; X[1]       ; Output[8]   ; 6.971 ; 6.986 ; 7.357 ; 7.362 ;
+; X[1]       ; Output[9]   ; 6.937 ; 8.592 ; 8.895 ; 7.304 ;
+; X[2]       ; Output[2]   ; 7.669 ; 7.762 ; 8.029 ; 8.128 ;
+; X[2]       ; Output[3]   ; 7.150 ; 7.116 ; 7.524 ; 7.490 ;
+; X[2]       ; Output[4]   ; 7.296 ; 7.277 ; 7.670 ; 7.653 ;
+; X[2]       ; Output[5]   ; 6.933 ; 6.916 ; 7.297 ; 7.275 ;
+; X[2]       ; Output[6]   ; 6.195 ; 6.180 ; 6.557 ; 6.530 ;
+; X[2]       ; Output[7]   ; 6.381 ; 6.368 ; 6.730 ; 6.711 ;
+; X[2]       ; Output[8]   ; 6.820 ; 6.835 ; 7.187 ; 7.192 ;
+; X[2]       ; Output[9]   ; 6.786 ; 7.969 ; 8.276 ; 7.134 ;
+; X[3]       ; Output[3]   ; 7.213 ; 7.183 ; 7.588 ; 7.554 ;
+; X[3]       ; Output[4]   ; 8.090 ; 8.077 ; 8.482 ; 8.469 ;
+; X[3]       ; Output[5]   ; 7.812 ; 7.776 ; 8.181 ; 8.145 ;
+; X[3]       ; Output[6]   ; 7.087 ; 7.071 ; 7.474 ; 7.458 ;
+; X[3]       ; Output[7]   ; 5.821 ; 5.806 ; 6.159 ; 6.172 ;
+; X[3]       ; Output[8]   ; 6.259 ; 6.274 ; 6.647 ; 6.652 ;
+; X[3]       ; Output[9]   ; 6.225 ; 7.677 ; 8.052 ; 6.594 ;
+; X[4]       ; Output[4]   ; 7.875 ; 7.856 ; 8.218 ; 8.199 ;
+; X[4]       ; Output[5]   ; 7.931 ; 7.895 ; 8.312 ; 8.276 ;
+; X[4]       ; Output[6]   ; 7.904 ; 7.888 ; 8.274 ; 8.258 ;
+; X[4]       ; Output[7]   ; 7.221 ; 7.233 ; 7.608 ; 7.614 ;
+; X[4]       ; Output[8]   ; 6.130 ; 6.144 ; 6.503 ; 6.507 ;
+; X[4]       ; Output[9]   ; 6.114 ; 7.641 ; 8.015 ; 6.447 ;
+; Y[0]       ; Output[0]   ; 6.121 ;       ;       ; 6.452 ;
+; Y[0]       ; Output[1]   ; 6.066 ; 6.012 ; 6.426 ; 6.366 ;
+; Y[0]       ; Output[2]   ; 7.974 ; 8.073 ; 8.352 ; 8.451 ;
+; Y[0]       ; Output[3]   ; 7.226 ; 7.196 ; 7.590 ; 7.556 ;
+; Y[0]       ; Output[4]   ; 7.992 ; 7.973 ; 8.363 ; 8.344 ;
+; Y[0]       ; Output[5]   ; 8.092 ; 8.056 ; 8.450 ; 8.414 ;
+; Y[0]       ; Output[6]   ; 8.033 ; 8.017 ; 8.380 ; 8.364 ;
+; Y[0]       ; Output[7]   ; 8.104 ; 8.116 ; 8.467 ; 8.474 ;
+; Y[0]       ; Output[8]   ; 7.943 ; 7.933 ; 8.291 ; 8.275 ;
+; Y[0]       ; Output[9]   ; 7.911 ; 7.993 ; 8.373 ; 8.238 ;
+; Y[1]       ; Output[1]   ; 5.965 ; 5.956 ; 6.367 ; 6.308 ;
+; Y[1]       ; Output[2]   ; 8.001 ; 8.094 ; 8.395 ; 8.488 ;
+; Y[1]       ; Output[3]   ; 7.296 ; 7.262 ; 7.691 ; 7.661 ;
+; Y[1]       ; Output[4]   ; 7.831 ; 7.812 ; 8.186 ; 8.167 ;
+; Y[1]       ; Output[5]   ; 7.772 ; 7.736 ; 8.157 ; 8.121 ;
+; Y[1]       ; Output[6]   ; 7.861 ; 7.845 ; 8.211 ; 8.195 ;
+; Y[1]       ; Output[7]   ; 7.932 ; 7.944 ; 8.298 ; 8.305 ;
+; Y[1]       ; Output[8]   ; 7.771 ; 7.761 ; 8.122 ; 8.106 ;
+; Y[1]       ; Output[9]   ; 7.739 ; 7.821 ; 8.204 ; 8.069 ;
+; Y[2]       ; Output[2]   ; 7.517 ; 7.609 ; 7.833 ; 7.958 ;
+; Y[2]       ; Output[3]   ; 6.641 ; 6.609 ; 6.969 ; 6.941 ;
+; Y[2]       ; Output[4]   ; 7.886 ; 7.873 ; 8.231 ; 8.212 ;
+; Y[2]       ; Output[5]   ; 8.143 ; 8.111 ; 8.488 ; 8.456 ;
+; Y[2]       ; Output[6]   ; 7.801 ; 7.785 ; 8.158 ; 8.142 ;
+; Y[2]       ; Output[7]   ; 7.870 ; 7.882 ; 8.277 ; 8.284 ;
+; Y[2]       ; Output[8]   ; 7.709 ; 7.699 ; 8.101 ; 8.085 ;
+; Y[2]       ; Output[9]   ; 7.677 ; 7.759 ; 8.151 ; 8.048 ;
+; Y[3]       ; Output[3]   ; 6.016 ; 5.986 ; 6.360 ; 6.358 ;
+; Y[3]       ; Output[4]   ; 7.038 ; 7.021 ; 7.406 ; 7.376 ;
+; Y[3]       ; Output[5]   ; 7.108 ; 7.072 ; 7.464 ; 7.447 ;
+; Y[3]       ; Output[6]   ; 7.235 ; 7.219 ; 7.582 ; 7.566 ;
+; Y[3]       ; Output[7]   ; 7.132 ; 7.134 ; 7.492 ; 7.504 ;
+; Y[3]       ; Output[8]   ; 6.984 ; 6.974 ; 7.344 ; 7.328 ;
+; Y[3]       ; Output[9]   ; 6.952 ; 7.538 ; 7.899 ; 7.291 ;
+; Y[4]       ; Output[4]   ; 6.153 ; 6.148 ; 6.543 ; 6.509 ;
+; Y[4]       ; Output[5]   ; 6.417 ; 6.385 ; 6.802 ; 6.764 ;
+; Y[4]       ; Output[6]   ; 6.218 ; 6.176 ; 6.577 ; 6.563 ;
+; Y[4]       ; Output[7]   ; 6.186 ; 6.197 ; 6.572 ; 6.573 ;
+; Y[4]       ; Output[8]   ; 6.129 ; 6.117 ; 6.490 ; 6.506 ;
+; Y[4]       ; Output[9]   ; 6.099 ;       ;       ; 6.470 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; X[0]       ; Output[0]   ; 3.987 ;       ;       ; 4.605 ;
+; X[0]       ; Output[1]   ; 4.075 ; 4.097 ; 4.653 ; 4.700 ;
+; X[0]       ; Output[2]   ; 5.446 ; 5.625 ; 6.051 ; 6.230 ;
+; X[0]       ; Output[3]   ; 5.288 ; 5.284 ; 5.893 ; 5.889 ;
+; X[0]       ; Output[4]   ; 6.379 ; 6.424 ; 6.984 ; 7.029 ;
+; X[0]       ; Output[5]   ; 6.799 ; 6.843 ; 7.404 ; 7.448 ;
+; X[0]       ; Output[6]   ; 7.229 ; 7.257 ; 7.834 ; 7.862 ;
+; X[0]       ; Output[7]   ; 7.355 ; 7.373 ; 7.960 ; 7.978 ;
+; X[0]       ; Output[8]   ; 7.697 ; 7.723 ; 8.302 ; 8.328 ;
+; X[0]       ; Output[9]   ; 7.548 ; 7.683 ; 8.153 ; 8.288 ;
+; X[1]       ; Output[1]   ; 4.002 ; 4.028 ; 4.559 ; 4.604 ;
+; X[1]       ; Output[2]   ; 5.550 ; 5.729 ; 6.155 ; 6.334 ;
+; X[1]       ; Output[3]   ; 5.392 ; 5.388 ; 5.997 ; 5.993 ;
+; X[1]       ; Output[4]   ; 6.483 ; 6.528 ; 7.088 ; 7.133 ;
+; X[1]       ; Output[5]   ; 6.903 ; 6.947 ; 7.508 ; 7.552 ;
+; X[1]       ; Output[6]   ; 7.333 ; 7.361 ; 7.938 ; 7.966 ;
+; X[1]       ; Output[7]   ; 7.459 ; 7.477 ; 8.064 ; 8.082 ;
+; X[1]       ; Output[8]   ; 7.801 ; 7.827 ; 8.406 ; 8.432 ;
+; X[1]       ; Output[9]   ; 7.652 ; 7.787 ; 8.257 ; 8.392 ;
+; X[2]       ; Output[2]   ; 5.083 ; 5.262 ; 5.651 ; 5.830 ;
+; X[2]       ; Output[3]   ; 4.925 ; 4.921 ; 5.493 ; 5.489 ;
+; X[2]       ; Output[4]   ; 6.016 ; 6.061 ; 6.584 ; 6.629 ;
+; X[2]       ; Output[5]   ; 6.436 ; 6.480 ; 7.004 ; 7.048 ;
+; X[2]       ; Output[6]   ; 6.866 ; 6.894 ; 7.434 ; 7.462 ;
+; X[2]       ; Output[7]   ; 6.992 ; 7.010 ; 7.560 ; 7.578 ;
+; X[2]       ; Output[8]   ; 7.334 ; 7.360 ; 7.902 ; 7.928 ;
+; X[2]       ; Output[9]   ; 7.185 ; 7.320 ; 7.753 ; 7.888 ;
+; X[3]       ; Output[3]   ; 4.831 ; 4.827 ; 5.409 ; 5.405 ;
+; X[3]       ; Output[4]   ; 5.869 ; 5.914 ; 6.447 ; 6.492 ;
+; X[3]       ; Output[5]   ; 6.276 ; 6.320 ; 6.854 ; 6.898 ;
+; X[3]       ; Output[6]   ; 6.706 ; 6.734 ; 7.284 ; 7.312 ;
+; X[3]       ; Output[7]   ; 6.832 ; 6.850 ; 7.410 ; 7.428 ;
+; X[3]       ; Output[8]   ; 7.174 ; 7.200 ; 7.752 ; 7.778 ;
+; X[3]       ; Output[9]   ; 7.025 ; 7.160 ; 7.603 ; 7.738 ;
+; X[4]       ; Output[4]   ; 5.270 ; 5.315 ; 5.844 ; 5.889 ;
+; X[4]       ; Output[5]   ; 5.690 ; 5.734 ; 6.264 ; 6.308 ;
+; X[4]       ; Output[6]   ; 6.120 ; 6.148 ; 6.694 ; 6.722 ;
+; X[4]       ; Output[7]   ; 6.246 ; 6.264 ; 6.820 ; 6.838 ;
+; X[4]       ; Output[8]   ; 6.588 ; 6.614 ; 7.162 ; 7.188 ;
+; X[4]       ; Output[9]   ; 6.439 ; 6.574 ; 7.013 ; 7.148 ;
+; Y[0]       ; Output[0]   ; 4.041 ;       ;       ; 4.665 ;
+; Y[0]       ; Output[1]   ; 3.962 ; 3.991 ; 4.541 ; 4.563 ;
+; Y[0]       ; Output[2]   ; 5.360 ; 5.539 ; 5.946 ; 6.125 ;
+; Y[0]       ; Output[3]   ; 5.202 ; 5.198 ; 5.788 ; 5.784 ;
+; Y[0]       ; Output[4]   ; 6.293 ; 6.338 ; 6.879 ; 6.924 ;
+; Y[0]       ; Output[5]   ; 6.713 ; 6.757 ; 7.299 ; 7.343 ;
+; Y[0]       ; Output[6]   ; 7.143 ; 7.171 ; 7.729 ; 7.757 ;
+; Y[0]       ; Output[7]   ; 7.269 ; 7.287 ; 7.855 ; 7.873 ;
+; Y[0]       ; Output[8]   ; 7.611 ; 7.637 ; 8.197 ; 8.223 ;
+; Y[0]       ; Output[9]   ; 7.462 ; 7.597 ; 8.048 ; 8.183 ;
+; Y[1]       ; Output[1]   ; 3.922 ; 3.945 ; 4.483 ; 4.532 ;
+; Y[1]       ; Output[2]   ; 5.469 ; 5.648 ; 6.069 ; 6.248 ;
+; Y[1]       ; Output[3]   ; 5.311 ; 5.307 ; 5.911 ; 5.907 ;
+; Y[1]       ; Output[4]   ; 6.402 ; 6.447 ; 7.002 ; 7.047 ;
+; Y[1]       ; Output[5]   ; 6.822 ; 6.866 ; 7.422 ; 7.466 ;
+; Y[1]       ; Output[6]   ; 7.252 ; 7.280 ; 7.852 ; 7.880 ;
+; Y[1]       ; Output[7]   ; 7.378 ; 7.396 ; 7.978 ; 7.996 ;
+; Y[1]       ; Output[8]   ; 7.720 ; 7.746 ; 8.320 ; 8.346 ;
+; Y[1]       ; Output[9]   ; 7.571 ; 7.706 ; 8.171 ; 8.306 ;
+; Y[2]       ; Output[2]   ; 4.964 ; 5.145 ; 5.546 ; 5.736 ;
+; Y[2]       ; Output[3]   ; 4.757 ; 4.753 ; 5.373 ; 5.369 ;
+; Y[2]       ; Output[4]   ; 5.795 ; 5.840 ; 6.411 ; 6.456 ;
+; Y[2]       ; Output[5]   ; 6.202 ; 6.246 ; 6.818 ; 6.862 ;
+; Y[2]       ; Output[6]   ; 6.632 ; 6.660 ; 7.248 ; 7.276 ;
+; Y[2]       ; Output[7]   ; 6.758 ; 6.776 ; 7.374 ; 7.392 ;
+; Y[2]       ; Output[8]   ; 7.100 ; 7.126 ; 7.716 ; 7.742 ;
+; Y[2]       ; Output[9]   ; 6.951 ; 7.086 ; 7.567 ; 7.702 ;
+; Y[3]       ; Output[3]   ; 3.964 ; 3.964 ; 4.548 ; 4.567 ;
+; Y[3]       ; Output[4]   ; 4.973 ; 5.018 ; 5.598 ; 5.643 ;
+; Y[3]       ; Output[5]   ; 5.159 ; 5.179 ; 5.784 ; 5.804 ;
+; Y[3]       ; Output[6]   ; 5.591 ; 5.611 ; 6.216 ; 6.236 ;
+; Y[3]       ; Output[7]   ; 5.720 ; 5.738 ; 6.345 ; 6.363 ;
+; Y[3]       ; Output[8]   ; 6.062 ; 6.088 ; 6.687 ; 6.713 ;
+; Y[3]       ; Output[9]   ; 5.857 ; 6.048 ; 6.495 ; 6.673 ;
+; Y[4]       ; Output[4]   ; 4.072 ; 4.118 ; 4.671 ; 4.689 ;
+; Y[4]       ; Output[5]   ; 4.247 ; 4.274 ; 4.859 ; 4.879 ;
+; Y[4]       ; Output[6]   ; 4.350 ; 4.377 ; 4.966 ; 4.986 ;
+; Y[4]       ; Output[7]   ; 4.466 ; 4.491 ; 5.095 ; 5.113 ;
+; Y[4]       ; Output[8]   ; 4.773 ; 4.812 ; 5.437 ; 5.463 ;
+; Y[4]       ; Output[9]   ; 4.742 ;       ;       ; 5.423 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; X[0]       ; Output[0]   ; 3.897 ;       ;       ; 4.506 ;
+; X[0]       ; Output[1]   ; 3.953 ; 4.002 ; 4.553 ; 4.567 ;
+; X[0]       ; Output[2]   ; 4.684 ; 4.865 ; 5.240 ; 5.440 ;
+; X[0]       ; Output[3]   ; 3.784 ; 3.771 ; 4.352 ; 4.363 ;
+; X[0]       ; Output[4]   ; 3.797 ; 3.825 ; 4.357 ; 4.378 ;
+; X[0]       ; Output[5]   ; 3.868 ; 3.890 ; 4.424 ; 4.465 ;
+; X[0]       ; Output[6]   ; 4.328 ; 4.354 ; 4.948 ; 4.967 ;
+; X[0]       ; Output[7]   ; 4.440 ; 4.464 ; 5.074 ; 5.091 ;
+; X[0]       ; Output[8]   ; 4.702 ; 4.736 ; 5.361 ; 5.395 ;
+; X[0]       ; Output[9]   ; 4.684 ; 5.670 ; 6.116 ; 5.354 ;
+; X[1]       ; Output[1]   ; 3.911 ; 3.935 ; 4.462 ; 4.505 ;
+; X[1]       ; Output[2]   ; 5.232 ; 5.417 ; 5.819 ; 6.004 ;
+; X[1]       ; Output[3]   ; 4.168 ; 4.171 ; 4.760 ; 4.763 ;
+; X[1]       ; Output[4]   ; 4.547 ; 4.571 ; 5.145 ; 5.169 ;
+; X[1]       ; Output[5]   ; 3.940 ; 3.976 ; 4.538 ; 4.539 ;
+; X[1]       ; Output[6]   ; 4.072 ; 4.098 ; 4.662 ; 4.681 ;
+; X[1]       ; Output[7]   ; 4.184 ; 4.208 ; 4.788 ; 4.805 ;
+; X[1]       ; Output[8]   ; 4.446 ; 4.480 ; 5.075 ; 5.109 ;
+; X[1]       ; Output[9]   ; 4.428 ; 5.555 ; 5.995 ; 5.068 ;
+; X[2]       ; Output[2]   ; 4.929 ; 5.114 ; 5.473 ; 5.658 ;
+; X[2]       ; Output[3]   ; 4.496 ; 4.499 ; 5.072 ; 5.075 ;
+; X[2]       ; Output[4]   ; 4.625 ; 4.649 ; 5.191 ; 5.215 ;
+; X[2]       ; Output[5]   ; 4.416 ; 4.444 ; 4.999 ; 5.027 ;
+; X[2]       ; Output[6]   ; 3.982 ; 4.015 ; 4.549 ; 4.581 ;
+; X[2]       ; Output[7]   ; 4.099 ; 4.123 ; 4.672 ; 4.689 ;
+; X[2]       ; Output[8]   ; 4.361 ; 4.395 ; 4.959 ; 4.993 ;
+; X[2]       ; Output[9]   ; 4.343 ; 5.155 ; 5.595 ; 4.952 ;
+; X[3]       ; Output[3]   ; 4.549 ; 4.552 ; 5.146 ; 5.149 ;
+; X[3]       ; Output[4]   ; 5.106 ; 5.130 ; 5.703 ; 5.727 ;
+; X[3]       ; Output[5]   ; 4.947 ; 4.975 ; 5.555 ; 5.583 ;
+; X[3]       ; Output[6]   ; 4.510 ; 4.541 ; 5.116 ; 5.147 ;
+; X[3]       ; Output[7]   ; 3.763 ; 3.782 ; 4.299 ; 4.338 ;
+; X[3]       ; Output[8]   ; 4.023 ; 4.057 ; 4.606 ; 4.640 ;
+; X[3]       ; Output[9]   ; 4.005 ; 4.966 ; 5.470 ; 4.599 ;
+; X[4]       ; Output[4]   ; 4.976 ; 5.000 ; 5.525 ; 5.549 ;
+; X[4]       ; Output[5]   ; 5.007 ; 5.035 ; 5.642 ; 5.670 ;
+; X[4]       ; Output[6]   ; 4.985 ; 5.016 ; 5.604 ; 5.635 ;
+; X[4]       ; Output[7]   ; 4.619 ; 4.650 ; 5.221 ; 5.252 ;
+; X[4]       ; Output[8]   ; 3.964 ; 3.996 ; 4.546 ; 4.575 ;
+; X[4]       ; Output[9]   ; 3.956 ; 4.961 ; 5.466 ; 4.536 ;
+; Y[0]       ; Output[0]   ; 3.923 ;       ;       ; 4.528 ;
+; Y[0]       ; Output[1]   ; 3.872 ; 3.900 ; 4.445 ; 4.466 ;
+; Y[0]       ; Output[2]   ; 5.125 ; 5.310 ; 5.702 ; 5.887 ;
+; Y[0]       ; Output[3]   ; 4.554 ; 4.557 ; 5.159 ; 5.162 ;
+; Y[0]       ; Output[4]   ; 5.049 ; 5.073 ; 5.631 ; 5.655 ;
+; Y[0]       ; Output[5]   ; 5.105 ; 5.133 ; 5.739 ; 5.767 ;
+; Y[0]       ; Output[6]   ; 5.063 ; 5.094 ; 5.684 ; 5.715 ;
+; Y[0]       ; Output[7]   ; 5.124 ; 5.155 ; 5.770 ; 5.801 ;
+; Y[0]       ; Output[8]   ; 5.023 ; 5.050 ; 5.697 ; 5.724 ;
+; Y[0]       ; Output[9]   ; 5.006 ; 5.148 ; 5.680 ; 5.705 ;
+; Y[1]       ; Output[1]   ; 3.806 ; 3.856 ; 4.389 ; 4.405 ;
+; Y[1]       ; Output[2]   ; 5.120 ; 5.305 ; 5.709 ; 5.894 ;
+; Y[1]       ; Output[3]   ; 4.591 ; 4.594 ; 5.157 ; 5.160 ;
+; Y[1]       ; Output[4]   ; 4.929 ; 4.953 ; 5.489 ; 5.513 ;
+; Y[1]       ; Output[5]   ; 4.906 ; 4.934 ; 5.528 ; 5.556 ;
+; Y[1]       ; Output[6]   ; 4.937 ; 4.968 ; 5.546 ; 5.577 ;
+; Y[1]       ; Output[7]   ; 4.998 ; 5.029 ; 5.632 ; 5.663 ;
+; Y[1]       ; Output[8]   ; 4.897 ; 4.924 ; 5.559 ; 5.586 ;
+; Y[1]       ; Output[9]   ; 4.880 ; 5.022 ; 5.542 ; 5.567 ;
+; Y[2]       ; Output[2]   ; 4.862 ; 5.034 ; 5.422 ; 5.616 ;
+; Y[2]       ; Output[3]   ; 4.213 ; 4.216 ; 4.772 ; 4.775 ;
+; Y[2]       ; Output[4]   ; 5.005 ; 5.029 ; 5.580 ; 5.604 ;
+; Y[2]       ; Output[5]   ; 5.148 ; 5.174 ; 5.723 ; 5.749 ;
+; Y[2]       ; Output[6]   ; 4.934 ; 4.965 ; 5.517 ; 5.548 ;
+; Y[2]       ; Output[7]   ; 4.996 ; 5.027 ; 5.627 ; 5.651 ;
+; Y[2]       ; Output[8]   ; 4.895 ; 4.922 ; 5.530 ; 5.557 ;
+; Y[2]       ; Output[9]   ; 4.878 ; 5.014 ; 5.513 ; 5.562 ;
+; Y[3]       ; Output[3]   ; 3.875 ; 3.874 ; 4.452 ; 4.470 ;
+; Y[3]       ; Output[4]   ; 4.504 ; 4.528 ; 5.083 ; 5.107 ;
+; Y[3]       ; Output[5]   ; 4.540 ; 4.568 ; 5.119 ; 5.147 ;
+; Y[3]       ; Output[6]   ; 4.621 ; 4.652 ; 5.202 ; 5.233 ;
+; Y[3]       ; Output[7]   ; 4.576 ; 4.607 ; 5.158 ; 5.189 ;
+; Y[3]       ; Output[8]   ; 4.474 ; 4.501 ; 5.111 ; 5.131 ;
+; Y[3]       ; Output[9]   ; 4.457 ; 4.908 ; 5.403 ; 5.107 ;
+; Y[4]       ; Output[4]   ; 3.975 ; 4.009 ; 4.560 ; 4.577 ;
+; Y[4]       ; Output[5]   ; 4.127 ; 4.153 ; 4.719 ; 4.738 ;
+; Y[4]       ; Output[6]   ; 4.015 ; 4.036 ; 4.573 ; 4.614 ;
+; Y[4]       ; Output[7]   ; 4.016 ; 4.045 ; 4.606 ; 4.632 ;
+; Y[4]       ; Output[8]   ; 3.983 ; 4.005 ; 4.542 ; 4.584 ;
+; Y[4]       ; Output[9]   ; 3.967 ;       ;       ; 4.560 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; X[0]       ; Output[0]   ; 6.667  ;        ;        ; 7.128  ;
+; X[0]       ; Output[1]   ; 6.889  ; 6.849  ; 7.290  ; 7.298  ;
+; X[0]       ; Output[2]   ; 9.015  ; 9.130  ; 9.464  ; 9.584  ;
+; X[0]       ; Output[3]   ; 8.936  ; 8.909  ; 9.381  ; 9.354  ;
+; X[0]       ; Output[4]   ; 10.800 ; 10.822 ; 11.245 ; 11.267 ;
+; X[0]       ; Output[5]   ; 11.521 ; 11.553 ; 11.966 ; 11.998 ;
+; X[0]       ; Output[6]   ; 12.272 ; 12.287 ; 12.717 ; 12.732 ;
+; X[0]       ; Output[7]   ; 12.499 ; 12.505 ; 12.944 ; 12.950 ;
+; X[0]       ; Output[8]   ; 13.102 ; 13.131 ; 13.547 ; 13.576 ;
+; X[0]       ; Output[9]   ; 12.944 ; 13.060 ; 13.389 ; 13.505 ;
+; X[1]       ; Output[1]   ; 6.727  ; 6.689  ; 7.149  ; 7.142  ;
+; X[1]       ; Output[2]   ; 9.187  ; 9.298  ; 9.666  ; 9.777  ;
+; X[1]       ; Output[3]   ; 9.108  ; 9.081  ; 9.587  ; 9.560  ;
+; X[1]       ; Output[4]   ; 10.972 ; 10.994 ; 11.451 ; 11.473 ;
+; X[1]       ; Output[5]   ; 11.693 ; 11.725 ; 12.172 ; 12.204 ;
+; X[1]       ; Output[6]   ; 12.444 ; 12.459 ; 12.923 ; 12.938 ;
+; X[1]       ; Output[7]   ; 12.671 ; 12.677 ; 13.150 ; 13.156 ;
+; X[1]       ; Output[8]   ; 13.274 ; 13.303 ; 13.753 ; 13.782 ;
+; X[1]       ; Output[9]   ; 13.116 ; 13.232 ; 13.595 ; 13.711 ;
+; X[2]       ; Output[2]   ; 8.348  ; 8.465  ; 8.788  ; 8.899  ;
+; X[2]       ; Output[3]   ; 8.269  ; 8.242  ; 8.709  ; 8.682  ;
+; X[2]       ; Output[4]   ; 10.133 ; 10.155 ; 10.573 ; 10.595 ;
+; X[2]       ; Output[5]   ; 10.854 ; 10.886 ; 11.294 ; 11.326 ;
+; X[2]       ; Output[6]   ; 11.605 ; 11.620 ; 12.045 ; 12.060 ;
+; X[2]       ; Output[7]   ; 11.832 ; 11.838 ; 12.272 ; 12.278 ;
+; X[2]       ; Output[8]   ; 12.435 ; 12.464 ; 12.875 ; 12.904 ;
+; X[2]       ; Output[9]   ; 12.277 ; 12.393 ; 12.717 ; 12.833 ;
+; X[3]       ; Output[3]   ; 8.081  ; 8.054  ; 8.507  ; 8.480  ;
+; X[3]       ; Output[4]   ; 9.892  ; 9.914  ; 10.318 ; 10.340 ;
+; X[3]       ; Output[5]   ; 10.588 ; 10.620 ; 11.014 ; 11.046 ;
+; X[3]       ; Output[6]   ; 11.339 ; 11.354 ; 11.765 ; 11.780 ;
+; X[3]       ; Output[7]   ; 11.566 ; 11.572 ; 11.992 ; 11.998 ;
+; X[3]       ; Output[8]   ; 12.169 ; 12.198 ; 12.595 ; 12.624 ;
+; X[3]       ; Output[9]   ; 12.011 ; 12.127 ; 12.437 ; 12.553 ;
+; X[4]       ; Output[4]   ; 8.892  ; 8.914  ; 9.343  ; 9.365  ;
+; X[4]       ; Output[5]   ; 9.613  ; 9.645  ; 10.064 ; 10.096 ;
+; X[4]       ; Output[6]   ; 10.364 ; 10.379 ; 10.815 ; 10.830 ;
+; X[4]       ; Output[7]   ; 10.591 ; 10.597 ; 11.042 ; 11.048 ;
+; X[4]       ; Output[8]   ; 11.194 ; 11.223 ; 11.645 ; 11.674 ;
+; X[4]       ; Output[9]   ; 11.036 ; 11.152 ; 11.487 ; 11.603 ;
+; Y[0]       ; Output[0]   ; 6.786  ;        ;        ; 7.225  ;
+; Y[0]       ; Output[1]   ; 6.657  ; 6.619  ; 7.098  ; 7.051  ;
+; Y[0]       ; Output[2]   ; 8.834  ; 8.949  ; 9.280  ; 9.400  ;
+; Y[0]       ; Output[3]   ; 8.755  ; 8.728  ; 9.197  ; 9.170  ;
+; Y[0]       ; Output[4]   ; 10.619 ; 10.641 ; 11.061 ; 11.083 ;
+; Y[0]       ; Output[5]   ; 11.340 ; 11.372 ; 11.782 ; 11.814 ;
+; Y[0]       ; Output[6]   ; 12.091 ; 12.106 ; 12.533 ; 12.548 ;
+; Y[0]       ; Output[7]   ; 12.318 ; 12.324 ; 12.760 ; 12.766 ;
+; Y[0]       ; Output[8]   ; 12.921 ; 12.950 ; 13.363 ; 13.392 ;
+; Y[0]       ; Output[9]   ; 12.763 ; 12.879 ; 13.205 ; 13.321 ;
+; Y[1]       ; Output[1]   ; 6.597  ; 6.558  ; 7.020  ; 7.035  ;
+; Y[1]       ; Output[2]   ; 9.057  ; 9.168  ; 9.536  ; 9.647  ;
+; Y[1]       ; Output[3]   ; 8.978  ; 8.951  ; 9.457  ; 9.430  ;
+; Y[1]       ; Output[4]   ; 10.842 ; 10.864 ; 11.321 ; 11.343 ;
+; Y[1]       ; Output[5]   ; 11.563 ; 11.595 ; 12.042 ; 12.074 ;
+; Y[1]       ; Output[6]   ; 12.314 ; 12.329 ; 12.793 ; 12.808 ;
+; Y[1]       ; Output[7]   ; 12.541 ; 12.547 ; 13.020 ; 13.026 ;
+; Y[1]       ; Output[8]   ; 13.144 ; 13.173 ; 13.623 ; 13.652 ;
+; Y[1]       ; Output[9]   ; 12.986 ; 13.102 ; 13.465 ; 13.581 ;
+; Y[2]       ; Output[2]   ; 8.162  ; 8.282  ; 8.599  ; 8.738  ;
+; Y[2]       ; Output[3]   ; 8.026  ; 7.999  ; 8.503  ; 8.476  ;
+; Y[2]       ; Output[4]   ; 9.837  ; 9.859  ; 10.314 ; 10.336 ;
+; Y[2]       ; Output[5]   ; 10.533 ; 10.565 ; 11.010 ; 11.042 ;
+; Y[2]       ; Output[6]   ; 11.284 ; 11.299 ; 11.761 ; 11.776 ;
+; Y[2]       ; Output[7]   ; 11.511 ; 11.517 ; 11.988 ; 11.994 ;
+; Y[2]       ; Output[8]   ; 12.114 ; 12.143 ; 12.591 ; 12.620 ;
+; Y[2]       ; Output[9]   ; 11.956 ; 12.072 ; 12.433 ; 12.549 ;
+; Y[3]       ; Output[3]   ; 6.619  ; 6.599  ; 7.041  ; 7.053  ;
+; Y[3]       ; Output[4]   ; 8.401  ; 8.423  ; 8.887  ; 8.909  ;
+; Y[3]       ; Output[5]   ; 8.736  ; 8.716  ; 9.222  ; 9.202  ;
+; Y[3]       ; Output[6]   ; 9.489  ; 9.474  ; 9.975  ; 9.960  ;
+; Y[3]       ; Output[7]   ; 9.705  ; 9.711  ; 10.191 ; 10.197 ;
+; Y[3]       ; Output[8]   ; 10.308 ; 10.337 ; 10.794 ; 10.823 ;
+; Y[3]       ; Output[9]   ; 10.071 ; 10.266 ; 10.571 ; 10.752 ;
+; Y[4]       ; Output[4]   ; 6.784  ; 6.810  ; 7.246  ; 7.231  ;
+; Y[4]       ; Output[5]   ; 7.107  ; 7.096  ; 7.597  ; 7.577  ;
+; Y[4]       ; Output[6]   ; 7.265  ; 7.259  ; 7.758  ; 7.743  ;
+; Y[4]       ; Output[7]   ; 7.473  ; 7.488  ; 7.974  ; 7.980  ;
+; Y[4]       ; Output[8]   ; 8.044  ; 8.087  ; 8.577  ; 8.606  ;
+; Y[4]       ; Output[9]   ; 7.985  ;        ;        ; 8.535  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; X[0]       ; Output[0]   ; 3.897 ;       ;       ; 4.506 ;
+; X[0]       ; Output[1]   ; 3.953 ; 4.002 ; 4.553 ; 4.567 ;
+; X[0]       ; Output[2]   ; 4.684 ; 4.865 ; 5.240 ; 5.440 ;
+; X[0]       ; Output[3]   ; 3.784 ; 3.771 ; 4.352 ; 4.363 ;
+; X[0]       ; Output[4]   ; 3.797 ; 3.825 ; 4.357 ; 4.378 ;
+; X[0]       ; Output[5]   ; 3.868 ; 3.890 ; 4.424 ; 4.465 ;
+; X[0]       ; Output[6]   ; 4.328 ; 4.354 ; 4.948 ; 4.967 ;
+; X[0]       ; Output[7]   ; 4.440 ; 4.464 ; 5.074 ; 5.091 ;
+; X[0]       ; Output[8]   ; 4.702 ; 4.736 ; 5.361 ; 5.395 ;
+; X[0]       ; Output[9]   ; 4.684 ; 5.670 ; 6.116 ; 5.354 ;
+; X[1]       ; Output[1]   ; 3.911 ; 3.935 ; 4.462 ; 4.505 ;
+; X[1]       ; Output[2]   ; 5.232 ; 5.417 ; 5.819 ; 6.004 ;
+; X[1]       ; Output[3]   ; 4.168 ; 4.171 ; 4.760 ; 4.763 ;
+; X[1]       ; Output[4]   ; 4.547 ; 4.571 ; 5.145 ; 5.169 ;
+; X[1]       ; Output[5]   ; 3.940 ; 3.976 ; 4.538 ; 4.539 ;
+; X[1]       ; Output[6]   ; 4.072 ; 4.098 ; 4.662 ; 4.681 ;
+; X[1]       ; Output[7]   ; 4.184 ; 4.208 ; 4.788 ; 4.805 ;
+; X[1]       ; Output[8]   ; 4.446 ; 4.480 ; 5.075 ; 5.109 ;
+; X[1]       ; Output[9]   ; 4.428 ; 5.555 ; 5.995 ; 5.068 ;
+; X[2]       ; Output[2]   ; 4.929 ; 5.114 ; 5.473 ; 5.658 ;
+; X[2]       ; Output[3]   ; 4.496 ; 4.499 ; 5.072 ; 5.075 ;
+; X[2]       ; Output[4]   ; 4.625 ; 4.649 ; 5.191 ; 5.215 ;
+; X[2]       ; Output[5]   ; 4.416 ; 4.444 ; 4.999 ; 5.027 ;
+; X[2]       ; Output[6]   ; 3.982 ; 4.015 ; 4.549 ; 4.581 ;
+; X[2]       ; Output[7]   ; 4.099 ; 4.123 ; 4.672 ; 4.689 ;
+; X[2]       ; Output[8]   ; 4.361 ; 4.395 ; 4.959 ; 4.993 ;
+; X[2]       ; Output[9]   ; 4.343 ; 5.155 ; 5.595 ; 4.952 ;
+; X[3]       ; Output[3]   ; 4.549 ; 4.552 ; 5.146 ; 5.149 ;
+; X[3]       ; Output[4]   ; 5.106 ; 5.130 ; 5.703 ; 5.727 ;
+; X[3]       ; Output[5]   ; 4.947 ; 4.975 ; 5.555 ; 5.583 ;
+; X[3]       ; Output[6]   ; 4.510 ; 4.541 ; 5.116 ; 5.147 ;
+; X[3]       ; Output[7]   ; 3.763 ; 3.782 ; 4.299 ; 4.338 ;
+; X[3]       ; Output[8]   ; 4.023 ; 4.057 ; 4.606 ; 4.640 ;
+; X[3]       ; Output[9]   ; 4.005 ; 4.966 ; 5.470 ; 4.599 ;
+; X[4]       ; Output[4]   ; 4.976 ; 5.000 ; 5.525 ; 5.549 ;
+; X[4]       ; Output[5]   ; 5.007 ; 5.035 ; 5.642 ; 5.670 ;
+; X[4]       ; Output[6]   ; 4.985 ; 5.016 ; 5.604 ; 5.635 ;
+; X[4]       ; Output[7]   ; 4.619 ; 4.650 ; 5.221 ; 5.252 ;
+; X[4]       ; Output[8]   ; 3.964 ; 3.996 ; 4.546 ; 4.575 ;
+; X[4]       ; Output[9]   ; 3.956 ; 4.961 ; 5.466 ; 4.536 ;
+; Y[0]       ; Output[0]   ; 3.923 ;       ;       ; 4.528 ;
+; Y[0]       ; Output[1]   ; 3.872 ; 3.900 ; 4.445 ; 4.466 ;
+; Y[0]       ; Output[2]   ; 5.125 ; 5.310 ; 5.702 ; 5.887 ;
+; Y[0]       ; Output[3]   ; 4.554 ; 4.557 ; 5.159 ; 5.162 ;
+; Y[0]       ; Output[4]   ; 5.049 ; 5.073 ; 5.631 ; 5.655 ;
+; Y[0]       ; Output[5]   ; 5.105 ; 5.133 ; 5.739 ; 5.767 ;
+; Y[0]       ; Output[6]   ; 5.063 ; 5.094 ; 5.684 ; 5.715 ;
+; Y[0]       ; Output[7]   ; 5.124 ; 5.155 ; 5.770 ; 5.801 ;
+; Y[0]       ; Output[8]   ; 5.023 ; 5.050 ; 5.697 ; 5.724 ;
+; Y[0]       ; Output[9]   ; 5.006 ; 5.148 ; 5.680 ; 5.705 ;
+; Y[1]       ; Output[1]   ; 3.806 ; 3.856 ; 4.389 ; 4.405 ;
+; Y[1]       ; Output[2]   ; 5.120 ; 5.305 ; 5.709 ; 5.894 ;
+; Y[1]       ; Output[3]   ; 4.591 ; 4.594 ; 5.157 ; 5.160 ;
+; Y[1]       ; Output[4]   ; 4.929 ; 4.953 ; 5.489 ; 5.513 ;
+; Y[1]       ; Output[5]   ; 4.906 ; 4.934 ; 5.528 ; 5.556 ;
+; Y[1]       ; Output[6]   ; 4.937 ; 4.968 ; 5.546 ; 5.577 ;
+; Y[1]       ; Output[7]   ; 4.998 ; 5.029 ; 5.632 ; 5.663 ;
+; Y[1]       ; Output[8]   ; 4.897 ; 4.924 ; 5.559 ; 5.586 ;
+; Y[1]       ; Output[9]   ; 4.880 ; 5.022 ; 5.542 ; 5.567 ;
+; Y[2]       ; Output[2]   ; 4.862 ; 5.034 ; 5.422 ; 5.616 ;
+; Y[2]       ; Output[3]   ; 4.213 ; 4.216 ; 4.772 ; 4.775 ;
+; Y[2]       ; Output[4]   ; 5.005 ; 5.029 ; 5.580 ; 5.604 ;
+; Y[2]       ; Output[5]   ; 5.148 ; 5.174 ; 5.723 ; 5.749 ;
+; Y[2]       ; Output[6]   ; 4.934 ; 4.965 ; 5.517 ; 5.548 ;
+; Y[2]       ; Output[7]   ; 4.996 ; 5.027 ; 5.627 ; 5.651 ;
+; Y[2]       ; Output[8]   ; 4.895 ; 4.922 ; 5.530 ; 5.557 ;
+; Y[2]       ; Output[9]   ; 4.878 ; 5.014 ; 5.513 ; 5.562 ;
+; Y[3]       ; Output[3]   ; 3.875 ; 3.874 ; 4.452 ; 4.470 ;
+; Y[3]       ; Output[4]   ; 4.504 ; 4.528 ; 5.083 ; 5.107 ;
+; Y[3]       ; Output[5]   ; 4.540 ; 4.568 ; 5.119 ; 5.147 ;
+; Y[3]       ; Output[6]   ; 4.621 ; 4.652 ; 5.202 ; 5.233 ;
+; Y[3]       ; Output[7]   ; 4.576 ; 4.607 ; 5.158 ; 5.189 ;
+; Y[3]       ; Output[8]   ; 4.474 ; 4.501 ; 5.111 ; 5.131 ;
+; Y[3]       ; Output[9]   ; 4.457 ; 4.908 ; 5.403 ; 5.107 ;
+; Y[4]       ; Output[4]   ; 3.975 ; 4.009 ; 4.560 ; 4.577 ;
+; Y[4]       ; Output[5]   ; 4.127 ; 4.153 ; 4.719 ; 4.738 ;
+; Y[4]       ; Output[6]   ; 4.015 ; 4.036 ; 4.573 ; 4.614 ;
+; Y[4]       ; Output[7]   ; 4.016 ; 4.045 ; 4.606 ; 4.632 ;
+; Y[4]       ; Output[8]   ; 3.983 ; 4.005 ; 4.542 ; 4.584 ;
+; Y[4]       ; Output[9]   ; 3.967 ;       ;       ; 4.560 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Output[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; Y[4]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[4]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[1]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[2]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[3]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[3]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[0]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[1]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[0]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[2]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 80    ; 80   ;
+; Unconstrained Output Ports      ; 10    ; 10   ;
+; Unconstrained Output Port Paths ; 80    ; 80   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 15:18:09 2016
+Info: Command: quartus_sta Comb_multiply -c Comb_multiply
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'Comb_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 509 megabytes
+    Info: Processing ended: Fri Feb 19 15:18:11 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/comb_multiply/output_files/Comb_multiply.sta.summary b/comb_multiply/output_files/Comb_multiply.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/comb_multiply/output_files/Comb_multiply.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply.sft b/comb_multiply/simulation/modelsim/Comb_multiply.sft
new file mode 100644
index 0000000..c82b907
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {Comb_multiply_6_1200mv_85c_slow.vho Comb_multiply_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {Comb_multiply_6_1200mv_0c_slow.vho Comb_multiply_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {Comb_multiply_min_1200mv_0c_fast.vho Comb_multiply_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply.vho b/comb_multiply/simulation/modelsim/Comb_multiply.vho
new file mode 100644
index 0000000..fd13896
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply.vho
@@ -0,0 +1,1200 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 15:18:13"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	Comb_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(4 DOWNTO 0);
+	X : IN std_logic_vector(4 DOWNTO 0)
+	);
+END Comb_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF Comb_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_X : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst|inst18~combout\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \inst|inst9|inst6~combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \inst|inst10|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~1_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~1_combout\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_Y <= Y;
+ww_X <= X;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst2~combout\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst13|inst2~1_combout\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst12|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|inst11|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1|inst10|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|inst9|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~combout\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\X[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\Y[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\Y[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N8
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\Y[1]~input_o\ & \X[4]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[4]~input_o\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\X[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\Y[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\X[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N14
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\Y[1]~input_o\ & \X[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[2]~input_o\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\X[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N24
+\inst|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst18~combout\ = (\Y[1]~input_o\ & \X[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[1]~input_o\,
+	combout => \inst|inst18~combout\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\X[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N2
+\inst|inst9|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst6~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ & (\X[1]~input_o\ & \Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y25_N28
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst|inst18~combout\ & ((\inst|inst9|inst6~combout\) # ((\Y[0]~input_o\ & \X[2]~input_o\)))) # (!\inst|inst18~combout\ & (\Y[0]~input_o\ & (\X[2]~input_o\ & \inst|inst9|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N22
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~0_combout\) # ((\X[3]~input_o\ & \Y[0]~input_o\)))) # (!\inst|inst19~combout\ & (\X[3]~input_o\ & (\Y[0]~input_o\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N0
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\X[3]~input_o\ & \Y[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[3]~input_o\,
+	datad => \Y[1]~input_o\,
+	combout => \inst|inst20~combout\);
+
+-- Location: LCCOMB_X1_Y25_N26
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst11|inst3~0_combout\ & ((\inst|inst20~combout\) # ((\Y[0]~input_o\ & \X[4]~input_o\)))) # (!\inst|inst11|inst3~0_combout\ & (\Y[0]~input_o\ & (\X[4]~input_o\ & \inst|inst20~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N18
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst11|inst3~0_combout\ $ (\inst|inst20~combout\ $ (((\Y[0]~input_o\ & \X[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\Y[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N10
+\inst|inst10|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~combout\ = \inst|inst18~combout\ $ (\inst|inst9|inst6~combout\ $ (((\Y[0]~input_o\ & \X[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N24
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\X[0]~input_o\ & \inst|inst10|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N16
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst19~combout\ $ (\inst|inst10|inst3~0_combout\ $ (((\X[3]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y25_N12
+\inst1|inst11|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~1_combout\ = (\Y[2]~input_o\ & ((\X[1]~input_o\ & ((\inst1|inst11|inst3~0_combout\) # (\inst|inst11|inst2~combout\))) # (!\X[1]~input_o\ & (\inst1|inst11|inst3~0_combout\ & \inst|inst11|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst11|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y25_N4
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[2]~input_o\)))) # (!\inst|inst12|inst2~combout\ & (\X[2]~input_o\ & (\Y[2]~input_o\ & \inst1|inst11|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N6
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\Y[2]~input_o\ & \X[3]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[3]~input_o\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X1_Y21_N28
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst12|inst3~0_combout\ & ((\inst1|inst21~combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst12|inst3~0_combout\ & (\inst1|inst21~combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011001100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N22
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\X[4]~input_o\ & \Y[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datac => \Y[2]~input_o\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: LCCOMB_X1_Y21_N8
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst13|inst3~0_combout\ & ((\inst1|inst22~combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst13|inst3~0_combout\ & (\inst|inst21~combout\ & (\inst1|inst22~combout\ & 
+-- \inst|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\Y[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y23_N2
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\Y[2]~input_o\ & (\X[0]~input_o\ & \inst|inst10|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst1|inst10|inst6~combout\ $ (\inst|inst11|inst2~combout\ $ (((\X[1]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst10|inst6~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N18
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\X[0]~input_o\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N20
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst|inst12|inst2~combout\ $ (\inst1|inst11|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N20
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\Y[3]~input_o\ & ((\X[1]~input_o\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\X[1]~input_o\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst12|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y21_N0
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\ $ (\inst1|inst21~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N10
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\X[2]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst12|inst3~1_combout\ & (\X[2]~input_o\ & (\Y[3]~input_o\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N16
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst13|inst3~0_combout\ $ (\inst1|inst22~combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst2|inst13|inst3~0_combout\ & ((\inst1|inst14|inst2~combout\) # ((\X[3]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst13|inst3~0_combout\ & (\X[3]~input_o\ & (\Y[3]~input_o\ & \inst1|inst14|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N2
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N4
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst2|inst13|inst3~0_combout\ $ (\inst1|inst14|inst2~combout\ $ (((\X[3]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N30
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\X[2]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N24
+\inst2|inst11|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst6~combout\ = (\X[0]~input_o\ & (\Y[3]~input_o\ & \inst1|inst11|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y21_N26
+\inst2|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~combout\ = \inst2|inst11|inst6~combout\ $ (\inst1|inst12|inst2~combout\ $ (((\X[1]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst11|inst6~combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N14
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst12|inst2~combout\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst12|inst2~combout\,
+	datac => \X[0]~input_o\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N0
+\inst3|inst13|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~1_combout\ = (\Y[4]~input_o\ & ((\inst2|inst13|inst2~combout\ & ((\inst3|inst13|inst3~0_combout\) # (\X[1]~input_o\))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst3~0_combout\ & \X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N10
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst2|inst14|inst2~combout\ & ((\inst3|inst13|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[4]~input_o\)))) # (!\inst2|inst14|inst2~combout\ & (\X[2]~input_o\ & (\Y[4]~input_o\ & \inst3|inst13|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst2|inst15|inst2~combout\ & ((\inst3|inst14|inst3~0_combout\) # ((\Y[4]~input_o\ & \X[3]~input_o\)))) # (!\inst2|inst15|inst2~combout\ & (\Y[4]~input_o\ & (\X[3]~input_o\ & \inst3|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N12
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[3]~input_o\)))) # (!\inst1|inst14|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[3]~input_o\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N6
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst3|inst15|inst3~0_combout\ & ((\inst2|inst15|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[4]~input_o\)))) # (!\inst3|inst15|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[4]~input_o\ & \inst2|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N8
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst3|inst15|inst3~0_combout\ $ (\inst2|inst15|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N18
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst2|inst15|inst2~combout\ $ (\inst3|inst14|inst3~0_combout\ $ (((\Y[4]~input_o\ & \X[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst2|inst14|inst2~combout\ $ (\inst3|inst13|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N12
+\inst3|inst13|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~0_combout\ = (\Y[4]~input_o\ & ((\inst2|inst12|inst2~combout\ $ (\X[1]~input_o\)) # (!\X[0]~input_o\))) # (!\Y[4]~input_o\ & (!\X[0]~input_o\ & ((!\X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0010101010110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N22
+\inst3|inst13|inst2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~1_combout\ = (\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ $ (((\X[1]~input_o\) # (\X[0]~input_o\))))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ & ((\X[1]~input_o\) # (\X[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011011001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \X[0]~input_o\,
+	datad => \inst3|inst13|inst2~0_combout\,
+	combout => \inst3|inst13|inst2~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~combout\ $ (((\Y[4]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[0]~input_o\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: LCCOMB_X1_Y21_N14
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\X[0]~input_o\ & \Y[3]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N30
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst|inst10|inst2~combout\ $ (((\Y[2]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: LCCOMB_X1_Y25_N30
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ $ (((\X[1]~input_o\ & \Y[0]~input_o\))))) # (!\Y[1]~input_o\ & (((\X[1]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N16
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\Y[0]~input_o\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[0]~input_o\,
+	datac => \X[0]~input_o\,
+	combout => \inst5~combout\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_slow.vho b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..fd13896
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_slow.vho
@@ -0,0 +1,1200 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 15:18:13"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	Comb_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(4 DOWNTO 0);
+	X : IN std_logic_vector(4 DOWNTO 0)
+	);
+END Comb_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF Comb_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_X : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst|inst18~combout\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \inst|inst9|inst6~combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \inst|inst10|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~1_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~1_combout\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_Y <= Y;
+ww_X <= X;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst2~combout\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst13|inst2~1_combout\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst12|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|inst11|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1|inst10|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|inst9|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~combout\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\X[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\Y[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\Y[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N8
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\Y[1]~input_o\ & \X[4]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[4]~input_o\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\X[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\Y[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\X[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N14
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\Y[1]~input_o\ & \X[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[2]~input_o\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\X[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N24
+\inst|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst18~combout\ = (\Y[1]~input_o\ & \X[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[1]~input_o\,
+	combout => \inst|inst18~combout\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\X[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N2
+\inst|inst9|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst6~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ & (\X[1]~input_o\ & \Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y25_N28
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst|inst18~combout\ & ((\inst|inst9|inst6~combout\) # ((\Y[0]~input_o\ & \X[2]~input_o\)))) # (!\inst|inst18~combout\ & (\Y[0]~input_o\ & (\X[2]~input_o\ & \inst|inst9|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N22
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~0_combout\) # ((\X[3]~input_o\ & \Y[0]~input_o\)))) # (!\inst|inst19~combout\ & (\X[3]~input_o\ & (\Y[0]~input_o\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N0
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\X[3]~input_o\ & \Y[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[3]~input_o\,
+	datad => \Y[1]~input_o\,
+	combout => \inst|inst20~combout\);
+
+-- Location: LCCOMB_X1_Y25_N26
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst11|inst3~0_combout\ & ((\inst|inst20~combout\) # ((\Y[0]~input_o\ & \X[4]~input_o\)))) # (!\inst|inst11|inst3~0_combout\ & (\Y[0]~input_o\ & (\X[4]~input_o\ & \inst|inst20~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N18
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst11|inst3~0_combout\ $ (\inst|inst20~combout\ $ (((\Y[0]~input_o\ & \X[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\Y[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N10
+\inst|inst10|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~combout\ = \inst|inst18~combout\ $ (\inst|inst9|inst6~combout\ $ (((\Y[0]~input_o\ & \X[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N24
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\X[0]~input_o\ & \inst|inst10|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N16
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst19~combout\ $ (\inst|inst10|inst3~0_combout\ $ (((\X[3]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y25_N12
+\inst1|inst11|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~1_combout\ = (\Y[2]~input_o\ & ((\X[1]~input_o\ & ((\inst1|inst11|inst3~0_combout\) # (\inst|inst11|inst2~combout\))) # (!\X[1]~input_o\ & (\inst1|inst11|inst3~0_combout\ & \inst|inst11|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst11|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y25_N4
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[2]~input_o\)))) # (!\inst|inst12|inst2~combout\ & (\X[2]~input_o\ & (\Y[2]~input_o\ & \inst1|inst11|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N6
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\Y[2]~input_o\ & \X[3]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[3]~input_o\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X1_Y21_N28
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst12|inst3~0_combout\ & ((\inst1|inst21~combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst12|inst3~0_combout\ & (\inst1|inst21~combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011001100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N22
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\X[4]~input_o\ & \Y[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datac => \Y[2]~input_o\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: LCCOMB_X1_Y21_N8
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst13|inst3~0_combout\ & ((\inst1|inst22~combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst13|inst3~0_combout\ & (\inst|inst21~combout\ & (\inst1|inst22~combout\ & 
+-- \inst|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\Y[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y23_N2
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\Y[2]~input_o\ & (\X[0]~input_o\ & \inst|inst10|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst1|inst10|inst6~combout\ $ (\inst|inst11|inst2~combout\ $ (((\X[1]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst10|inst6~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N18
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\X[0]~input_o\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N20
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst|inst12|inst2~combout\ $ (\inst1|inst11|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N20
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\Y[3]~input_o\ & ((\X[1]~input_o\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\X[1]~input_o\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst12|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y21_N0
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\ $ (\inst1|inst21~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N10
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\X[2]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst12|inst3~1_combout\ & (\X[2]~input_o\ & (\Y[3]~input_o\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N16
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst13|inst3~0_combout\ $ (\inst1|inst22~combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst2|inst13|inst3~0_combout\ & ((\inst1|inst14|inst2~combout\) # ((\X[3]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst13|inst3~0_combout\ & (\X[3]~input_o\ & (\Y[3]~input_o\ & \inst1|inst14|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N2
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N4
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst2|inst13|inst3~0_combout\ $ (\inst1|inst14|inst2~combout\ $ (((\X[3]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N30
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\X[2]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N24
+\inst2|inst11|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst6~combout\ = (\X[0]~input_o\ & (\Y[3]~input_o\ & \inst1|inst11|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y21_N26
+\inst2|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~combout\ = \inst2|inst11|inst6~combout\ $ (\inst1|inst12|inst2~combout\ $ (((\X[1]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst11|inst6~combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N14
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst12|inst2~combout\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst12|inst2~combout\,
+	datac => \X[0]~input_o\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N0
+\inst3|inst13|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~1_combout\ = (\Y[4]~input_o\ & ((\inst2|inst13|inst2~combout\ & ((\inst3|inst13|inst3~0_combout\) # (\X[1]~input_o\))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst3~0_combout\ & \X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N10
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst2|inst14|inst2~combout\ & ((\inst3|inst13|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[4]~input_o\)))) # (!\inst2|inst14|inst2~combout\ & (\X[2]~input_o\ & (\Y[4]~input_o\ & \inst3|inst13|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst2|inst15|inst2~combout\ & ((\inst3|inst14|inst3~0_combout\) # ((\Y[4]~input_o\ & \X[3]~input_o\)))) # (!\inst2|inst15|inst2~combout\ & (\Y[4]~input_o\ & (\X[3]~input_o\ & \inst3|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N12
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[3]~input_o\)))) # (!\inst1|inst14|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[3]~input_o\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N6
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst3|inst15|inst3~0_combout\ & ((\inst2|inst15|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[4]~input_o\)))) # (!\inst3|inst15|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[4]~input_o\ & \inst2|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N8
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst3|inst15|inst3~0_combout\ $ (\inst2|inst15|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N18
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst2|inst15|inst2~combout\ $ (\inst3|inst14|inst3~0_combout\ $ (((\Y[4]~input_o\ & \X[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst2|inst14|inst2~combout\ $ (\inst3|inst13|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N12
+\inst3|inst13|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~0_combout\ = (\Y[4]~input_o\ & ((\inst2|inst12|inst2~combout\ $ (\X[1]~input_o\)) # (!\X[0]~input_o\))) # (!\Y[4]~input_o\ & (!\X[0]~input_o\ & ((!\X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0010101010110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N22
+\inst3|inst13|inst2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~1_combout\ = (\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ $ (((\X[1]~input_o\) # (\X[0]~input_o\))))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ & ((\X[1]~input_o\) # (\X[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011011001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \X[0]~input_o\,
+	datad => \inst3|inst13|inst2~0_combout\,
+	combout => \inst3|inst13|inst2~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~combout\ $ (((\Y[4]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[0]~input_o\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: LCCOMB_X1_Y21_N14
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\X[0]~input_o\ & \Y[3]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N30
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst|inst10|inst2~combout\ $ (((\Y[2]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: LCCOMB_X1_Y25_N30
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ $ (((\X[1]~input_o\ & \Y[0]~input_o\))))) # (!\Y[1]~input_o\ & (((\X[1]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N16
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\Y[0]~input_o\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[0]~input_o\,
+	datac => \X[0]~input_o\,
+	combout => \inst5~combout\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_vhd_slow.sdo b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..6c3099a
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,947 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "Comb_multiply")
+  (DATE "02/19/2016 15:18:13")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (554:554:554) (563:563:563))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (587:587:587) (602:602:602))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (580:580:580) (592:592:592))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (695:695:695) (679:679:679))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (559:559:559) (552:552:552))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (576:576:576) (570:570:570))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (295:295:295) (292:292:292))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (579:579:579) (591:591:591))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (713:713:713) (682:682:682))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (615:615:615) (639:639:639))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2169:2169:2169) (2390:2390:2390))
+        (PORT datac (2374:2374:2374) (2582:2582:2582))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2170:2170:2170) (2391:2391:2391))
+        (PORT datac (2150:2150:2150) (2362:2362:2362))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2173:2173:2173) (2390:2390:2390))
+        (PORT datac (2385:2385:2385) (2596:2596:2596))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2169:2169:2169) (2387:2387:2387))
+        (PORT datab (2436:2436:2436) (2624:2624:2624))
+        (PORT datac (2386:2386:2386) (2601:2601:2601))
+        (PORT datad (2418:2418:2418) (2631:2631:2631))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2418:2418:2418) (2633:2633:2633))
+        (PORT datab (190:190:190) (226:226:226))
+        (PORT datac (2151:2151:2151) (2363:2363:2363))
+        (PORT datad (170:170:170) (194:194:194))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2434:2434:2434) (2651:2651:2651))
+        (PORT datab (2453:2453:2453) (2664:2664:2664))
+        (PORT datac (165:165:165) (197:197:197))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2410:2410:2410) (2625:2625:2625))
+        (PORT datad (2143:2143:2143) (2348:2348:2348))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (193:193:193) (234:234:234))
+        (PORT datab (2455:2455:2455) (2665:2665:2665))
+        (PORT datac (2378:2378:2378) (2586:2586:2586))
+        (PORT datad (170:170:170) (194:194:194))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (194:194:194) (237:237:237))
+        (PORT datab (2455:2455:2455) (2670:2670:2670))
+        (PORT datac (2377:2377:2377) (2585:2585:2585))
+        (PORT datad (169:169:169) (194:194:194))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2419:2419:2419) (2637:2637:2637))
+        (PORT datab (192:192:192) (230:230:230))
+        (PORT datac (2150:2150:2150) (2367:2367:2367))
+        (PORT datad (167:167:167) (191:191:191))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2407:2407:2407) (2612:2612:2612))
+        (PORT datad (600:600:600) (609:609:609))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2436:2436:2436) (2654:2654:2654))
+        (PORT datab (2455:2455:2455) (2667:2667:2667))
+        (PORT datac (165:165:165) (199:199:199))
+        (PORT datad (168:168:168) (191:191:191))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2411:2411:2411) (2630:2630:2630))
+        (PORT datab (599:599:599) (599:599:599))
+        (PORT datac (2850:2850:2850) (3041:3041:3041))
+        (PORT datad (180:180:180) (203:203:203))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2190:2190:2190) (2400:2400:2400))
+        (PORT datab (190:190:190) (228:228:228))
+        (PORT datac (2849:2849:2849) (3039:3039:3039))
+        (PORT datad (166:166:166) (189:189:189))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2878:2878:2878) (3067:3067:3067))
+        (PORT datac (2410:2410:2410) (2621:2621:2621))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (594:594:594) (619:619:619))
+        (PORT datab (611:611:611) (635:635:635))
+        (PORT datac (582:582:582) (590:590:590))
+        (PORT datad (560:560:560) (580:580:580))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2711:2711:2711) (2936:2936:2936))
+        (PORT datac (2582:2582:2582) (2774:2774:2774))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (614:614:614))
+        (PORT datab (192:192:192) (229:229:229))
+        (PORT datac (165:165:165) (198:198:198))
+        (PORT datad (589:589:589) (603:603:603))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2612:2612:2612) (2800:2800:2800))
+        (PORT datac (2408:2408:2408) (2616:2616:2616))
+        (PORT datad (602:602:602) (613:613:613))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2469:2469:2469) (2689:2689:2689))
+        (PORT datab (187:187:187) (221:221:221))
+        (PORT datac (2582:2582:2582) (2776:2776:2776))
+        (PORT datad (584:584:584) (585:585:585))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2453:2453:2453) (2680:2680:2680))
+        (PORT datad (610:610:610) (632:632:632))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2189:2189:2189) (2405:2405:2405))
+        (PORT datab (191:191:191) (229:229:229))
+        (PORT datac (2851:2851:2851) (3043:3043:3043))
+        (PORT datad (168:168:168) (192:192:192))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2683:2683:2683) (2894:2894:2894))
+        (PORT datab (185:185:185) (219:219:219))
+        (PORT datac (2654:2654:2654) (2870:2870:2870))
+        (PORT datad (573:573:573) (581:581:581))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (614:614:614))
+        (PORT datab (616:616:616) (642:642:642))
+        (PORT datac (578:578:578) (584:584:584))
+        (PORT datad (557:557:557) (576:576:576))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2429:2429:2429) (2634:2634:2634))
+        (PORT datab (192:192:192) (230:230:230))
+        (PORT datac (2662:2662:2662) (2873:2873:2873))
+        (PORT datad (167:167:167) (191:191:191))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (590:590:590) (618:618:618))
+        (PORT datab (191:191:191) (229:229:229))
+        (PORT datac (165:165:165) (199:199:199))
+        (PORT datad (587:587:587) (604:604:604))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (193:193:193) (233:233:233))
+        (PORT datab (2462:2462:2462) (2694:2694:2694))
+        (PORT datac (2660:2660:2660) (2873:2873:2873))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2713:2713:2713) (2940:2940:2940))
+        (PORT datab (190:190:190) (227:227:227))
+        (PORT datac (2662:2662:2662) (2875:2875:2875))
+        (PORT datad (166:166:166) (189:189:189))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (193:193:193) (233:233:233))
+        (PORT datab (2462:2462:2462) (2694:2694:2694))
+        (PORT datac (2661:2661:2661) (2873:2873:2873))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2430:2430:2430) (2633:2633:2633))
+        (PORT datab (190:190:190) (227:227:227))
+        (PORT datac (2643:2643:2643) (2863:2863:2863))
+        (PORT datad (170:170:170) (194:194:194))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2455:2455:2455) (2677:2677:2677))
+        (PORT datac (2641:2641:2641) (2864:2864:2864))
+        (PORT datad (608:608:608) (629:629:629))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2684:2684:2684) (2894:2894:2894))
+        (PORT datab (183:183:183) (216:216:216))
+        (PORT datac (2642:2642:2642) (2863:2863:2863))
+        (PORT datad (572:572:572) (578:578:578))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (618:618:618) (642:642:642))
+        (PORT datac (2404:2404:2404) (2616:2616:2616))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2448:2448:2448) (2679:2679:2679))
+        (PORT datab (608:608:608) (624:624:624))
+        (PORT datac (158:158:158) (189:189:189))
+        (PORT datad (2420:2420:2420) (2639:2639:2639))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (592:592:592) (614:614:614))
+        (PORT datab (2392:2392:2392) (2598:2598:2598))
+        (PORT datac (2415:2415:2415) (2641:2641:2641))
+        (PORT datad (167:167:167) (191:191:191))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2447:2447:2447) (2678:2678:2678))
+        (PORT datab (598:598:598) (595:595:595))
+        (PORT datac (2139:2139:2139) (2341:2341:2341))
+        (PORT datad (166:166:166) (189:189:189))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2712:2712:2712) (2940:2940:2940))
+        (PORT datab (191:191:191) (229:229:229))
+        (PORT datac (2661:2661:2661) (2873:2873:2873))
+        (PORT datad (167:167:167) (192:192:192))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2428:2428:2428) (2641:2641:2641))
+        (PORT datab (190:190:190) (227:227:227))
+        (PORT datac (2416:2416:2416) (2643:2643:2643))
+        (PORT datad (567:567:567) (571:571:571))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2428:2428:2428) (2641:2641:2641))
+        (PORT datab (190:190:190) (227:227:227))
+        (PORT datac (2415:2415:2415) (2642:2642:2642))
+        (PORT datad (567:567:567) (571:571:571))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2441:2441:2441) (2667:2667:2667))
+        (PORT datab (595:595:595) (596:596:596))
+        (PORT datac (2142:2142:2142) (2345:2345:2345))
+        (PORT datad (168:168:168) (192:192:192))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (593:593:593) (616:616:616))
+        (PORT datab (2393:2393:2393) (2600:2600:2600))
+        (PORT datac (2409:2409:2409) (2634:2634:2634))
+        (PORT datad (169:169:169) (193:193:193))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2444:2444:2444) (2674:2674:2674))
+        (PORT datab (2394:2394:2394) (2598:2598:2598))
+        (PORT datac (589:589:589) (612:612:612))
+        (PORT datad (2419:2419:2419) (2643:2643:2643))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2468:2468:2468) (2685:2685:2685))
+        (PORT datab (611:611:611) (629:629:629))
+        (PORT datac (2407:2407:2407) (2612:2612:2612))
+        (PORT datad (161:161:161) (182:182:182))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2433:2433:2433) (2661:2661:2661))
+        (PORT datac (589:589:589) (608:608:608))
+        (PORT datad (2368:2368:2368) (2561:2561:2561))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2452:2452:2452) (2677:2677:2677))
+        (PORT datac (2660:2660:2660) (2871:2871:2871))
+        (PORT datad (611:611:611) (632:632:632))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2612:2612:2612) (2804:2804:2804))
+        (PORT datac (2407:2407:2407) (2613:2613:2613))
+        (PORT datad (600:600:600) (609:609:609))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2173:2173:2173) (2395:2395:2395))
+        (PORT datab (2434:2434:2434) (2620:2620:2620))
+        (PORT datac (2385:2385:2385) (2597:2597:2597))
+        (PORT datad (2416:2416:2416) (2628:2628:2628))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2427:2427:2427) (2612:2612:2612))
+        (PORT datac (2406:2406:2406) (2615:2615:2615))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+)
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_slow.vho b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..fd13896
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_slow.vho
@@ -0,0 +1,1200 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 15:18:13"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	Comb_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(4 DOWNTO 0);
+	X : IN std_logic_vector(4 DOWNTO 0)
+	);
+END Comb_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF Comb_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_X : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst|inst18~combout\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \inst|inst9|inst6~combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \inst|inst10|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~1_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~1_combout\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_Y <= Y;
+ww_X <= X;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst2~combout\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst13|inst2~1_combout\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst12|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|inst11|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1|inst10|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|inst9|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~combout\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\X[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\Y[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\Y[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N8
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\Y[1]~input_o\ & \X[4]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[4]~input_o\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\X[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\Y[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\X[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N14
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\Y[1]~input_o\ & \X[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[2]~input_o\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\X[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N24
+\inst|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst18~combout\ = (\Y[1]~input_o\ & \X[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[1]~input_o\,
+	combout => \inst|inst18~combout\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\X[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N2
+\inst|inst9|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst6~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ & (\X[1]~input_o\ & \Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y25_N28
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst|inst18~combout\ & ((\inst|inst9|inst6~combout\) # ((\Y[0]~input_o\ & \X[2]~input_o\)))) # (!\inst|inst18~combout\ & (\Y[0]~input_o\ & (\X[2]~input_o\ & \inst|inst9|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N22
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~0_combout\) # ((\X[3]~input_o\ & \Y[0]~input_o\)))) # (!\inst|inst19~combout\ & (\X[3]~input_o\ & (\Y[0]~input_o\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N0
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\X[3]~input_o\ & \Y[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[3]~input_o\,
+	datad => \Y[1]~input_o\,
+	combout => \inst|inst20~combout\);
+
+-- Location: LCCOMB_X1_Y25_N26
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst11|inst3~0_combout\ & ((\inst|inst20~combout\) # ((\Y[0]~input_o\ & \X[4]~input_o\)))) # (!\inst|inst11|inst3~0_combout\ & (\Y[0]~input_o\ & (\X[4]~input_o\ & \inst|inst20~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N18
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst11|inst3~0_combout\ $ (\inst|inst20~combout\ $ (((\Y[0]~input_o\ & \X[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\Y[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N10
+\inst|inst10|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~combout\ = \inst|inst18~combout\ $ (\inst|inst9|inst6~combout\ $ (((\Y[0]~input_o\ & \X[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N24
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\X[0]~input_o\ & \inst|inst10|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N16
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst19~combout\ $ (\inst|inst10|inst3~0_combout\ $ (((\X[3]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y25_N12
+\inst1|inst11|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~1_combout\ = (\Y[2]~input_o\ & ((\X[1]~input_o\ & ((\inst1|inst11|inst3~0_combout\) # (\inst|inst11|inst2~combout\))) # (!\X[1]~input_o\ & (\inst1|inst11|inst3~0_combout\ & \inst|inst11|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst11|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y25_N4
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[2]~input_o\)))) # (!\inst|inst12|inst2~combout\ & (\X[2]~input_o\ & (\Y[2]~input_o\ & \inst1|inst11|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N6
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\Y[2]~input_o\ & \X[3]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[3]~input_o\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X1_Y21_N28
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst12|inst3~0_combout\ & ((\inst1|inst21~combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst12|inst3~0_combout\ & (\inst1|inst21~combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011001100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N22
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\X[4]~input_o\ & \Y[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datac => \Y[2]~input_o\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: LCCOMB_X1_Y21_N8
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst13|inst3~0_combout\ & ((\inst1|inst22~combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst13|inst3~0_combout\ & (\inst|inst21~combout\ & (\inst1|inst22~combout\ & 
+-- \inst|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\Y[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y23_N2
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\Y[2]~input_o\ & (\X[0]~input_o\ & \inst|inst10|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst1|inst10|inst6~combout\ $ (\inst|inst11|inst2~combout\ $ (((\X[1]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst10|inst6~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N18
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\X[0]~input_o\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N20
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst|inst12|inst2~combout\ $ (\inst1|inst11|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N20
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\Y[3]~input_o\ & ((\X[1]~input_o\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\X[1]~input_o\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst12|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y21_N0
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\ $ (\inst1|inst21~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N10
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\X[2]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst12|inst3~1_combout\ & (\X[2]~input_o\ & (\Y[3]~input_o\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N16
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst13|inst3~0_combout\ $ (\inst1|inst22~combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst2|inst13|inst3~0_combout\ & ((\inst1|inst14|inst2~combout\) # ((\X[3]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst13|inst3~0_combout\ & (\X[3]~input_o\ & (\Y[3]~input_o\ & \inst1|inst14|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N2
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N4
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst2|inst13|inst3~0_combout\ $ (\inst1|inst14|inst2~combout\ $ (((\X[3]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N30
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\X[2]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N24
+\inst2|inst11|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst6~combout\ = (\X[0]~input_o\ & (\Y[3]~input_o\ & \inst1|inst11|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y21_N26
+\inst2|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~combout\ = \inst2|inst11|inst6~combout\ $ (\inst1|inst12|inst2~combout\ $ (((\X[1]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst11|inst6~combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N14
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst12|inst2~combout\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst12|inst2~combout\,
+	datac => \X[0]~input_o\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N0
+\inst3|inst13|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~1_combout\ = (\Y[4]~input_o\ & ((\inst2|inst13|inst2~combout\ & ((\inst3|inst13|inst3~0_combout\) # (\X[1]~input_o\))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst3~0_combout\ & \X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N10
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst2|inst14|inst2~combout\ & ((\inst3|inst13|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[4]~input_o\)))) # (!\inst2|inst14|inst2~combout\ & (\X[2]~input_o\ & (\Y[4]~input_o\ & \inst3|inst13|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst2|inst15|inst2~combout\ & ((\inst3|inst14|inst3~0_combout\) # ((\Y[4]~input_o\ & \X[3]~input_o\)))) # (!\inst2|inst15|inst2~combout\ & (\Y[4]~input_o\ & (\X[3]~input_o\ & \inst3|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N12
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[3]~input_o\)))) # (!\inst1|inst14|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[3]~input_o\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N6
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst3|inst15|inst3~0_combout\ & ((\inst2|inst15|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[4]~input_o\)))) # (!\inst3|inst15|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[4]~input_o\ & \inst2|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N8
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst3|inst15|inst3~0_combout\ $ (\inst2|inst15|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N18
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst2|inst15|inst2~combout\ $ (\inst3|inst14|inst3~0_combout\ $ (((\Y[4]~input_o\ & \X[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst2|inst14|inst2~combout\ $ (\inst3|inst13|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N12
+\inst3|inst13|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~0_combout\ = (\Y[4]~input_o\ & ((\inst2|inst12|inst2~combout\ $ (\X[1]~input_o\)) # (!\X[0]~input_o\))) # (!\Y[4]~input_o\ & (!\X[0]~input_o\ & ((!\X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0010101010110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N22
+\inst3|inst13|inst2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~1_combout\ = (\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ $ (((\X[1]~input_o\) # (\X[0]~input_o\))))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ & ((\X[1]~input_o\) # (\X[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011011001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \X[0]~input_o\,
+	datad => \inst3|inst13|inst2~0_combout\,
+	combout => \inst3|inst13|inst2~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~combout\ $ (((\Y[4]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[0]~input_o\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: LCCOMB_X1_Y21_N14
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\X[0]~input_o\ & \Y[3]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N30
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst|inst10|inst2~combout\ $ (((\Y[2]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: LCCOMB_X1_Y25_N30
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ $ (((\X[1]~input_o\ & \Y[0]~input_o\))))) # (!\Y[1]~input_o\ & (((\X[1]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N16
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\Y[0]~input_o\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[0]~input_o\,
+	datac => \X[0]~input_o\,
+	combout => \inst5~combout\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_vhd_slow.sdo b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..ffb3cfe
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,947 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "Comb_multiply")
+  (DATE "02/19/2016 15:18:13")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (608:608:608) (636:636:636))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (642:642:642) (679:679:679))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (634:634:634) (671:671:671))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (747:747:747) (763:763:763))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (622:622:622))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (631:631:631) (644:644:644))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (324:324:324) (328:328:328))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (632:632:632) (661:661:661))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (762:762:762) (746:746:746))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (670:670:670) (710:710:710))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2541:2541:2541) (2817:2817:2817))
+        (PORT datac (2762:2762:2762) (3040:3040:3040))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2542:2542:2542) (2821:2821:2821))
+        (PORT datac (2531:2531:2531) (2797:2797:2797))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2545:2545:2545) (2818:2818:2818))
+        (PORT datac (2773:2773:2773) (3053:3053:3053))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2541:2541:2541) (2815:2815:2815))
+        (PORT datab (2834:2834:2834) (3087:3087:3087))
+        (PORT datac (2776:2776:2776) (3058:3058:3058))
+        (PORT datad (2816:2816:2816) (3098:3098:3098))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2812:2812:2812) (3098:3098:3098))
+        (PORT datab (209:209:209) (251:251:251))
+        (PORT datac (2532:2532:2532) (2794:2794:2794))
+        (PORT datad (185:185:185) (214:214:214))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2834:2834:2834) (3100:3100:3100))
+        (PORT datab (2853:2853:2853) (3136:3136:3136))
+        (PORT datac (182:182:182) (218:218:218))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2807:2807:2807) (3064:3064:3064))
+        (PORT datad (2511:2511:2511) (2768:2768:2768))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (259:259:259))
+        (PORT datab (2853:2853:2853) (3136:3136:3136))
+        (PORT datac (2766:2766:2766) (3044:3044:3044))
+        (PORT datad (185:185:185) (215:215:215))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (212:212:212) (262:262:262))
+        (PORT datab (2853:2853:2853) (3142:3142:3142))
+        (PORT datac (2765:2765:2765) (3044:3044:3044))
+        (PORT datad (184:184:184) (214:214:214))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2813:2813:2813) (3102:3102:3102))
+        (PORT datab (212:212:212) (255:255:255))
+        (PORT datac (2531:2531:2531) (2799:2799:2799))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2802:2802:2802) (3073:3073:3073))
+        (PORT datad (647:647:647) (663:663:663))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2836:2836:2836) (3102:3102:3102))
+        (PORT datab (2853:2853:2853) (3139:3139:3139))
+        (PORT datac (182:182:182) (220:220:220))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2804:2804:2804) (3095:3095:3095))
+        (PORT datab (639:639:639) (660:660:660))
+        (PORT datac (3287:3287:3287) (3562:3562:3562))
+        (PORT datad (198:198:198) (224:224:224))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2571:2571:2571) (2835:2835:2835))
+        (PORT datab (209:209:209) (252:252:252))
+        (PORT datac (3286:3286:3286) (3559:3559:3559))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3316:3316:3316) (3595:3595:3595))
+        (PORT datac (2806:2806:2806) (3062:3062:3062))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (635:635:635) (697:697:697))
+        (PORT datab (664:664:664) (713:713:713))
+        (PORT datac (623:623:623) (669:669:669))
+        (PORT datad (607:607:607) (656:656:656))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3130:3130:3130) (3418:3418:3418))
+        (PORT datac (2984:2984:2984) (3248:3248:3248))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (693:693:693))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (182:182:182) (219:219:219))
+        (PORT datad (640:640:640) (678:678:678))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3017:3017:3017) (3297:3297:3297))
+        (PORT datac (2806:2806:2806) (3077:3077:3077))
+        (PORT datad (650:650:650) (667:667:667))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2867:2867:2867) (3159:3159:3159))
+        (PORT datab (204:204:204) (245:245:245))
+        (PORT datac (2983:2983:2983) (3268:3268:3268))
+        (PORT datad (626:626:626) (641:641:641))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2853:2853:2853) (3150:3150:3150))
+        (PORT datad (653:653:653) (702:702:702))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2571:2571:2571) (2839:2839:2839))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (3288:3288:3288) (3564:3564:3564))
+        (PORT datad (183:183:183) (213:213:213))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3098:3098:3098) (3398:3398:3398))
+        (PORT datab (202:202:202) (242:242:242))
+        (PORT datac (3075:3075:3075) (3358:3358:3358))
+        (PORT datad (612:612:612) (657:657:657))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (692:692:692))
+        (PORT datab (668:668:668) (720:720:720))
+        (PORT datac (618:618:618) (663:663:663))
+        (PORT datad (604:604:604) (653:653:653))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2823:2823:2823) (3103:3103:3103))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (3083:3083:3083) (3366:3366:3366))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (696:696:696))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (182:182:182) (220:220:220))
+        (PORT datad (637:637:637) (678:678:678))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (259:259:259))
+        (PORT datab (2866:2866:2866) (3157:3157:3157))
+        (PORT datac (3082:3082:3082) (3369:3369:3369))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3132:3132:3132) (3422:3422:3422))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (3083:3083:3083) (3367:3367:3367))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (258:258:258))
+        (PORT datab (2866:2866:2866) (3158:3158:3158))
+        (PORT datac (3082:3082:3082) (3370:3370:3370))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2824:2824:2824) (3101:3101:3101))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (3069:3069:3069) (3351:3351:3351))
+        (PORT datad (185:185:185) (215:215:215))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2856:2856:2856) (3146:3146:3146))
+        (PORT datac (3067:3067:3067) (3356:3356:3356))
+        (PORT datad (651:651:651) (699:699:699))
+        (IOPATH dataa combout (304:304:304) (307:307:307))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3099:3099:3099) (3397:3397:3397))
+        (PORT datab (201:201:201) (240:240:240))
+        (PORT datac (3068:3068:3068) (3350:3350:3350))
+        (PORT datad (611:611:611) (654:654:654))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (677:677:677) (729:729:729))
+        (PORT datac (2801:2801:2801) (3076:3076:3076))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2846:2846:2846) (3129:3129:3129))
+        (PORT datab (665:665:665) (684:684:684))
+        (PORT datac (174:174:174) (208:208:208))
+        (PORT datad (2821:2821:2821) (3104:3104:3104))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (639:639:639) (671:671:671))
+        (PORT datab (2779:2779:2779) (3039:3039:3039))
+        (PORT datac (2807:2807:2807) (3083:3083:3083))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2844:2844:2844) (3125:3125:3125))
+        (PORT datab (639:639:639) (658:658:658))
+        (PORT datac (2510:2510:2510) (2767:2767:2767))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3131:3131:3131) (3422:3422:3422))
+        (PORT datab (210:210:210) (254:254:254))
+        (PORT datac (3082:3082:3082) (3366:3366:3366))
+        (PORT datad (182:182:182) (212:212:212))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2821:2821:2821) (3110:3110:3110))
+        (PORT datab (209:209:209) (251:251:251))
+        (PORT datac (2807:2807:2807) (3086:3086:3086))
+        (PORT datad (611:611:611) (623:623:623))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2820:2820:2820) (3110:3110:3110))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (2807:2807:2807) (3085:3085:3085))
+        (PORT datad (612:612:612) (623:623:623))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2838:2838:2838) (3116:3116:3116))
+        (PORT datab (636:636:636) (659:659:659))
+        (PORT datac (2513:2513:2513) (2771:2771:2771))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (640:640:640) (673:673:673))
+        (PORT datab (2781:2781:2781) (3040:3040:3040))
+        (PORT datac (2801:2801:2801) (3076:3076:3076))
+        (PORT datad (184:184:184) (214:214:214))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2842:2842:2842) (3127:3127:3127))
+        (PORT datab (2785:2785:2785) (3055:3055:3055))
+        (PORT datac (645:645:645) (691:691:691))
+        (PORT datad (2821:2821:2821) (3108:3108:3108))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2866:2866:2866) (3155:3155:3155))
+        (PORT datab (668:668:668) (688:688:688))
+        (PORT datac (2802:2802:2802) (3073:3073:3073))
+        (PORT datad (176:176:176) (201:201:201))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2829:2829:2829) (3109:3109:3109))
+        (PORT datac (644:644:644) (686:686:686))
+        (PORT datad (2759:2759:2759) (3014:3014:3014))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2852:2852:2852) (3148:3148:3148))
+        (PORT datac (3081:3081:3081) (3364:3364:3364))
+        (PORT datad (654:654:654) (702:702:702))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3017:3017:3017) (3302:3302:3302))
+        (PORT datac (2803:2803:2803) (3074:3074:3074))
+        (PORT datad (648:648:648) (664:664:664))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2545:2545:2545) (2822:2822:2822))
+        (PORT datab (2832:2832:2832) (3083:3083:3083))
+        (PORT datac (2773:2773:2773) (3054:3054:3054))
+        (PORT datad (2814:2814:2814) (3095:3095:3095))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2823:2823:2823) (3073:3073:3073))
+        (PORT datac (2803:2803:2803) (3076:3076:3076))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+)
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_fast.vho b/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..fd13896
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_fast.vho
@@ -0,0 +1,1200 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 15:18:13"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	Comb_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(4 DOWNTO 0);
+	X : IN std_logic_vector(4 DOWNTO 0)
+	);
+END Comb_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF Comb_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_X : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst|inst18~combout\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \inst|inst9|inst6~combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \inst|inst10|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~1_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst2~1_combout\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_Y <= Y;
+ww_X <= X;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst16|inst2~combout\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst13|inst2~1_combout\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3|inst12|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2|inst11|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1|inst10|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|inst9|inst~combout\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~combout\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\X[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\Y[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\Y[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N8
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\Y[1]~input_o\ & \X[4]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[4]~input_o\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\X[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\Y[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\X[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N14
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\Y[1]~input_o\ & \X[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[2]~input_o\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\X[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N24
+\inst|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst18~combout\ = (\Y[1]~input_o\ & \X[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datac => \X[1]~input_o\,
+	combout => \inst|inst18~combout\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\X[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N2
+\inst|inst9|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst6~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ & (\X[1]~input_o\ & \Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y25_N28
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst|inst18~combout\ & ((\inst|inst9|inst6~combout\) # ((\Y[0]~input_o\ & \X[2]~input_o\)))) # (!\inst|inst18~combout\ & (\Y[0]~input_o\ & (\X[2]~input_o\ & \inst|inst9|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N22
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~0_combout\) # ((\X[3]~input_o\ & \Y[0]~input_o\)))) # (!\inst|inst19~combout\ & (\X[3]~input_o\ & (\Y[0]~input_o\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N0
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\X[3]~input_o\ & \Y[1]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[3]~input_o\,
+	datad => \Y[1]~input_o\,
+	combout => \inst|inst20~combout\);
+
+-- Location: LCCOMB_X1_Y25_N26
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst11|inst3~0_combout\ & ((\inst|inst20~combout\) # ((\Y[0]~input_o\ & \X[4]~input_o\)))) # (!\inst|inst11|inst3~0_combout\ & (\Y[0]~input_o\ & (\X[4]~input_o\ & \inst|inst20~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N18
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst11|inst3~0_combout\ $ (\inst|inst20~combout\ $ (((\Y[0]~input_o\ & \X[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst3~0_combout\,
+	datab => \Y[0]~input_o\,
+	datac => \X[4]~input_o\,
+	datad => \inst|inst20~combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\Y[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: LCCOMB_X1_Y25_N10
+\inst|inst10|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~combout\ = \inst|inst18~combout\ $ (\inst|inst9|inst6~combout\ $ (((\Y[0]~input_o\ & \X[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[0]~input_o\,
+	datab => \inst|inst18~combout\,
+	datac => \X[2]~input_o\,
+	datad => \inst|inst9|inst6~combout\,
+	combout => \inst|inst10|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N24
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\X[0]~input_o\ & \inst|inst10|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N16
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst19~combout\ $ (\inst|inst10|inst3~0_combout\ $ (((\X[3]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \Y[0]~input_o\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y25_N12
+\inst1|inst11|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~1_combout\ = (\Y[2]~input_o\ & ((\X[1]~input_o\ & ((\inst1|inst11|inst3~0_combout\) # (\inst|inst11|inst2~combout\))) # (!\X[1]~input_o\ & (\inst1|inst11|inst3~0_combout\ & \inst|inst11|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst11|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y25_N4
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[2]~input_o\)))) # (!\inst|inst12|inst2~combout\ & (\X[2]~input_o\ & (\Y[2]~input_o\ & \inst1|inst11|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N6
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\Y[2]~input_o\ & \X[3]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[3]~input_o\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X1_Y21_N28
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst12|inst3~0_combout\ & ((\inst1|inst21~combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst12|inst3~0_combout\ & (\inst1|inst21~combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011001100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N22
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\X[4]~input_o\ & \Y[2]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datac => \Y[2]~input_o\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: LCCOMB_X1_Y21_N8
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst13|inst3~0_combout\ & ((\inst1|inst22~combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst13|inst3~0_combout\ & (\inst|inst21~combout\ & (\inst1|inst22~combout\ & 
+-- \inst|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\Y[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y23_N2
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\Y[2]~input_o\ & (\X[0]~input_o\ & \inst|inst10|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst1|inst10|inst6~combout\ $ (\inst|inst11|inst2~combout\ $ (((\X[1]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst1|inst10|inst6~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N18
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\X[0]~input_o\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y25_N20
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst|inst12|inst2~combout\ $ (\inst1|inst11|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst|inst12|inst2~combout\,
+	datac => \Y[2]~input_o\,
+	datad => \inst1|inst11|inst3~1_combout\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N20
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\Y[3]~input_o\ & ((\X[1]~input_o\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\X[1]~input_o\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110000010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst12|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y21_N0
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\ $ (\inst1|inst21~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst|inst12|inst3~0_combout\,
+	datac => \inst1|inst12|inst3~0_combout\,
+	datad => \inst1|inst21~combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N10
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\X[2]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst12|inst3~1_combout\ & (\X[2]~input_o\ & (\Y[3]~input_o\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N16
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst13|inst3~0_combout\ $ (\inst1|inst22~combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst13|inst3~0_combout\,
+	datac => \inst1|inst22~combout\,
+	datad => \inst|inst12|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst2|inst13|inst3~0_combout\ & ((\inst1|inst14|inst2~combout\) # ((\X[3]~input_o\ & \Y[3]~input_o\)))) # (!\inst2|inst13|inst3~0_combout\ & (\X[3]~input_o\ & (\Y[3]~input_o\ & \inst1|inst14|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N2
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N4
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst2|inst13|inst3~0_combout\ $ (\inst1|inst14|inst2~combout\ $ (((\X[3]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst13|inst3~0_combout\,
+	datab => \X[3]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst14|inst2~combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N30
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\X[2]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst2|inst12|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y21_N24
+\inst2|inst11|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst6~combout\ = (\X[0]~input_o\ & (\Y[3]~input_o\ & \inst1|inst11|inst2~combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y21_N26
+\inst2|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~combout\ = \inst2|inst11|inst6~combout\ $ (\inst1|inst12|inst2~combout\ $ (((\X[1]~input_o\ & \Y[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst11|inst6~combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N14
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst12|inst2~combout\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010000010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst12|inst2~combout\,
+	datac => \X[0]~input_o\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N0
+\inst3|inst13|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~1_combout\ = (\Y[4]~input_o\ & ((\inst2|inst13|inst2~combout\ & ((\inst3|inst13|inst3~0_combout\) # (\X[1]~input_o\))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst3~0_combout\ & \X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N10
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst2|inst14|inst2~combout\ & ((\inst3|inst13|inst3~1_combout\) # ((\X[2]~input_o\ & \Y[4]~input_o\)))) # (!\inst2|inst14|inst2~combout\ & (\X[2]~input_o\ & (\Y[4]~input_o\ & \inst3|inst13|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst2|inst15|inst2~combout\ & ((\inst3|inst14|inst3~0_combout\) # ((\Y[4]~input_o\ & \X[3]~input_o\)))) # (!\inst2|inst15|inst2~combout\ & (\Y[4]~input_o\ & (\X[3]~input_o\ & \inst3|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y21_N12
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[3]~input_o\)))) # (!\inst1|inst14|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[3]~input_o\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst1|inst14|inst3~0_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N6
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst3|inst15|inst3~0_combout\ & ((\inst2|inst15|inst3~0_combout\) # ((\X[4]~input_o\ & \Y[4]~input_o\)))) # (!\inst3|inst15|inst3~0_combout\ & (\X[4]~input_o\ & (\Y[4]~input_o\ & \inst2|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N8
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst3|inst15|inst3~0_combout\ $ (\inst2|inst15|inst3~0_combout\ $ (((\X[4]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \inst3|inst15|inst3~0_combout\,
+	datac => \Y[4]~input_o\,
+	datad => \inst2|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y23_N18
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst2|inst15|inst2~combout\ $ (\inst3|inst14|inst3~0_combout\ $ (((\Y[4]~input_o\ & \X[3]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \inst2|inst15|inst2~combout\,
+	datac => \X[3]~input_o\,
+	datad => \inst3|inst14|inst3~0_combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst2|inst14|inst2~combout\ $ (\inst3|inst13|inst3~1_combout\ $ (((\X[2]~input_o\ & \Y[4]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2|inst14|inst2~combout\,
+	datab => \X[2]~input_o\,
+	datac => \Y[4]~input_o\,
+	datad => \inst3|inst13|inst3~1_combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N12
+\inst3|inst13|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~0_combout\ = (\Y[4]~input_o\ & ((\inst2|inst12|inst2~combout\ $ (\X[1]~input_o\)) # (!\X[0]~input_o\))) # (!\Y[4]~input_o\ & (!\X[0]~input_o\ & ((!\X[1]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0010101010110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[1]~input_o\,
+	combout => \inst3|inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y23_N22
+\inst3|inst13|inst2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~1_combout\ = (\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ $ (((\X[1]~input_o\) # (\X[0]~input_o\))))) # (!\inst2|inst13|inst2~combout\ & (\inst3|inst13|inst2~0_combout\ & ((\X[1]~input_o\) # (\X[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011011001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[1]~input_o\,
+	datab => \inst2|inst13|inst2~combout\,
+	datac => \X[0]~input_o\,
+	datad => \inst3|inst13|inst2~0_combout\,
+	combout => \inst3|inst13|inst2~1_combout\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~combout\ $ (((\Y[4]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[4]~input_o\,
+	datac => \inst2|inst12|inst2~combout\,
+	datad => \X[0]~input_o\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: LCCOMB_X1_Y21_N14
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\X[0]~input_o\ & \Y[3]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[0]~input_o\,
+	datac => \Y[3]~input_o\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N30
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst|inst10|inst2~combout\ $ (((\Y[2]~input_o\ & \X[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[2]~input_o\,
+	datac => \X[0]~input_o\,
+	datad => \inst|inst10|inst2~combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: LCCOMB_X1_Y25_N30
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\Y[1]~input_o\ & (\X[0]~input_o\ $ (((\X[1]~input_o\ & \Y[0]~input_o\))))) # (!\Y[1]~input_o\ & (((\X[1]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \X[1]~input_o\,
+	datad => \Y[0]~input_o\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: LCCOMB_X1_Y23_N16
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\Y[0]~input_o\ & \X[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[0]~input_o\,
+	datac => \X[0]~input_o\,
+	combout => \inst5~combout\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_vhd_fast.sdo b/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..341bf73
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,947 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16F484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "Comb_multiply")
+  (DATE "02/19/2016 15:18:13")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (340:340:340) (378:378:378))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (357:357:357) (403:403:403))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (354:354:354) (397:397:397))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (409:409:409) (454:454:454))
+        (IOPATH i o (1496:1496:1496) (1480:1480:1480))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (325:325:325) (370:370:370))
+        (IOPATH i o (1486:1486:1486) (1470:1470:1470))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (337:337:337) (384:384:384))
+        (IOPATH i o (1486:1486:1486) (1470:1470:1470))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (162:162:162) (183:183:183))
+        (IOPATH i o (1476:1476:1476) (1460:1460:1460))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (338:338:338) (397:397:397))
+        (IOPATH i o (2288:2288:2288) (2417:2417:2417))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (401:401:401) (448:448:448))
+        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (375:375:375) (432:432:432))
+        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (431:431:431) (813:813:813))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1482:1482:1482) (1658:1658:1658))
+        (PORT datac (1617:1617:1617) (1801:1801:1801))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1483:1483:1483) (1663:1663:1663))
+        (PORT datac (1471:1471:1471) (1647:1647:1647))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1484:1484:1484) (1663:1663:1663))
+        (PORT datac (1623:1623:1623) (1809:1809:1809))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1482:1482:1482) (1659:1659:1659))
+        (PORT datab (1641:1641:1641) (1836:1836:1836))
+        (PORT datac (1627:1627:1627) (1813:1813:1813))
+        (PORT datad (1648:1648:1648) (1842:1842:1842))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1647:1647:1647) (1834:1834:1834))
+        (PORT datab (108:108:108) (138:138:138))
+        (PORT datac (1473:1473:1473) (1649:1649:1649))
+        (PORT datad (98:98:98) (117:117:117))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1651:1651:1651) (1845:1845:1845))
+        (PORT datab (1666:1666:1666) (1865:1865:1865))
+        (PORT datac (96:96:96) (118:118:118))
+        (PORT datad (95:95:95) (113:113:113))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1641:1641:1641) (1826:1826:1826))
+        (PORT datad (1468:1468:1468) (1633:1633:1633))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (142:142:142))
+        (PORT datab (1665:1665:1665) (1865:1865:1865))
+        (PORT datac (1621:1621:1621) (1805:1805:1805))
+        (PORT datad (98:98:98) (118:118:118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (144:144:144))
+        (PORT datab (1665:1665:1665) (1864:1864:1864))
+        (PORT datac (1620:1620:1620) (1804:1804:1804))
+        (PORT datad (98:98:98) (117:117:117))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1649:1649:1649) (1838:1838:1838))
+        (PORT datab (109:109:109) (141:141:141))
+        (PORT datac (1475:1475:1475) (1653:1653:1653))
+        (PORT datad (95:95:95) (113:113:113))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1634:1634:1634) (1825:1825:1825))
+        (PORT datad (349:349:349) (403:403:403))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1653:1653:1653) (1848:1848:1848))
+        (PORT datab (1666:1666:1666) (1866:1866:1866))
+        (PORT datac (94:94:94) (117:117:117))
+        (PORT datad (96:96:96) (114:114:114))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1641:1641:1641) (1838:1838:1838))
+        (PORT datab (344:344:344) (401:401:401))
+        (PORT datac (1908:1908:1908) (2118:2118:2118))
+        (PORT datad (103:103:103) (120:120:120))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1496:1496:1496) (1673:1673:1673))
+        (PORT datab (110:110:110) (140:140:140))
+        (PORT datac (1906:1906:1906) (2116:2116:2116))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1921:1921:1921) (2138:2138:2138))
+        (PORT datac (1640:1640:1640) (1822:1822:1822))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (418:418:418))
+        (PORT datab (358:358:358) (421:421:421))
+        (PORT datac (346:346:346) (401:401:401))
+        (PORT datad (346:346:346) (391:391:391))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1829:1829:1829) (2044:2044:2044))
+        (PORT datac (1747:1747:1747) (1941:1941:1941))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (413:413:413))
+        (PORT datab (111:111:111) (141:141:141))
+        (PORT datac (97:97:97) (119:119:119))
+        (PORT datad (348:348:348) (400:400:400))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1756:1756:1756) (1952:1952:1952))
+        (PORT datac (1638:1638:1638) (1830:1830:1830))
+        (PORT datad (352:352:352) (407:407:407))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1677:1677:1677) (1881:1881:1881))
+        (PORT datab (107:107:107) (136:136:136))
+        (PORT datac (1742:1742:1742) (1936:1936:1936))
+        (PORT datad (342:342:342) (390:390:390))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1671:1671:1671) (1873:1873:1873))
+        (PORT datad (347:347:347) (421:421:421))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1495:1495:1495) (1673:1673:1673))
+        (PORT datab (109:109:109) (139:139:139))
+        (PORT datac (1910:1910:1910) (2120:2120:2120))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1817:1817:1817) (2028:2028:2028))
+        (PORT datab (104:104:104) (132:132:132))
+        (PORT datac (1797:1797:1797) (2014:2014:2014))
+        (PORT datad (337:337:337) (388:388:388))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (413:413:413))
+        (PORT datab (364:364:364) (428:428:428))
+        (PORT datac (340:340:340) (395:395:395))
+        (PORT datad (344:344:344) (388:388:388))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1645:1645:1645) (1841:1841:1841))
+        (PORT datab (109:109:109) (140:140:140))
+        (PORT datac (1805:1805:1805) (2016:2016:2016))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (413:413:413))
+        (PORT datab (110:110:110) (139:139:139))
+        (PORT datac (95:95:95) (118:118:118))
+        (PORT datad (347:347:347) (401:401:401))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (142:142:142))
+        (PORT datab (1662:1662:1662) (1886:1886:1886))
+        (PORT datac (1808:1808:1808) (2025:2025:2025))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1832:1832:1832) (2048:2048:2048))
+        (PORT datab (109:109:109) (138:138:138))
+        (PORT datac (1807:1807:1807) (2024:2024:2024))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (1662:1662:1662) (1886:1886:1886))
+        (PORT datac (1808:1808:1808) (2025:2025:2025))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1645:1645:1645) (1840:1840:1840))
+        (PORT datab (109:109:109) (138:138:138))
+        (PORT datac (1793:1793:1793) (2008:2008:2008))
+        (PORT datad (98:98:98) (118:118:118))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1671:1671:1671) (1871:1871:1871))
+        (PORT datac (1797:1797:1797) (2007:2007:2007))
+        (PORT datad (347:347:347) (421:421:421))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1818:1818:1818) (2029:2029:2029))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (1791:1791:1791) (2007:2007:2007))
+        (PORT datad (337:337:337) (388:388:388))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (433:433:433))
+        (PORT datac (1633:1633:1633) (1829:1829:1829))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1668:1668:1668) (1866:1866:1866))
+        (PORT datab (361:361:361) (415:415:415))
+        (PORT datac (91:91:91) (112:112:112))
+        (PORT datad (1650:1650:1650) (1846:1846:1846))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (343:343:343) (405:405:405))
+        (PORT datab (1625:1625:1625) (1810:1810:1810))
+        (PORT datac (1648:1648:1648) (1836:1836:1836))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1667:1667:1667) (1871:1871:1871))
+        (PORT datab (345:345:345) (399:399:399))
+        (PORT datac (1462:1462:1462) (1631:1631:1631))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1829:1829:1829) (2046:2046:2046))
+        (PORT datab (109:109:109) (140:140:140))
+        (PORT datac (1804:1804:1804) (2015:2015:2015))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1653:1653:1653) (1847:1847:1847))
+        (PORT datab (109:109:109) (138:138:138))
+        (PORT datac (1649:1649:1649) (1844:1844:1844))
+        (PORT datad (330:330:330) (377:377:377))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1653:1653:1653) (1847:1847:1847))
+        (PORT datab (109:109:109) (139:139:139))
+        (PORT datac (1649:1649:1649) (1843:1843:1843))
+        (PORT datad (330:330:330) (377:377:377))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1657:1657:1657) (1860:1860:1860))
+        (PORT datab (343:343:343) (398:398:398))
+        (PORT datac (1465:1465:1465) (1635:1635:1635))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (408:408:408))
+        (PORT datab (1628:1628:1628) (1811:1811:1811))
+        (PORT datac (1640:1640:1640) (1834:1834:1834))
+        (PORT datad (97:97:97) (117:117:117))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1664:1664:1664) (1862:1862:1862))
+        (PORT datab (1624:1624:1624) (1815:1815:1815))
+        (PORT datac (355:355:355) (409:409:409))
+        (PORT datad (1650:1650:1650) (1845:1845:1845))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1675:1675:1675) (1877:1877:1877))
+        (PORT datab (365:365:365) (419:419:419))
+        (PORT datac (1634:1634:1634) (1825:1825:1825))
+        (PORT datad (92:92:92) (108:108:108))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1653:1653:1653) (1849:1849:1849))
+        (PORT datac (352:352:352) (405:405:405))
+        (PORT datad (1610:1610:1610) (1790:1790:1790))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1670:1670:1670) (1871:1871:1871))
+        (PORT datac (1805:1805:1805) (2018:2018:2018))
+        (PORT datad (347:347:347) (421:421:421))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1759:1759:1759) (1956:1956:1956))
+        (PORT datac (1635:1635:1635) (1826:1826:1826))
+        (PORT datad (349:349:349) (404:404:404))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1486:1486:1486) (1667:1667:1667))
+        (PORT datab (1637:1637:1637) (1832:1832:1832))
+        (PORT datac (1624:1624:1624) (1810:1810:1810))
+        (PORT datad (1646:1646:1646) (1839:1839:1839))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1631:1631:1631) (1827:1827:1827))
+        (PORT datac (1635:1635:1635) (1827:1827:1827))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+)
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_modelsim.xrf b/comb_multiply/simulation/modelsim/Comb_multiply_modelsim.xrf
new file mode 100644
index 0000000..b0dae72
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_modelsim.xrf
@@ -0,0 +1,74 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bsf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/comb_multiply/Comb_multiply.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/comb_multiply/db/Comb_multiply.cbx.xml
+design_name = Comb_multiply
+instance = comp, \Output[9]~output\, Output[9]~output, Comb_multiply, 1
+instance = comp, \Output[8]~output\, Output[8]~output, Comb_multiply, 1
+instance = comp, \Output[7]~output\, Output[7]~output, Comb_multiply, 1
+instance = comp, \Output[6]~output\, Output[6]~output, Comb_multiply, 1
+instance = comp, \Output[5]~output\, Output[5]~output, Comb_multiply, 1
+instance = comp, \Output[4]~output\, Output[4]~output, Comb_multiply, 1
+instance = comp, \Output[3]~output\, Output[3]~output, Comb_multiply, 1
+instance = comp, \Output[2]~output\, Output[2]~output, Comb_multiply, 1
+instance = comp, \Output[1]~output\, Output[1]~output, Comb_multiply, 1
+instance = comp, \Output[0]~output\, Output[0]~output, Comb_multiply, 1
+instance = comp, \X[4]~input\, X[4]~input, Comb_multiply, 1
+instance = comp, \Y[4]~input\, Y[4]~input, Comb_multiply, 1
+instance = comp, \Y[1]~input\, Y[1]~input, Comb_multiply, 1
+instance = comp, \inst|inst21\, inst|inst21, Comb_multiply, 1
+instance = comp, \X[3]~input\, X[3]~input, Comb_multiply, 1
+instance = comp, \Y[0]~input\, Y[0]~input, Comb_multiply, 1
+instance = comp, \X[2]~input\, X[2]~input, Comb_multiply, 1
+instance = comp, \inst|inst19\, inst|inst19, Comb_multiply, 1
+instance = comp, \X[1]~input\, X[1]~input, Comb_multiply, 1
+instance = comp, \inst|inst18\, inst|inst18, Comb_multiply, 1
+instance = comp, \X[0]~input\, X[0]~input, Comb_multiply, 1
+instance = comp, \inst|inst9|inst6\, inst|inst9|inst6, Comb_multiply, 1
+instance = comp, \inst|inst10|inst3~0\, inst|inst10|inst3~0, Comb_multiply, 1
+instance = comp, \inst|inst11|inst3~0\, inst|inst11|inst3~0, Comb_multiply, 1
+instance = comp, \inst|inst20\, inst|inst20, Comb_multiply, 1
+instance = comp, \inst|inst12|inst3~0\, inst|inst12|inst3~0, Comb_multiply, 1
+instance = comp, \inst|inst12|inst2\, inst|inst12|inst2, Comb_multiply, 1
+instance = comp, \Y[2]~input\, Y[2]~input, Comb_multiply, 1
+instance = comp, \inst|inst10|inst2\, inst|inst10|inst2, Comb_multiply, 1
+instance = comp, \inst1|inst11|inst3~0\, inst1|inst11|inst3~0, Comb_multiply, 1
+instance = comp, \inst|inst11|inst2\, inst|inst11|inst2, Comb_multiply, 1
+instance = comp, \inst1|inst11|inst3~1\, inst1|inst11|inst3~1, Comb_multiply, 1
+instance = comp, \inst1|inst12|inst3~0\, inst1|inst12|inst3~0, Comb_multiply, 1
+instance = comp, \inst1|inst21\, inst1|inst21, Comb_multiply, 1
+instance = comp, \inst1|inst13|inst3~0\, inst1|inst13|inst3~0, Comb_multiply, 1
+instance = comp, \inst1|inst22\, inst1|inst22, Comb_multiply, 1
+instance = comp, \inst1|inst14|inst3~0\, inst1|inst14|inst3~0, Comb_multiply, 1
+instance = comp, \Y[3]~input\, Y[3]~input, Comb_multiply, 1
+instance = comp, \inst1|inst10|inst6\, inst1|inst10|inst6, Comb_multiply, 1
+instance = comp, \inst1|inst11|inst2\, inst1|inst11|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst12|inst3~0\, inst2|inst12|inst3~0, Comb_multiply, 1
+instance = comp, \inst1|inst12|inst2\, inst1|inst12|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst12|inst3~1\, inst2|inst12|inst3~1, Comb_multiply, 1
+instance = comp, \inst1|inst13|inst2\, inst1|inst13|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst13|inst3~0\, inst2|inst13|inst3~0, Comb_multiply, 1
+instance = comp, \inst1|inst14|inst2\, inst1|inst14|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst14|inst3~0\, inst2|inst14|inst3~0, Comb_multiply, 1
+instance = comp, \inst2|inst15|inst2\, inst2|inst15|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst14|inst2\, inst2|inst14|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst13|inst2\, inst2|inst13|inst2, Comb_multiply, 1
+instance = comp, \inst2|inst11|inst6\, inst2|inst11|inst6, Comb_multiply, 1
+instance = comp, \inst2|inst12|inst2\, inst2|inst12|inst2, Comb_multiply, 1
+instance = comp, \inst3|inst13|inst3~0\, inst3|inst13|inst3~0, Comb_multiply, 1
+instance = comp, \inst3|inst13|inst3~1\, inst3|inst13|inst3~1, Comb_multiply, 1
+instance = comp, \inst3|inst14|inst3~0\, inst3|inst14|inst3~0, Comb_multiply, 1
+instance = comp, \inst3|inst15|inst3~0\, inst3|inst15|inst3~0, Comb_multiply, 1
+instance = comp, \inst2|inst15|inst3~0\, inst2|inst15|inst3~0, Comb_multiply, 1
+instance = comp, \inst3|inst16|inst3~0\, inst3|inst16|inst3~0, Comb_multiply, 1
+instance = comp, \inst3|inst16|inst2\, inst3|inst16|inst2, Comb_multiply, 1
+instance = comp, \inst3|inst15|inst2~0\, inst3|inst15|inst2~0, Comb_multiply, 1
+instance = comp, \inst3|inst14|inst2~0\, inst3|inst14|inst2~0, Comb_multiply, 1
+instance = comp, \inst3|inst13|inst2~0\, inst3|inst13|inst2~0, Comb_multiply, 1
+instance = comp, \inst3|inst13|inst2~1\, inst3|inst13|inst2~1, Comb_multiply, 1
+instance = comp, \inst3|inst12|inst\, inst3|inst12|inst, Comb_multiply, 1
+instance = comp, \inst2|inst11|inst\, inst2|inst11|inst, Comb_multiply, 1
+instance = comp, \inst1|inst10|inst\, inst1|inst10|inst, Comb_multiply, 1
+instance = comp, \inst|inst9|inst\, inst|inst9|inst, Comb_multiply, 1
diff --git a/comb_multiply/simulation/modelsim/Comb_multiply_vhd.sdo b/comb_multiply/simulation/modelsim/Comb_multiply_vhd.sdo
new file mode 100644
index 0000000..ffb3cfe
--- /dev/null
+++ b/comb_multiply/simulation/modelsim/Comb_multiply_vhd.sdo
@@ -0,0 +1,947 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "Comb_multiply")
+  (DATE "02/19/2016 15:18:13")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (608:608:608) (636:636:636))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (642:642:642) (679:679:679))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (634:634:634) (671:671:671))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (747:747:747) (763:763:763))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (622:622:622))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (631:631:631) (644:644:644))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (324:324:324) (328:328:328))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (632:632:632) (661:661:661))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (762:762:762) (746:746:746))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (670:670:670) (710:710:710))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2541:2541:2541) (2817:2817:2817))
+        (PORT datac (2762:2762:2762) (3040:3040:3040))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2542:2542:2542) (2821:2821:2821))
+        (PORT datac (2531:2531:2531) (2797:2797:2797))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2545:2545:2545) (2818:2818:2818))
+        (PORT datac (2773:2773:2773) (3053:3053:3053))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2541:2541:2541) (2815:2815:2815))
+        (PORT datab (2834:2834:2834) (3087:3087:3087))
+        (PORT datac (2776:2776:2776) (3058:3058:3058))
+        (PORT datad (2816:2816:2816) (3098:3098:3098))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2812:2812:2812) (3098:3098:3098))
+        (PORT datab (209:209:209) (251:251:251))
+        (PORT datac (2532:2532:2532) (2794:2794:2794))
+        (PORT datad (185:185:185) (214:214:214))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2834:2834:2834) (3100:3100:3100))
+        (PORT datab (2853:2853:2853) (3136:3136:3136))
+        (PORT datac (182:182:182) (218:218:218))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2807:2807:2807) (3064:3064:3064))
+        (PORT datad (2511:2511:2511) (2768:2768:2768))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (259:259:259))
+        (PORT datab (2853:2853:2853) (3136:3136:3136))
+        (PORT datac (2766:2766:2766) (3044:3044:3044))
+        (PORT datad (185:185:185) (215:215:215))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (212:212:212) (262:262:262))
+        (PORT datab (2853:2853:2853) (3142:3142:3142))
+        (PORT datac (2765:2765:2765) (3044:3044:3044))
+        (PORT datad (184:184:184) (214:214:214))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2813:2813:2813) (3102:3102:3102))
+        (PORT datab (212:212:212) (255:255:255))
+        (PORT datac (2531:2531:2531) (2799:2799:2799))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2802:2802:2802) (3073:3073:3073))
+        (PORT datad (647:647:647) (663:663:663))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2836:2836:2836) (3102:3102:3102))
+        (PORT datab (2853:2853:2853) (3139:3139:3139))
+        (PORT datac (182:182:182) (220:220:220))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2804:2804:2804) (3095:3095:3095))
+        (PORT datab (639:639:639) (660:660:660))
+        (PORT datac (3287:3287:3287) (3562:3562:3562))
+        (PORT datad (198:198:198) (224:224:224))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2571:2571:2571) (2835:2835:2835))
+        (PORT datab (209:209:209) (252:252:252))
+        (PORT datac (3286:3286:3286) (3559:3559:3559))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3316:3316:3316) (3595:3595:3595))
+        (PORT datac (2806:2806:2806) (3062:3062:3062))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (635:635:635) (697:697:697))
+        (PORT datab (664:664:664) (713:713:713))
+        (PORT datac (623:623:623) (669:669:669))
+        (PORT datad (607:607:607) (656:656:656))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3130:3130:3130) (3418:3418:3418))
+        (PORT datac (2984:2984:2984) (3248:3248:3248))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (693:693:693))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (182:182:182) (219:219:219))
+        (PORT datad (640:640:640) (678:678:678))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3017:3017:3017) (3297:3297:3297))
+        (PORT datac (2806:2806:2806) (3077:3077:3077))
+        (PORT datad (650:650:650) (667:667:667))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2867:2867:2867) (3159:3159:3159))
+        (PORT datab (204:204:204) (245:245:245))
+        (PORT datac (2983:2983:2983) (3268:3268:3268))
+        (PORT datad (626:626:626) (641:641:641))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2853:2853:2853) (3150:3150:3150))
+        (PORT datad (653:653:653) (702:702:702))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2571:2571:2571) (2839:2839:2839))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (3288:3288:3288) (3564:3564:3564))
+        (PORT datad (183:183:183) (213:213:213))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3098:3098:3098) (3398:3398:3398))
+        (PORT datab (202:202:202) (242:242:242))
+        (PORT datac (3075:3075:3075) (3358:3358:3358))
+        (PORT datad (612:612:612) (657:657:657))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (692:692:692))
+        (PORT datab (668:668:668) (720:720:720))
+        (PORT datac (618:618:618) (663:663:663))
+        (PORT datad (604:604:604) (653:653:653))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2823:2823:2823) (3103:3103:3103))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (3083:3083:3083) (3366:3366:3366))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (696:696:696))
+        (PORT datab (211:211:211) (254:254:254))
+        (PORT datac (182:182:182) (220:220:220))
+        (PORT datad (637:637:637) (678:678:678))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (259:259:259))
+        (PORT datab (2866:2866:2866) (3157:3157:3157))
+        (PORT datac (3082:3082:3082) (3369:3369:3369))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3132:3132:3132) (3422:3422:3422))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (3083:3083:3083) (3367:3367:3367))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (258:258:258))
+        (PORT datab (2866:2866:2866) (3158:3158:3158))
+        (PORT datac (3082:3082:3082) (3370:3370:3370))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2824:2824:2824) (3101:3101:3101))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (3069:3069:3069) (3351:3351:3351))
+        (PORT datad (185:185:185) (215:215:215))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2856:2856:2856) (3146:3146:3146))
+        (PORT datac (3067:3067:3067) (3356:3356:3356))
+        (PORT datad (651:651:651) (699:699:699))
+        (IOPATH dataa combout (304:304:304) (307:307:307))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3099:3099:3099) (3397:3397:3397))
+        (PORT datab (201:201:201) (240:240:240))
+        (PORT datac (3068:3068:3068) (3350:3350:3350))
+        (PORT datad (611:611:611) (654:654:654))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (677:677:677) (729:729:729))
+        (PORT datac (2801:2801:2801) (3076:3076:3076))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2846:2846:2846) (3129:3129:3129))
+        (PORT datab (665:665:665) (684:684:684))
+        (PORT datac (174:174:174) (208:208:208))
+        (PORT datad (2821:2821:2821) (3104:3104:3104))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (639:639:639) (671:671:671))
+        (PORT datab (2779:2779:2779) (3039:3039:3039))
+        (PORT datac (2807:2807:2807) (3083:3083:3083))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2844:2844:2844) (3125:3125:3125))
+        (PORT datab (639:639:639) (658:658:658))
+        (PORT datac (2510:2510:2510) (2767:2767:2767))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3131:3131:3131) (3422:3422:3422))
+        (PORT datab (210:210:210) (254:254:254))
+        (PORT datac (3082:3082:3082) (3366:3366:3366))
+        (PORT datad (182:182:182) (212:212:212))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2821:2821:2821) (3110:3110:3110))
+        (PORT datab (209:209:209) (251:251:251))
+        (PORT datac (2807:2807:2807) (3086:3086:3086))
+        (PORT datad (611:611:611) (623:623:623))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2820:2820:2820) (3110:3110:3110))
+        (PORT datab (210:210:210) (252:252:252))
+        (PORT datac (2807:2807:2807) (3085:3085:3085))
+        (PORT datad (612:612:612) (623:623:623))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2838:2838:2838) (3116:3116:3116))
+        (PORT datab (636:636:636) (659:659:659))
+        (PORT datac (2513:2513:2513) (2771:2771:2771))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (640:640:640) (673:673:673))
+        (PORT datab (2781:2781:2781) (3040:3040:3040))
+        (PORT datac (2801:2801:2801) (3076:3076:3076))
+        (PORT datad (184:184:184) (214:214:214))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2842:2842:2842) (3127:3127:3127))
+        (PORT datab (2785:2785:2785) (3055:3055:3055))
+        (PORT datac (645:645:645) (691:691:691))
+        (PORT datad (2821:2821:2821) (3108:3108:3108))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2866:2866:2866) (3155:3155:3155))
+        (PORT datab (668:668:668) (688:688:688))
+        (PORT datac (2802:2802:2802) (3073:3073:3073))
+        (PORT datad (176:176:176) (201:201:201))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2829:2829:2829) (3109:3109:3109))
+        (PORT datac (644:644:644) (686:686:686))
+        (PORT datad (2759:2759:2759) (3014:3014:3014))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2852:2852:2852) (3148:3148:3148))
+        (PORT datac (3081:3081:3081) (3364:3364:3364))
+        (PORT datad (654:654:654) (702:702:702))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3017:3017:3017) (3302:3302:3302))
+        (PORT datac (2803:2803:2803) (3074:3074:3074))
+        (PORT datad (648:648:648) (664:664:664))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2545:2545:2545) (2822:2822:2822))
+        (PORT datab (2832:2832:2832) (3083:3083:3083))
+        (PORT datac (2773:2773:2773) (3054:3054:3054))
+        (PORT datad (2814:2814:2814) (3095:3095:3095))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2823:2823:2823) (3073:3073:3073))
+        (PORT datac (2803:2803:2803) (3076:3076:3076))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+)
diff --git a/glue_logic/db/glu_Logic.(0).cnf.cdb b/glue_logic/db/glu_Logic.(0).cnf.cdb
new file mode 100644
index 0000000..fa33eea
--- /dev/null
+++ b/glue_logic/db/glu_Logic.(0).cnf.cdb
diff --git a/glue_logic/db/glu_Logic.(0).cnf.hdb b/glue_logic/db/glu_Logic.(0).cnf.hdb
new file mode 100644
index 0000000..208b17b
--- /dev/null
+++ b/glue_logic/db/glu_Logic.(0).cnf.hdb
diff --git a/glue_logic/db/glu_Logic.asm.qmsg b/glue_logic/db/glu_Logic.asm.qmsg
new file mode 100644
index 0000000..c0f11df
--- /dev/null
+++ b/glue_logic/db/glu_Logic.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635769000 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:08 2016 " "Processing started: Tue Feb 16 15:16:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455635769976 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455635770011 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:10 2016 " "Processing ended: Tue Feb 16 15:16:10 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455635770639 ""}
diff --git a/glue_logic/db/glu_Logic.asm.rdb b/glue_logic/db/glu_Logic.asm.rdb
new file mode 100644
index 0000000..679bc42
--- /dev/null
+++ b/glue_logic/db/glu_Logic.asm.rdb
diff --git a/glue_logic/db/glu_Logic.cbx.xml b/glue_logic/db/glu_Logic.cbx.xml
new file mode 100644
index 0000000..d7104e1
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="glu_Logic">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/glue_logic/db/glu_Logic.cmp.idb b/glue_logic/db/glu_Logic.cmp.idb
new file mode 100644
index 0000000..039a95c
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cmp.idb
diff --git a/glue_logic/db/glu_Logic.cmp.kpt b/glue_logic/db/glu_Logic.cmp.kpt
new file mode 100644
index 0000000..c36d492
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cmp.kpt
diff --git a/glue_logic/db/glu_Logic.cmp.rdb b/glue_logic/db/glu_Logic.cmp.rdb
new file mode 100644
index 0000000..d675571
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cmp.rdb
diff --git a/glue_logic/db/glu_Logic.cmp_merge.kpt b/glue_logic/db/glu_Logic.cmp_merge.kpt
new file mode 100644
index 0000000..432cbbd
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cmp_merge.kpt
diff --git a/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..e765b81
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..dab2df3
--- /dev/null
+++ b/glue_logic/db/glu_Logic.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/glue_logic/db/glu_Logic.db_info b/glue_logic/db/glu_Logic.db_info
new file mode 100644
index 0000000..cda06f9
--- /dev/null
+++ b/glue_logic/db/glu_Logic.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Feb 16 15:10:26 2016
diff --git a/glue_logic/db/glu_Logic.fit.qmsg b/glue_logic/db/glu_Logic.fit.qmsg
new file mode 100644
index 0000000..3457b41
--- /dev/null
+++ b/glue_logic/db/glu_Logic.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1455635758479 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "glu_Logic EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"glu_Logic\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455635758896 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759013 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455635759095 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455635759287 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 49 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455635759296 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455635759303 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455635760262 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455635760265 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455635760268 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455635760270 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455635760273 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455635760276 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455635760283 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455635760286 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760288 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760291 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760294 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760296 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455635760298 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455635760301 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455635760303 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455635760305 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455635760310 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455635760310 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760325 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455635760952 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760998 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455635761007 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455635761055 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761057 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455635761406 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455635761783 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455635761783 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761859 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455635761870 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455635761881 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635761988 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762283 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635762365 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762664 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635763015 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/output_files/glu_Logic.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455635763758 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1111 " "Peak virtual memory: 1111 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:05 2016 " "Processing ended: Tue Feb 16 15:16:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455635765258 ""}
diff --git a/glue_logic/db/glu_Logic.hier_info b/glue_logic/db/glu_Logic.hier_info
new file mode 100644
index 0000000..99591ae
--- /dev/null
+++ b/glue_logic/db/glu_Logic.hier_info
@@ -0,0 +1,23 @@
+|glu_Logic
+Output[0] <= Input[0].DB_MAX_OUTPUT_PORT_TYPE
+Output[1] <= Input[1].DB_MAX_OUTPUT_PORT_TYPE
+Output[2] <= Input[2].DB_MAX_OUTPUT_PORT_TYPE
+Output[3] <= Input[3].DB_MAX_OUTPUT_PORT_TYPE
+Output[4] <= Input[4].DB_MAX_OUTPUT_PORT_TYPE
+Output[5] <= Input[5].DB_MAX_OUTPUT_PORT_TYPE
+Output[6] <= Input[6].DB_MAX_OUTPUT_PORT_TYPE
+Output[7] <= Input[7].DB_MAX_OUTPUT_PORT_TYPE
+Output[8] <= Input[8].DB_MAX_OUTPUT_PORT_TYPE
+Output[9] <= Input[9].DB_MAX_OUTPUT_PORT_TYPE
+Input[0] => Output[0].DATAIN
+Input[1] => Output[1].DATAIN
+Input[2] => Output[2].DATAIN
+Input[3] => Output[3].DATAIN
+Input[4] => Output[4].DATAIN
+Input[5] => Output[5].DATAIN
+Input[6] => Output[6].DATAIN
+Input[7] => Output[7].DATAIN
+Input[8] => Output[8].DATAIN
+Input[9] => Output[9].DATAIN
+
+
diff --git a/glue_logic/db/glu_Logic.hif b/glue_logic/db/glu_Logic.hif
new file mode 100644
index 0000000..baa8ed2
--- /dev/null
+++ b/glue_logic/db/glu_Logic.hif
diff --git a/glue_logic/db/glu_Logic.ipinfo b/glue_logic/db/glu_Logic.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/glue_logic/db/glu_Logic.ipinfo
diff --git a/glue_logic/db/glu_Logic.lpc.html b/glue_logic/db/glu_Logic.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/glue_logic/db/glu_Logic.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/glue_logic/db/glu_Logic.lpc.rdb b/glue_logic/db/glu_Logic.lpc.rdb
new file mode 100644
index 0000000..da6029a
--- /dev/null
+++ b/glue_logic/db/glu_Logic.lpc.rdb
diff --git a/glue_logic/db/glu_Logic.lpc.txt b/glue_logic/db/glu_Logic.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/glue_logic/db/glu_Logic.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/glue_logic/db/glu_Logic.map.ammdb b/glue_logic/db/glu_Logic.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.ammdb
diff --git a/glue_logic/db/glu_Logic.map.bpm b/glue_logic/db/glu_Logic.map.bpm
new file mode 100644
index 0000000..7d25716
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.bpm
diff --git a/glue_logic/db/glu_Logic.map.cdb b/glue_logic/db/glu_Logic.map.cdb
new file mode 100644
index 0000000..bd11818
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.cdb
diff --git a/glue_logic/db/glu_Logic.map.hdb b/glue_logic/db/glu_Logic.map.hdb
new file mode 100644
index 0000000..e76e1e4
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.hdb
diff --git a/glue_logic/db/glu_Logic.map.kpt b/glue_logic/db/glu_Logic.map.kpt
new file mode 100644
index 0000000..8a58f05
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.kpt
diff --git a/glue_logic/db/glu_Logic.map.logdb b/glue_logic/db/glu_Logic.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/glue_logic/db/glu_Logic.map.qmsg b/glue_logic/db/glu_Logic.map.qmsg
new file mode 100644
index 0000000..010dfc6
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.qmsg
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635783353 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:22 2016 " "Processing started: Tue Feb 16 15:16:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635783359 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635784489 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "glu_logic.bdf 1 1 " "Found 1 design units, including 1 entities, in source file glu_logic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 glu_Logic " "Found entity 1: glu_Logic" {  } { { "glu_Logic.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455635784576 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455635784576 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "glu_Logic " "Elaborating entity \"glu_Logic\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455635784637 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455635786197 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455635786197 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455635786515 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455635786515 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455635786515 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "458 " "Peak virtual memory: 458 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:26 2016 " "Processing ended: Tue Feb 16 15:16:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635786650 ""}
diff --git a/glue_logic/db/glu_Logic.map.rdb b/glue_logic/db/glu_Logic.map.rdb
new file mode 100644
index 0000000..01c0276
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map.rdb
diff --git a/glue_logic/db/glu_Logic.map_bb.cdb b/glue_logic/db/glu_Logic.map_bb.cdb
new file mode 100644
index 0000000..4de5b57
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map_bb.cdb
diff --git a/glue_logic/db/glu_Logic.map_bb.hdb b/glue_logic/db/glu_Logic.map_bb.hdb
new file mode 100644
index 0000000..0f7c577
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map_bb.hdb
diff --git a/glue_logic/db/glu_Logic.map_bb.logdb b/glue_logic/db/glu_Logic.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/glue_logic/db/glu_Logic.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/glue_logic/db/glu_Logic.pplq.rdb b/glue_logic/db/glu_Logic.pplq.rdb
new file mode 100644
index 0000000..8502917
--- /dev/null
+++ b/glue_logic/db/glu_Logic.pplq.rdb
diff --git a/glue_logic/db/glu_Logic.pre_map.hdb b/glue_logic/db/glu_Logic.pre_map.hdb
new file mode 100644
index 0000000..b58383e
--- /dev/null
+++ b/glue_logic/db/glu_Logic.pre_map.hdb
diff --git a/glue_logic/db/glu_Logic.pti_db_list.ddb b/glue_logic/db/glu_Logic.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/glue_logic/db/glu_Logic.pti_db_list.ddb
diff --git a/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb b/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..e48cb51
--- /dev/null
+++ b/glue_logic/db/glu_Logic.root_partition.map.reg_db.cdb
diff --git a/glue_logic/db/glu_Logic.routing.rdb b/glue_logic/db/glu_Logic.routing.rdb
new file mode 100644
index 0000000..5826080
--- /dev/null
+++ b/glue_logic/db/glu_Logic.routing.rdb
diff --git a/glue_logic/db/glu_Logic.rtlv.hdb b/glue_logic/db/glu_Logic.rtlv.hdb
new file mode 100644
index 0000000..f4f21bc
--- /dev/null
+++ b/glue_logic/db/glu_Logic.rtlv.hdb
diff --git a/glue_logic/db/glu_Logic.rtlv_sg.cdb b/glue_logic/db/glu_Logic.rtlv_sg.cdb
new file mode 100644
index 0000000..8d895cc
--- /dev/null
+++ b/glue_logic/db/glu_Logic.rtlv_sg.cdb
diff --git a/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb b/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..c194c18
--- /dev/null
+++ b/glue_logic/db/glu_Logic.rtlv_sg_swap.cdb
diff --git a/glue_logic/db/glu_Logic.sgdiff.cdb b/glue_logic/db/glu_Logic.sgdiff.cdb
new file mode 100644
index 0000000..0858bcf
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sgdiff.cdb
diff --git a/glue_logic/db/glu_Logic.sgdiff.hdb b/glue_logic/db/glu_Logic.sgdiff.hdb
new file mode 100644
index 0000000..d86c614
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sgdiff.hdb
diff --git a/glue_logic/db/glu_Logic.sld_design_entry.sci b/glue_logic/db/glu_Logic.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sld_design_entry.sci
diff --git a/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci b/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sld_design_entry_dsc.sci
diff --git a/glue_logic/db/glu_Logic.smart_action.txt b/glue_logic/db/glu_Logic.smart_action.txt
new file mode 100644
index 0000000..e04bbcf
--- /dev/null
+++ b/glue_logic/db/glu_Logic.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/glue_logic/db/glu_Logic.sta.qmsg b/glue_logic/db/glu_Logic.sta.qmsg
new file mode 100644
index 0000000..79eb0ed
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sta.qmsg
@@ -0,0 +1,49 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635772538 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:11 2016 " "Processing started: Tue Feb 16 15:16:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta glu_Logic -c glu_Logic " "Command: quartus_sta glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635772553 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455635772647 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635773041 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773045 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455635773623 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635773628 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635773633 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635773638 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455635773642 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635773645 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455635773668 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455635773723 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455635773745 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773750 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773792 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773815 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773840 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773863 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773882 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635773948 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455635773983 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455635774419 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774498 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774533 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774556 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774577 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774597 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774615 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635774664 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774906 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774928 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774948 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774969 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774991 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635775012 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "487 " "Peak virtual memory: 487 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:15 2016 " "Processing ended: Tue Feb 16 15:16:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""}
diff --git a/glue_logic/db/glu_Logic.sta.rdb b/glue_logic/db/glu_Logic.sta.rdb
new file mode 100644
index 0000000..8ab6516
--- /dev/null
+++ b/glue_logic/db/glu_Logic.sta.rdb
diff --git a/glue_logic/db/glu_Logic.syn_hier_info b/glue_logic/db/glu_Logic.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/glue_logic/db/glu_Logic.syn_hier_info
diff --git a/glue_logic/db/glu_Logic.tis_db_list.ddb b/glue_logic/db/glu_Logic.tis_db_list.ddb
new file mode 100644
index 0000000..180899a
--- /dev/null
+++ b/glue_logic/db/glu_Logic.tis_db_list.ddb
diff --git a/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb b/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..50c6e4c
--- /dev/null
+++ b/glue_logic/db/glu_Logic.tiscmp.fast_1200mv_0c.ddb
diff --git a/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..a542856
--- /dev/null
+++ b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_0c.ddb
diff --git a/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..1d08652
--- /dev/null
+++ b/glue_logic/db/glu_Logic.tiscmp.slow_1200mv_85c.ddb
diff --git a/glue_logic/db/glu_Logic.vpr.ammdb b/glue_logic/db/glu_Logic.vpr.ammdb
new file mode 100644
index 0000000..170d7e1
--- /dev/null
+++ b/glue_logic/db/glu_Logic.vpr.ammdb
diff --git a/glue_logic/db/logic_util_heursitic.dat b/glue_logic/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/glue_logic/db/logic_util_heursitic.dat
diff --git a/glue_logic/db/prev_cmp_glu_Logic.qmsg b/glue_logic/db/prev_cmp_glu_Logic.qmsg
new file mode 100644
index 0000000..b545053
--- /dev/null
+++ b/glue_logic/db/prev_cmp_glu_Logic.qmsg
@@ -0,0 +1,116 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635751781 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:15:51 2016 " "Processing started: Tue Feb 16 15:15:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635751788 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635751789 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635752936 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "glu_logic.bdf 1 1 " "Found 1 design units, including 1 entities, in source file glu_logic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 glu_Logic " "Found entity 1: glu_Logic" {  } { { "glu_Logic.bdf" "" { Schematic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455635753027 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455635753027 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "glu_Logic " "Elaborating entity \"glu_Logic\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455635753116 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455635754836 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455635754836 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455635755072 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455635755072 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455635755072 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "458 " "Peak virtual memory: 458 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:15:55 2016 " "Processing ended: Tue Feb 16 15:15:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635755206 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455635757583 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635757615 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:15:56 2016 " "Processing started: Tue Feb 16 15:15:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635757615 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455635757615 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_fit --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455635757626 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455635757715 ""}
+{ "Info" "0" "" "Project  = glu_Logic" {  } {  } 0 0 "Project  = glu_Logic" 0 0 "Fitter" 0 0 1455635757716 ""}
+{ "Info" "0" "" "Revision = glu_Logic" {  } {  } 0 0 "Revision = glu_Logic" 0 0 "Fitter" 0 0 1455635757716 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1455635758479 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "glu_Logic EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"glu_Logic\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455635758896 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759013 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455635759014 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455635759095 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455635759287 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455635759287 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 49 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455635759296 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455635759296 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455635759303 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455635760262 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455635760265 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455635760268 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455635760270 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455635760273 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455635760276 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455635760283 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455635760286 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760288 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455635760291 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760294 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455635760296 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455635760298 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455635760301 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455635760303 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455635760305 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455635760310 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455635760310 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760325 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455635760952 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635760998 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455635761007 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455635761055 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761057 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455635761406 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455635761783 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455635761783 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635761859 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455635761870 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455635761870 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455635761881 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635761988 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762283 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455635762365 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455635762664 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455635763015 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/EIE1 FPGA/output_files/glu_Logic.fit.smsg " "Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455635763758 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1111 " "Peak virtual memory: 1111 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:05 2016 " "Processing ended: Tue Feb 16 15:16:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635765258 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455635765258 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455635769000 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:08 2016 " "Processing started: Tue Feb 16 15:16:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635769004 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic " "Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455635769004 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455635769976 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455635770011 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:10 2016 " "Processing ended: Tue Feb 16 15:16:10 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635770639 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455635770639 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455635771599 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455635772538 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 16 15:16:11 2016 " "Processing started: Tue Feb 16 15:16:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455635772550 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta glu_Logic -c glu_Logic " "Command: quartus_sta glu_Logic -c glu_Logic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455635772553 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455635772647 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1455635773041 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773045 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455635773132 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "glu_Logic.sdc " "Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455635773623 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635773628 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635773633 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635773638 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455635773642 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635773645 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455635773668 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455635773723 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455635773745 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773750 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773792 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773815 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773840 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773863 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635773882 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635773948 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455635773983 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455635774419 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774497 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774498 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774533 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774556 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774577 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774597 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774615 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455635774664 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455635774905 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455635774906 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774928 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774948 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774969 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635774991 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455635775012 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455635775477 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "487 " "Peak virtual memory: 487 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 16 15:16:15 2016 " "Processing ended: Tue Feb 16 15:16:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635775820 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 7 s " "Quartus II Full Compilation was successful. 0 errors, 7 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455635777402 ""}
diff --git a/glue_logic/glu_Logic.bdf b/glue_logic/glu_Logic.bdf
new file mode 100644
index 0000000..26fb82b
--- /dev/null
+++ b/glue_logic/glu_Logic.bdf
@@ -0,0 +1,58 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 648 464 816 480)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Input[9..0]" (rect 5 0 56 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 864 464 1040 480)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "Output[9..0]" (rect 90 0 149 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(connector
+	(pt 816 472)
+	(pt 864 472)
+	(bus)
+)
diff --git a/glue_logic/glu_Logic.qpf b/glue_logic/glu_Logic.qpf
new file mode 100644
index 0000000..34de522
--- /dev/null
+++ b/glue_logic/glu_Logic.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 15:10:25  February 16, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "15:10:25  February 16, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "glu_Logic"
diff --git a/glue_logic/glu_Logic.qsf b/glue_logic/glu_Logic.qsf
new file mode 100644
index 0000000..bc9f5ca
--- /dev/null
+++ b/glue_logic/glu_Logic.qsf
@@ -0,0 +1,76 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 15:10:25  February 16, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		glu_Logic_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY glu_Logic
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:25  FEBRUARY 16, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name BDF_FILE glu_Logic.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_D2 -to Input[9]
+set_location_assignment PIN_E4 -to Input[8]
+set_location_assignment PIN_E3 -to Input[7]
+set_location_assignment PIN_H7 -to Input[6]
+set_location_assignment PIN_J7 -to Input[5]
+set_location_assignment PIN_G5 -to Input[4]
+set_location_assignment PIN_G4 -to Input[3]
+set_location_assignment PIN_H6 -to Input[2]
+set_location_assignment PIN_H5 -to Input[1]
+set_location_assignment PIN_J6 -to Input[0]
+set_location_assignment PIN_B1 -to Output[9]
+set_location_assignment PIN_B2 -to Output[8]
+set_location_assignment PIN_C2 -to Output[7]
+set_location_assignment PIN_C1 -to Output[6]
+set_location_assignment PIN_E1 -to Output[5]
+set_location_assignment PIN_F2 -to Output[4]
+set_location_assignment PIN_H1 -to Output[3]
+set_location_assignment PIN_J3 -to Output[2]
+set_location_assignment PIN_J2 -to Output[1]
+set_location_assignment PIN_J1 -to Output[0]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name CDF_FILE output_files/Chain1.cdf
\ No newline at end of file
diff --git a/glue_logic/glu_Logic.qws b/glue_logic/glu_Logic.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/glue_logic/glu_Logic.qws
diff --git a/glue_logic/incremental_db/README b/glue_logic/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/glue_logic/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info b/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info
new file mode 100644
index 0000000..5fd933f
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Feb 16 15:12:31 2016
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb
new file mode 100644
index 0000000..1a57b15
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.ammdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb
new file mode 100644
index 0000000..1906e65
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.cdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.dfp
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb
new file mode 100644
index 0000000..c32a041
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.hdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.kpt
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..166bbfc
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.cmp.rcfdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb
new file mode 100644
index 0000000..9c73857
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.cdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi
new file mode 100644
index 0000000..4ae522e
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.dpi
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..d47c66e
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.cdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hb_info
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..8397de6
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.hdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb
new file mode 100644
index 0000000..3903d4f
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.hdb
diff --git a/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt
new file mode 100644
index 0000000..52f7807
--- /dev/null
+++ b/glue_logic/incremental_db/compiled_partitions/glu_Logic.root_partition.map.kpt
diff --git a/glue_logic/output_files/Chain1.cdf b/glue_logic/output_files/Chain1.cdf
new file mode 100644
index 0000000..ff8f9b9
--- /dev/null
+++ b/glue_logic/output_files/Chain1.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/output_files/") File("glu_Logic.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/glue_logic/output_files/glu_Logic.asm.rpt b/glue_logic/output_files/glu_Logic.asm.rpt
new file mode 100644
index 0000000..837dbe8
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for glu_Logic
+Tue Feb 16 15:16:10 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: /EIE1 FPGA/output_files/glu_Logic.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Feb 16 15:16:10 2016 ;
+; Revision Name         ; glu_Logic                             ;
+; Top-level Entity Name ; glu_Logic                             ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------+
+; Assembler Generated Files             ;
++---------------------------------------+
+; File Name                             ;
++---------------------------------------+
+; /EIE1 FPGA/output_files/glu_Logic.sof ;
++---------------------------------------+
+
+
++-----------------------------------------------------------------+
+; Assembler Device Options: /EIE1 FPGA/output_files/glu_Logic.sof ;
++----------------+------------------------------------------------+
+; Option         ; Setting                                        ;
++----------------+------------------------------------------------+
+; Device         ; EP3C16F484C6                                   ;
+; JTAG usercode  ; 0x000C87E7                                     ;
+; Checksum       ; 0x000C87E7                                     ;
++----------------+------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 16 15:16:08 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off glu_Logic -c glu_Logic
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 427 megabytes
+    Info: Processing ended: Tue Feb 16 15:16:10 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/glue_logic/output_files/glu_Logic.done b/glue_logic/output_files/glu_Logic.done
new file mode 100644
index 0000000..6f7edbf
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.done
@@ -0,0 +1 @@
+Tue Feb 16 15:16:27 2016
diff --git a/glue_logic/output_files/glu_Logic.fit.rpt b/glue_logic/output_files/glu_Logic.fit.rpt
new file mode 100644
index 0000000..bb750e3
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.fit.rpt
@@ -0,0 +1,1188 @@
+Fitter report for glu_Logic
+Tue Feb 16 15:16:03 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Other Routing Usage Summary
+ 22. I/O Rules Summary
+ 23. I/O Rules Details
+ 24. I/O Rules Matrix
+ 25. Fitter Device Options
+ 26. Operating Settings and Conditions
+ 27. Fitter Messages
+ 28. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Feb 16 15:16:03 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; glu_Logic                                        ;
+; Top-level Entity Name              ; glu_Logic                                        ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 0 / 15,408 ( 0 % )                               ;
+;     Total combinational functions  ; 0 / 15,408 ( 0 % )                               ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                               ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 20 / 347 ( 6 % )                                 ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; Output[9] ; Missing drive strength and slew rate ;
+; Output[8] ; Missing drive strength and slew rate ;
+; Output[7] ; Missing drive strength and slew rate ;
+; Output[6] ; Missing drive strength and slew rate ;
+; Output[5] ; Missing drive strength and slew rate ;
+; Output[4] ; Missing drive strength and slew rate ;
+; Output[3] ; Missing drive strength and slew rate ;
+; Output[2] ; Missing drive strength and slew rate ;
+; Output[1] ; Missing drive strength and slew rate ;
+; Output[0] ; Missing drive strength and slew rate ;
++-----------+--------------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 51 ( 0.00 % )      ;
+;     -- Achieved     ; 0 / 51 ( 0.00 % )      ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 41      ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /EIE1 FPGA/output_files/glu_Logic.pin.
+
+
++-------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                     ;
++---------------------------------------------+---------------------+
+; Resource                                    ; Usage               ;
++---------------------------------------------+---------------------+
+; Total logic elements                        ; 0 / 15,408 ( 0 % )  ;
+;     -- Combinational with no register       ; 0                   ;
+;     -- Register only                        ; 0                   ;
+;     -- Combinational with a register        ; 0                   ;
+;                                             ;                     ;
+; Logic element usage by number of LUT inputs ;                     ;
+;     -- 4 input functions                    ; 0                   ;
+;     -- 3 input functions                    ; 0                   ;
+;     -- <=2 input functions                  ; 0                   ;
+;     -- Register only                        ; 0                   ;
+;                                             ;                     ;
+; Logic elements by mode                      ;                     ;
+;     -- normal mode                          ; 0                   ;
+;     -- arithmetic mode                      ; 0                   ;
+;                                             ;                     ;
+; Total registers*                            ; 0 / 17,068 ( 0 % )  ;
+;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )  ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )   ;
+;                                             ;                     ;
+; Total LABs:  partially or completely used   ; 0 / 963 ( 0 % )     ;
+; Virtual pins                                ; 0                   ;
+; I/O pins                                    ; 20 / 347 ( 6 % )    ;
+;     -- Clock pins                           ; 0 / 8 ( 0 % )       ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )       ;
+;                                             ;                     ;
+; Global signals                              ; 0                   ;
+; M9Ks                                        ; 0 / 56 ( 0 % )      ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % ) ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ;
+; PLLs                                        ; 0 / 4 ( 0 % )       ;
+; Global clocks                               ; 0 / 20 ( 0 % )      ;
+; JTAGs                                       ; 0 / 1 ( 0 % )       ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )       ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )       ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )       ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%        ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%        ;
+; Maximum fan-out                             ; 1                   ;
+; Highest non-global fan-out                  ; 1                   ;
+; Total fan-out                               ; 35                  ;
+; Average fan-out                             ; 0.70                ;
++---------------------------------------------+---------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++--------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                      ;
++---------------------------------------------+-------------------+--------------------------------+
+; Statistic                                   ; Top               ; hard_block:auto_generated_inst ;
++---------------------------------------------+-------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low               ; Low                            ;
+;                                             ;                   ;                                ;
+; Total logic elements                        ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 0                 ; 0                              ;
+;     -- Register only                        ; 0                 ; 0                              ;
+;     -- Combinational with a register        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Logic element usage by number of LUT inputs ;                   ;                                ;
+;     -- 4 input functions                    ; 0                 ; 0                              ;
+;     -- 3 input functions                    ; 0                 ; 0                              ;
+;     -- <=2 input functions                  ; 0                 ; 0                              ;
+;     -- Register only                        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Logic elements by mode                      ;                   ;                                ;
+;     -- normal mode                          ; 0                 ; 0                              ;
+;     -- arithmetic mode                      ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Total registers                             ; 0                 ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                   ;                                ;
+; Total LABs:  partially or completely used   ; 0 / 963 ( 0 % )   ; 0 / 963 ( 0 % )                ;
+;                                             ;                   ;                                ;
+; Virtual pins                                ; 0                 ; 0                              ;
+; I/O pins                                    ; 20                ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )   ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                 ; 0                              ;
+; Total RAM block bits                        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Connections                                 ;                   ;                                ;
+;     -- Input Connections                    ; 0                 ; 0                              ;
+;     -- Registered Input Connections         ; 0                 ; 0                              ;
+;     -- Output Connections                   ; 0                 ; 0                              ;
+;     -- Registered Output Connections        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Internal Connections                        ;                   ;                                ;
+;     -- Total Connections                    ; 30                ; 5                              ;
+;     -- Registered Connections               ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; External Connections                        ;                   ;                                ;
+;     -- Top                                  ; 0                 ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Partition Interface                         ;                   ;                                ;
+;     -- Input Ports                          ; 10                ; 0                              ;
+;     -- Output Ports                         ; 10                ; 0                              ;
+;     -- Bidir Ports                          ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Registered Ports                            ;                   ;                                ;
+;     -- Registered Input Ports               ; 0                 ; 0                              ;
+;     -- Registered Output Ports              ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Port Connectivity                           ;                   ;                                ;
+;     -- Input Ports driven by GND            ; 0                 ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                 ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                 ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                 ; 0                              ;
+;     -- Input Ports with no Source           ; 0                 ; 0                              ;
+;     -- Output Ports with no Source          ; 0                 ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                 ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                 ; 0                              ;
++---------------------------------------------+-------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                    ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Input[0] ; J6    ; 1        ; 0            ; 24           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[1] ; H5    ; 1        ; 0            ; 27           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[2] ; H6    ; 1        ; 0            ; 25           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[3] ; G4    ; 1        ; 0            ; 23           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[4] ; G5    ; 1        ; 0            ; 27           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[5] ; J7    ; 1        ; 0            ; 22           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[6] ; H7    ; 1        ; 0            ; 25           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[7] ; E3    ; 1        ; 0            ; 26           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[8] ; E4    ; 1        ; 0            ; 26           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Input[9] ; D2    ; 1        ; 0            ; 25           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Output[0] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[1] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[2] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[3] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[4] ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[5] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[6] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[7] ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[8] ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[9] ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; Input[8]                ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 24 / 33 ( 73 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; Output[9]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; Output[8]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; Output[6]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; Output[7]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; Input[9]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; Output[5]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; Input[7]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; Input[8]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F2       ; 15         ; 1        ; Output[4]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; Input[3]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; Input[4]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; Output[3]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; Input[1]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; Input[2]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; Input[6]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; Output[0]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; Output[1]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; Output[2]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; Input[0]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; Input[5]                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |glu_Logic                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 20   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |glu_Logic          ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                       ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name      ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Output[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Input[9]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Input[8]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Input[7]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Input[6]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Input[5]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Input[4]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Input[3]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Input[2]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Input[1]  ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Input[0]  ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++-------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                        ;
++-------------------------+-------------------+---------+
+; Source Pin / Fanout     ; Pad To Core Index ; Setting ;
++-------------------------+-------------------+---------+
+; Input[9]                ;                   ;         ;
+;      - Output[9]~output ; 0                 ; 6       ;
+; Input[8]                ;                   ;         ;
+;      - Output[8]~output ; 0                 ; 6       ;
+; Input[7]                ;                   ;         ;
+;      - Output[7]~output ; 0                 ; 6       ;
+; Input[6]                ;                   ;         ;
+;      - Output[6]~output ; 1                 ; 6       ;
+; Input[5]                ;                   ;         ;
+;      - Output[5]~output ; 1                 ; 6       ;
+; Input[4]                ;                   ;         ;
+;      - Output[4]~output ; 0                 ; 6       ;
+; Input[3]                ;                   ;         ;
+;      - Output[3]~output ; 1                 ; 6       ;
+; Input[2]                ;                   ;         ;
+;      - Output[2]~output ; 0                 ; 6       ;
+; Input[1]                ;                   ;         ;
+;      - Output[1]~output ; 1                 ; 6       ;
+; Input[0]                ;                   ;         ;
+;      - Output[0]~output ; 0                 ; 6       ;
++-------------------------+-------------------+---------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++----------------+----------------+
+; Name           ; Fan-Out        ;
++----------------+----------------+
+; Input[0]~input ; 1              ;
+; Input[1]~input ; 1              ;
+; Input[2]~input ; 1              ;
+; Input[3]~input ; 1              ;
+; Input[4]~input ; 1              ;
+; Input[5]~input ; 1              ;
+; Input[6]~input ; 1              ;
+; Input[7]~input ; 1              ;
+; Input[8]~input ; 1              ;
+; Input[9]~input ; 1              ;
++----------------+----------------+
+
+
++-----------------------------------------------------+
+; Other Routing Usage Summary                         ;
++-----------------------------+-----------------------+
+; Other Routing Resource Type ; Usage                 ;
++-----------------------------+-----------------------+
+; Block interconnects         ; 10 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects            ; 10 / 31,272 ( < 1 % ) ;
+; Global clocks               ; 0 / 20 ( 0 % )        ;
+; Local interconnects         ; 0 / 15,408 ( 0 % )    ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects            ; 2 / 41,310 ( < 1 % )  ;
++-----------------------------+-----------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 20        ; 0            ; 20        ; 0            ; 0            ; 20        ; 20        ; 0            ; 20        ; 20        ; 0            ; 10           ; 0            ; 0            ; 10           ; 0            ; 10           ; 10           ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 20        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 20           ; 0         ; 20           ; 20           ; 0         ; 0         ; 20           ; 0         ; 0         ; 20           ; 10           ; 20           ; 20           ; 10           ; 20           ; 10           ; 10           ; 20           ; 20           ; 20           ; 10           ; 20           ; 20           ; 20           ; 20           ; 20           ; 0         ; 20           ; 20           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Output[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[9]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[8]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[7]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[6]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[5]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[4]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[3]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[2]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[1]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Input[0]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "glu_Logic"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Info (144001): Generated suppressed messages file /EIE1 FPGA/output_files/glu_Logic.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 1111 megabytes
+    Info: Processing ended: Tue Feb 16 15:16:05 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:05
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /EIE1 FPGA/output_files/glu_Logic.fit.smsg.
+
+
diff --git a/glue_logic/output_files/glu_Logic.fit.smsg b/glue_logic/output_files/glu_Logic.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/glue_logic/output_files/glu_Logic.fit.summary b/glue_logic/output_files/glu_Logic.fit.summary
new file mode 100644
index 0000000..a142eb4
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Feb 16 15:16:03 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : glu_Logic
+Top-level Entity Name : glu_Logic
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 0 / 15,408 ( 0 % )
+    Total combinational functions : 0 / 15,408 ( 0 % )
+    Dedicated logic registers : 0 / 15,408 ( 0 % )
+Total registers : 0
+Total pins : 20 / 347 ( 6 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/glue_logic/output_files/glu_Logic.flow.rpt b/glue_logic/output_files/glu_Logic.flow.rpt
new file mode 100644
index 0000000..4b4d005
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.flow.rpt
@@ -0,0 +1,114 @@
+Flow report for glu_Logic
+Tue Feb 16 15:16:26 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Feb 16 15:16:26 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; glu_Logic                                        ;
+; Top-level Entity Name              ; glu_Logic                                        ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 0                                                ;
+;     Total combinational functions  ; 0                                                ;
+;     Dedicated logic registers      ; 0                                                ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 20                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/16/2016 15:16:24 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; glu_Logic           ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                 ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564169585.145563578405340 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top        ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:03     ; 1.0                     ; 448 MB              ; 00:00:01                           ;
+; Total                ; 00:00:03     ; --                      ; --                  ; 00:00:01                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; Flow OS Summary                                                                   ;
++----------------------+------------------+-----------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++----------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; eews104a-012     ; Windows 7 ; 6.1        ; x86_64         ;
++----------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic
+
+
+
diff --git a/glue_logic/output_files/glu_Logic.jdi b/glue_logic/output_files/glu_Logic.jdi
new file mode 100644
index 0000000..39e5c82
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="379951d8e352e4b13b31"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="glu_Logic.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/glue_logic/output_files/glu_Logic.map.rpt b/glue_logic/output_files/glu_Logic.map.rpt
new file mode 100644
index 0000000..1adfe57
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.map.rpt
@@ -0,0 +1,260 @@
+Analysis & Synthesis report for glu_Logic
+Tue Feb 16 15:16:26 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Feb 16 15:16:26 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; glu_Logic                                        ;
+; Top-level Entity Name              ; glu_Logic                                        ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 0                                                ;
+;     Total combinational functions  ; 0                                                ;
+;     Dedicated logic registers      ; 0                                                ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 20                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; glu_Logic          ; glu_Logic          ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                  ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                        ; Library ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+
+; glu_Logic.bdf                    ; yes             ; User Block Diagram/Schematic File  ; //icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/glu_Logic.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+-----------------------------------------------------+---------+
+
+
++----------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                    ;
++---------------------------------------------+------------------+
+; Resource                                    ; Usage            ;
++---------------------------------------------+------------------+
+;                                             ;                  ;
+; Total combinational functions               ; 0                ;
+; Logic element usage by number of LUT inputs ;                  ;
+;     -- 4 input functions                    ; 0                ;
+;     -- 3 input functions                    ; 0                ;
+;     -- <=2 input functions                  ; 0                ;
+;                                             ;                  ;
+; Logic elements by mode                      ;                  ;
+;     -- normal mode                          ; 0                ;
+;     -- arithmetic mode                      ; 0                ;
+;                                             ;                  ;
+; Total registers                             ; 0                ;
+;     -- Dedicated logic registers            ; 0                ;
+;     -- I/O registers                        ; 0                ;
+;                                             ;                  ;
+; I/O pins                                    ; 20               ;
+; Embedded Multiplier 9-bit elements          ; 0                ;
+; Maximum fan-out node                        ; Output[9]~output ;
+; Maximum fan-out                             ; 1                ;
+; Total fan-out                               ; 30               ;
+; Average fan-out                             ; 0.75             ;
++---------------------------------------------+------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |glu_Logic                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |glu_Logic          ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 16 15:16:22 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off glu_Logic -c glu_Logic
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file glu_logic.bdf
+    Info (12023): Found entity 1: glu_Logic
+Info (12127): Elaborating entity "glu_Logic" for the top level hierarchy
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 20 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 10 input pins
+    Info (21059): Implemented 10 output pins
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 458 megabytes
+    Info: Processing ended: Tue Feb 16 15:16:26 2016
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/glue_logic/output_files/glu_Logic.map.summary b/glue_logic/output_files/glu_Logic.map.summary
new file mode 100644
index 0000000..081dcdb
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Feb 16 15:16:26 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : glu_Logic
+Top-level Entity Name : glu_Logic
+Family : Cyclone III
+Total logic elements : 0
+    Total combinational functions : 0
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 20
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/glue_logic/output_files/glu_Logic.pin b/glue_logic/output_files/glu_Logic.pin
new file mode 100644
index 0000000..8b2ec3a
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "glu_Logic"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+Output[9]                    : B1        : output : 2.5 V             :         : 1         : Y              
+Output[8]                    : B2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+Output[6]                    : C1        : output : 2.5 V             :         : 1         : Y              
+Output[7]                    : C2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+Input[9]                     : D2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+Output[5]                    : E1        : output : 2.5 V             :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+Input[7]                     : E3        : input  : 2.5 V             :         : 1         : Y              
+Input[8]                     : E4        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+Output[4]                    : F2        : output : 2.5 V             :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+Input[3]                     : G4        : input  : 2.5 V             :         : 1         : Y              
+Input[4]                     : G5        : input  : 2.5 V             :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+Output[3]                    : H1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+Input[1]                     : H5        : input  : 2.5 V             :         : 1         : Y              
+Input[2]                     : H6        : input  : 2.5 V             :         : 1         : Y              
+Input[6]                     : H7        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+Output[0]                    : J1        : output : 2.5 V             :         : 1         : Y              
+Output[1]                    : J2        : output : 2.5 V             :         : 1         : Y              
+Output[2]                    : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+Input[0]                     : J6        : input  : 2.5 V             :         : 1         : Y              
+Input[5]                     : J7        : input  : 2.5 V             :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/glue_logic/output_files/glu_Logic.sof b/glue_logic/output_files/glu_Logic.sof
new file mode 100644
index 0000000..d84404c
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.sof
diff --git a/glue_logic/output_files/glu_Logic.sta.rpt b/glue_logic/output_files/glu_Logic.sta.rpt
new file mode 100644
index 0000000..1102eb4
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.sta.rpt
@@ -0,0 +1,563 @@
+TimeQuest Timing Analyzer report for glu_Logic
+Tue Feb 16 15:16:15 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Progagation Delay
+ 34. Minimum Progagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Slow Corner Signal Integrity Metrics
+ 38. Fast Corner Signal Integrity Metrics
+ 39. Clock Transfers
+ 40. Report TCCS
+ 41. Report RSKM
+ 42. Unconstrained Paths
+ 43. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; glu_Logic                                                          ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------+
+; Propagation Delay                                  ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 5.696 ;    ;    ; 6.097 ;
+; Input[1]   ; Output[1]   ; 5.962 ;    ;    ; 6.381 ;
+; Input[2]   ; Output[2]   ; 6.904 ;    ;    ; 7.417 ;
+; Input[3]   ; Output[3]   ; 5.775 ;    ;    ; 6.192 ;
+; Input[4]   ; Output[4]   ; 5.720 ;    ;    ; 6.123 ;
+; Input[5]   ; Output[5]   ; 5.734 ;    ;    ; 6.126 ;
+; Input[6]   ; Output[6]   ; 5.724 ;    ;    ; 6.101 ;
+; Input[7]   ; Output[7]   ; 5.838 ;    ;    ; 6.196 ;
+; Input[8]   ; Output[8]   ; 5.683 ;    ;    ; 6.062 ;
+; Input[9]   ; Output[9]   ; 5.775 ;    ;    ; 6.153 ;
++------------+-------------+-------+----+----+-------+
+
+
++----------------------------------------------------+
+; Minimum Propagation Delay                          ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 5.581 ;    ;    ; 5.970 ;
+; Input[1]   ; Output[1]   ; 5.837 ;    ;    ; 6.243 ;
+; Input[2]   ; Output[2]   ; 6.788 ;    ;    ; 7.290 ;
+; Input[3]   ; Output[3]   ; 5.658 ;    ;    ; 6.062 ;
+; Input[4]   ; Output[4]   ; 5.604 ;    ;    ; 5.996 ;
+; Input[5]   ; Output[5]   ; 5.618 ;    ;    ; 5.999 ;
+; Input[6]   ; Output[6]   ; 5.609 ;    ;    ; 5.975 ;
+; Input[7]   ; Output[7]   ; 5.719 ;    ;    ; 6.067 ;
+; Input[8]   ; Output[8]   ; 5.570 ;    ;    ; 5.939 ;
+; Input[9]   ; Output[9]   ; 5.660 ;    ;    ; 6.027 ;
++------------+-------------+-------+----+----+-------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------+
+; Propagation Delay                                  ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 5.307 ;    ;    ; 5.639 ;
+; Input[1]   ; Output[1]   ; 5.553 ;    ;    ; 5.885 ;
+; Input[2]   ; Output[2]   ; 6.515 ;    ;    ; 6.959 ;
+; Input[3]   ; Output[3]   ; 5.382 ;    ;    ; 5.737 ;
+; Input[4]   ; Output[4]   ; 5.331 ;    ;    ; 5.665 ;
+; Input[5]   ; Output[5]   ; 5.343 ;    ;    ; 5.685 ;
+; Input[6]   ; Output[6]   ; 5.334 ;    ;    ; 5.652 ;
+; Input[7]   ; Output[7]   ; 5.454 ;    ;    ; 5.737 ;
+; Input[8]   ; Output[8]   ; 5.301 ;    ;    ; 5.624 ;
+; Input[9]   ; Output[9]   ; 5.387 ;    ;    ; 5.714 ;
++------------+-------------+-------+----+----+-------+
+
+
++----------------------------------------------------+
+; Minimum Propagation Delay                          ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 5.211 ;    ;    ; 5.533 ;
+; Input[1]   ; Output[1]   ; 5.447 ;    ;    ; 5.770 ;
+; Input[2]   ; Output[2]   ; 6.419 ;    ;    ; 6.853 ;
+; Input[3]   ; Output[3]   ; 5.283 ;    ;    ; 5.628 ;
+; Input[4]   ; Output[4]   ; 5.234 ;    ;    ; 5.559 ;
+; Input[5]   ; Output[5]   ; 5.246 ;    ;    ; 5.578 ;
+; Input[6]   ; Output[6]   ; 5.237 ;    ;    ; 5.546 ;
+; Input[7]   ; Output[7]   ; 5.353 ;    ;    ; 5.629 ;
+; Input[8]   ; Output[8]   ; 5.207 ;    ;    ; 5.521 ;
+; Input[9]   ; Output[9]   ; 5.291 ;    ;    ; 5.609 ;
++------------+-------------+-------+----+----+-------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------+
+; Propagation Delay                                  ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 3.452 ;    ;    ; 3.988 ;
+; Input[1]   ; Output[1]   ; 3.612 ;    ;    ; 4.166 ;
+; Input[2]   ; Output[2]   ; 4.272 ;    ;    ; 4.953 ;
+; Input[3]   ; Output[3]   ; 3.494 ;    ;    ; 4.059 ;
+; Input[4]   ; Output[4]   ; 3.478 ;    ;    ; 4.012 ;
+; Input[5]   ; Output[5]   ; 3.478 ;    ;    ; 4.020 ;
+; Input[6]   ; Output[6]   ; 3.470 ;    ;    ; 4.008 ;
+; Input[7]   ; Output[7]   ; 3.523 ;    ;    ; 4.054 ;
+; Input[8]   ; Output[8]   ; 3.453 ;    ;    ; 3.986 ;
+; Input[9]   ; Output[9]   ; 3.532 ;    ;    ; 4.066 ;
++------------+-------------+-------+----+----+-------+
+
+
++----------------------------------------------------+
+; Minimum Propagation Delay                          ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 3.383 ;    ;    ; 3.914 ;
+; Input[1]   ; Output[1]   ; 3.537 ;    ;    ; 4.085 ;
+; Input[2]   ; Output[2]   ; 4.203 ;    ;    ; 4.878 ;
+; Input[3]   ; Output[3]   ; 3.424 ;    ;    ; 3.982 ;
+; Input[4]   ; Output[4]   ; 3.409 ;    ;    ; 3.937 ;
+; Input[5]   ; Output[5]   ; 3.408 ;    ;    ; 3.945 ;
+; Input[6]   ; Output[6]   ; 3.401 ;    ;    ; 3.934 ;
+; Input[7]   ; Output[7]   ; 3.453 ;    ;    ; 3.979 ;
+; Input[8]   ; Output[8]   ; 3.385 ;    ;    ; 3.914 ;
+; Input[9]   ; Output[9]   ; 3.463 ;    ;    ; 3.992 ;
++------------+-------------+-------+----+----+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++----------------------------------------------------+
+; Progagation Delay                                  ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 5.696 ;    ;    ; 6.097 ;
+; Input[1]   ; Output[1]   ; 5.962 ;    ;    ; 6.381 ;
+; Input[2]   ; Output[2]   ; 6.904 ;    ;    ; 7.417 ;
+; Input[3]   ; Output[3]   ; 5.775 ;    ;    ; 6.192 ;
+; Input[4]   ; Output[4]   ; 5.720 ;    ;    ; 6.123 ;
+; Input[5]   ; Output[5]   ; 5.734 ;    ;    ; 6.126 ;
+; Input[6]   ; Output[6]   ; 5.724 ;    ;    ; 6.101 ;
+; Input[7]   ; Output[7]   ; 5.838 ;    ;    ; 6.196 ;
+; Input[8]   ; Output[8]   ; 5.683 ;    ;    ; 6.062 ;
+; Input[9]   ; Output[9]   ; 5.775 ;    ;    ; 6.153 ;
++------------+-------------+-------+----+----+-------+
+
+
++----------------------------------------------------+
+; Minimum Progagation Delay                          ;
++------------+-------------+-------+----+----+-------+
+; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
++------------+-------------+-------+----+----+-------+
+; Input[0]   ; Output[0]   ; 3.383 ;    ;    ; 3.914 ;
+; Input[1]   ; Output[1]   ; 3.537 ;    ;    ; 4.085 ;
+; Input[2]   ; Output[2]   ; 4.203 ;    ;    ; 4.878 ;
+; Input[3]   ; Output[3]   ; 3.424 ;    ;    ; 3.982 ;
+; Input[4]   ; Output[4]   ; 3.409 ;    ;    ; 3.937 ;
+; Input[5]   ; Output[5]   ; 3.408 ;    ;    ; 3.945 ;
+; Input[6]   ; Output[6]   ; 3.401 ;    ;    ; 3.934 ;
+; Input[7]   ; Output[7]   ; 3.453 ;    ;    ; 3.979 ;
+; Input[8]   ; Output[8]   ; 3.385 ;    ;    ; 3.914 ;
+; Input[9]   ; Output[9]   ; 3.463 ;    ;    ; 3.992 ;
++------------+-------------+-------+----+----+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Output[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; Input[9]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[8]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[7]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[6]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[5]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[4]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[3]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[2]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[1]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Input[0]                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 10    ; 10   ;
+; Unconstrained Output Ports      ; 10    ; 10   ;
+; Unconstrained Output Port Paths ; 10    ; 10   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 16 15:16:11 2016
+Info: Command: quartus_sta glu_Logic -c glu_Logic
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'glu_Logic.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 487 megabytes
+    Info: Processing ended: Tue Feb 16 15:16:15 2016
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/glue_logic/output_files/glu_Logic.sta.summary b/glue_logic/output_files/glu_Logic.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/glue_logic/output_files/glu_Logic.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/one_hertz_clock/db/logic_util_heursitic.dat b/one_hertz_clock/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..fef33b4
--- /dev/null
+++ b/one_hertz_clock/db/logic_util_heursitic.dat
diff --git a/one_hertz_clock/db/one_hertz_clock.(0).cnf.cdb b/one_hertz_clock/db/one_hertz_clock.(0).cnf.cdb
new file mode 100644
index 0000000..fb46c2b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.(0).cnf.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.(0).cnf.hdb b/one_hertz_clock/db/one_hertz_clock.(0).cnf.hdb
new file mode 100644
index 0000000..c515268
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.(0).cnf.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.(1).cnf.cdb b/one_hertz_clock/db/one_hertz_clock.(1).cnf.cdb
new file mode 100644
index 0000000..679b722
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.(1).cnf.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.(1).cnf.hdb b/one_hertz_clock/db/one_hertz_clock.(1).cnf.hdb
new file mode 100644
index 0000000..96ef63d
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.(1).cnf.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.asm.qmsg b/one_hertz_clock/db/one_hertz_clock.asm.qmsg
new file mode 100644
index 0000000..2c36a8b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456243337848 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243337849 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 16:02:17 2016 " "Processing started: Tue Feb 23 16:02:17 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243337849 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456243337849 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456243337849 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456243338449 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456243338465 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243338684 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 16:02:18 2016 " "Processing ended: Tue Feb 23 16:02:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243338684 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243338684 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243338684 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456243338684 ""}
diff --git a/one_hertz_clock/db/one_hertz_clock.asm.rdb b/one_hertz_clock/db/one_hertz_clock.asm.rdb
new file mode 100644
index 0000000..96d8cbc
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.asm.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.asm_labs.ddb b/one_hertz_clock/db/one_hertz_clock.asm_labs.ddb
new file mode 100644
index 0000000..994027c
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.asm_labs.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.cbx.xml b/one_hertz_clock/db/one_hertz_clock.cbx.xml
new file mode 100644
index 0000000..6ad7e3b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="one_hertz_clock">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.bpm b/one_hertz_clock/db/one_hertz_clock.cmp.bpm
new file mode 100644
index 0000000..2f2bfeb
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.bpm
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.cdb b/one_hertz_clock/db/one_hertz_clock.cmp.cdb
new file mode 100644
index 0000000..5c63db3
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.hdb b/one_hertz_clock/db/one_hertz_clock.cmp.hdb
new file mode 100644
index 0000000..7088022
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.idb b/one_hertz_clock/db/one_hertz_clock.cmp.idb
new file mode 100644
index 0000000..3901ffb
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.idb
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.kpt b/one_hertz_clock/db/one_hertz_clock.cmp.kpt
new file mode 100644
index 0000000..414443a
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.kpt
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.logdb b/one_hertz_clock/db/one_hertz_clock.cmp.logdb
new file mode 100644
index 0000000..2d047df
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.logdb
@@ -0,0 +1,44 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;2;0;0;2;2;0;1;0;0;1;0;1;1;0;0;0;1;0;0;0;0;0;2;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,2;2;2;2;2;0;2;2;0;0;2;1;2;2;1;2;1;1;2;2;2;1;2;2;2;2;2;0;2;2,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,1_Hz,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp.rdb b/one_hertz_clock/db/one_hertz_clock.cmp.rdb
new file mode 100644
index 0000000..8d9d97b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.cmp_merge.kpt b/one_hertz_clock/db/one_hertz_clock.cmp_merge.kpt
new file mode 100644
index 0000000..91179e3
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cmp_merge.kpt
diff --git a/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..48e9c1b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..e9cbe95
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/one_hertz_clock/db/one_hertz_clock.db_info b/one_hertz_clock/db/one_hertz_clock.db_info
new file mode 100644
index 0000000..cde781d
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Feb 23 14:11:14 2016
diff --git a/one_hertz_clock/db/one_hertz_clock.fit.qmsg b/one_hertz_clock/db/one_hertz_clock.fit.qmsg
new file mode 100644
index 0000000..46d8535
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456243332282 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "one_hertz_clock EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"one_hertz_clock\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456243332518 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243332600 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243332600 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243332600 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456243332665 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243332837 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243332837 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243332837 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456243332837 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 84 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243332838 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 86 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243332838 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 88 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243332838 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243332838 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 92 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243332838 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456243332838 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456243332839 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 2 " "No exact pin location assignment(s) for 2 pins of 2 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "1_Hz " "Pin 1_Hz not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { 1_Hz } } } { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 536 744 920 552 "1_Hz" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { 1_Hz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 22 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456243333504 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLK } } } { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2928 600 768 2944 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 23 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456243333504 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456243333504 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "one_hertz_clock.sdc " "Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456243333593 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456243333593 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456243333594 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456243333594 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456243333594 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node CLK~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456243333606 ""}  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2928 600 768 2944 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 79 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456243333606 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456243333705 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456243333705 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456243333705 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456243333706 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456243333706 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456243333706 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456243333706 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456243333706 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456243333707 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456243333707 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456243333707 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456243333708 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456243333708 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456243333708 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243333709 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456243333709 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456243333709 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243333713 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456243334119 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243334174 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456243334181 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456243334423 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243334423 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456243334558 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X31_Y10 X41_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19" {  } { { "loc" "" { Generic "C:/one_hertz_clock/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} 31 10 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456243334888 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456243334888 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243335398 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456243335400 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456243335400 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456243335404 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456243335429 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456243335638 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456243335661 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456243335724 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243335992 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg " "Generated suppressed messages file C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456243336637 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1090 " "Peak virtual memory: 1090 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243336774 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 16:02:16 2016 " "Processing ended: Tue Feb 23 16:02:16 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243336774 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243336774 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243336774 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456243336774 ""}
diff --git a/one_hertz_clock/db/one_hertz_clock.hier_info b/one_hertz_clock/db/one_hertz_clock.hier_info
new file mode 100644
index 0000000..aa51ae1
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.hier_info
@@ -0,0 +1,289 @@
+|one_hertz_clock
+1_Hz <= inst30.DB_MAX_OUTPUT_PORT_TYPE
+CLK => inst77.CLK
+CLK => inst72.CLK
+CLK => inst67.CLK
+CLK => inst63.CLK
+CLK => inst58.CLK
+CLK => inst48.CLK
+CLK => inst43.CLK
+CLK => inst389.CLK
+CLK => inst50.CLK
+CLK => inst459.CLK
+CLK => inst40.CLK
+CLK => inst38.CLK
+CLK => inst3799999.CLK
+CLK => inst82.CLK
+CLK => inst97.CLK
+CLK => inst92.CLK
+CLK => inst87.CLK
+CLK => inst102.CLK
+CLK => inst107.CLK
+
+
+|one_hertz_clock|full_adder:inst78
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst73
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst68
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst37
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst59
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst49
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst449
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst369
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst51
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst46
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst41
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst36
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst999
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst83
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst98
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst93
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst88
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst103
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|one_hertz_clock|full_adder:inst108
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/one_hertz_clock/db/one_hertz_clock.hif b/one_hertz_clock/db/one_hertz_clock.hif
new file mode 100644
index 0000000..1534d8f
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.hif
diff --git a/one_hertz_clock/db/one_hertz_clock.ipinfo b/one_hertz_clock/db/one_hertz_clock.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.ipinfo
diff --git a/one_hertz_clock/db/one_hertz_clock.lpc.html b/one_hertz_clock/db/one_hertz_clock.lpc.html
new file mode 100644
index 0000000..2e863bc
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.lpc.html
@@ -0,0 +1,322 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst108</TD>
+<TD >3</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst103</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst88</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst93</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst98</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst83</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst999</TD>
+<TD >3</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst36</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst41</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst46</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst51</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst369</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst449</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst49</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst59</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst37</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst68</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst73</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst78</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/one_hertz_clock/db/one_hertz_clock.lpc.rdb b/one_hertz_clock/db/one_hertz_clock.lpc.rdb
new file mode 100644
index 0000000..25efad3
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.lpc.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.lpc.txt b/one_hertz_clock/db/one_hertz_clock.lpc.txt
new file mode 100644
index 0000000..af7f492
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.lpc.txt
@@ -0,0 +1,25 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst108   ; 3     ; 2              ; 0            ; 2              ; 2      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst103   ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst88    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst93    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst98    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst83    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst999   ; 3     ; 2              ; 0            ; 2              ; 2      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst36    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst41    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst46    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst51    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst369   ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst449   ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst49    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst59    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst37    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst68    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst73    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst78    ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/one_hertz_clock/db/one_hertz_clock.map.ammdb b/one_hertz_clock/db/one_hertz_clock.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.ammdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map.bpm b/one_hertz_clock/db/one_hertz_clock.map.bpm
new file mode 100644
index 0000000..a0089db
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.bpm
diff --git a/one_hertz_clock/db/one_hertz_clock.map.cdb b/one_hertz_clock/db/one_hertz_clock.map.cdb
new file mode 100644
index 0000000..9a0d54b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map.hdb b/one_hertz_clock/db/one_hertz_clock.map.hdb
new file mode 100644
index 0000000..aa7c760
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map.kpt b/one_hertz_clock/db/one_hertz_clock.map.kpt
new file mode 100644
index 0000000..eef70e9
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.kpt
diff --git a/one_hertz_clock/db/one_hertz_clock.map.logdb b/one_hertz_clock/db/one_hertz_clock.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/one_hertz_clock/db/one_hertz_clock.map.qmsg b/one_hertz_clock/db/one_hertz_clock.map.qmsg
new file mode 100644
index 0000000..af6a07c
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.qmsg
@@ -0,0 +1,14 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456243330079 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243330080 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 16:02:09 2016 " "Processing started: Tue Feb 23 16:02:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243330080 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456243330080 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock " "Command: quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456243330080 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456243330319 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456243330356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456243330356 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "one_hertz_clock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file one_hertz_clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 one_hertz_clock " "Found entity 1: one_hertz_clock" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456243330357 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456243330357 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "one_hertz_clock " "Elaborating entity \"one_hertz_clock\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456243330376 ""}
+{ "Warning" "WGDFX_NOT_ALL_BITS_USED" "N\[14..5\] " "Not all bits in bus \"N\[14..5\]\" are used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } { 480 312 336 496 "N\[6\]" "" } { 496 312 336 512 "N\[7\]" "" } { 472 496 521 488 "N\[9\]" "" } { 488 496 526 504 "N\[10\]" "" } { 504 496 526 520 "N\[11\]" "" } { 520 496 526 536 "N\[12\]" "" } { 552 496 523 568 "N\[14\]" "" } { 1288 968 997 1304 "N\[5\]" "" } { 1408 968 997 1424 "N\[6\]" "" } { 1528 968 997 1544 "N\[7\]" "" } { 1768 968 997 1784 "N\[9\]" "" } { 1888 968 1003 1904 "N\[10\]" "" } { 2008 968 1003 2024 "N\[11\]" "" } { 2128 968 1003 2144 "N\[12\]" "" } { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275089 "Not all bits in bus \"%1!s!\" are used" 0 0 "Quartus II" 0 -1 1456243330384 ""}
+{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "N " "Converted elements in bus name \"N\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[5\] N5 " "Converted element name(s) from \"N\[5\]\" to \"N5\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[6\] N6 " "Converted element name(s) from \"N\[6\]\" to \"N6\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 480 312 336 496 "N\[6\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[7\] N7 " "Converted element name(s) from \"N\[7\]\" to \"N7\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 496 312 336 512 "N\[7\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[9\] N9 " "Converted element name(s) from \"N\[9\]\" to \"N9\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 472 496 521 488 "N\[9\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[10\] N10 " "Converted element name(s) from \"N\[10\]\" to \"N10\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 488 496 526 504 "N\[10\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[11\] N11 " "Converted element name(s) from \"N\[11\]\" to \"N11\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 504 496 526 520 "N\[11\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[12\] N12 " "Converted element name(s) from \"N\[12\]\" to \"N12\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 520 496 526 536 "N\[12\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[14\] N14 " "Converted element name(s) from \"N\[14\]\" to \"N14\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 552 496 523 568 "N\[14\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[5\] N5 " "Converted element name(s) from \"N\[5\]\" to \"N5\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1288 968 997 1304 "N\[5\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[6\] N6 " "Converted element name(s) from \"N\[6\]\" to \"N6\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1408 968 997 1424 "N\[6\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[7\] N7 " "Converted element name(s) from \"N\[7\]\" to \"N7\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1528 968 997 1544 "N\[7\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[9\] N9 " "Converted element name(s) from \"N\[9\]\" to \"N9\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1768 968 997 1784 "N\[9\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[10\] N10 " "Converted element name(s) from \"N\[10\]\" to \"N10\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1888 968 1003 1904 "N\[10\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[11\] N11 " "Converted element name(s) from \"N\[11\]\" to \"N11\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2008 968 1003 2024 "N\[11\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[12\] N12 " "Converted element name(s) from \"N\[12\]\" to \"N12\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2128 968 1003 2144 "N\[12\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[14\] N14 " "Converted element name(s) from \"N\[14\]\" to \"N14\"" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330384 ""}  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } { 480 312 336 496 "N\[6\]" "" } { 496 312 336 512 "N\[7\]" "" } { 472 496 521 488 "N\[9\]" "" } { 488 496 526 504 "N\[10\]" "" } { 504 496 526 520 "N\[11\]" "" } { 520 496 526 536 "N\[12\]" "" } { 552 496 523 568 "N\[14\]" "" } { 1288 968 997 1304 "N\[5\]" "" } { 1408 968 997 1424 "N\[6\]" "" } { 1528 968 997 1544 "N\[7\]" "" } { 1768 968 997 1784 "N\[9\]" "" } { 1888 968 1003 1904 "N\[10\]" "" } { 2008 968 1003 2024 "N\[11\]" "" } { 2128 968 1003 2144 "N\[12\]" "" } { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275080 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "Quartus II" 0 -1 1456243330384 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder full_adder:inst78 " "Elaborating entity \"full_adder\" for hierarchy \"full_adder:inst78\"" {  } { { "one_hertz_clock.bdf" "inst78" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2120 488 584 2216 "inst78" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243330391 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456243330809 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456243330972 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456243330972 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456243330994 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456243330994 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456243330994 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456243330994 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "464 " "Peak virtual memory: 464 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243331005 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 16:02:11 2016 " "Processing ended: Tue Feb 23 16:02:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243331005 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243331005 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243331005 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456243331005 ""}
diff --git a/one_hertz_clock/db/one_hertz_clock.map.rdb b/one_hertz_clock/db/one_hertz_clock.map.rdb
new file mode 100644
index 0000000..636156a
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map_bb.cdb b/one_hertz_clock/db/one_hertz_clock.map_bb.cdb
new file mode 100644
index 0000000..33749bd
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map_bb.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map_bb.hdb b/one_hertz_clock/db/one_hertz_clock.map_bb.hdb
new file mode 100644
index 0000000..82ddcc8
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map_bb.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.map_bb.logdb b/one_hertz_clock/db/one_hertz_clock.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/one_hertz_clock/db/one_hertz_clock.pre_map.hdb b/one_hertz_clock/db/one_hertz_clock.pre_map.hdb
new file mode 100644
index 0000000..ad7e2a1
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.pre_map.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.pti_db_list.ddb b/one_hertz_clock/db/one_hertz_clock.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.pti_db_list.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.root_partition.map.reg_db.cdb b/one_hertz_clock/db/one_hertz_clock.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..140922b
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.root_partition.map.reg_db.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.routing.rdb b/one_hertz_clock/db/one_hertz_clock.routing.rdb
new file mode 100644
index 0000000..5ebf43f
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.routing.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.rtlv.hdb b/one_hertz_clock/db/one_hertz_clock.rtlv.hdb
new file mode 100644
index 0000000..5b75f98
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.rtlv.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.rtlv_sg.cdb b/one_hertz_clock/db/one_hertz_clock.rtlv_sg.cdb
new file mode 100644
index 0000000..f539613
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.rtlv_sg.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.rtlv_sg_swap.cdb b/one_hertz_clock/db/one_hertz_clock.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..e344c01
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.rtlv_sg_swap.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.sgdiff.cdb b/one_hertz_clock/db/one_hertz_clock.sgdiff.cdb
new file mode 100644
index 0000000..de82f00
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sgdiff.cdb
diff --git a/one_hertz_clock/db/one_hertz_clock.sgdiff.hdb b/one_hertz_clock/db/one_hertz_clock.sgdiff.hdb
new file mode 100644
index 0000000..43d3754
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sgdiff.hdb
diff --git a/one_hertz_clock/db/one_hertz_clock.sld_design_entry.sci b/one_hertz_clock/db/one_hertz_clock.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sld_design_entry.sci
diff --git a/one_hertz_clock/db/one_hertz_clock.sld_design_entry_dsc.sci b/one_hertz_clock/db/one_hertz_clock.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sld_design_entry_dsc.sci
diff --git a/one_hertz_clock/db/one_hertz_clock.smart_action.txt b/one_hertz_clock/db/one_hertz_clock.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/one_hertz_clock/db/one_hertz_clock.sta.qmsg b/one_hertz_clock/db/one_hertz_clock.sta.qmsg
new file mode 100644
index 0000000..34cca06
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456243339865 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243339865 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 16:02:19 2016 " "Processing started: Tue Feb 23 16:02:19 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243339865 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456243339865 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta one_hertz_clock -c one_hertz_clock " "Command: quartus_sta one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456243339865 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456243339923 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456243340006 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243340006 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243340048 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243340049 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "one_hertz_clock.sdc " "Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456243340161 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456243340161 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340162 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340162 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456243340260 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340260 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456243340261 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456243340267 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243340273 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243340273 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.948 " "Worst-case setup slack is -1.948" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340275 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.948       -30.172 CLK  " "   -1.948       -30.172 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340275 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340275 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.344         0.000 CLK  " "    0.344         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340276 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340276 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340278 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340279 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340280 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340280 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 CLK  " "   -3.000       -22.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340280 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340280 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456243340297 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456243340315 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456243340603 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340629 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243340633 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243340633 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.632 " "Worst-case setup slack is -1.632" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.632       -25.089 CLK  " "   -1.632       -25.089 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340635 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340635 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298         0.000 CLK  " "    0.298         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340637 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340637 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340639 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340641 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340643 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340643 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 CLK  " "   -3.000       -22.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340643 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340643 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456243340662 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340713 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243340714 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243340714 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.652 " "Worst-case setup slack is -0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.652        -8.911 CLK  " "   -0.652        -8.911 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340717 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340717 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.180 " "Worst-case hold slack is 0.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340719 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340719 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180         0.000 CLK  " "    0.180         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340719 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340719 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340722 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243340725 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340727 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340727 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -23.093 CLK  " "   -3.000       -23.093 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243340727 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243340727 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456243340832 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456243340832 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "485 " "Peak virtual memory: 485 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243340868 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 16:02:20 2016 " "Processing ended: Tue Feb 23 16:02:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243340868 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243340868 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243340868 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456243340868 ""}
diff --git a/one_hertz_clock/db/one_hertz_clock.sta.rdb b/one_hertz_clock/db/one_hertz_clock.sta.rdb
new file mode 100644
index 0000000..1816c90
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sta.rdb
diff --git a/one_hertz_clock/db/one_hertz_clock.sta_cmp.6_slow_1200mv_85c.tdb b/one_hertz_clock/db/one_hertz_clock.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..b723eae
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/one_hertz_clock/db/one_hertz_clock.syn_hier_info b/one_hertz_clock/db/one_hertz_clock.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.syn_hier_info
diff --git a/one_hertz_clock/db/one_hertz_clock.tis_db_list.ddb b/one_hertz_clock/db/one_hertz_clock.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.tis_db_list.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.tiscmp.fast_1200mv_0c.ddb b/one_hertz_clock/db/one_hertz_clock.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..28109ad
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.tiscmp.fast_1200mv_0c.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_0c.ddb b/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..c208981
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_0c.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_85c.ddb b/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..1172d3c
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.tiscmp.slow_1200mv_85c.ddb
diff --git a/one_hertz_clock/db/one_hertz_clock.tmw_info b/one_hertz_clock/db/one_hertz_clock.tmw_info
new file mode 100644
index 0000000..ca0e6d2
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:12
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:06-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/one_hertz_clock/db/one_hertz_clock.vpr.ammdb b/one_hertz_clock/db/one_hertz_clock.vpr.ammdb
new file mode 100644
index 0000000..f721fcc
--- /dev/null
+++ b/one_hertz_clock/db/one_hertz_clock.vpr.ammdb
diff --git a/one_hertz_clock/db/prev_cmp_one_hertz_clock.qmsg b/one_hertz_clock/db/prev_cmp_one_hertz_clock.qmsg
new file mode 100644
index 0000000..c0b690d
--- /dev/null
+++ b/one_hertz_clock/db/prev_cmp_one_hertz_clock.qmsg
@@ -0,0 +1,125 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456243190033 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243190033 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 15:59:49 2016 " "Processing started: Tue Feb 23 15:59:49 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243190033 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456243190033 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock " "Command: quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456243190033 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456243190240 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456243190281 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456243190281 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "one_hertz_clock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file one_hertz_clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 one_hertz_clock " "Found entity 1: one_hertz_clock" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456243190282 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456243190282 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "one_hertz_clock " "Elaborating entity \"one_hertz_clock\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456243190299 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst112 " "Primitive \"NOT\" of instance \"inst112\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2848 920 968 2880 "inst112" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst113 " "Primitive \"NOT\" of instance \"inst113\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2728 920 968 2760 "inst113" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst114 " "Primitive \"NOT\" of instance \"inst114\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2608 920 968 2640 "inst114" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst115 " "Primitive \"NOT\" of instance \"inst115\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2488 920 968 2520 "inst115" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst117 " "Primitive \"NOT\" of instance \"inst117\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2248 920 968 2280 "inst117" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst123 " "Primitive \"NOT\" of instance \"inst123\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1168 920 968 1200 "inst123" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst124 " "Primitive \"NOT\" of instance \"inst124\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1048 920 968 1080 "inst124" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst125 " "Primitive \"NOT\" of instance \"inst125\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 928 920 968 960 "inst125" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst126 " "Primitive \"NOT\" of instance \"inst126\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 808 920 968 840 "inst126" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst127 " "Primitive \"NOT\" of instance \"inst127\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 688 920 968 720 "inst127" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190315 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "NOT inst130 " "Primitive \"NOT\" of instance \"inst130\" not used" {  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 1648 920 968 1680 "inst130" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1456243190316 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder full_adder:inst78 " "Elaborating entity \"full_adder\" for hierarchy \"full_adder:inst78\"" {  } { { "one_hertz_clock.bdf" "inst78" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2120 488 584 2216 "inst78" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456243190320 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456243190806 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456243190983 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456243190983 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456243191004 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456243191004 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456243191004 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456243191004 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "464 " "Peak virtual memory: 464 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243191015 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 15:59:51 2016 " "Processing ended: Tue Feb 23 15:59:51 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243191015 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243191015 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243191015 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456243191015 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456243192189 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243192189 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 15:59:51 2016 " "Processing started: Tue Feb 23 15:59:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243192189 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1456243192189 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock " "Command: quartus_fit --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1456243192189 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1456243192255 ""}
+{ "Info" "0" "" "Project  = one_hertz_clock" {  } {  } 0 0 "Project  = one_hertz_clock" 0 0 "Fitter" 0 0 1456243192256 ""}
+{ "Info" "0" "" "Revision = one_hertz_clock" {  } {  } 0 0 "Revision = one_hertz_clock" 0 0 "Fitter" 0 0 1456243192256 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456243192293 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "one_hertz_clock EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"one_hertz_clock\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456243192527 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243192594 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243192595 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456243192595 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456243192656 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243192832 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243192832 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456243192832 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456243192832 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 84 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243192833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 86 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243192833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 88 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243192833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243192833 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 92 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456243192833 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456243192833 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456243192834 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 2 " "No exact pin location assignment(s) for 2 pins of 2 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "1_Hz " "Pin 1_Hz not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { 1_Hz } } } { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 536 744 920 552 "1_Hz" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { 1_Hz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 22 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456243193487 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLK } } } { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2928 600 768 2944 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 23 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456243193487 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456243193487 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "one_hertz_clock.sdc " "Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456243193573 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456243193573 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456243193574 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456243193574 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456243193574 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node CLK~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456243193587 ""}  } { { "one_hertz_clock.bdf" "" { Schematic "C:/one_hertz_clock/one_hertz_clock.bdf" { { 2928 600 768 2944 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/one_hertz_clock/" { { 0 { 0 ""} 0 79 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456243193587 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456243193685 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456243193686 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456243193686 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456243193686 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456243193686 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456243193687 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456243193687 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456243193687 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456243193687 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456243193687 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456243193687 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456243193688 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456243193688 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456243193688 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 28 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456243193689 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456243193689 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456243193689 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243193695 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456243194084 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243194142 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456243194149 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456243194393 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243194393 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456243194527 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X31_Y10 X41_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19" {  } { { "loc" "" { Generic "C:/one_hertz_clock/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19"} 31 10 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456243194857 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456243194857 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243195358 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456243195360 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456243195360 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.17 " "Total time spent on timing analysis during the Fitter is 0.17 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456243195364 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456243195389 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456243195598 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456243195621 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456243195684 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456243195952 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg " "Generated suppressed messages file C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456243196589 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1101 " "Peak virtual memory: 1101 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243196726 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 15:59:56 2016 " "Processing ended: Tue Feb 23 15:59:56 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243196726 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243196726 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243196726 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456243196726 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1456243197808 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243197809 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 15:59:57 2016 " "Processing started: Tue Feb 23 15:59:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243197809 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456243197809 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456243197810 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456243198429 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456243198447 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243198663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 15:59:58 2016 " "Processing ended: Tue Feb 23 15:59:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243198663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243198663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243198663 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456243198663 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1456243199282 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1456243199844 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456243199844 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 23 15:59:59 2016 " "Processing started: Tue Feb 23 15:59:59 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456243199844 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456243199844 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta one_hertz_clock -c one_hertz_clock " "Command: quartus_sta one_hertz_clock -c one_hertz_clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456243199844 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456243199902 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456243199985 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243199986 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243200027 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456243200027 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "one_hertz_clock.sdc " "Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456243200138 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456243200139 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200139 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200139 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456243200236 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200236 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456243200236 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456243200241 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243200248 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243200248 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.948 " "Worst-case setup slack is -1.948" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.948       -30.172 CLK  " "   -1.948       -30.172 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200249 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200249 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.344         0.000 CLK  " "    0.344         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200251 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200251 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200252 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200254 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200255 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200255 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 CLK  " "   -3.000       -22.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200255 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200255 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456243200283 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456243200301 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456243200589 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200608 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243200611 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243200611 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.632 " "Worst-case setup slack is -1.632" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.632       -25.089 CLK  " "   -1.632       -25.089 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200613 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200613 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.298         0.000 CLK  " "    0.298         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200615 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200615 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200617 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200620 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200621 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200621 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 CLK  " "   -3.000       -22.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200621 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200621 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456243200642 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200692 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456243200693 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456243200693 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.652 " "Worst-case setup slack is -0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.652        -8.911 CLK  " "   -0.652        -8.911 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200696 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200696 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.180 " "Worst-case hold slack is 0.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180         0.000 CLK  " "    0.180         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200699 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200699 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200701 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456243200704 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -23.093 CLK  " "   -3.000       -23.093 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456243200706 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456243200706 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456243200810 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456243200810 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "485 " "Peak virtual memory: 485 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456243200848 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 23 16:00:00 2016 " "Processing ended: Tue Feb 23 16:00:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456243200848 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456243200848 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456243200848 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456243200848 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus II Full Compilation was successful. 0 errors, 18 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456243201476 ""}
diff --git a/one_hertz_clock/incremental_db/README b/one_hertz_clock/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/one_hertz_clock/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.db_info b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.db_info
new file mode 100644
index 0000000..7e4ecaa
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Feb 23 14:51:00 2016
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.ammdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.ammdb
new file mode 100644
index 0000000..ba6afff
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.ammdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.cdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.cdb
new file mode 100644
index 0000000..66321bb
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.cdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.dfp b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.dfp
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.hdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.hdb
new file mode 100644
index 0000000..0b8cfef
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.hdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.kpt b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.kpt
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.logdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.rcfdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..1e85087
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.cmp.rcfdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.cdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.cdb
new file mode 100644
index 0000000..cdfa405
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.cdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.dpi b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.dpi
new file mode 100644
index 0000000..d6cb6e2
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.dpi
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.cdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..83b2a7b
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.cdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hb_info b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hb_info
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..7df70a0
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.hdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.sig b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hdb b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hdb
new file mode 100644
index 0000000..1cac056
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.hdb
diff --git a/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.kpt b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.kpt
new file mode 100644
index 0000000..94c6b1b
--- /dev/null
+++ b/one_hertz_clock/incremental_db/compiled_partitions/one_hertz_clock.root_partition.map.kpt
diff --git a/one_hertz_clock/one_hertz_clock.bdf b/one_hertz_clock/one_hertz_clock.bdf
new file mode 100644
index 0000000..798e347
--- /dev/null
+++ b/one_hertz_clock/one_hertz_clock.bdf
@@ -0,0 +1,4467 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 600 2928 768 2944)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLK" (rect 5 0 27 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 744 536 920 552)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "1_Hz" (rect 90 0 114 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
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+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst29" (rect 3 37 32 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12))
+		(line (pt 14 37)(pt 31 37))
+		(line (pt 14 12)(pt 14 37))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
+	)
+)
+(symbol
+	(rect 520 440 584 648)
+	(text "AND12" (rect 1 0 30 10)(font "Arial" (font_size 6)))
+	(text "inst30" (rect 3 197 32 209)(font "Arial" ))
+	(port
+		(pt 0 96)
+		(input)
+		(text "IN6" (rect 2 87 19 99)(font "Courier New" (bold))(invisible))
+		(text "IN6" (rect 2 87 19 99)(font "Courier New" (bold))(invisible))
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+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "IN7" (rect 2 103 19 115)(font "Courier New" (bold))(invisible))
+		(text "IN7" (rect 2 103 19 115)(font "Courier New" (bold))(invisible))
+		(line (pt 0 112)(pt 18 112))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 18 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
+		(line (pt 0 48)(pt 18 48))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "IN10" (rect 2 151 25 163)(font "Courier New" (bold))(invisible))
+		(text "IN10" (rect 2 151 25 163)(font "Courier New" (bold))(invisible))
+		(line (pt 0 160)(pt 18 160))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "IN8" (rect 2 119 19 131)(font "Courier New" (bold))(invisible))
+		(text "IN8" (rect 2 119 19 131)(font "Courier New" (bold))(invisible))
+		(line (pt 0 128)(pt 18 128))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "IN9" (rect 2 135 19 147)(font "Courier New" (bold))(invisible))
+		(text "IN9" (rect 2 135 19 147)(font "Courier New" (bold))(invisible))
+		(line (pt 0 144)(pt 18 144))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "IN11" (rect 2 167 25 179)(font "Courier New" (bold))(invisible))
+		(text "IN11" (rect 2 167 25 179)(font "Courier New" (bold))(invisible))
+		(line (pt 0 176)(pt 18 176))
+	)
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 18 16))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "IN5" (rect 2 71 19 83)(font "Courier New" (bold))(invisible))
+		(text "IN5" (rect 2 71 19 83)(font "Courier New" (bold))(invisible))
+		(line (pt 0 80)(pt 18 80))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
+		(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
+		(line (pt 0 64)(pt 18 64))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "IN12" (rect 2 183 25 195)(font "Courier New" (bold))(invisible))
+		(text "IN12" (rect 2 183 25 195)(font "Courier New" (bold))(invisible))
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+	)
+	(port
+		(pt 64 104)
+		(output)
+		(text "OUT" (rect 48 95 65 107)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 95 65 107)(font "Courier New" (bold))(invisible))
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+	)
+	(drawing
+		(line (pt 18 92)(pt 32 92))
+		(line (pt 18 195)(pt 18 13))
+		(line (pt 18 116)(pt 18 92))
+		(line (pt 19 117)(pt 32 117))
+		(arc (pt 32 116)(pt 32 92)(rect 20 92 45 117))
+	)
+)
+(symbol
+	(rect 336 384 400 528)
+	(text "AND8" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst31" (rect 3 133 32 145)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 18 16))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
+		(line (pt 0 48)(pt 18 48))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 18 32))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
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+		(line (pt 0 64)(pt 18 64))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "IN7" (rect 2 103 19 115)(font "Courier New" (bold))(invisible))
+		(text "IN7" (rect 2 103 19 115)(font "Courier New" (bold))(invisible))
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+	)
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+		(pt 0 96)
+		(input)
+		(text "IN6" (rect 2 87 19 99)(font "Courier New" (bold))(invisible))
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+		(input)
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+		(pt 0 80)
+		(input)
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+		(pt 64 72)
+		(output)
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+		(line (pt 18 59)(pt 33 59))
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+)
+(symbol
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+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst35" (rect 0 2 12 31)(font "Arial" )(vertical)(invisible))
+	(port
+		(pt 32 16)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
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+	(drawing
+		(line (pt 24 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 24))
+		(line (pt 24 8)(pt 24 24))
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+	(rotate270)
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+(symbol
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+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst38" (rect 3 68 32 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
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+		(line (pt 32 80)(pt 32 76))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
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+	)
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+		(pt 32 0)
+		(input)
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
+		(line (pt 32 4)(pt 32 0))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
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+		(line (pt 52 24)(pt 64 24))
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+		(circle (rect 28 68 36 76))
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+)
+(symbol
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+	(text "full_adder" (rect 5 0 61 14)(font "Arial" (font_size 8)))
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+		(input)
+		(text "X" (rect 0 0 8 14)(font "Arial" (font_size 8)))
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+	)
+	(port
+		(pt 0 48)
+		(input)
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+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Cin" (rect 0 0 17 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "SUM" (rect 0 0 25 14)(font "Arial" (font_size 8)))
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+	)
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+		(output)
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+	)
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+		(rectangle (rect 16 16 80 80))
+	)
+)
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+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
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+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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+	(pt 688 1296)
+)
+(connector
+	(pt 688 1536)
+	(pt 712 1536)
+)
+(connector
+	(pt 688 1296)
+	(pt 688 1416)
+)
+(connector
+	(pt 688 1656)
+	(pt 712 1656)
+)
+(connector
+	(pt 688 1416)
+	(pt 688 1536)
+)
+(connector
+	(pt 688 1776)
+	(pt 712 1776)
+)
+(connector
+	(pt 688 1536)
+	(pt 688 1656)
+)
+(connector
+	(pt 688 1896)
+	(pt 712 1896)
+)
+(connector
+	(pt 688 1656)
+	(pt 688 1776)
+)
+(connector
+	(pt 688 2016)
+	(pt 712 2016)
+)
+(connector
+	(pt 688 1776)
+	(pt 688 1896)
+)
+(connector
+	(pt 688 2136)
+	(pt 712 2136)
+)
+(connector
+	(pt 688 2256)
+	(pt 712 2256)
+)
+(connector
+	(pt 688 2376)
+	(pt 712 2376)
+)
+(connector
+	(pt 688 2496)
+	(pt 712 2496)
+)
+(connector
+	(pt 688 2616)
+	(pt 712 2616)
+)
+(connector
+	(pt 688 2736)
+	(pt 712 2736)
+)
+(connector
+	(pt 688 2856)
+	(pt 712 2856)
+)
+(connector
+	(pt 688 1896)
+	(pt 688 2016)
+)
+(connector
+	(pt 688 2016)
+	(pt 688 2136)
+)
+(connector
+	(pt 688 2136)
+	(pt 688 2256)
+)
+(connector
+	(pt 688 2256)
+	(pt 688 2376)
+)
+(connector
+	(pt 688 2376)
+	(pt 688 2496)
+)
+(connector
+	(pt 688 2496)
+	(pt 688 2616)
+)
+(connector
+	(pt 688 2616)
+	(pt 688 2736)
+)
+(connector
+	(pt 688 2736)
+	(pt 688 2856)
+)
+(connector
+	(text "Q[18]" (rect 492 616 519 628)(font "Arial" ))
+	(pt 520 632)
+	(pt 496 632)
+)
+(junction (pt 816 2880))
+(junction (pt 816 2760))
+(junction (pt 816 2640))
+(junction (pt 816 2520))
+(junction (pt 816 2280))
+(junction (pt 816 2160))
+(junction (pt 816 2040))
+(junction (pt 816 1920))
+(junction (pt 816 2400))
+(junction (pt 816 1800))
+(junction (pt 816 1680))
+(junction (pt 816 1560))
+(junction (pt 816 1440))
+(junction (pt 816 1200))
+(junction (pt 816 1080))
+(junction (pt 816 960))
+(junction (pt 816 840))
+(junction (pt 816 1320))
+(junction (pt 688 816))
+(junction (pt 688 696))
+(junction (pt 688 544))
+(junction (pt 688 936))
+(junction (pt 688 1176))
+(junction (pt 688 1056))
+(junction (pt 688 1296))
+(junction (pt 688 1536))
+(junction (pt 688 1416))
+(junction (pt 688 1656))
+(junction (pt 688 1776))
+(junction (pt 688 1896))
+(junction (pt 688 2016))
+(junction (pt 688 2136))
+(junction (pt 688 2256))
+(junction (pt 688 2376))
+(junction (pt 688 2496))
+(junction (pt 688 2616))
+(junction (pt 688 2736))
diff --git a/one_hertz_clock/one_hertz_clock.qpf b/one_hertz_clock/one_hertz_clock.qpf
new file mode 100644
index 0000000..bba644f
--- /dev/null
+++ b/one_hertz_clock/one_hertz_clock.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:11:14  February 23, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:11:14  February 23, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "one_hertz_clock"
diff --git a/one_hertz_clock/one_hertz_clock.qsf b/one_hertz_clock/one_hertz_clock.qsf
new file mode 100644
index 0000000..35e2d83
--- /dev/null
+++ b/one_hertz_clock/one_hertz_clock.qsf
@@ -0,0 +1,57 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:11:14  February 23, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		one_hertz_clock_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16U484C6
+set_global_assignment -name TOP_LEVEL_ENTITY one_hertz_clock
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:11:14  FEBRUARY 23, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name BDF_FILE one_hertz_clock.bdf
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/one_hertz_clock/one_hertz_clock.qws b/one_hertz_clock/one_hertz_clock.qws
new file mode 100644
index 0000000..6b70de3
--- /dev/null
+++ b/one_hertz_clock/one_hertz_clock.qws
diff --git a/one_hertz_clock/output_files/one_hertz_clock.asm.rpt b/one_hertz_clock/output_files/one_hertz_clock.asm.rpt
new file mode 100644
index 0000000..4285052
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for one_hertz_clock
+Tue Feb 23 16:02:18 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/one_hertz_clock/output_files/one_hertz_clock.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Feb 23 16:02:18 2016 ;
+; Revision Name         ; one_hertz_clock                       ;
+; Top-level Entity Name ; one_hertz_clock                       ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16U484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------+
+; Assembler Generated Files                           ;
++-----------------------------------------------------+
+; File Name                                           ;
++-----------------------------------------------------+
+; C:/one_hertz_clock/output_files/one_hertz_clock.sof ;
++-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Assembler Device Options: C:/one_hertz_clock/output_files/one_hertz_clock.sof ;
++----------------+--------------------------------------------------------------+
+; Option         ; Setting                                                      ;
++----------------+--------------------------------------------------------------+
+; Device         ; EP3C16U484C6                                                 ;
+; JTAG usercode  ; 0x000CB833                                                   ;
+; Checksum       ; 0x000CB833                                                   ;
++----------------+--------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 23 16:02:17 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 420 megabytes
+    Info: Processing ended: Tue Feb 23 16:02:18 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/one_hertz_clock/output_files/one_hertz_clock.done b/one_hertz_clock/output_files/one_hertz_clock.done
new file mode 100644
index 0000000..91e5ea4
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.done
@@ -0,0 +1 @@
+Tue Feb 23 16:02:21 2016
diff --git a/one_hertz_clock/output_files/one_hertz_clock.fit.rpt b/one_hertz_clock/output_files/one_hertz_clock.fit.rpt
new file mode 100644
index 0000000..7897f4a
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.fit.rpt
@@ -0,0 +1,1297 @@
+Fitter report for one_hertz_clock
+Tue Feb 23 16:02:16 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Other Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Fitter Messages
+ 35. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Feb 23 16:02:16 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; one_hertz_clock                                  ;
+; Top-level Entity Name              ; one_hertz_clock                                  ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16U484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 35 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 35 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 19 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 19                                               ;
+; Total pins                         ; 2 / 347 ( < 1 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16U484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; 1_Hz     ; Incomplete set of assignments ;
+; CLK      ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 70 ( 0.00 % )      ;
+;     -- Achieved     ; 0 / 70 ( 0.00 % )      ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 60      ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/one_hertz_clock/output_files/one_hertz_clock.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 35 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 16                    ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 19                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 19                    ;
+;     -- 3 input functions                    ; 12                    ;
+;     -- <=2 input functions                  ; 4                     ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 35                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 19 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 19 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 3 / 963 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 2 / 347 ( < 1 % )     ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
+; Maximum fan-out                             ; 19                    ;
+; Highest non-global fan-out                  ; 19                    ;
+; Total fan-out                               ; 166                   ;
+; Average fan-out                             ; 2.41                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 35 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 16                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 19                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 19                   ; 0                              ;
+;     -- 3 input functions                    ; 12                   ; 0                              ;
+;     -- <=2 input functions                  ; 4                    ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 35                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 19                   ; 0                              ;
+;     -- Dedicated logic registers            ; 19 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 3 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 2                    ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+; Clock control block                         ; 1 / 24 ( 4 % )       ; 0 / 24 ( 0 % )                 ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 161                  ; 5                              ;
+;     -- Registered Connections               ; 70                   ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 1                    ; 0                              ;
+;     -- Output Ports                         ; 1                    ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLK  ; G2    ; 1        ; 0            ; 14           ; 0            ; 19                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; Fitter               ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; 1_Hz ; R21   ; 5        ; 41           ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++-----------------------------------------------------------+
+; I/O Bank Usage                                            ;
++----------+-----------------+---------------+--------------+
+; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
++----------+-----------------+---------------+--------------+
+; 1        ; 5 / 33 ( 15 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )  ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )  ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )  ; 2.5V          ; --           ;
+; 5        ; 1 / 46 ( 2 % )  ; 2.5V          ; --           ;
+; 6        ; 1 / 43 ( 2 % )  ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )  ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )  ; 2.5V          ; --           ;
++----------+-----------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; CLK                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; 1_Hz                                                      ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                 ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
+; |one_hertz_clock           ; 35 (26)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 2    ; 0            ; 16 (7)       ; 0 (0)             ; 19 (19)          ; |one_hertz_clock                    ; work         ;
+;    |full_adder:inst369|    ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |one_hertz_clock|full_adder:inst369 ; work         ;
+;    |full_adder:inst59|     ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |one_hertz_clock|full_adder:inst59  ; work         ;
+;    |full_adder:inst73|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |one_hertz_clock|full_adder:inst73  ; work         ;
+;    |full_adder:inst88|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |one_hertz_clock|full_adder:inst88  ; work         ;
+;    |full_adder:inst98|     ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |one_hertz_clock|full_adder:inst98  ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                  ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; 1_Hz ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; CLK  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; CLK                 ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                  ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_G2   ; 19      ; Clock ; yes    ; Global Clock         ; GCLK4            ; --                        ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                            ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_G2   ; 19      ; 1                                    ; Global Clock         ; GCLK4            ; --                        ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------+
+; Non-Global High Fan-Out Signals     ;
++---------------------------+---------+
+; Name                      ; Fan-Out ;
++---------------------------+---------+
+; inst30                    ; 19      ;
+; inst43                    ; 5       ;
+; inst63                    ; 5       ;
+; inst77                    ; 5       ;
+; inst30~0                  ; 5       ;
+; inst459                   ; 5       ;
+; full_adder:inst73|inst6   ; 4       ;
+; full_adder:inst59|inst6   ; 4       ;
+; inst92                    ; 4       ;
+; inst82                    ; 4       ;
+; inst389                   ; 4       ;
+; inst48                    ; 4       ;
+; inst67                    ; 4       ;
+; inst3799999               ; 4       ;
+; inst50                    ; 4       ;
+; full_adder:inst88|inst6   ; 3       ;
+; full_adder:inst369|inst6  ; 3       ;
+; inst102                   ; 3       ;
+; inst87                    ; 3       ;
+; inst97                    ; 3       ;
+; inst58                    ; 3       ;
+; inst72                    ; 3       ;
+; inst38                    ; 3       ;
+; full_adder:inst98|inst6   ; 2       ;
+; inst107                   ; 2       ;
+; inst30~1                  ; 2       ;
+; inst40                    ; 2       ;
+; inst3799999~0             ; 1       ;
+; inst109                   ; 1       ;
+; inst104                   ; 1       ;
+; inst89                    ; 1       ;
+; full_adder:inst88|inst    ; 1       ;
+; inst94                    ; 1       ;
+; inst99                    ; 1       ;
+; inst84                    ; 1       ;
+; inst399                   ; 1       ;
+; inst45                    ; 1       ;
+; inst55                    ; 1       ;
+; inst60                    ; 1       ;
+; full_adder:inst59|inst    ; 1       ;
+; inst64                    ; 1       ;
+; inst69                    ; 1       ;
+; inst74                    ; 1       ;
+; full_adder:inst73|inst    ; 1       ;
+; inst79                    ; 1       ;
+; full_adder:inst59|inst6~0 ; 1       ;
+; inst39                    ; 1       ;
+; inst4299                  ; 1       ;
+; inst497                   ; 1       ;
+; inst52                    ; 1       ;
+; inst30~5                  ; 1       ;
+; inst30~4                  ; 1       ;
+; inst30~3                  ; 1       ;
+; inst30~2                  ; 1       ;
++---------------------------+---------+
+
+
++-----------------------------------------------------+
+; Other Routing Usage Summary                         ;
++-----------------------------+-----------------------+
+; Other Routing Resource Type ; Usage                 ;
++-----------------------------+-----------------------+
+; Block interconnects         ; 30 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects            ; 0 / 31,272 ( 0 % )    ;
+; Direct links                ; 23 / 47,787 ( < 1 % ) ;
+; Global clocks               ; 1 / 20 ( 5 % )        ;
+; Local interconnects         ; 26 / 15,408 ( < 1 % ) ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects            ; 6 / 41,310 ( < 1 % )  ;
++-----------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 11.67) ; Number of LABs  (Total = 3) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 1                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 0                           ;
+; 16                                          ; 2                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 3) ;
++------------------------------------+-----------------------------+
+; 1 Clock                            ; 3                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 18.00) ; Number of LABs  (Total = 3) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 1                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 0                           ;
+; 20                                           ; 0                           ;
+; 21                                           ; 0                           ;
+; 22                                           ; 0                           ;
+; 23                                           ; 0                           ;
+; 24                                           ; 2                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 5.33) ; Number of LABs  (Total = 3) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 1                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 1                           ;
+; 7                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 6.67) ; Number of LABs  (Total = 3) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 1                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 1                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 2         ; 0            ; 0            ; 2         ; 2         ; 0            ; 1            ; 0            ; 0            ; 1            ; 0            ; 1            ; 1            ; 0            ; 0            ; 0            ; 1            ; 0            ; 0            ; 0            ; 0            ; 0            ; 2         ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 2            ; 2            ; 2            ; 2            ; 2            ; 0         ; 2            ; 2            ; 0         ; 0         ; 2            ; 1            ; 2            ; 2            ; 1            ; 2            ; 1            ; 1            ; 2            ; 2            ; 2            ; 1            ; 2            ; 2            ; 2            ; 2            ; 2            ; 0         ; 2            ; 2            ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; 1_Hz               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16U484C6 for design "one_hertz_clock"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40U484C6 is compatible
+    Info (176445): Device EP3C55U484C6 is compatible
+    Info (176445): Device EP3C80U484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 2 total pins
+    Info (169086): Pin 1_Hz not assigned to an exact location on the device
+    Info (169086): Pin CLK not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node CLK~input (placed in PIN G2 (CLK0, DIFFCLK_0p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X31_Y10 to location X41_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Info (144001): Generated suppressed messages file C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 1090 megabytes
+    Info: Processing ended: Tue Feb 23 16:02:16 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/one_hertz_clock/output_files/one_hertz_clock.fit.smsg.
+
+
diff --git a/one_hertz_clock/output_files/one_hertz_clock.fit.smsg b/one_hertz_clock/output_files/one_hertz_clock.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/one_hertz_clock/output_files/one_hertz_clock.fit.summary b/one_hertz_clock/output_files/one_hertz_clock.fit.summary
new file mode 100644
index 0000000..20e671a
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Feb 23 16:02:16 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : one_hertz_clock
+Top-level Entity Name : one_hertz_clock
+Family : Cyclone III
+Device : EP3C16U484C6
+Timing Models : Final
+Total logic elements : 35 / 15,408 ( < 1 % )
+    Total combinational functions : 35 / 15,408 ( < 1 % )
+    Dedicated logic registers : 19 / 15,408 ( < 1 % )
+Total registers : 19
+Total pins : 2 / 347 ( < 1 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/one_hertz_clock/output_files/one_hertz_clock.flow.rpt b/one_hertz_clock/output_files/one_hertz_clock.flow.rpt
new file mode 100644
index 0000000..7f6aa06
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.flow.rpt
@@ -0,0 +1,125 @@
+Flow report for one_hertz_clock
+Tue Feb 23 16:02:20 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Feb 23 16:02:18 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; one_hertz_clock                                  ;
+; Top-level Entity Name              ; one_hertz_clock                                  ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16U484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 35 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 35 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 19 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 19                                               ;
+; Total pins                         ; 2 / 347 ( < 1 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/23/2016 16:02:10 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; one_hertz_clock     ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564169585.145624333007612       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 464 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:05     ; 1.0                     ; 1090 MB             ; 00:00:05                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 420 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 485 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:08     ; --                      ; --                  ; 00:00:08                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-012     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-012     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-012     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-012     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock
+quartus_fit --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock
+quartus_asm --read_settings_files=off --write_settings_files=off one_hertz_clock -c one_hertz_clock
+quartus_sta one_hertz_clock -c one_hertz_clock
+
+
+
diff --git a/one_hertz_clock/output_files/one_hertz_clock.jdi b/one_hertz_clock/output_files/one_hertz_clock.jdi
new file mode 100644
index 0000000..c18e470
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="9c505f5fec1ea6e95139"/>
+  </project>
+  <file_info>
+    <file device="EP3C16U484C6" path="one_hertz_clock.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/one_hertz_clock/output_files/one_hertz_clock.map.rpt b/one_hertz_clock/output_files/one_hertz_clock.map.rpt
new file mode 100644
index 0000000..3455ba8
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.map.rpt
@@ -0,0 +1,290 @@
+Analysis & Synthesis report for one_hertz_clock
+Tue Feb 23 16:02:11 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Feb 23 16:02:10 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; one_hertz_clock                                  ;
+; Top-level Entity Name              ; one_hertz_clock                                  ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 35                                               ;
+;     Total combinational functions  ; 35                                               ;
+;     Dedicated logic registers      ; 19                                               ;
+; Total registers                    ; 19                                               ;
+; Total pins                         ; 2                                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16U484C6       ;                    ;
+; Top-level entity name                                                      ; one_hertz_clock    ; one_hertz_clock    ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                     ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path           ; Library ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------+---------+
+; ../adder/full_adder.bdf          ; yes             ; User Block Diagram/Schematic File  ; C:/adder/full_adder.bdf                ;         ;
+; one_hertz_clock.bdf              ; yes             ; User Block Diagram/Schematic File  ; C:/one_hertz_clock/one_hertz_clock.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------+---------+
+
+
++------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary          ;
++---------------------------------------------+--------+
+; Resource                                    ; Usage  ;
++---------------------------------------------+--------+
+; Estimated Total logic elements              ; 35     ;
+;                                             ;        ;
+; Total combinational functions               ; 35     ;
+; Logic element usage by number of LUT inputs ;        ;
+;     -- 4 input functions                    ; 19     ;
+;     -- 3 input functions                    ; 12     ;
+;     -- <=2 input functions                  ; 4      ;
+;                                             ;        ;
+; Logic elements by mode                      ;        ;
+;     -- normal mode                          ; 35     ;
+;     -- arithmetic mode                      ; 0      ;
+;                                             ;        ;
+; Total registers                             ; 19     ;
+;     -- Dedicated logic registers            ; 19     ;
+;     -- I/O registers                        ; 0      ;
+;                                             ;        ;
+; I/O pins                                    ; 2      ;
+; Embedded Multiplier 9-bit elements          ; 0      ;
+; Maximum fan-out node                        ; inst30 ;
+; Maximum fan-out                             ; 19     ;
+; Total fan-out                               ; 160    ;
+; Average fan-out                             ; 2.76   ;
++---------------------------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                 ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
+; |one_hertz_clock           ; 35 (26)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 2    ; 0            ; |one_hertz_clock                    ; work         ;
+;    |full_adder:inst369|    ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |one_hertz_clock|full_adder:inst369 ; work         ;
+;    |full_adder:inst59|     ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |one_hertz_clock|full_adder:inst59  ; work         ;
+;    |full_adder:inst73|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |one_hertz_clock|full_adder:inst73  ; work         ;
+;    |full_adder:inst88|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |one_hertz_clock|full_adder:inst88  ; work         ;
+;    |full_adder:inst98|     ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |one_hertz_clock|full_adder:inst98  ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 19    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 23 16:02:09 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off one_hertz_clock -c one_hertz_clock
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file /adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file one_hertz_clock.bdf
+    Info (12023): Found entity 1: one_hertz_clock
+Info (12127): Elaborating entity "one_hertz_clock" for the top level hierarchy
+Warning (275089): Not all bits in bus "N[14..5]" are used
+Warning (275080): Converted elements in bus name "N" using legacy naming rules. Make any assignments on the new names, not on the original names.
+    Warning (275081): Converted element name(s) from "N[5]" to "N5"
+    Warning (275081): Converted element name(s) from "N[6]" to "N6"
+    Warning (275081): Converted element name(s) from "N[7]" to "N7"
+    Warning (275081): Converted element name(s) from "N[9]" to "N9"
+    Warning (275081): Converted element name(s) from "N[10]" to "N10"
+    Warning (275081): Converted element name(s) from "N[11]" to "N11"
+    Warning (275081): Converted element name(s) from "N[12]" to "N12"
+    Warning (275081): Converted element name(s) from "N[14]" to "N14"
+    Warning (275081): Converted element name(s) from "N[5]" to "N5"
+    Warning (275081): Converted element name(s) from "N[6]" to "N6"
+    Warning (275081): Converted element name(s) from "N[7]" to "N7"
+    Warning (275081): Converted element name(s) from "N[9]" to "N9"
+    Warning (275081): Converted element name(s) from "N[10]" to "N10"
+    Warning (275081): Converted element name(s) from "N[11]" to "N11"
+    Warning (275081): Converted element name(s) from "N[12]" to "N12"
+    Warning (275081): Converted element name(s) from "N[14]" to "N14"
+Info (12128): Elaborating entity "full_adder" for hierarchy "full_adder:inst78"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 37 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 1 input pins
+    Info (21059): Implemented 1 output pins
+    Info (21061): Implemented 35 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 18 warnings
+    Info: Peak virtual memory: 464 megabytes
+    Info: Processing ended: Tue Feb 23 16:02:11 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/one_hertz_clock/output_files/one_hertz_clock.map.summary b/one_hertz_clock/output_files/one_hertz_clock.map.summary
new file mode 100644
index 0000000..3540a8a
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Feb 23 16:02:10 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : one_hertz_clock
+Top-level Entity Name : one_hertz_clock
+Family : Cyclone III
+Total logic elements : 35
+    Total combinational functions : 35
+    Dedicated logic registers : 19
+Total registers : 19
+Total pins : 2
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/one_hertz_clock/output_files/one_hertz_clock.pin b/one_hertz_clock/output_files/one_hertz_clock.pin
new file mode 100644
index 0000000..5de5929
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "one_hertz_clock"  ASSIGNED TO AN: EP3C16U484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+CLK                          : G2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+1_Hz                         : R21       : output : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/one_hertz_clock/output_files/one_hertz_clock.sof b/one_hertz_clock/output_files/one_hertz_clock.sof
new file mode 100644
index 0000000..3ed4f06
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.sof
diff --git a/one_hertz_clock/output_files/one_hertz_clock.sta.rpt b/one_hertz_clock/output_files/one_hertz_clock.sta.rpt
new file mode 100644
index 0000000..d6a59b0
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.sta.rpt
@@ -0,0 +1,1515 @@
+TimeQuest Timing Analyzer report for one_hertz_clock
+Tue Feb 23 16:02:20 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'CLK'
+ 13. Slow 1200mV 85C Model Hold: 'CLK'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'
+ 15. Clock to Output Times
+ 16. Minimum Clock to Output Times
+ 17. Slow 1200mV 85C Model Metastability Report
+ 18. Slow 1200mV 0C Model Fmax Summary
+ 19. Slow 1200mV 0C Model Setup Summary
+ 20. Slow 1200mV 0C Model Hold Summary
+ 21. Slow 1200mV 0C Model Recovery Summary
+ 22. Slow 1200mV 0C Model Removal Summary
+ 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 24. Slow 1200mV 0C Model Setup: 'CLK'
+ 25. Slow 1200mV 0C Model Hold: 'CLK'
+ 26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 27. Clock to Output Times
+ 28. Minimum Clock to Output Times
+ 29. Slow 1200mV 0C Model Metastability Report
+ 30. Fast 1200mV 0C Model Setup Summary
+ 31. Fast 1200mV 0C Model Hold Summary
+ 32. Fast 1200mV 0C Model Recovery Summary
+ 33. Fast 1200mV 0C Model Removal Summary
+ 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 35. Fast 1200mV 0C Model Setup: 'CLK'
+ 36. Fast 1200mV 0C Model Hold: 'CLK'
+ 37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 38. Clock to Output Times
+ 39. Minimum Clock to Output Times
+ 40. Fast 1200mV 0C Model Metastability Report
+ 41. Multicorner Timing Analysis Summary
+ 42. Clock to Output Times
+ 43. Minimum Clock to Output Times
+ 44. Board Trace Model Assignments
+ 45. Input Transition Times
+ 46. Slow Corner Signal Integrity Metrics
+ 47. Fast Corner Signal Integrity Metrics
+ 48. Setup Transfers
+ 49. Hold Transfers
+ 50. Report TCCS
+ 51. Report RSKM
+ 52. Unconstrained Paths
+ 53. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; one_hertz_clock                                                    ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16U484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; CLK        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                        ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 339.21 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-------+--------+--------------------+
+; Clock ; Slack  ; End Point TNS      ;
++-------+--------+--------------------+
+; CLK   ; -1.948 ; -30.172            ;
++-------+--------+--------------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; CLK   ; 0.344 ; 0.000              ;
++-------+-------+--------------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-------+--------+----------------------------------+
+; Clock ; Slack  ; End Point TNS                    ;
++-------+--------+----------------------------------+
+; CLK   ; -3.000 ; -22.000                          ;
++-------+--------+----------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLK'                                                                   ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; -1.948 ; inst50      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.881      ;
+; -1.946 ; inst43      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.879      ;
+; -1.933 ; inst92      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.867      ;
+; -1.925 ; inst50      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.858      ;
+; -1.924 ; inst50      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.857      ;
+; -1.923 ; inst43      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.856      ;
+; -1.922 ; inst43      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.855      ;
+; -1.908 ; inst97      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.842      ;
+; -1.904 ; inst92      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.838      ;
+; -1.879 ; inst97      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.813      ;
+; -1.846 ; inst389     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.779      ;
+; -1.823 ; inst389     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.756      ;
+; -1.822 ; inst389     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.755      ;
+; -1.816 ; inst102     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.386      ;
+; -1.795 ; inst40      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.728      ;
+; -1.787 ; inst82      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.721      ;
+; -1.787 ; inst102     ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.357      ;
+; -1.784 ; inst92      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.718      ;
+; -1.781 ; inst92      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.715      ;
+; -1.780 ; inst92      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.714      ;
+; -1.772 ; inst40      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.705      ;
+; -1.771 ; inst40      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.704      ;
+; -1.759 ; inst97      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.693      ;
+; -1.758 ; inst82      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.692      ;
+; -1.756 ; inst97      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.690      ;
+; -1.755 ; inst97      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.689      ;
+; -1.741 ; inst50      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.674      ;
+; -1.739 ; inst43      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.672      ;
+; -1.728 ; inst50      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.661      ;
+; -1.726 ; inst43      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.659      ;
+; -1.722 ; inst50      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.655      ;
+; -1.720 ; inst43      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.653      ;
+; -1.719 ; inst38      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.652      ;
+; -1.706 ; inst77      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.640      ;
+; -1.704 ; inst459     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.637      ;
+; -1.696 ; inst38      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.629      ;
+; -1.695 ; inst38      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.628      ;
+; -1.681 ; inst459     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.614      ;
+; -1.680 ; inst459     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.613      ;
+; -1.677 ; inst77      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.611      ;
+; -1.667 ; inst102     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.237      ;
+; -1.664 ; inst102     ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.234      ;
+; -1.663 ; inst102     ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.233      ;
+; -1.660 ; inst92      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.594      ;
+; -1.659 ; inst92      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.593      ;
+; -1.657 ; inst92      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.591      ;
+; -1.655 ; inst92      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.589      ;
+; -1.654 ; inst92      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.588      ;
+; -1.639 ; inst389     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.572      ;
+; -1.638 ; inst82      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.572      ;
+; -1.635 ; inst82      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.569      ;
+; -1.635 ; inst97      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.569      ;
+; -1.634 ; inst82      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.568      ;
+; -1.634 ; inst97      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.568      ;
+; -1.632 ; inst97      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.566      ;
+; -1.630 ; inst97      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.564      ;
+; -1.629 ; inst97      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.563      ;
+; -1.626 ; inst389     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.559      ;
+; -1.620 ; inst389     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.553      ;
+; -1.601 ; inst87      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.535      ;
+; -1.600 ; inst50      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.287      ; 2.882      ;
+; -1.598 ; inst43      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.287      ; 2.880      ;
+; -1.588 ; inst40      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.521      ;
+; -1.582 ; inst92      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.288      ; 2.865      ;
+; -1.580 ; inst3799999 ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.513      ;
+; -1.575 ; inst40      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.508      ;
+; -1.569 ; inst40      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.502      ;
+; -1.561 ; inst87      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.495      ;
+; -1.559 ; inst77      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.493      ;
+; -1.557 ; inst3799999 ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.490      ;
+; -1.557 ; inst77      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.491      ;
+; -1.557 ; inst77      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.491      ;
+; -1.557 ; inst97      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.288      ; 2.840      ;
+; -1.556 ; inst3799999 ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.489      ;
+; -1.543 ; inst102     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.113      ;
+; -1.542 ; inst102     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.112      ;
+; -1.540 ; inst102     ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.110      ;
+; -1.538 ; inst102     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.108      ;
+; -1.537 ; inst102     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.425     ; 2.107      ;
+; -1.523 ; inst72      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.457      ;
+; -1.518 ; inst67      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.452      ;
+; -1.514 ; inst82      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.448      ;
+; -1.513 ; inst82      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.447      ;
+; -1.512 ; inst38      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.445      ;
+; -1.511 ; inst82      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.445      ;
+; -1.509 ; inst82      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.443      ;
+; -1.508 ; inst82      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.442      ;
+; -1.506 ; inst58      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.439      ;
+; -1.504 ; inst40      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.437      ;
+; -1.499 ; inst38      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.432      ;
+; -1.498 ; inst389     ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.287      ; 2.780      ;
+; -1.497 ; inst459     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.430      ;
+; -1.493 ; inst38      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.062     ; 2.426      ;
+; -1.492 ; inst72      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.426      ;
+; -1.490 ; inst92      ; inst459 ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.424      ;
+; -1.489 ; inst92      ; inst43  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.423      ;
+; -1.489 ; inst92      ; inst58  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.423      ;
+; -1.489 ; inst67      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.423      ;
+; -1.485 ; inst92      ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.419      ;
+; -1.485 ; inst92      ; inst50  ; CLK          ; CLK         ; 1.000        ; -0.061     ; 2.419      ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLK'                                                                       ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.344 ; inst102     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.076      ; 0.577      ;
+; 0.358 ; inst38      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; inst40      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; inst459     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; inst389     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; inst43      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; inst50      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; inst48      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst63      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst67      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst77      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst82      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst92      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst97      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst107     ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.361 ; inst3799999 ; inst3799999 ; CLK          ; CLK         ; 0.000        ; 0.062      ; 0.580      ;
+; 0.425 ; inst92      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.007      ;
+; 0.497 ; inst97      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.079      ;
+; 0.618 ; inst92      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.836      ;
+; 0.738 ; inst82      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.320      ;
+; 0.759 ; inst63      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.977      ;
+; 0.789 ; inst92      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.007      ;
+; 0.800 ; inst77      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.018      ;
+; 0.802 ; inst43      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.020      ;
+; 0.814 ; inst87      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.396      ;
+; 0.861 ; inst97      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.079      ;
+; 0.895 ; inst82      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.113      ;
+; 0.902 ; inst3799999 ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.121      ;
+; 0.903 ; inst3799999 ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.122      ;
+; 0.909 ; inst459     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.128      ;
+; 0.922 ; inst38      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.141      ;
+; 0.942 ; inst72      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.160      ;
+; 0.953 ; inst3799999 ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.172      ;
+; 0.956 ; inst3799999 ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.175      ;
+; 0.970 ; inst87      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.188      ;
+; 0.993 ; inst77      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.575      ;
+; 1.016 ; inst58      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.235      ;
+; 1.034 ; inst67      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.252      ;
+; 1.035 ; inst82      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.253      ;
+; 1.037 ; inst82      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.255      ;
+; 1.043 ; inst389     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.262      ;
+; 1.052 ; inst63      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.270      ;
+; 1.058 ; inst38      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.277      ;
+; 1.061 ; inst38      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.280      ;
+; 1.074 ; inst102     ; inst107     ; CLK          ; CLK         ; 0.000        ; -0.288     ; 0.943      ;
+; 1.102 ; inst82      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.320      ;
+; 1.111 ; inst87      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.329      ;
+; 1.113 ; inst87      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.331      ;
+; 1.115 ; inst40      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.334      ;
+; 1.118 ; inst40      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.337      ;
+; 1.135 ; inst50      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.354      ;
+; 1.165 ; inst77      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.383      ;
+; 1.172 ; inst389     ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.390      ;
+; 1.178 ; inst87      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.396      ;
+; 1.208 ; inst48      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.427      ;
+; 1.215 ; inst67      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.797      ;
+; 1.236 ; inst50      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.455      ;
+; 1.258 ; inst3799999 ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.477      ;
+; 1.264 ; inst107     ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.483      ;
+; 1.264 ; inst107     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.483      ;
+; 1.264 ; inst50      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.482      ;
+; 1.266 ; inst107     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.485      ;
+; 1.267 ; inst107     ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.486      ;
+; 1.267 ; inst107     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.486      ;
+; 1.267 ; inst107     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.486      ;
+; 1.268 ; inst107     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.487      ;
+; 1.279 ; inst3799999 ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.498      ;
+; 1.281 ; inst72      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.863      ;
+; 1.288 ; inst107     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.870      ;
+; 1.290 ; inst77      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.508      ;
+; 1.292 ; inst77      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.510      ;
+; 1.305 ; inst48      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.523      ;
+; 1.317 ; inst63      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.899      ;
+; 1.317 ; inst459     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.536      ;
+; 1.324 ; inst389     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.543      ;
+; 1.338 ; inst67      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.556      ;
+; 1.341 ; inst67      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.559      ;
+; 1.357 ; inst77      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.575      ;
+; 1.358 ; inst58      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.576      ;
+; 1.363 ; inst38      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.582      ;
+; 1.367 ; inst43      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.586      ;
+; 1.374 ; inst67      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.592      ;
+; 1.375 ; inst50      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.594      ;
+; 1.377 ; inst50      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.596      ;
+; 1.378 ; inst50      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.597      ;
+; 1.378 ; inst50      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.597      ;
+; 1.384 ; inst38      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.603      ;
+; 1.399 ; inst50      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 1.981      ;
+; 1.399 ; inst3799999 ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.618      ;
+; 1.404 ; inst72      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.622      ;
+; 1.407 ; inst72      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.625      ;
+; 1.408 ; inst3799999 ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.626      ;
+; 1.409 ; inst459     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.628      ;
+; 1.413 ; inst48      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.631      ;
+; 1.414 ; inst48      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.632      ;
+; 1.420 ; inst40      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.062      ; 1.639      ;
+; 1.421 ; inst3799999 ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.425      ; 2.003      ;
+; 1.433 ; inst107     ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.651      ;
+; 1.434 ; inst107     ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.652      ;
+; 1.435 ; inst107     ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.061      ; 1.653      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'                                                           ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst102                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst107                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3799999               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst389                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst43                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst459                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst48                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst50                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst58                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst63                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst67                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst72                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst77                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst82                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst87                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst92                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst97                    ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst102                   ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst107                   ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst48                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst63                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst67                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst72                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst77                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst82                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst87                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst92                    ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst97                    ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999               ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38                    ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst389                   ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40                    ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst43                    ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst459                   ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst50                    ;
+; 0.187  ; 0.371        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst58                    ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst102|clk               ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst107|clk               ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst389|clk               ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst43|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst459|clk               ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst48|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst50|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst58|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst63|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst67|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst72|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst77|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst82|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst87|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst92|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst97|clk                ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst107                   ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3799999               ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst389                   ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst43                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst459                   ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst48                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst50                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst58                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst63                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst67                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst72                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst77                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst82                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst87                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst92                    ;
+; 0.412  ; 0.628        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst97                    ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst102                   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst389|clk               ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk                ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk                ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst43|clk                ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst459|clk               ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst50|clk                ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst58|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst107|clk               ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst48|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst63|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst67|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst72|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst77|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst82|clk                ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst87|clk                ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 6.727 ; 6.886 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 5.932 ; 5.992 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                         ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 379.94 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-------+--------+-------------------+
+; Clock ; Slack  ; End Point TNS     ;
++-------+--------+-------------------+
+; CLK   ; -1.632 ; -25.089           ;
++-------+--------+-------------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.298 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -22.000                         ;
++-------+--------+---------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLK'                                                                    ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; -1.632 ; inst50      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.572      ;
+; -1.629 ; inst43      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.569      ;
+; -1.622 ; inst92      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.563      ;
+; -1.603 ; inst50      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.543      ;
+; -1.602 ; inst50      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.542      ;
+; -1.600 ; inst43      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.540      ;
+; -1.599 ; inst43      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.539      ;
+; -1.598 ; inst97      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.539      ;
+; -1.591 ; inst92      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.532      ;
+; -1.567 ; inst97      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.508      ;
+; -1.547 ; inst389     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.487      ;
+; -1.520 ; inst102     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.386     ; 2.129      ;
+; -1.518 ; inst389     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.458      ;
+; -1.517 ; inst389     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.457      ;
+; -1.500 ; inst92      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.440      ;
+; -1.496 ; inst92      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.436      ;
+; -1.496 ; inst92      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.436      ;
+; -1.495 ; inst82      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.436      ;
+; -1.491 ; inst40      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.431      ;
+; -1.489 ; inst102     ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 2.098      ;
+; -1.476 ; inst97      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.416      ;
+; -1.472 ; inst97      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.412      ;
+; -1.472 ; inst97      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.412      ;
+; -1.464 ; inst82      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.405      ;
+; -1.462 ; inst40      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.402      ;
+; -1.461 ; inst40      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.401      ;
+; -1.444 ; inst50      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.384      ;
+; -1.441 ; inst43      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.381      ;
+; -1.433 ; inst77      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.374      ;
+; -1.429 ; inst38      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.369      ;
+; -1.423 ; inst50      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.362      ;
+; -1.420 ; inst43      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.359      ;
+; -1.418 ; inst50      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.358      ;
+; -1.415 ; inst459     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.355      ;
+; -1.415 ; inst43      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.355      ;
+; -1.400 ; inst38      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.340      ;
+; -1.399 ; inst38      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.339      ;
+; -1.398 ; inst102     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.387     ; 2.006      ;
+; -1.396 ; inst77      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.337      ;
+; -1.394 ; inst102     ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.387     ; 2.002      ;
+; -1.394 ; inst102     ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.387     ; 2.002      ;
+; -1.386 ; inst459     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.326      ;
+; -1.385 ; inst459     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.325      ;
+; -1.381 ; inst92      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.322      ;
+; -1.380 ; inst92      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.321      ;
+; -1.375 ; inst92      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.316      ;
+; -1.373 ; inst92      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.314      ;
+; -1.373 ; inst82      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.313      ;
+; -1.372 ; inst92      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.313      ;
+; -1.369 ; inst82      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.309      ;
+; -1.369 ; inst82      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.309      ;
+; -1.361 ; inst87      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.302      ;
+; -1.359 ; inst389     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.299      ;
+; -1.357 ; inst97      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.298      ;
+; -1.356 ; inst97      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.297      ;
+; -1.351 ; inst97      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.292      ;
+; -1.349 ; inst97      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.290      ;
+; -1.348 ; inst97      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.289      ;
+; -1.338 ; inst389     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.277      ;
+; -1.333 ; inst389     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.273      ;
+; -1.324 ; inst87      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.265      ;
+; -1.318 ; inst77      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.258      ;
+; -1.316 ; inst50      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.262      ; 2.573      ;
+; -1.316 ; inst77      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.256      ;
+; -1.316 ; inst77      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.256      ;
+; -1.313 ; inst43      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.262      ; 2.570      ;
+; -1.303 ; inst40      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.243      ;
+; -1.300 ; inst3799999 ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.240      ;
+; -1.300 ; inst92      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.263      ; 2.558      ;
+; -1.282 ; inst40      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.221      ;
+; -1.281 ; inst72      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.222      ;
+; -1.279 ; inst102     ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 1.888      ;
+; -1.278 ; inst102     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 1.887      ;
+; -1.277 ; inst40      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.217      ;
+; -1.276 ; inst67      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.217      ;
+; -1.276 ; inst97      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.263      ; 2.534      ;
+; -1.273 ; inst102     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 1.882      ;
+; -1.271 ; inst3799999 ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.211      ;
+; -1.271 ; inst102     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 1.880      ;
+; -1.270 ; inst3799999 ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.210      ;
+; -1.270 ; inst102     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.386     ; 1.879      ;
+; -1.254 ; inst82      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.195      ;
+; -1.253 ; inst82      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.194      ;
+; -1.248 ; inst82      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.189      ;
+; -1.246 ; inst87      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.186      ;
+; -1.246 ; inst82      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.187      ;
+; -1.245 ; inst82      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.186      ;
+; -1.244 ; inst72      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.185      ;
+; -1.244 ; inst87      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.184      ;
+; -1.244 ; inst87      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.184      ;
+; -1.241 ; inst38      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.181      ;
+; -1.239 ; inst67      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.180      ;
+; -1.233 ; inst92      ; inst459 ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.174      ;
+; -1.232 ; inst92      ; inst43  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.173      ;
+; -1.232 ; inst92      ; inst58  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.173      ;
+; -1.231 ; inst389     ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.262      ; 2.488      ;
+; -1.229 ; inst92      ; inst50  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.170      ;
+; -1.229 ; inst58      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.055     ; 2.169      ;
+; -1.228 ; inst92      ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.169      ;
+; -1.228 ; inst92      ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.054     ; 2.169      ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLK'                                                                        ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.298 ; inst102     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.069      ; 0.511      ;
+; 0.312 ; inst38      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst40      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst459     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst389     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst43      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst63      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst67      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst77      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst50      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; inst48      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; inst82      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; inst92      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; inst97      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; inst107     ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; inst3799999 ; inst3799999 ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.519      ;
+; 0.379 ; inst92      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 0.909      ;
+; 0.440 ; inst97      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 0.970      ;
+; 0.553 ; inst92      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.751      ;
+; 0.660 ; inst82      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.190      ;
+; 0.690 ; inst63      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.889      ;
+; 0.711 ; inst92      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.909      ;
+; 0.717 ; inst77      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.916      ;
+; 0.728 ; inst87      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.258      ;
+; 0.732 ; inst43      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.930      ;
+; 0.772 ; inst97      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.054      ; 0.970      ;
+; 0.808 ; inst82      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.006      ;
+; 0.826 ; inst3799999 ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.025      ;
+; 0.826 ; inst3799999 ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.025      ;
+; 0.832 ; inst459     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.031      ;
+; 0.850 ; inst38      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.049      ;
+; 0.853 ; inst72      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.051      ;
+; 0.859 ; inst3799999 ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.058      ;
+; 0.862 ; inst3799999 ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.061      ;
+; 0.875 ; inst87      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.073      ;
+; 0.887 ; inst77      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.387      ; 1.418      ;
+; 0.915 ; inst58      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.114      ;
+; 0.929 ; inst82      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.127      ;
+; 0.931 ; inst82      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.129      ;
+; 0.938 ; inst389     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.137      ;
+; 0.940 ; inst67      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.139      ;
+; 0.952 ; inst38      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.151      ;
+; 0.955 ; inst38      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.154      ;
+; 0.960 ; inst63      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.159      ;
+; 0.979 ; inst102     ; inst107     ; CLK          ; CLK         ; 0.000        ; -0.263     ; 0.860      ;
+; 0.992 ; inst82      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.190      ;
+; 0.997 ; inst87      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.195      ;
+; 0.999 ; inst87      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.197      ;
+; 1.003 ; inst40      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.202      ;
+; 1.006 ; inst40      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.205      ;
+; 1.019 ; inst50      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.218      ;
+; 1.052 ; inst77      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.251      ;
+; 1.060 ; inst87      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.258      ;
+; 1.065 ; inst389     ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.263      ;
+; 1.093 ; inst48      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.292      ;
+; 1.098 ; inst67      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.387      ; 1.629      ;
+; 1.117 ; inst50      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.316      ;
+; 1.139 ; inst3799999 ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.338      ;
+; 1.146 ; inst50      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.344      ;
+; 1.149 ; inst107     ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.348      ;
+; 1.149 ; inst107     ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.348      ;
+; 1.149 ; inst107     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.348      ;
+; 1.150 ; inst107     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.349      ;
+; 1.151 ; inst107     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.350      ;
+; 1.151 ; inst107     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.350      ;
+; 1.152 ; inst107     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.351      ;
+; 1.156 ; inst77      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.355      ;
+; 1.157 ; inst3799999 ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.356      ;
+; 1.158 ; inst77      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.357      ;
+; 1.159 ; inst72      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.689      ;
+; 1.175 ; inst107     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.705      ;
+; 1.185 ; inst48      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.383      ;
+; 1.193 ; inst63      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.387      ; 1.724      ;
+; 1.195 ; inst389     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.394      ;
+; 1.203 ; inst459     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.402      ;
+; 1.219 ; inst67      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.418      ;
+; 1.219 ; inst77      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.418      ;
+; 1.222 ; inst67      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.421      ;
+; 1.232 ; inst38      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.431      ;
+; 1.233 ; inst58      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.431      ;
+; 1.244 ; inst50      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.443      ;
+; 1.244 ; inst50      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.443      ;
+; 1.245 ; inst50      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.444      ;
+; 1.246 ; inst50      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.445      ;
+; 1.249 ; inst67      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.448      ;
+; 1.250 ; inst43      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.449      ;
+; 1.250 ; inst38      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.449      ;
+; 1.268 ; inst3799999 ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.467      ;
+; 1.270 ; inst50      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.800      ;
+; 1.280 ; inst72      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.478      ;
+; 1.282 ; inst459     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.481      ;
+; 1.283 ; inst40      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.482      ;
+; 1.283 ; inst72      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.481      ;
+; 1.284 ; inst3799999 ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.482      ;
+; 1.292 ; inst3799999 ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.386      ; 1.822      ;
+; 1.294 ; inst48      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.492      ;
+; 1.295 ; inst48      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.493      ;
+; 1.301 ; inst40      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.055      ; 1.500      ;
+; 1.306 ; inst107     ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.504      ;
+; 1.307 ; inst107     ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.054      ; 1.505      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst102                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst107                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3799999               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst389                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst43                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst459                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst48                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst50                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst58                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst63                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst67                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst72                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst77                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst82                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst87                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst92                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst97                    ;
+; 0.175  ; 0.359        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst102                   ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst107                   ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999               ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst389                   ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst43                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst459                   ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst48                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst50                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst58                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst63                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst67                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst72                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst77                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst82                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst87                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst92                    ;
+; 0.182  ; 0.366        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst97                    ;
+; 0.335  ; 0.335        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst102|clk               ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst107|clk               ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst389|clk               ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst43|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst459|clk               ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst48|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst50|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst58|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst63|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst67|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst72|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst77|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst82|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst87|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst92|clk                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst97|clk                ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3799999               ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst389                   ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst43                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst459                   ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst50                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst58                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst63                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst67                    ;
+; 0.417  ; 0.633        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst77                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst107                   ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst48                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst72                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst82                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst87                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst92                    ;
+; 0.418  ; 0.634        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst97                    ;
+; 0.423  ; 0.639        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst102                   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst389|clk               ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst43|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst459|clk               ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst50|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst58|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst63|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst67|clk                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst77|clk                ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst107|clk               ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst48|clk                ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst72|clk                ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst82|clk                ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst87|clk                ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 6.345 ; 6.459 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 5.632 ; 5.660 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-------+--------+-------------------+
+; Clock ; Slack  ; End Point TNS     ;
++-------+--------+-------------------+
+; CLK   ; -0.652 ; -8.911            ;
++-------+--------+-------------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.180 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -23.093                         ;
++-------+--------+---------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLK'                                                                    ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node   ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+; -0.652 ; inst92      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.603      ;
+; -0.641 ; inst50      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.592      ;
+; -0.639 ; inst97      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.590      ;
+; -0.637 ; inst43      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.588      ;
+; -0.635 ; inst50      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.586      ;
+; -0.633 ; inst92      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.584      ;
+; -0.633 ; inst50      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.584      ;
+; -0.631 ; inst43      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.582      ;
+; -0.629 ; inst43      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.580      ;
+; -0.620 ; inst97      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.571      ;
+; -0.587 ; inst102     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.341      ;
+; -0.579 ; inst389     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.530      ;
+; -0.573 ; inst389     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.524      ;
+; -0.571 ; inst389     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.522      ;
+; -0.569 ; inst92      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.520      ;
+; -0.568 ; inst102     ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.322      ;
+; -0.567 ; inst82      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.518      ;
+; -0.566 ; inst92      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.517      ;
+; -0.565 ; inst92      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.516      ;
+; -0.561 ; inst40      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.512      ;
+; -0.556 ; inst97      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.507      ;
+; -0.555 ; inst40      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.506      ;
+; -0.553 ; inst40      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.504      ;
+; -0.553 ; inst97      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.504      ;
+; -0.552 ; inst97      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.503      ;
+; -0.548 ; inst82      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.499      ;
+; -0.528 ; inst50      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.479      ;
+; -0.526 ; inst50      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.477      ;
+; -0.524 ; inst43      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.475      ;
+; -0.522 ; inst50      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.473      ;
+; -0.522 ; inst43      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.473      ;
+; -0.518 ; inst43      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.469      ;
+; -0.511 ; inst38      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.462      ;
+; -0.507 ; inst77      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.458      ;
+; -0.505 ; inst38      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.456      ;
+; -0.504 ; inst102     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.258      ;
+; -0.503 ; inst38      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.454      ;
+; -0.501 ; inst102     ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.255      ;
+; -0.500 ; inst459     ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.451      ;
+; -0.500 ; inst102     ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.254      ;
+; -0.494 ; inst459     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.445      ;
+; -0.492 ; inst459     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.443      ;
+; -0.489 ; inst92      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.440      ;
+; -0.488 ; inst77      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.439      ;
+; -0.487 ; inst92      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.438      ;
+; -0.486 ; inst92      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.437      ;
+; -0.485 ; inst92      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.436      ;
+; -0.484 ; inst82      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.435      ;
+; -0.484 ; inst92      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.435      ;
+; -0.481 ; inst82      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.432      ;
+; -0.480 ; inst82      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.431      ;
+; -0.476 ; inst97      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.427      ;
+; -0.474 ; inst97      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.425      ;
+; -0.473 ; inst97      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.424      ;
+; -0.472 ; inst97      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.423      ;
+; -0.471 ; inst97      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.422      ;
+; -0.466 ; inst389     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.417      ;
+; -0.464 ; inst389     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.415      ;
+; -0.460 ; inst389     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.411      ;
+; -0.459 ; inst92      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.154      ; 1.600      ;
+; -0.457 ; inst87      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.408      ;
+; -0.451 ; inst50      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.154      ; 1.592      ;
+; -0.448 ; inst40      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.399      ;
+; -0.447 ; inst43      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.154      ; 1.588      ;
+; -0.446 ; inst40      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.397      ;
+; -0.446 ; inst97      ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.154      ; 1.587      ;
+; -0.442 ; inst40      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.393      ;
+; -0.438 ; inst87      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.389      ;
+; -0.437 ; inst3799999 ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.388      ;
+; -0.431 ; inst3799999 ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.382      ;
+; -0.429 ; inst3799999 ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.380      ;
+; -0.424 ; inst77      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.375      ;
+; -0.424 ; inst102     ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.178      ;
+; -0.422 ; inst72      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.373      ;
+; -0.422 ; inst102     ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.176      ;
+; -0.421 ; inst77      ; inst63  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.372      ;
+; -0.421 ; inst102     ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.175      ;
+; -0.420 ; inst77      ; inst67  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.371      ;
+; -0.420 ; inst102     ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.174      ;
+; -0.419 ; inst102     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.233     ; 1.173      ;
+; -0.416 ; inst40      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.367      ;
+; -0.412 ; inst67      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.363      ;
+; -0.404 ; inst82      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.355      ;
+; -0.403 ; inst72      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.354      ;
+; -0.402 ; inst82      ; inst48  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.353      ;
+; -0.401 ; inst82      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.352      ;
+; -0.400 ; inst58      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.351      ;
+; -0.400 ; inst82      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.351      ;
+; -0.399 ; inst82      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.350      ;
+; -0.398 ; inst38      ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.349      ;
+; -0.396 ; inst38      ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.347      ;
+; -0.394 ; inst58      ; inst92  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.345      ;
+; -0.394 ; inst102     ; inst102 ; CLK          ; CLK         ; 1.000        ; -0.043     ; 1.338      ;
+; -0.393 ; inst67      ; inst72  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.344      ;
+; -0.392 ; inst58      ; inst97  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.343      ;
+; -0.392 ; inst38      ; inst87  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.343      ;
+; -0.389 ; inst389     ; inst102 ; CLK          ; CLK         ; 1.000        ; 0.154      ; 1.530      ;
+; -0.387 ; inst459     ; inst77  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.338      ;
+; -0.385 ; inst459     ; inst82  ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.336      ;
+; -0.383 ; inst48      ; inst107 ; CLK          ; CLK         ; 1.000        ; -0.036     ; 1.334      ;
++--------+-------------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLK'                                                                        ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node   ; To Node     ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+; 0.180 ; inst102     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.043      ; 0.307      ;
+; 0.187 ; inst48      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst63      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst67      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst77      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst82      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst92      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst97      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; inst107     ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; inst38      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst40      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst459     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst389     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst43      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst50      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; inst3799999 ; inst3799999 ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.314      ;
+; 0.221 ; inst92      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.538      ;
+; 0.259 ; inst97      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.576      ;
+; 0.334 ; inst92      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.454      ;
+; 0.389 ; inst82      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.706      ;
+; 0.402 ; inst63      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.522      ;
+; 0.418 ; inst92      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.538      ;
+; 0.419 ; inst77      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.539      ;
+; 0.422 ; inst43      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.541      ;
+; 0.431 ; inst87      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.748      ;
+; 0.456 ; inst97      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.576      ;
+; 0.477 ; inst82      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.597      ;
+; 0.477 ; inst3799999 ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.596      ;
+; 0.477 ; inst3799999 ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.596      ;
+; 0.481 ; inst459     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.600      ;
+; 0.489 ; inst38      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.608      ;
+; 0.495 ; inst72      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.615      ;
+; 0.512 ; inst3799999 ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.631      ;
+; 0.512 ; inst77      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.829      ;
+; 0.513 ; inst3799999 ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.632      ;
+; 0.516 ; inst87      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.636      ;
+; 0.545 ; inst67      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.665      ;
+; 0.546 ; inst58      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.665      ;
+; 0.554 ; inst63      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.674      ;
+; 0.560 ; inst82      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.680      ;
+; 0.561 ; inst82      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.681      ;
+; 0.562 ; inst389     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.681      ;
+; 0.571 ; inst102     ; inst107     ; CLK          ; CLK         ; 0.000        ; -0.154     ; 0.501      ;
+; 0.572 ; inst38      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.691      ;
+; 0.573 ; inst38      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.692      ;
+; 0.586 ; inst82      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.706      ;
+; 0.602 ; inst87      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.722      ;
+; 0.603 ; inst87      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.723      ;
+; 0.604 ; inst40      ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.723      ;
+; 0.605 ; inst40      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.724      ;
+; 0.608 ; inst77      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.728      ;
+; 0.613 ; inst50      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.732      ;
+; 0.627 ; inst389     ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.746      ;
+; 0.628 ; inst87      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.748      ;
+; 0.632 ; inst67      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.949      ;
+; 0.643 ; inst48      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.763      ;
+; 0.662 ; inst50      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.781      ;
+; 0.670 ; inst107     ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.790      ;
+; 0.670 ; inst107     ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.790      ;
+; 0.670 ; inst107     ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.790      ;
+; 0.670 ; inst107     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.790      ;
+; 0.672 ; inst72      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.989      ;
+; 0.673 ; inst107     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.793      ;
+; 0.673 ; inst107     ; inst50      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.793      ;
+; 0.673 ; inst107     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.793      ;
+; 0.673 ; inst3799999 ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.792      ;
+; 0.675 ; inst107     ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 0.992      ;
+; 0.678 ; inst50      ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.797      ;
+; 0.683 ; inst77      ; inst97      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.803      ;
+; 0.684 ; inst77      ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.804      ;
+; 0.685 ; inst3799999 ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.804      ;
+; 0.687 ; inst48      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.807      ;
+; 0.690 ; inst63      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.233      ; 1.007      ;
+; 0.702 ; inst459     ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.821      ;
+; 0.707 ; inst67      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.827      ;
+; 0.709 ; inst67      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.829      ;
+; 0.709 ; inst389     ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.828      ;
+; 0.709 ; inst77      ; inst107     ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.829      ;
+; 0.713 ; inst58      ; inst72      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.832      ;
+; 0.721 ; inst67      ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.841      ;
+; 0.726 ; inst43      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.845      ;
+; 0.733 ; inst38      ; inst389     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.852      ;
+; 0.735 ; inst50      ; inst38      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.854      ;
+; 0.735 ; inst50      ; inst40      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.854      ;
+; 0.735 ; inst50      ; inst459     ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.854      ;
+; 0.738 ; inst50      ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.857      ;
+; 0.740 ; inst50      ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.232      ; 1.056      ;
+; 0.745 ; inst38      ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.864      ;
+; 0.747 ; inst72      ; inst77      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.867      ;
+; 0.748 ; inst48      ; inst63      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.868      ;
+; 0.749 ; inst48      ; inst67      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.869      ;
+; 0.749 ; inst72      ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.869      ;
+; 0.749 ; inst3799999 ; inst58      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.868      ;
+; 0.750 ; inst459     ; inst43      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.869      ;
+; 0.750 ; inst3799999 ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.869      ;
+; 0.751 ; inst3799999 ; inst102     ; CLK          ; CLK         ; 0.000        ; 0.232      ; 1.067      ;
+; 0.755 ; inst107     ; inst82      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.875      ;
+; 0.756 ; inst107     ; inst92      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.876      ;
+; 0.757 ; inst107     ; inst87      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.877      ;
+; 0.758 ; inst107     ; inst48      ; CLK          ; CLK         ; 0.000        ; 0.036      ; 0.878      ;
++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst102                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst107                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3799999               ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst389                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst43                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst459                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst48                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst50                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst58                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst63                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst67                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst72                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst77                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst82                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst87                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst92                    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst97                    ;
+; -0.085 ; 0.099        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst102                   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst107                   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999               ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst389                   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst43                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst459                   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst48                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst50                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst58                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst63                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst67                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst72                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst77                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst82                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst87                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst92                    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst97                    ;
+; 0.095  ; 0.095        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst102|clk               ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst107|clk               ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst48|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst63|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst67|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst72|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst77|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst82|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst87|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst92|clk                ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst97|clk                ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst389|clk               ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk                ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk                ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst43|clk                ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst459|clk               ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst50|clk                ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst58|clk                ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3799999               ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38                    ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst389                   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40                    ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst43                    ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst459                   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst50                    ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst58                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst107                   ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst48                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst63                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst67                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst72                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst77                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst82                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst87                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst92                    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst97                    ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst102                   ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst107|clk               ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3799999|clk           ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst389|clk               ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst43|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst459|clk               ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst48|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst50|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst58|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst63|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst67|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst72|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst77|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst82|clk                ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst87|clk                ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 3.973 ; 4.093 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 3.531 ; 3.594 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+---------+-------+----------+---------+---------------------+
+; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -1.948  ; 0.180 ; N/A      ; N/A     ; -3.000              ;
+;  CLK             ; -1.948  ; 0.180 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -30.172 ; 0.0   ; 0.0      ; 0.0     ; -23.093             ;
+;  CLK             ; -30.172 ; 0.000 ; N/A      ; N/A     ; -23.093             ;
++------------------+---------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 6.727 ; 6.886 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; 1_Hz      ; CLK        ; 3.531 ; 3.594 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; 1_Hz          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; CLK                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; 1_Hz          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; 1_Hz          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 532      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 532      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 0     ; 0    ;
+; Unconstrained Input Port Paths  ; 0     ; 0    ;
+; Unconstrained Output Ports      ; 1     ; 1    ;
+; Unconstrained Output Port Paths ; 19    ; 19   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Feb 23 16:02:19 2016
+Info: Command: quartus_sta one_hertz_clock -c one_hertz_clock
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'one_hertz_clock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLK CLK
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.948
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -1.948       -30.172 CLK 
+Info (332146): Worst-case hold slack is 0.344
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.344         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -22.000 CLK 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.632
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -1.632       -25.089 CLK 
+Info (332146): Worst-case hold slack is 0.298
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.298         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -22.000 CLK 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.652
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.652        -8.911 CLK 
+Info (332146): Worst-case hold slack is 0.180
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.180         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -23.093 CLK 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 485 megabytes
+    Info: Processing ended: Tue Feb 23 16:02:20 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/one_hertz_clock/output_files/one_hertz_clock.sta.summary b/one_hertz_clock/output_files/one_hertz_clock.sta.summary
new file mode 100644
index 0000000..8cc44fe
--- /dev/null
+++ b/one_hertz_clock/output_files/one_hertz_clock.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'CLK'
+Slack : -1.948
+TNS   : -30.172
+
+Type  : Slow 1200mV 85C Model Hold 'CLK'
+Slack : 0.344
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -22.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLK'
+Slack : -1.632
+TNS   : -25.089
+
+Type  : Slow 1200mV 0C Model Hold 'CLK'
+Slack : 0.298
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -22.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLK'
+Slack : -0.652
+TNS   : -8.911
+
+Type  : Fast 1200mV 0C Model Hold 'CLK'
+Slack : 0.180
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -23.093
+
+------------------------------------------------------------
diff --git a/pipelined_multiply/db/pipelined_multiply.db_info b/pipelined_multiply/db/pipelined_multiply.db_info
new file mode 100644
index 0000000..8666c74
--- /dev/null
+++ b/pipelined_multiply/db/pipelined_multiply.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 17:01:23 2016
diff --git a/pipelined_multiply/db/pipelined_multiply.ipinfo b/pipelined_multiply/db/pipelined_multiply.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/pipelined_multiply/db/pipelined_multiply.ipinfo
diff --git a/pipelined_multiply/db/pipelined_multiply.sld_design_entry.sci b/pipelined_multiply/db/pipelined_multiply.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/pipelined_multiply/db/pipelined_multiply.sld_design_entry.sci
diff --git a/pipelined_multiply/pipelined_multiply.bdf b/pipelined_multiply/pipelined_multiply.bdf
new file mode 100644
index 0000000..d9fa03a
--- /dev/null
+++ b/pipelined_multiply/pipelined_multiply.bdf
@@ -0,0 +1,2093 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
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+	(text "X[4]" (rect 1601 688 1619 700)(font "Arial" ))
+	(pt 1624 704)
+	(pt 1592 704)
+)
+(connector
+	(pt 1624 560)
+	(pt 1480 560)
+)
+(connector
+	(pt 904 624)
+	(pt 864 624)
+)
+(connector
+	(pt 1144 736)
+	(pt 1136 736)
+)
+(connector
+	(pt 1240 592)
+	(pt 1248 592)
+)
+(connector
+	(pt 1248 592)
+	(pt 1248 784)
+)
+(connector
+	(pt 1000 608)
+	(pt 1008 608)
+)
+(connector
+	(pt 1008 608)
+	(pt 1008 792)
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+(connector
+	(pt 1480 576)
+	(pt 1488 576)
+)
+(connector
+	(pt 1488 576)
+	(pt 1488 768)
+)
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+	(pt 1624 600)
+	(pt 1608 600)
+)
+(connector
+	(pt 1624 720)
+	(pt 1616 720)
+)
+(connector
+	(text "A[4..0]" (rect 502 320 535 332)(font "Arial" ))
+	(pt 488 336)
+	(pt 512 336)
+	(bus)
+)
+(connector
+	(text "O[9..0]" (rect 357 352 391 364)(font "Arial" ))
+	(pt 408 368)
+	(pt 392 368)
+	(bus)
+)
+(connector
+	(text "X[6]" (rect 875 432 893 444)(font "Arial" ))
+	(pt 904 448)
+	(pt 875 448)
+)
+(connector
+	(text "X[7]" (rect 1115 416 1133 428)(font "Arial" ))
+	(pt 1115 432)
+	(pt 1144 432)
+)
+(connector
+	(text "X[9]" (rect 1592 384 1610 396)(font "Arial" ))
+	(pt 1592 400)
+	(pt 1624 400)
+)
+(connector
+	(text "X[8]" (rect 1352 400 1370 412)(font "Arial" ))
+	(pt 1352 416)
+	(pt 1384 416)
+)
+(connector
+	(text "A[9..5]" (rect 506 288 539 300)(font "Arial" ))
+	(pt 488 304)
+	(pt 512 304)
+	(bus)
+)
+(connector
+	(text "M[9..0]" (rect 646 272 680 284)(font "Arial" ))
+	(pt 688 288)
+	(pt 672 288)
+	(bus)
+)
+(connector
+	(text "O[9..0]" (rect 816 256 850 268)(font "Arial" ))
+	(pt 816 272)
+	(pt 840 272)
+	(bus)
+)
+(connector
+	(text "A[9..0]" (rect 656 368 689 380)(font "Arial" ))
+	(pt 672 384)
+	(pt 688 384)
+	(bus)
+)
+(connector
+	(text "X[9..0]" (rect 816 352 847 364)(font "Arial" ))
+	(pt 816 368)
+	(pt 840 368)
+	(bus)
+)
+(connector
+	(pt 688 368)
+	(pt 624 368)
+)
+(connector
+	(pt 624 368)
+	(pt 624 272)
+)
+(connector
+	(pt 896 720)
+	(pt 896 736)
+)
+(connector
+	(pt 896 736)
+	(pt 896 744)
+)
+(connector
+	(pt 896 744)
+	(pt 896 752)
+)
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+	(pt 896 752)
+	(pt 896 768)
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+	(pt 880 544)
+	(pt 880 560)
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+	(pt 880 560)
+	(pt 880 576)
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+	(pt 880 592)
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+	(pt 880 608)
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+	(pt 608 600)
+	(pt 680 600)
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+	(pt 464 600)
+	(pt 536 600)
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+	(pt 536 600)
+	(pt 608 600)
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+	(pt 1384 592)
+	(pt 1384 608)
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+(connector
+	(pt 1384 608)
+	(pt 1384 624)
+)
+(connector
+	(pt 1144 720)
+	(pt 1144 736)
+)
+(connector
+	(pt 1144 736)
+	(pt 1144 752)
+)
+(connector
+	(pt 1624 576)
+	(pt 1624 592)
+)
+(connector
+	(pt 1624 592)
+	(pt 1624 600)
+)
+(connector
+	(pt 1624 600)
+	(pt 1624 608)
+)
+(connector
+	(pt 1624 608)
+	(pt 1624 624)
+)
+(connector
+	(text "X[5]" (rect 338 584 356 596)(font "Arial" ))
+	(pt 336 600)
+	(pt 368 600)
+)
+(connector
+	(pt 368 600)
+	(pt 464 600)
+)
+(connector
+	(pt 488 272)
+	(pt 624 272)
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+(connector
+	(pt 624 272)
+	(pt 688 272)
+)
+(junction (pt 1144 608))
+(junction (pt 1384 720))
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+(junction (pt 896 744))
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+(junction (pt 368 600))
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+(junction (pt 1384 608))
+(junction (pt 1144 736))
+(junction (pt 1624 600))
+(junction (pt 1624 592))
+(junction (pt 1624 608))
+(junction (pt 624 272))
+(text "X[0]" (rect 866 624 884 636)(font "Arial" ))
+(text "X[0]" (rect 866 624 884 636)(font "Arial" ))
diff --git a/pipelined_multiply/pipelined_multiply.qpf b/pipelined_multiply/pipelined_multiply.qpf
new file mode 100644
index 0000000..528dff5
--- /dev/null
+++ b/pipelined_multiply/pipelined_multiply.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 16:21:18  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:21:18  February 19, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "pipelined_multiply"
diff --git a/pipelined_multiply/pipelined_multiply.qsf b/pipelined_multiply/pipelined_multiply.qsf
new file mode 100644
index 0000000..7cf4a03
--- /dev/null
+++ b/pipelined_multiply/pipelined_multiply.qsf
@@ -0,0 +1,54 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 16:21:18  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		pipelined_multiply_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY pipelined_multiply
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:18  FEBRUARY 19, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name BDF_FILE ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE pipelined_multiply.bdf
\ No newline at end of file
diff --git a/pipelined_multiply/pipelined_multiply.qws b/pipelined_multiply/pipelined_multiply.qws
new file mode 100644
index 0000000..f819637
--- /dev/null
+++ b/pipelined_multiply/pipelined_multiply.qws
diff --git a/registered_multiply/db/.cmp.kpt b/registered_multiply/db/.cmp.kpt
new file mode 100644
index 0000000..5f7584a
--- /dev/null
+++ b/registered_multiply/db/.cmp.kpt
diff --git a/registered_multiply/db/logic_util_heursitic.dat b/registered_multiply/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/registered_multiply/db/logic_util_heursitic.dat
diff --git a/registered_multiply/db/prev_cmp_registered_multiply.qmsg b/registered_multiply/db/prev_cmp_registered_multiply.qmsg
new file mode 100644
index 0000000..a85fbac
--- /dev/null
+++ b/registered_multiply/db/prev_cmp_registered_multiply.qmsg
@@ -0,0 +1,130 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898230590 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898230591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:30 2016 " "Processing started: Fri Feb 19 16:10:30 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898230591 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898230591 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898230591 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455898230876 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898230919 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898230919 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898230921 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898230921 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/comb_multiply/registered_multiply.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/comb_multiply/registered_multiply.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 registered_multiply " "Found entity 1: registered_multiply" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898230923 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898230923 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "registered_multiply " "Elaborating entity \"registered_multiply\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455898230947 ""}
+{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "GND inst21 " "Block or symbol \"GND\" of instance \"inst21\" overlaps another block or symbol" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 592 1400 1432 624 "inst21" "" } } } }  } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Quartus II" 0 -1 1455898230948 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst21 " "Primitive \"GND\" of instance \"inst21\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 592 1400 1432 624 "inst21" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898230949 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst22 " "Primitive \"GND\" of instance \"inst22\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 584 1640 1672 616 "inst22" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898230949 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst23 " "Primitive \"GND\" of instance \"inst23\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 568 1880 1912 600 "inst23" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898230949 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst24 " "Primitive \"GND\" of instance \"inst24\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 344 2168 2200 376 "inst24" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898230949 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_bit_adder_NO_BUS ten_bit_adder_NO_BUS:inst3 " "Elaborating entity \"ten_bit_adder_NO_BUS\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\"" {  } { { "../comb_multiply/registered_multiply.bdf" "inst3" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 168 2032 2128 552 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455898230950 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder ten_bit_adder_NO_BUS:inst3\|full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\|full_adder:inst17\"" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1424 888 984 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455898230952 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455898231793 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455898232055 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455898232055 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "83 " "Implemented 83 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455898232105 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455898232105 ""} { "Info" "ICUT_CUT_TM_LCELLS" "62 " "Implemented 62 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455898232105 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455898232105 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898232123 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:32 2016 " "Processing ended: Fri Feb 19 16:10:32 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898232123 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898232123 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898232123 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898232123 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898233950 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898233951 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:33 2016 " "Processing started: Fri Feb 19 16:10:33 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898233951 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455898233951 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_fit --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455898233951 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455898234024 ""}
+{ "Info" "0" "" "Project  = registered_multiply" {  } {  } 0 0 "Project  = registered_multiply" 0 0 "Fitter" 0 0 1455898234025 ""}
+{ "Info" "0" "" "Revision = registered_multiply" {  } {  } 0 0 "Revision = registered_multiply" 0 0 "Fitter" 0 0 1455898234025 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455898234083 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "registered_multiply EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"registered_multiply\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455898234088 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234150 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234151 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234151 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455898234235 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455898234247 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455898234450 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 189 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 191 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 193 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 195 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 197 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455898234452 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455898234453 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "registered_multiply.sdc " "Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455898235536 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455898235536 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455898235691 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455898235691 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455898235692 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455898235695 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455898235703 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455898235704 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455898235704 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898235722 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455898236531 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898236591 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455898236598 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455898236984 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898236985 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455898237132 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455898237661 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455898237661 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898238138 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455898238138 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455898238138 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455898238147 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455898238188 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455898238464 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455898238502 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455898238804 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898239142 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455898240091 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "822 " "Peak virtual memory: 822 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:40 2016 " "Processing ended: Fri Feb 19 16:10:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455898240309 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455898241999 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898241999 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:41 2016 " "Processing started: Fri Feb 19 16:10:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898241999 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455898241999 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_asm --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455898242000 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455898242749 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455898242778 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:43 2016 " "Processing ended: Fri Feb 19 16:10:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455898243066 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455898243650 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455898244824 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:44 2016 " "Processing started: Fri Feb 19 16:10:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta registered_multiply -c registered_multiply " "Command: quartus_sta registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455898244893 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455898245017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245086 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245086 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "registered_multiply.sdc " "Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455898245266 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455898245266 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245267 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245267 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455898245268 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898245268 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455898245269 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455898245278 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898245406 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898245406 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.478 " "Worst-case setup slack is -4.478" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.478             -28.219 CLK  " "   -4.478             -28.219 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.617 " "Worst-case hold slack is 0.617" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.617               0.000 CLK  " "    0.617               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245419 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245423 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 CLK  " "   -3.000             -23.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455898245477 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455898245502 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455898245873 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898245903 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898245908 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898245908 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.877 " "Worst-case setup slack is -3.877" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.877             -24.107 CLK  " "   -3.877             -24.107 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.550 " "Worst-case hold slack is 0.550" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.550               0.000 CLK  " "    0.550               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245922 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245927 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 CLK  " "   -3.000             -23.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455898245991 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898246065 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898246066 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898246066 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.060 " "Worst-case setup slack is -2.060" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.060             -11.543 CLK  " "   -2.060             -11.543 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.332 " "Worst-case hold slack is 0.332" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.332               0.000 CLK  " "    0.332               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898246082 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898246086 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -25.072 CLK  " "   -3.000             -25.072 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455898246279 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455898246279 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "505 " "Peak virtual memory: 505 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:46 2016 " "Processing ended: Fri Feb 19 16:10:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:47 2016 " "Processing started: Fri Feb 19 16:10:47 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_eda --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248392 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248416 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248441 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248468 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248494 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248515 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248537 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_vhd.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248562 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:48 2016 " "Processing ended: Fri Feb 19 16:10:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 15 s " "Quartus II Full Compilation was successful. 0 errors, 15 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898249214 ""}
diff --git a/registered_multiply/db/registered_multiply.(0).cnf.cdb b/registered_multiply/db/registered_multiply.(0).cnf.cdb
new file mode 100644
index 0000000..411033c
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(0).cnf.cdb
diff --git a/registered_multiply/db/registered_multiply.(0).cnf.hdb b/registered_multiply/db/registered_multiply.(0).cnf.hdb
new file mode 100644
index 0000000..a6ba90d
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(0).cnf.hdb
diff --git a/registered_multiply/db/registered_multiply.(1).cnf.cdb b/registered_multiply/db/registered_multiply.(1).cnf.cdb
new file mode 100644
index 0000000..5b9adec
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(1).cnf.cdb
diff --git a/registered_multiply/db/registered_multiply.(1).cnf.hdb b/registered_multiply/db/registered_multiply.(1).cnf.hdb
new file mode 100644
index 0000000..58266b2
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(1).cnf.hdb
diff --git a/registered_multiply/db/registered_multiply.(2).cnf.cdb b/registered_multiply/db/registered_multiply.(2).cnf.cdb
new file mode 100644
index 0000000..f11fe38
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(2).cnf.cdb
diff --git a/registered_multiply/db/registered_multiply.(2).cnf.hdb b/registered_multiply/db/registered_multiply.(2).cnf.hdb
new file mode 100644
index 0000000..44c7154
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.(2).cnf.hdb
diff --git a/registered_multiply/db/registered_multiply.asm.qmsg b/registered_multiply/db/registered_multiply.asm.qmsg
new file mode 100644
index 0000000..82d6bce
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898241999 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898241999 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:41 2016 " "Processing started: Fri Feb 19 16:10:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898241999 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455898241999 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_asm --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455898242000 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455898242749 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455898242778 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:43 2016 " "Processing ended: Fri Feb 19 16:10:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898243066 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455898243066 ""}
diff --git a/registered_multiply/db/registered_multiply.asm.rdb b/registered_multiply/db/registered_multiply.asm.rdb
new file mode 100644
index 0000000..120c837
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.asm.rdb
diff --git a/registered_multiply/db/registered_multiply.cbx.xml b/registered_multiply/db/registered_multiply.cbx.xml
new file mode 100644
index 0000000..07a9fab
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="registered_multiply">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/registered_multiply/db/registered_multiply.cmp.idb b/registered_multiply/db/registered_multiply.cmp.idb
new file mode 100644
index 0000000..dbe0fbb
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cmp.idb
diff --git a/registered_multiply/db/registered_multiply.cmp.rdb b/registered_multiply/db/registered_multiply.cmp.rdb
new file mode 100644
index 0000000..a5a6000
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cmp.rdb
diff --git a/registered_multiply/db/registered_multiply.cmp_merge.kpt b/registered_multiply/db/registered_multiply.cmp_merge.kpt
new file mode 100644
index 0000000..c4e930c
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cmp_merge.kpt
diff --git a/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..999f11c
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..4436436
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/registered_multiply/db/registered_multiply.db_info b/registered_multiply/db/registered_multiply.db_info
new file mode 100644
index 0000000..182d5f4
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 15:32:11 2016
diff --git a/registered_multiply/db/registered_multiply.eda.qmsg b/registered_multiply/db/registered_multiply.eda.qmsg
new file mode 100644
index 0000000..6ce21e0
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:47 2016 " "Processing started: Fri Feb 19 16:10:47 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_eda --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898248024 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248392 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248416 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248441 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply.vho C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply.vho in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248468 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248494 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248515 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248537 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "registered_multiply_vhd.sdo C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/ simulation " "Generated file registered_multiply_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455898248562 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:48 2016 " "Processing ended: Fri Feb 19 16:10:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898248606 ""}
diff --git a/registered_multiply/db/registered_multiply.fit.qmsg b/registered_multiply/db/registered_multiply.fit.qmsg
new file mode 100644
index 0000000..d4237a9
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.fit.qmsg
@@ -0,0 +1,43 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455898234083 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "registered_multiply EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"registered_multiply\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1455898234088 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234150 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234151 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1455898234151 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455898234235 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455898234247 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455898234450 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455898234450 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 189 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 191 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 193 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 195 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 0 { 0 ""} 0 197 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455898234452 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455898234452 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455898234453 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "registered_multiply.sdc " "Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455898235536 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455898235536 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455898235538 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455898235691 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455898235691 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455898235692 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1455898235694 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455898235695 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455898235703 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455898235704 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455898235704 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898235722 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455898236531 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898236591 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455898236598 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455898236984 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898236985 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455898237132 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/registered_multiply/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455898237661 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455898237661 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898238138 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455898238138 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455898238138 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455898238147 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455898238188 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455898238464 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455898238502 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455898238804 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455898239142 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455898240091 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "822 " "Peak virtual memory: 822 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:40 2016 " "Processing ended: Fri Feb 19 16:10:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898240309 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455898240309 ""}
diff --git a/registered_multiply/db/registered_multiply.hier_info b/registered_multiply/db/registered_multiply.hier_info
new file mode 100644
index 0000000..eac19a8
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.hier_info
@@ -0,0 +1,779 @@
+|registered_multiply
+Output[0] <= inst31.DB_MAX_OUTPUT_PORT_TYPE
+Output[1] <= inst32.DB_MAX_OUTPUT_PORT_TYPE
+Output[2] <= inst33.DB_MAX_OUTPUT_PORT_TYPE
+Output[3] <= inst34.DB_MAX_OUTPUT_PORT_TYPE
+Output[4] <= inst35.DB_MAX_OUTPUT_PORT_TYPE
+Output[5] <= inst36.DB_MAX_OUTPUT_PORT_TYPE
+Output[6] <= inst37.DB_MAX_OUTPUT_PORT_TYPE
+Output[7] <= inst38.DB_MAX_OUTPUT_PORT_TYPE
+Output[8] <= inst39.DB_MAX_OUTPUT_PORT_TYPE
+Output[9] <= inst40.DB_MAX_OUTPUT_PORT_TYPE
+CLK => inst31.CLK
+CLK => inst30.CLK
+CLK => inst27.CLK
+CLK => inst15.CLK
+CLK => inst14.CLK
+CLK => inst4.CLK
+CLK => inst13.CLK
+CLK => inst91.CLK
+CLK => inst10.CLK
+CLK => inst11.CLK
+CLK => inst12.CLK
+CLK => inst32.CLK
+CLK => inst33.CLK
+CLK => inst34.CLK
+CLK => inst35.CLK
+CLK => inst36.CLK
+CLK => inst37.CLK
+CLK => inst38.CLK
+CLK => inst39.CLK
+CLK => inst40.CLK
+B[0] => inst13.DATAIN
+B[1] => inst14.DATAIN
+B[2] => inst15.DATAIN
+B[3] => inst27.DATAIN
+B[4] => inst30.DATAIN
+A[0] => inst4.DATAIN
+A[1] => inst91.DATAIN
+A[2] => inst10.DATAIN
+A[3] => inst11.DATAIN
+A[4] => inst12.DATAIN
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/registered_multiply/db/registered_multiply.hif b/registered_multiply/db/registered_multiply.hif
new file mode 100644
index 0000000..42e4196
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.hif
diff --git a/registered_multiply/db/registered_multiply.ipinfo b/registered_multiply/db/registered_multiply.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.ipinfo
diff --git a/registered_multiply/db/registered_multiply.lpc.html b/registered_multiply/db/registered_multiply.lpc.html
new file mode 100644
index 0000000..2f64a91
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.lpc.html
@@ -0,0 +1,722 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst|inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst9</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst10</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst11</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst12</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst13</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst15</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst16</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|inst17</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >2</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >21</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >11</TD>
+<TD >11</TD>
+<TD >11</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
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+</TR>
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+<TD >0</TD>
+</TR>
+<TR >
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+<TD >3</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|inst13</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|inst14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|inst15</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1|inst16</TD>
+<TD >3</TD>
+<TD >0</TD>
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+</TR>
+<TR >
+<TD >inst1|inst17</TD>
+<TD >3</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1</TD>
+<TD >21</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >6</TD>
+<TD >11</TD>
+<TD >6</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst2|inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
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+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst2|inst9</TD>
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+<TD >0</TD>
+</TR>
+<TR >
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+<TD >3</TD>
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+</TR>
+<TR >
+<TD >inst2|inst11</TD>
+<TD >3</TD>
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+<TD >0</TD>
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diff --git a/registered_multiply/db/registered_multiply.lpc.rdb b/registered_multiply/db/registered_multiply.lpc.rdb
new file mode 100644
index 0000000..0092a24
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.lpc.rdb
diff --git a/registered_multiply/db/registered_multiply.lpc.txt b/registered_multiply/db/registered_multiply.lpc.txt
new file mode 100644
index 0000000..93b9c91
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.lpc.txt
@@ -0,0 +1,50 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                        ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy    ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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+; inst3|inst14 ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
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+; inst3        ; 21    ; 6              ; 0            ; 6              ; 11     ; 6               ; 6             ; 6               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/registered_multiply/db/registered_multiply.map.ammdb b/registered_multiply/db/registered_multiply.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.ammdb
diff --git a/registered_multiply/db/registered_multiply.map.bpm b/registered_multiply/db/registered_multiply.map.bpm
new file mode 100644
index 0000000..d969f88
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.bpm
diff --git a/registered_multiply/db/registered_multiply.map.cdb b/registered_multiply/db/registered_multiply.map.cdb
new file mode 100644
index 0000000..0c16a27
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.cdb
diff --git a/registered_multiply/db/registered_multiply.map.hdb b/registered_multiply/db/registered_multiply.map.hdb
new file mode 100644
index 0000000..e606c01
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.hdb
diff --git a/registered_multiply/db/registered_multiply.map.kpt b/registered_multiply/db/registered_multiply.map.kpt
new file mode 100644
index 0000000..21f8a13
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.kpt
diff --git a/registered_multiply/db/registered_multiply.map.logdb b/registered_multiply/db/registered_multiply.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/registered_multiply/db/registered_multiply.map.qmsg b/registered_multiply/db/registered_multiply.map.qmsg
new file mode 100644
index 0000000..263ecdf
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.qmsg
@@ -0,0 +1,19 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898325165 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898325166 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:12:05 2016 " "Processing started: Fri Feb 19 16:12:05 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898325166 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898325166 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply " "Command: quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898325166 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455898325442 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898325496 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898325496 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898325498 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898325498 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/comb_multiply/registered_multiply.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/comb_multiply/registered_multiply.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 registered_multiply " "Found entity 1: registered_multiply" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455898325500 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455898325500 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "registered_multiply " "Elaborating entity \"registered_multiply\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455898325525 ""}
+{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "GND inst21 " "Block or symbol \"GND\" of instance \"inst21\" overlaps another block or symbol" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 592 1400 1432 624 "inst21" "" } } } }  } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Quartus II" 0 -1 1455898325526 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst21 " "Primitive \"GND\" of instance \"inst21\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 592 1400 1432 624 "inst21" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898325526 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst22 " "Primitive \"GND\" of instance \"inst22\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 584 1640 1672 616 "inst22" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898325526 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst23 " "Primitive \"GND\" of instance \"inst23\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 568 1880 1912 600 "inst23" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898325526 ""}
+{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "GND inst24 " "Primitive \"GND\" of instance \"inst24\" not used" {  } { { "../comb_multiply/registered_multiply.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 344 2168 2200 376 "inst24" "" } } } }  } 0 275008 "Primitive \"%1!s!\" of instance \"%2!s!\" not used" 0 0 "Quartus II" 0 -1 1455898325526 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_bit_adder_NO_BUS ten_bit_adder_NO_BUS:inst3 " "Elaborating entity \"ten_bit_adder_NO_BUS\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\"" {  } { { "../comb_multiply/registered_multiply.bdf" "inst3" { Schematic "C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf" { { 168 2032 2128 552 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455898325527 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder ten_bit_adder_NO_BUS:inst3\|full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"ten_bit_adder_NO_BUS:inst3\|full_adder:inst17\"" {  } { { "../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1424 888 984 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455898325529 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455898326360 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455898326632 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455898326632 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "83 " "Implemented 83 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455898326700 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455898326700 ""} { "Info" "ICUT_CUT_TM_LCELLS" "62 " "Implemented 62 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455898326700 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455898326700 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898326720 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:12:06 2016 " "Processing ended: Fri Feb 19 16:12:06 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898326720 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898326720 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898326720 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898326720 ""}
diff --git a/registered_multiply/db/registered_multiply.map.rdb b/registered_multiply/db/registered_multiply.map.rdb
new file mode 100644
index 0000000..77f55fe
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map.rdb
diff --git a/registered_multiply/db/registered_multiply.map_bb.cdb b/registered_multiply/db/registered_multiply.map_bb.cdb
new file mode 100644
index 0000000..d29d374
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map_bb.cdb
diff --git a/registered_multiply/db/registered_multiply.map_bb.hdb b/registered_multiply/db/registered_multiply.map_bb.hdb
new file mode 100644
index 0000000..2152295
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map_bb.hdb
diff --git a/registered_multiply/db/registered_multiply.map_bb.logdb b/registered_multiply/db/registered_multiply.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/registered_multiply/db/registered_multiply.pplq.rdb b/registered_multiply/db/registered_multiply.pplq.rdb
new file mode 100644
index 0000000..2765321
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.pplq.rdb
diff --git a/registered_multiply/db/registered_multiply.pre_map.hdb b/registered_multiply/db/registered_multiply.pre_map.hdb
new file mode 100644
index 0000000..86d5021
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.pre_map.hdb
diff --git a/registered_multiply/db/registered_multiply.pti_db_list.ddb b/registered_multiply/db/registered_multiply.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.pti_db_list.ddb
diff --git a/registered_multiply/db/registered_multiply.root_partition.map.reg_db.cdb b/registered_multiply/db/registered_multiply.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..57b09e6
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.root_partition.map.reg_db.cdb
diff --git a/registered_multiply/db/registered_multiply.routing.rdb b/registered_multiply/db/registered_multiply.routing.rdb
new file mode 100644
index 0000000..cfdc3bc
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.routing.rdb
diff --git a/registered_multiply/db/registered_multiply.rtlv.hdb b/registered_multiply/db/registered_multiply.rtlv.hdb
new file mode 100644
index 0000000..6d83b8c
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.rtlv.hdb
diff --git a/registered_multiply/db/registered_multiply.rtlv_sg.cdb b/registered_multiply/db/registered_multiply.rtlv_sg.cdb
new file mode 100644
index 0000000..0f3d07d
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.rtlv_sg.cdb
diff --git a/registered_multiply/db/registered_multiply.rtlv_sg_swap.cdb b/registered_multiply/db/registered_multiply.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..0495194
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.rtlv_sg_swap.cdb
diff --git a/registered_multiply/db/registered_multiply.sgdiff.cdb b/registered_multiply/db/registered_multiply.sgdiff.cdb
new file mode 100644
index 0000000..43d1e0f
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sgdiff.cdb
diff --git a/registered_multiply/db/registered_multiply.sgdiff.hdb b/registered_multiply/db/registered_multiply.sgdiff.hdb
new file mode 100644
index 0000000..fd24f69
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sgdiff.hdb
diff --git a/registered_multiply/db/registered_multiply.sld_design_entry.sci b/registered_multiply/db/registered_multiply.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sld_design_entry.sci
diff --git a/registered_multiply/db/registered_multiply.sld_design_entry_dsc.sci b/registered_multiply/db/registered_multiply.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sld_design_entry_dsc.sci
diff --git a/registered_multiply/db/registered_multiply.smart_action.txt b/registered_multiply/db/registered_multiply.smart_action.txt
new file mode 100644
index 0000000..e04bbcf
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.smart_action.txt
@@ -0,0 +1 @@
+FIT
diff --git a/registered_multiply/db/registered_multiply.sta.qmsg b/registered_multiply/db/registered_multiply.sta.qmsg
new file mode 100644
index 0000000..a8f79c4
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455898244824 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:10:44 2016 " "Processing started: Fri Feb 19 16:10:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta registered_multiply -c registered_multiply " "Command: quartus_sta registered_multiply -c registered_multiply" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455898244825 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455898244893 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455898245017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245086 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1455898245086 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "registered_multiply.sdc " "Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455898245266 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455898245266 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245267 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245267 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455898245268 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898245268 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455898245269 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455898245278 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898245406 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898245406 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.478 " "Worst-case setup slack is -4.478" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.478             -28.219 CLK  " "   -4.478             -28.219 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245411 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.617 " "Worst-case hold slack is 0.617" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.617               0.000 CLK  " "    0.617               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245415 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245419 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245423 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 CLK  " "   -3.000             -23.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245426 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455898245477 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455898245502 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455898245873 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898245903 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898245908 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898245908 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.877 " "Worst-case setup slack is -3.877" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.877             -24.107 CLK  " "   -3.877             -24.107 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245912 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.550 " "Worst-case hold slack is 0.550" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.550               0.000 CLK  " "    0.550               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245917 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245922 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898245927 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 CLK  " "   -3.000             -23.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898245933 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455898245991 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455898246065 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455898246066 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455898246066 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.060 " "Worst-case setup slack is -2.060" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.060             -11.543 CLK  " "   -2.060             -11.543 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246070 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.332 " "Worst-case hold slack is 0.332" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.332               0.000 CLK  " "    0.332               0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246076 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898246082 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455898246086 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -25.072 CLK  " "   -3.000             -25.072 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455898246091 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455898246279 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455898246279 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "505 " "Peak virtual memory: 505 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:10:46 2016 " "Processing ended: Fri Feb 19 16:10:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455898246340 ""}
diff --git a/registered_multiply/db/registered_multiply.sta.rdb b/registered_multiply/db/registered_multiply.sta.rdb
new file mode 100644
index 0000000..b2f0be2
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.sta.rdb
diff --git a/registered_multiply/db/registered_multiply.tis_db_list.ddb b/registered_multiply/db/registered_multiply.tis_db_list.ddb
new file mode 100644
index 0000000..8f8e99d
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.tis_db_list.ddb
diff --git a/registered_multiply/db/registered_multiply.tiscmp.fast_1200mv_0c.ddb b/registered_multiply/db/registered_multiply.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..0a67ff8
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.tiscmp.fast_1200mv_0c.ddb
diff --git a/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_0c.ddb b/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..d3baf6f
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_0c.ddb
diff --git a/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_85c.ddb b/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..c46b465
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.tiscmp.slow_1200mv_85c.ddb
diff --git a/registered_multiply/db/registered_multiply.vpr.ammdb b/registered_multiply/db/registered_multiply.vpr.ammdb
new file mode 100644
index 0000000..de6aaa2
--- /dev/null
+++ b/registered_multiply/db/registered_multiply.vpr.ammdb
diff --git a/registered_multiply/incremental_db/README b/registered_multiply/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/registered_multiply/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.db_info b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.db_info
new file mode 100644
index 0000000..eebab00
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 16:07:08 2016
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.ammdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.ammdb
new file mode 100644
index 0000000..82352df
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.ammdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.cdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.cdb
new file mode 100644
index 0000000..2a36b66
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.cdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.dfp b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.dfp
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.hdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.hdb
new file mode 100644
index 0000000..3934ad6
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.hdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.logdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.rcfdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..065c0f9
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.cmp.rcfdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.cdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.cdb
new file mode 100644
index 0000000..d736b12
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.cdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.dpi b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.dpi
new file mode 100644
index 0000000..27bda85
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.dpi
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.cdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..24e0447
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.cdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hb_info b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hb_info
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..cac383b
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.hdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.sig b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hdb b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hdb
new file mode 100644
index 0000000..69f9712
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.hdb
diff --git a/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.kpt b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.kpt
new file mode 100644
index 0000000..dab052c
--- /dev/null
+++ b/registered_multiply/incremental_db/compiled_partitions/registered_multiply.root_partition.map.kpt
diff --git a/registered_multiply/output_files/Chain3.cdf b/registered_multiply/output_files/Chain3.cdf
new file mode 100644
index 0000000..4da79d9
--- /dev/null
+++ b/registered_multiply/output_files/Chain3.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/") File("registered_multiply.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/registered_multiply/output_files/registered_multiply.asm.rpt b/registered_multiply/output_files/registered_multiply.asm.rpt
new file mode 100644
index 0000000..9dfdf85
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for registered_multiply
+Fri Feb 19 16:10:43 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 19 16:10:43 2016 ;
+; Revision Name         ; registered_multiply                   ;
+; Top-level Entity Name ; registered_multiply                   ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                               ;
++-----------------------------------------------------------------------------------------+
+; File Name                                                                               ;
++-----------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.sof ;
++-----------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.sof ;
++----------------+--------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                          ;
++----------------+--------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                                     ;
+; JTAG usercode  ; 0x000D0F80                                                                                       ;
+; Checksum       ; 0x000D0F80                                                                                       ;
++----------------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:10:41 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 465 megabytes
+    Info: Processing ended: Fri Feb 19 16:10:43 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/registered_multiply/output_files/registered_multiply.done b/registered_multiply/output_files/registered_multiply.done
new file mode 100644
index 0000000..fc4496e
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.done
@@ -0,0 +1 @@
+Fri Feb 19 16:12:07 2016
diff --git a/registered_multiply/output_files/registered_multiply.eda.rpt b/registered_multiply/output_files/registered_multiply.eda.rpt
new file mode 100644
index 0000000..bc21363
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for registered_multiply
+Fri Feb 19 16:10:48 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb 19 16:10:48 2016 ;
+; Revision Name             ; registered_multiply                   ;
+; Top-level Entity Name     ; registered_multiply                   ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                            ;
++-----------------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                                       ;
++-----------------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply.vho                        ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/registered_multiply_vhd.sdo                    ;
++-----------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:10:47 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off registered_multiply -c registered_multiply
+Info (204019): Generated file registered_multiply_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply.vho in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file registered_multiply_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/registered_multiply/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 427 megabytes
+    Info: Processing ended: Fri Feb 19 16:10:48 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/registered_multiply/output_files/registered_multiply.fit.rpt b/registered_multiply/output_files/registered_multiply.fit.rpt
new file mode 100644
index 0000000..00b49ad
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.fit.rpt
@@ -0,0 +1,1450 @@
+Fitter report for registered_multiply
+Fri Feb 19 16:10:40 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Non-Global High Fan-Out Signals
+ 22. Routing Usage Summary
+ 23. LAB Logic Elements
+ 24. LAB-wide Signals
+ 25. LAB Signals Sourced
+ 26. LAB Signals Sourced Out
+ 27. LAB Distinct Inputs
+ 28. I/O Rules Summary
+ 29. I/O Rules Details
+ 30. I/O Rules Matrix
+ 31. Fitter Device Options
+ 32. Operating Settings and Conditions
+ 33. Estimated Delay Added for Hold Timing Summary
+ 34. Estimated Delay Added for Hold Timing Details
+ 35. Fitter Messages
+ 36. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 19 16:10:40 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; registered_multiply                        ;
+; Top-level Entity Name              ; registered_multiply                        ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 57 / 15,408 ( < 1 % )                      ;
+;     Total combinational functions  ; 52 / 15,408 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 20 / 15,408 ( < 1 % )                      ;
+; Total registers                    ; 20                                         ;
+; Total pins                         ; 21 / 347 ( 6 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; Output[9] ; Missing drive strength and slew rate ;
+; Output[8] ; Missing drive strength and slew rate ;
+; Output[7] ; Missing drive strength and slew rate ;
+; Output[6] ; Missing drive strength and slew rate ;
+; Output[5] ; Missing drive strength and slew rate ;
+; Output[4] ; Missing drive strength and slew rate ;
+; Output[3] ; Missing drive strength and slew rate ;
+; Output[2] ; Missing drive strength and slew rate ;
+; Output[1] ; Missing drive strength and slew rate ;
+; Output[0] ; Missing drive strength and slew rate ;
++-----------+--------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 125 ) ; 0.00 % ( 0 / 125 )         ; 0.00 % ( 0 / 125 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 125 ) ; 0.00 % ( 0 / 125 )         ; 0.00 % ( 0 / 125 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 115 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 57 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 37                    ;
+;     -- Register only                        ; 5                     ;
+;     -- Combinational with a register        ; 15                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 37                    ;
+;     -- 3 input functions                    ; 4                     ;
+;     -- <=2 input functions                  ; 11                    ;
+;     -- Register only                        ; 5                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 52                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 20 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 20 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 5 / 963 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 21 / 347 ( 6 % )      ;
+;     -- Clock pins                           ; 0 / 8 ( 0 % )         ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 0                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 0 / 20 ( 0 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 1% / 0% / 1%          ;
+; Maximum fan-out                             ; 20                    ;
+; Highest non-global fan-out                  ; 20                    ;
+; Total fan-out                               ; 263                   ;
+; Average fan-out                             ; 2.04                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 57 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 37                   ; 0                              ;
+;     -- Register only                        ; 5                    ; 0                              ;
+;     -- Combinational with a register        ; 15                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 37                   ; 0                              ;
+;     -- 3 input functions                    ; 4                    ; 0                              ;
+;     -- <=2 input functions                  ; 11                   ; 0                              ;
+;     -- Register only                        ; 5                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 52                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 20                   ; 0                              ;
+;     -- Dedicated logic registers            ; 20 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 5 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 21                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 258                  ; 5                              ;
+;     -- Registered Connections               ; 105                  ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 11                   ; 0                              ;
+;     -- Output Ports                         ; 10                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; A[0] ; J6    ; 1        ; 0            ; 24           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; A[1] ; H5    ; 1        ; 0            ; 27           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; A[2] ; H6    ; 1        ; 0            ; 25           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; A[3] ; G4    ; 1        ; 0            ; 23           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; A[4] ; G5    ; 1        ; 0            ; 27           ; 21           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; B[0] ; J7    ; 1        ; 0            ; 22           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; B[1] ; H7    ; 1        ; 0            ; 25           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; B[2] ; E3    ; 1        ; 0            ; 26           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; B[3] ; E4    ; 1        ; 0            ; 26           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; B[4] ; D2    ; 1        ; 0            ; 25           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; CLK  ; F1    ; 1        ; 0            ; 23           ; 0            ; 20                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Output[0] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[1] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[2] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[3] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[4] ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[5] ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[6] ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[7] ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[8] ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Output[9] ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET          ; Use as regular IO        ; B[3]                    ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 25 / 33 ( 76 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; Output[9]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; Output[8]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; Output[6]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; Output[7]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; B[4]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; Output[5]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; B[2]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; B[3]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; CLK                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; Output[4]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G4       ; 17         ; 1        ; A[3]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; A[4]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; Output[3]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; A[1]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; A[2]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; B[1]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; Output[0]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; Output[1]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; Output[2]                                                 ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; A[0]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; B[0]                                                      ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                              ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                               ; Library Name ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------+--------------+
+; |registered_multiply            ; 57 (19)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 21   ; 0            ; 37 (0)       ; 5 (5)             ; 15 (1)           ; |registered_multiply                                              ; work         ;
+;    |ten_bit_adder_NO_BUS:inst1| ; 16 (4)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (1)       ; 0 (0)             ; 4 (3)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1                   ; work         ;
+;       |full_adder:inst10|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10 ; work         ;
+;       |full_adder:inst11|       ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst2| ; 10 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 1 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2                   ; work         ;
+;       |full_adder:inst11|       ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst3| ; 13 (1)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (1)        ; 0 (0)             ; 6 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3                   ; work         ;
+;       |full_adder:inst12|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15 ; work         ;
+;       |full_adder:inst16|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 2 (2)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst|  ; 12 (3)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (3)        ; 0 (0)             ; 3 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst                    ; work         ;
+;       |full_adder:inst10|       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10  ; work         ;
+;       |full_adder:inst11|       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11  ; work         ;
+;       |full_adder:inst12|       ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12  ; work         ;
+;       |full_adder:inst9|        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9   ; work         ;
++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                       ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name      ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+; Output[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Output[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; CLK       ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --  ; --   ;
+; B[4]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; A[4]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; A[2]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; A[3]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; B[3]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; B[1]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; B[0]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; A[1]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; A[0]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; B[2]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++-----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------+
+; Pad To Core Delay Chain Fanout                     ;
++----------------------+-------------------+---------+
+; Source Pin / Fanout  ; Pad To Core Index ; Setting ;
++----------------------+-------------------+---------+
+; CLK                  ;                   ;         ;
+;      - inst31        ; 1                 ; 0       ;
+;      - inst30        ; 1                 ; 0       ;
+;      - inst27        ; 1                 ; 0       ;
+;      - inst15        ; 0                 ; 0       ;
+;      - inst14        ; 0                 ; 0       ;
+;      - inst4         ; 0                 ; 0       ;
+;      - inst13        ; 0                 ; 0       ;
+;      - inst91        ; 0                 ; 0       ;
+;      - inst10        ; 0                 ; 0       ;
+;      - inst11        ; 1                 ; 0       ;
+;      - inst12        ; 1                 ; 0       ;
+;      - inst32        ; 1                 ; 0       ;
+;      - inst33        ; 1                 ; 0       ;
+;      - inst34        ; 1                 ; 0       ;
+;      - inst35        ; 1                 ; 0       ;
+;      - inst36        ; 1                 ; 0       ;
+;      - inst37        ; 1                 ; 0       ;
+;      - inst38        ; 1                 ; 0       ;
+;      - inst39        ; 1                 ; 0       ;
+;      - inst40        ; 1                 ; 0       ;
+; B[4]                 ;                   ;         ;
+;      - inst30~feeder ; 0                 ; 6       ;
+; A[4]                 ;                   ;         ;
+;      - inst12~feeder ; 0                 ; 6       ;
+; A[2]                 ;                   ;         ;
+;      - inst10        ; 0                 ; 6       ;
+; A[3]                 ;                   ;         ;
+;      - inst11~feeder ; 1                 ; 6       ;
+; B[3]                 ;                   ;         ;
+;      - inst27~feeder ; 0                 ; 6       ;
+; B[1]                 ;                   ;         ;
+;      - inst14        ; 0                 ; 6       ;
+; B[0]                 ;                   ;         ;
+;      - inst13        ; 1                 ; 6       ;
+; A[1]                 ;                   ;         ;
+;      - inst91        ; 1                 ; 6       ;
+; A[0]                 ;                   ;         ;
+;      - inst4~feeder  ; 0                 ; 6       ;
+; B[2]                 ;                   ;         ;
+;      - inst15        ; 0                 ; 6       ;
++----------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                  ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_F1   ; 20      ; Clock ; no     ; --                   ; --               ; --                        ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                ;
++------------------------------------------------------+---------+
+; Name                                                 ; Fan-Out ;
++------------------------------------------------------+---------+
+; CLK~input                                            ; 20      ;
+; inst4                                                ; 12      ;
+; inst13                                               ; 12      ;
+; inst10                                               ; 11      ;
+; inst91                                               ; 10      ;
+; inst30                                               ; 10      ;
+; inst27                                               ; 9       ;
+; inst11                                               ; 9       ;
+; inst12                                               ; 8       ;
+; inst15                                               ; 7       ;
+; inst14                                               ; 7       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst2   ; 4       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst3~0  ; 4       ;
+; ten_bit_adder_NO_BUS:inst|inst21                     ; 4       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst2~0 ; 3       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst2   ; 3       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst2~0  ; 3       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst3~1  ; 3       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst15|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst5~1 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst12|inst6   ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst14|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst13|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~1 ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst13|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst14|inst2   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst22                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst13|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst21                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst12|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst12|inst2    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst3~0 ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst6   ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst18                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst1|inst19                    ; 2       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst3~0  ; 2       ;
+; ten_bit_adder_NO_BUS:inst|inst19                     ; 2       ;
+; ten_bit_adder_NO_BUS:inst|inst20                     ; 2       ;
+; ten_bit_adder_NO_BUS:inst3|inst22                    ; 2       ;
+; B[2]~input                                           ; 1       ;
+; A[0]~input                                           ; 1       ;
+; A[1]~input                                           ; 1       ;
+; B[0]~input                                           ; 1       ;
+; B[1]~input                                           ; 1       ;
+; B[3]~input                                           ; 1       ;
+; A[3]~input                                           ; 1       ;
+; A[2]~input                                           ; 1       ;
+; A[4]~input                                           ; 1       ;
+; B[4]~input                                           ; 1       ;
+; inst5                                                ; 1       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst9|inst      ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst10|inst    ; 1       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst11|inst    ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst12|inst    ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst2   ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst14|inst2~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst15|inst2~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst2   ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst16|inst3~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst3|full_adder:inst13|inst5~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst2|full_adder:inst12|inst3~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst2~0  ; 1       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst11|inst2    ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst5~1 ; 1       ;
+; ten_bit_adder_NO_BUS:inst1|full_adder:inst11|inst5~0 ; 1       ;
+; ten_bit_adder_NO_BUS:inst|full_adder:inst10|inst3~0  ; 1       ;
+; inst31                                               ; 1       ;
+; inst32                                               ; 1       ;
+; inst33                                               ; 1       ;
+; inst34                                               ; 1       ;
+; inst35                                               ; 1       ;
+; inst36                                               ; 1       ;
+; inst37                                               ; 1       ;
+; inst38                                               ; 1       ;
+; inst39                                               ; 1       ;
+; inst40                                               ; 1       ;
++------------------------------------------------------+---------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary                         ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage                 ;
++-----------------------+-----------------------+
+; Block interconnects   ; 86 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects      ; 39 / 31,272 ( < 1 % ) ;
+; Direct links          ; 23 / 47,787 ( < 1 % ) ;
+; Global clocks         ; 0 / 20 ( 0 % )        ;
+; Local interconnects   ; 37 / 15,408 ( < 1 % ) ;
+; R24 interconnects     ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects      ; 31 / 41,310 ( < 1 % ) ;
++-----------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 11.40) ; Number of LABs  (Total = 5) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 1                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 1                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 1                           ;
+; 16                                          ; 2                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 5) ;
++------------------------------------+-----------------------------+
+; 1 Clock                            ; 5                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 15.40) ; Number of LABs  (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 2                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 1                           ;
+; 20                                           ; 1                           ;
+; 21                                           ; 0                           ;
+; 22                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 7.40) ; Number of LABs  (Total = 5) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 2                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 1                           ;
+; 8                                               ; 1                           ;
+; 9                                               ; 0                           ;
+; 10                                              ; 0                           ;
+; 11                                              ; 0                           ;
+; 12                                              ; 0                           ;
+; 13                                              ; 0                           ;
+; 14                                              ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 11.40) ; Number of LABs  (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 1                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 1                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 1                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 21        ; 0            ; 21        ; 0            ; 0            ; 21        ; 21        ; 0            ; 21        ; 21        ; 0            ; 10           ; 0            ; 0            ; 11           ; 0            ; 10           ; 11           ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 21        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 21           ; 0         ; 21           ; 21           ; 0         ; 0         ; 21           ; 0         ; 0         ; 21           ; 11           ; 21           ; 21           ; 10           ; 21           ; 11           ; 10           ; 21           ; 21           ; 21           ; 11           ; 21           ; 21           ; 21           ; 21           ; 21           ; 0         ; 21           ; 21           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Output[9]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[8]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Output[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; B[4]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; A[4]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; A[2]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; A[3]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; B[3]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; B[1]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; B[0]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; A[1]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; A[0]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; B[2]               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details              ;
++-----------------+----------------------+-------------------+
+; Source Register ; Destination Register ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; CLK             ; inst27               ; 0.177             ;
++-----------------+----------------------+-------------------+
+Note: This table only shows the top 1 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EP3C16F484C6 for design "registered_multiply"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 822 megabytes
+    Info: Processing ended: Fri Feb 19 16:10:40 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:07
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/registered_multiply/output_files/registered_multiply.fit.smsg.
+
+
diff --git a/registered_multiply/output_files/registered_multiply.fit.smsg b/registered_multiply/output_files/registered_multiply.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/registered_multiply/output_files/registered_multiply.fit.summary b/registered_multiply/output_files/registered_multiply.fit.summary
new file mode 100644
index 0000000..bebf109
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Fri Feb 19 16:10:40 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : registered_multiply
+Top-level Entity Name : registered_multiply
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 57 / 15,408 ( < 1 % )
+    Total combinational functions : 52 / 15,408 ( < 1 % )
+    Dedicated logic registers : 20 / 15,408 ( < 1 % )
+Total registers : 20
+Total pins : 21 / 347 ( 6 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/registered_multiply/output_files/registered_multiply.flow.rpt b/registered_multiply/output_files/registered_multiply.flow.rpt
new file mode 100644
index 0000000..9e2e4ec
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.flow.rpt
@@ -0,0 +1,116 @@
+Flow report for registered_multiply
+Fri Feb 19 16:12:06 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 19 16:12:06 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; registered_multiply                        ;
+; Top-level Entity Name              ; registered_multiply                        ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16F484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 62                                         ;
+;     Total combinational functions  ; 52                                         ;
+;     Dedicated logic registers      ; 20                                         ;
+; Total registers                    ; 20                                         ;
+; Total pins                         ; 21                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/19/2016 16:12:05 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; registered_multiply ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145589832503200 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:01     ; 1.0                     ; 495 MB              ; 00:00:01                           ;
+; Total                ; 00:00:01     ; --                      ; --                  ; 00:00:01                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; Flow OS Summary                                                                   ;
++----------------------+------------------+-----------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++----------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++----------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply
+
+
+
diff --git a/registered_multiply/output_files/registered_multiply.jdi b/registered_multiply/output_files/registered_multiply.jdi
new file mode 100644
index 0000000..ee27c58
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="252ad6221fd03992994b"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="registered_multiply.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/registered_multiply/output_files/registered_multiply.map.rpt b/registered_multiply/output_files/registered_multiply.map.rpt
new file mode 100644
index 0000000..9570a11
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.map.rpt
@@ -0,0 +1,293 @@
+Analysis & Synthesis report for registered_multiply
+Fri Feb 19 16:12:06 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 19 16:12:06 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; registered_multiply                        ;
+; Top-level Entity Name              ; registered_multiply                        ;
+; Family                             ; Cyclone III                                ;
+; Total logic elements               ; 62                                         ;
+;     Total combinational functions  ; 52                                         ;
+;     Dedicated logic registers      ; 20                                         ;
+; Total registers                    ; 20                                         ;
+; Total pins                         ; 21                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                          ;
++----------------------------------------------------------------------------+---------------------+---------------------+
+; Option                                                                     ; Setting             ; Default Value       ;
++----------------------------------------------------------------------------+---------------------+---------------------+
+; Device                                                                     ; EP3C16F484C6        ;                     ;
+; Top-level entity name                                                      ; registered_multiply ; registered_multiply ;
+; Family name                                                                ; Cyclone III         ; Cyclone IV GX       ;
+; Use smart compilation                                                      ; Off                 ; Off                 ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                  ; On                  ;
+; Enable compact report table                                                ; Off                 ; Off                 ;
+; Restructure Multiplexers                                                   ; Auto                ; Auto                ;
+; Create Debugging Nodes for IP Cores                                        ; Off                 ; Off                 ;
+; Preserve fewer node names                                                  ; On                  ; On                  ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                 ; Off                 ;
+; Verilog Version                                                            ; Verilog_2001        ; Verilog_2001        ;
+; VHDL Version                                                               ; VHDL_1993           ; VHDL_1993           ;
+; State Machine Processing                                                   ; Auto                ; Auto                ;
+; Safe State Machine                                                         ; Off                 ; Off                 ;
+; Extract Verilog State Machines                                             ; On                  ; On                  ;
+; Extract VHDL State Machines                                                ; On                  ; On                  ;
+; Ignore Verilog initial constructs                                          ; Off                 ; Off                 ;
+; Iteration limit for constant Verilog loops                                 ; 5000                ; 5000                ;
+; Iteration limit for non-constant Verilog loops                             ; 250                 ; 250                 ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                  ; On                  ;
+; Infer RAMs from Raw Logic                                                  ; On                  ; On                  ;
+; Parallel Synthesis                                                         ; On                  ; On                  ;
+; DSP Block Balancing                                                        ; Auto                ; Auto                ;
+; NOT Gate Push-Back                                                         ; On                  ; On                  ;
+; Power-Up Don't Care                                                        ; On                  ; On                  ;
+; Remove Redundant Logic Cells                                               ; Off                 ; Off                 ;
+; Remove Duplicate Registers                                                 ; On                  ; On                  ;
+; Ignore CARRY Buffers                                                       ; Off                 ; Off                 ;
+; Ignore CASCADE Buffers                                                     ; Off                 ; Off                 ;
+; Ignore GLOBAL Buffers                                                      ; Off                 ; Off                 ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                 ; Off                 ;
+; Ignore LCELL Buffers                                                       ; Off                 ; Off                 ;
+; Ignore SOFT Buffers                                                        ; On                  ; On                  ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                 ; Off                 ;
+; Optimization Technique                                                     ; Balanced            ; Balanced            ;
+; Carry Chain Length                                                         ; 70                  ; 70                  ;
+; Auto Carry Chains                                                          ; On                  ; On                  ;
+; Auto Open-Drain Pins                                                       ; On                  ; On                  ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                 ; Off                 ;
+; Auto ROM Replacement                                                       ; On                  ; On                  ;
+; Auto RAM Replacement                                                       ; On                  ; On                  ;
+; Auto DSP Block Replacement                                                 ; On                  ; On                  ;
+; Auto Shift Register Replacement                                            ; Auto                ; Auto                ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto                ; Auto                ;
+; Auto Clock Enable Replacement                                              ; On                  ; On                  ;
+; Strict RAM Replacement                                                     ; Off                 ; Off                 ;
+; Allow Synchronous Control Signals                                          ; On                  ; On                  ;
+; Force Use of Synchronous Clear Signals                                     ; Off                 ; Off                 ;
+; Auto RAM Block Balancing                                                   ; On                  ; On                  ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                 ; Off                 ;
+; Auto Resource Sharing                                                      ; Off                 ; Off                 ;
+; Allow Any RAM Size For Recognition                                         ; Off                 ; Off                 ;
+; Allow Any ROM Size For Recognition                                         ; Off                 ; Off                 ;
+; Allow Any Shift Register Size For Recognition                              ; Off                 ; Off                 ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                  ; On                  ;
+; Ignore translate_off and synthesis_off directives                          ; Off                 ; Off                 ;
+; Timing-Driven Synthesis                                                    ; On                  ; On                  ;
+; Report Parameter Settings                                                  ; On                  ; On                  ;
+; Report Source Assignments                                                  ; On                  ; On                  ;
+; Report Connectivity Checks                                                 ; On                  ; On                  ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                 ; Off                 ;
+; Synchronization Register Chain Length                                      ; 2                   ; 2                   ;
+; PowerPlay Power Optimization                                               ; Normal compilation  ; Normal compilation  ;
+; HDL message level                                                          ; Level2              ; Level2              ;
+; Suppress Register Optimization Related Messages                            ; Off                 ; Off                 ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000                ; 5000                ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                ; 5000                ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                 ; 100                 ;
+; Clock MUX Protection                                                       ; On                  ; On                  ;
+; Auto Gated Clock Conversion                                                ; Off                 ; Off                 ;
+; Block Design Naming                                                        ; Auto                ; Auto                ;
+; SDC constraint protection                                                  ; Off                 ; Off                 ;
+; Synthesis Effort                                                           ; Auto                ; Auto                ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                  ; On                  ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                 ; Off                 ;
+; Analysis & Synthesis Message Level                                         ; Medium              ; Medium              ;
+; Disable Register Merging Across Hierarchies                                ; Auto                ; Auto                ;
+; Resource Aware Inference For Block RAM                                     ; On                  ; On                  ;
+; Synthesis Seed                                                             ; 1                   ; 1                   ;
++----------------------------------------------------------------------------+---------------------+---------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                           ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path                 ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                 ; Library ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf ;         ;
+; ../adder/full_adder.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf                          ;         ;
+; ../comb_multiply/registered_multiply.bdf         ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf         ;         ;
++--------------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary             ;
++---------------------------------------------+-----------+
+; Resource                                    ; Usage     ;
++---------------------------------------------+-----------+
+; Estimated Total logic elements              ; 62        ;
+;                                             ;           ;
+; Total combinational functions               ; 52        ;
+; Logic element usage by number of LUT inputs ;           ;
+;     -- 4 input functions                    ; 37        ;
+;     -- 3 input functions                    ; 4         ;
+;     -- <=2 input functions                  ; 11        ;
+;                                             ;           ;
+; Logic elements by mode                      ;           ;
+;     -- normal mode                          ; 52        ;
+;     -- arithmetic mode                      ; 0         ;
+;                                             ;           ;
+; Total registers                             ; 20        ;
+;     -- Dedicated logic registers            ; 20        ;
+;     -- I/O registers                        ; 0         ;
+;                                             ;           ;
+; I/O pins                                    ; 21        ;
+; Embedded Multiplier 9-bit elements          ; 0         ;
+; Maximum fan-out node                        ; CLK~input ;
+; Maximum fan-out                             ; 20        ;
+; Total fan-out                               ; 253       ;
+; Average fan-out                             ; 2.22      ;
++---------------------------------------------+-----------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                            ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                               ; Library Name ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------+--------------+
+; |registered_multiply            ; 52 (1)            ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 21   ; 0            ; |registered_multiply                                              ; work         ;
+;    |ten_bit_adder_NO_BUS:inst1| ; 16 (4)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1                   ; work         ;
+;       |full_adder:inst10|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst10 ; work         ;
+;       |full_adder:inst11|       ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst1|full_adder:inst14 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst2| ; 10 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2                   ; work         ;
+;       |full_adder:inst11|       ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst11 ; work         ;
+;       |full_adder:inst12|       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst2|full_adder:inst15 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst3| ; 13 (1)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3                   ; work         ;
+;       |full_adder:inst12|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst12 ; work         ;
+;       |full_adder:inst13|       ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst13 ; work         ;
+;       |full_adder:inst14|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst14 ; work         ;
+;       |full_adder:inst15|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst15 ; work         ;
+;       |full_adder:inst16|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst3|full_adder:inst16 ; work         ;
+;    |ten_bit_adder_NO_BUS:inst|  ; 12 (3)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst                    ; work         ;
+;       |full_adder:inst10|       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst10  ; work         ;
+;       |full_adder:inst11|       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst11  ; work         ;
+;       |full_adder:inst12|       ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst12  ; work         ;
+;       |full_adder:inst9|        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |registered_multiply|ten_bit_adder_NO_BUS:inst|full_adder:inst9   ; work         ;
++---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 20    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:12:05 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off registered_multiply -c registered_multiply
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/ten_bit_adder_no_bus/ten_bit_adder_no_bus.bdf
+    Info (12023): Found entity 1: ten_bit_adder_NO_BUS
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/comb_multiply/registered_multiply.bdf
+    Info (12023): Found entity 1: registered_multiply
+Info (12127): Elaborating entity "registered_multiply" for the top level hierarchy
+Warning (275011): Block or symbol "GND" of instance "inst21" overlaps another block or symbol
+Warning (275008): Primitive "GND" of instance "inst21" not used
+Warning (275008): Primitive "GND" of instance "inst22" not used
+Warning (275008): Primitive "GND" of instance "inst23" not used
+Warning (275008): Primitive "GND" of instance "inst24" not used
+Info (12128): Elaborating entity "ten_bit_adder_NO_BUS" for hierarchy "ten_bit_adder_NO_BUS:inst3"
+Info (12128): Elaborating entity "full_adder" for hierarchy "ten_bit_adder_NO_BUS:inst3|full_adder:inst17"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 83 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 11 input pins
+    Info (21059): Implemented 10 output pins
+    Info (21061): Implemented 62 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 506 megabytes
+    Info: Processing ended: Fri Feb 19 16:12:06 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/registered_multiply/output_files/registered_multiply.map.summary b/registered_multiply/output_files/registered_multiply.map.summary
new file mode 100644
index 0000000..febd821
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Fri Feb 19 16:12:06 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : registered_multiply
+Top-level Entity Name : registered_multiply
+Family : Cyclone III
+Total logic elements : 62
+    Total combinational functions : 52
+    Dedicated logic registers : 20
+Total registers : 20
+Total pins : 21
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/registered_multiply/output_files/registered_multiply.pin b/registered_multiply/output_files/registered_multiply.pin
new file mode 100644
index 0000000..bad7297
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "registered_multiply"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+Output[9]                    : B1        : output : 2.5 V             :         : 1         : Y              
+Output[8]                    : B2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+Output[6]                    : C1        : output : 2.5 V             :         : 1         : Y              
+Output[7]                    : C2        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+B[4]                         : D2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+Output[5]                    : E1        : output : 2.5 V             :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+B[2]                         : E3        : input  : 2.5 V             :         : 1         : Y              
+B[3]                         : E4        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+CLK                          : F1        : input  : 2.5 V             :         : 1         : Y              
+Output[4]                    : F2        : output : 2.5 V             :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3        :        :                   :         : 1         :                
+A[3]                         : G4        : input  : 2.5 V             :         : 1         : Y              
+A[4]                         : G5        : input  : 2.5 V             :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+GND+                         : G21       :        :                   :         : 6         :                
+GND+                         : G22       :        :                   :         : 6         :                
+Output[3]                    : H1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+A[1]                         : H5        : input  : 2.5 V             :         : 1         : Y              
+A[2]                         : H6        : input  : 2.5 V             :         : 1         : Y              
+B[1]                         : H7        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+Output[0]                    : J1        : output : 2.5 V             :         : 1         : Y              
+Output[1]                    : J2        : output : 2.5 V             :         : 1         : Y              
+Output[2]                    : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+A[0]                         : J6        : input  : 2.5 V             :         : 1         : Y              
+B[0]                         : J7        : input  : 2.5 V             :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/registered_multiply/output_files/registered_multiply.sof b/registered_multiply/output_files/registered_multiply.sof
new file mode 100644
index 0000000..2c7984a
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.sof
diff --git a/registered_multiply/output_files/registered_multiply.sta.rpt b/registered_multiply/output_files/registered_multiply.sta.rpt
new file mode 100644
index 0000000..990927b
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.sta.rpt
@@ -0,0 +1,1673 @@
+TimeQuest Timing Analyzer report for registered_multiply
+Fri Feb 19 16:10:46 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'CLK'
+ 13. Slow 1200mV 85C Model Hold: 'CLK'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'
+ 15. Setup Times
+ 16. Hold Times
+ 17. Clock to Output Times
+ 18. Minimum Clock to Output Times
+ 19. Slow 1200mV 85C Model Metastability Report
+ 20. Slow 1200mV 0C Model Fmax Summary
+ 21. Slow 1200mV 0C Model Setup Summary
+ 22. Slow 1200mV 0C Model Hold Summary
+ 23. Slow 1200mV 0C Model Recovery Summary
+ 24. Slow 1200mV 0C Model Removal Summary
+ 25. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 26. Slow 1200mV 0C Model Setup: 'CLK'
+ 27. Slow 1200mV 0C Model Hold: 'CLK'
+ 28. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 29. Setup Times
+ 30. Hold Times
+ 31. Clock to Output Times
+ 32. Minimum Clock to Output Times
+ 33. Slow 1200mV 0C Model Metastability Report
+ 34. Fast 1200mV 0C Model Setup Summary
+ 35. Fast 1200mV 0C Model Hold Summary
+ 36. Fast 1200mV 0C Model Recovery Summary
+ 37. Fast 1200mV 0C Model Removal Summary
+ 38. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 39. Fast 1200mV 0C Model Setup: 'CLK'
+ 40. Fast 1200mV 0C Model Hold: 'CLK'
+ 41. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 42. Setup Times
+ 43. Hold Times
+ 44. Clock to Output Times
+ 45. Minimum Clock to Output Times
+ 46. Fast 1200mV 0C Model Metastability Report
+ 47. Multicorner Timing Analysis Summary
+ 48. Setup Times
+ 49. Hold Times
+ 50. Clock to Output Times
+ 51. Minimum Clock to Output Times
+ 52. Board Trace Model Assignments
+ 53. Input Transition Times
+ 54. Slow Corner Signal Integrity Metrics
+ 55. Fast Corner Signal Integrity Metrics
+ 56. Setup Transfers
+ 57. Hold Transfers
+ 58. Report TCCS
+ 59. Report RSKM
+ 60. Unconstrained Paths
+ 61. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; registered_multiply                                ;
+; Device Family      ; Cyclone III                                        ;
+; Device Name        ; EP3C16F484C6                                       ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; CLK        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
++--------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary               ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 182.55 MHz ; 182.55 MHz      ; CLK        ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-------+--------+--------------------+
+; Clock ; Slack  ; End Point TNS      ;
++-------+--------+--------------------+
+; CLK   ; -4.478 ; -28.219            ;
++-------+--------+--------------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; CLK   ; 0.617 ; 0.000              ;
++-------+-------+--------------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-------+--------+----------------------------------+
+; Clock ; Slack  ; End Point TNS                    ;
++-------+--------+----------------------------------+
+; CLK   ; -3.000 ; -23.000                          ;
++-------+--------+----------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLK'                                                                 ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -4.478 ; inst11    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 5.351      ;
+; -4.476 ; inst11    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 5.349      ;
+; -4.321 ; inst91    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.455      ;
+; -4.319 ; inst91    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.453      ;
+; -4.302 ; inst14    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.436      ;
+; -4.300 ; inst14    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.434      ;
+; -4.294 ; inst10    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.428      ;
+; -4.292 ; inst10    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.426      ;
+; -4.290 ; inst13    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.424      ;
+; -4.288 ; inst13    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.422      ;
+; -4.183 ; inst15    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.317      ;
+; -4.181 ; inst15    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.315      ;
+; -4.156 ; inst11    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 5.029      ;
+; -4.145 ; inst4     ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.279      ;
+; -4.143 ; inst4     ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.277      ;
+; -3.999 ; inst91    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.133      ;
+; -3.980 ; inst14    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.114      ;
+; -3.972 ; inst10    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.106      ;
+; -3.968 ; inst13    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 5.102      ;
+; -3.861 ; inst15    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 4.995      ;
+; -3.843 ; inst11    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 4.731      ;
+; -3.823 ; inst4     ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.119      ; 4.957      ;
+; -3.688 ; inst91    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.835      ;
+; -3.669 ; inst14    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.816      ;
+; -3.661 ; inst10    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.808      ;
+; -3.657 ; inst13    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.804      ;
+; -3.550 ; inst15    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.697      ;
+; -3.512 ; inst4     ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.659      ;
+; -3.407 ; inst12    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 4.280      ;
+; -3.405 ; inst12    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 4.278      ;
+; -3.085 ; inst12    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.142     ; 3.958      ;
+; -3.072 ; inst11    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 3.960      ;
+; -2.917 ; inst91    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.064      ;
+; -2.898 ; inst14    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.045      ;
+; -2.890 ; inst10    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.037      ;
+; -2.886 ; inst13    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.033      ;
+; -2.779 ; inst15    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.926      ;
+; -2.772 ; inst12    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 3.660      ;
+; -2.741 ; inst4     ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.888      ;
+; -2.669 ; inst11    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.598     ; 3.086      ;
+; -2.495 ; inst11    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 3.383      ;
+; -2.463 ; inst10    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 3.141      ;
+; -2.300 ; inst91    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.978      ;
+; -2.292 ; inst27    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 3.223      ;
+; -2.291 ; inst10    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.438      ;
+; -2.290 ; inst27    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 3.221      ;
+; -2.281 ; inst14    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.959      ;
+; -2.274 ; inst13    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.952      ;
+; -2.203 ; inst15    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.881      ;
+; -2.176 ; inst30    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 3.107      ;
+; -2.174 ; inst30    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 3.105      ;
+; -2.165 ; inst4     ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.843      ;
+; -2.134 ; inst91    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.281      ;
+; -2.115 ; inst14    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.262      ;
+; -2.103 ; inst13    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.250      ;
+; -2.007 ; inst15    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.154      ;
+; -2.001 ; inst12    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 2.889      ;
+; -1.993 ; inst4     ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.140      ;
+; -1.970 ; inst27    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 2.901      ;
+; -1.854 ; inst30    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.084     ; 2.785      ;
+; -1.596 ; inst27    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 2.567      ;
+; -1.389 ; inst15    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.067      ;
+; -1.351 ; inst4     ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 2.029      ;
+; -1.226 ; inst13    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.904      ;
+; -1.224 ; inst91    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.902      ;
+; -1.222 ; inst30    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 2.193      ;
+; -1.218 ; inst12    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.127     ; 2.106      ;
+; -1.205 ; inst14    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.883      ;
+; -0.996 ; inst27    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 1.967      ;
+; -0.985 ; inst91    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.663      ;
+; -0.864 ; inst13    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.542      ;
+; -0.815 ; inst27    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.540     ; 1.290      ;
+; -0.778 ; inst10    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.456      ;
+; -0.656 ; inst4     ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.334      ;
+; -0.653 ; inst4     ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.331      ;
+; -0.643 ; inst14    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.321      ;
+; -0.563 ; inst13    ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.337     ; 1.241      ;
+; -0.533 ; inst27    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 1.504      ;
+; -0.502 ; inst30    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 1.473      ;
+; -0.341 ; inst30    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.044     ; 1.312      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLK'                                                                 ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.617 ; inst30    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 0.818      ;
+; 0.753 ; inst30    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.967      ;
+; 0.753 ; inst30    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.967      ;
+; 0.754 ; inst30    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 0.968      ;
+; 0.907 ; inst27    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 1.108      ;
+; 0.910 ; inst30    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 1.111      ;
+; 1.003 ; inst15    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.455      ;
+; 1.016 ; inst27    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 1.217      ;
+; 1.093 ; inst12    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.251      ;
+; 1.099 ; inst12    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.257      ;
+; 1.099 ; inst11    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.257      ;
+; 1.111 ; inst91    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.563      ;
+; 1.135 ; inst13    ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.098      ;
+; 1.161 ; inst30    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 1.362      ;
+; 1.178 ; inst10    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.630      ;
+; 1.203 ; inst10    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.655      ;
+; 1.206 ; inst4     ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.169      ;
+; 1.206 ; inst4     ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.169      ;
+; 1.228 ; inst14    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.191      ;
+; 1.249 ; inst4     ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.701      ;
+; 1.258 ; inst10    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.221      ;
+; 1.279 ; inst27    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 1.493      ;
+; 1.300 ; inst4     ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.263      ;
+; 1.315 ; inst4     ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.767      ;
+; 1.327 ; inst13    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.290      ;
+; 1.329 ; inst13    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.292      ;
+; 1.380 ; inst27    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 1.594      ;
+; 1.385 ; inst27    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.057      ; 1.599      ;
+; 1.392 ; inst12    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.550      ;
+; 1.393 ; inst11    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.551      ;
+; 1.396 ; inst11    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.001      ; 1.554      ;
+; 1.397 ; inst27    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.418     ; 1.136      ;
+; 1.409 ; inst15    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.861      ;
+; 1.444 ; inst10    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.896      ;
+; 1.461 ; inst27    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.044      ; 1.662      ;
+; 1.471 ; inst91    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.434      ;
+; 1.500 ; inst15    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.952      ;
+; 1.509 ; inst91    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 1.961      ;
+; 1.520 ; inst4     ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.483      ;
+; 1.623 ; inst13    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.075      ;
+; 1.653 ; inst12    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 1.823      ;
+; 1.654 ; inst91    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.106      ;
+; 1.681 ; inst11    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 1.851      ;
+; 1.702 ; inst10    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.140      ;
+; 1.714 ; inst91    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.677      ;
+; 1.750 ; inst4     ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.202      ;
+; 1.750 ; inst14    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.713      ;
+; 1.950 ; inst11    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 2.120      ;
+; 1.957 ; inst15    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 1.920      ;
+; 1.982 ; inst91    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.420      ;
+; 2.002 ; inst10    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.440      ;
+; 2.005 ; inst10    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.443      ;
+; 2.028 ; inst14    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.480      ;
+; 2.029 ; inst13    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.481      ;
+; 2.059 ; inst12    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 2.229      ;
+; 2.094 ; inst15    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.532      ;
+; 2.120 ; inst13    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.572      ;
+; 2.134 ; inst14    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.586      ;
+; 2.150 ; inst12    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 2.320      ;
+; 2.194 ; inst4     ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.632      ;
+; 2.261 ; inst10    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 2.224      ;
+; 2.277 ; inst13    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 2.240      ;
+; 2.282 ; inst91    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.720      ;
+; 2.285 ; inst91    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.723      ;
+; 2.289 ; inst14    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.727      ;
+; 2.298 ; inst11    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.013      ; 2.468      ;
+; 2.375 ; inst13    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.813      ;
+; 2.393 ; inst14    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.831      ;
+; 2.394 ; inst15    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.832      ;
+; 2.397 ; inst15    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.835      ;
+; 2.398 ; inst14    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.836      ;
+; 2.412 ; inst14    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.295      ; 2.864      ;
+; 2.456 ; inst91    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 2.419      ;
+; 2.479 ; inst13    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.917      ;
+; 2.484 ; inst13    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.922      ;
+; 2.494 ; inst4     ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.932      ;
+; 2.497 ; inst4     ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.281      ; 2.935      ;
+; 2.500 ; inst14    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 2.463      ;
+; 2.599 ; inst15    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.194     ; 2.562      ;
+; 3.022 ; inst11    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.474     ; 2.705      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'                                             ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst10      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst11      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst12      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst13      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst14      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst15      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst27      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst30      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst31      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst32      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst33      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst34      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst35      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst36      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst37      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst39      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst91      ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst10      ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst13      ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst14      ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst15      ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4       ;
+; 0.151  ; 0.335        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst91      ;
+; 0.159  ; 0.343        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst27      ;
+; 0.159  ; 0.343        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst30      ;
+; 0.159  ; 0.343        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst35      ;
+; 0.159  ; 0.343        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst36      ;
+; 0.159  ; 0.343        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst37      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst11      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst12      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst31      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst32      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst33      ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst34      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst39      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40      ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst10|clk  ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst13|clk  ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst14|clk  ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst15|clk  ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk   ;
+; 0.312  ; 0.312        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst91|clk  ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst27|clk  ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst30|clk  ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst35|clk  ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst36|clk  ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst37|clk  ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst11|clk  ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst12|clk  ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst31|clk  ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst32|clk  ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst33|clk  ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst34|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst39|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk  ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst39      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst11      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst12      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst31      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst32      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst33      ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst34      ;
+; 0.441  ; 0.657        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst27      ;
+; 0.441  ; 0.657        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst30      ;
+; 0.441  ; 0.657        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst35      ;
+; 0.441  ; 0.657        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst36      ;
+; 0.441  ; 0.657        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst37      ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst10      ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst13      ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst14      ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst15      ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4       ;
+; 0.448  ; 0.664        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst91      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk  ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst39|clk  ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst11|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst12|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst31|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst32|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst33|clk  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst34|clk  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst27|clk  ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst30|clk  ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst35|clk  ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst36|clk  ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst37|clk  ;
+; 0.687  ; 0.687        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst10|clk  ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; A[*]      ; CLK        ; 2.043 ; 2.446 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; 1.665 ; 2.092 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; 1.505 ; 1.912 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; 2.043 ; 2.446 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; 1.631 ; 2.019 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; 1.305 ; 1.702 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; 2.083 ; 2.531 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; 2.083 ; 2.531 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; 1.777 ; 2.196 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; 1.951 ; 2.345 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; 1.172 ; 1.577 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; 1.511 ; 1.911 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; A[*]      ; CLK        ; -0.943 ; -1.318 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; -1.310 ; -1.715 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; -1.168 ; -1.563 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; -1.684 ; -2.076 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; -1.256 ; -1.624 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; -0.943 ; -1.318 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; -0.819 ; -1.204 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; -1.723 ; -2.158 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; -1.429 ; -1.836 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; -1.596 ; -1.980 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; -0.819 ; -1.204 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; -1.146 ; -1.525 ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 6.123 ; 6.296 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 4.974 ; 5.049 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 4.959 ; 5.024 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 6.123 ; 6.296 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 4.948 ; 5.015 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 5.392 ; 5.450 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 5.401 ; 5.434 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 5.127 ; 5.161 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 5.317 ; 5.338 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 5.587 ; 5.610 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 5.499 ; 5.513 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 4.854 ; 4.918 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 4.879 ; 4.950 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 4.865 ; 4.927 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 6.030 ; 6.200 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 4.854 ; 4.918 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 5.280 ; 5.335 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 5.289 ; 5.320 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 5.027 ; 5.059 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 5.209 ; 5.230 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 5.469 ; 5.491 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 5.384 ; 5.397 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 205.04 MHz ; 205.04 MHz      ; CLK        ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-------+--------+-------------------+
+; Clock ; Slack  ; End Point TNS     ;
++-------+--------+-------------------+
+; CLK   ; -3.877 ; -24.107           ;
++-------+--------+-------------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.550 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -23.000                         ;
++-------+--------+---------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLK'                                                                  ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -3.877 ; inst11    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 4.768      ;
+; -3.868 ; inst11    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 4.759      ;
+; -3.731 ; inst13    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.867      ;
+; -3.731 ; inst91    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.867      ;
+; -3.722 ; inst13    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.858      ;
+; -3.722 ; inst91    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.858      ;
+; -3.721 ; inst10    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.857      ;
+; -3.714 ; inst14    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.850      ;
+; -3.712 ; inst10    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.848      ;
+; -3.705 ; inst14    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.841      ;
+; -3.622 ; inst15    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.758      ;
+; -3.613 ; inst15    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.749      ;
+; -3.584 ; inst11    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 4.475      ;
+; -3.570 ; inst4     ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.706      ;
+; -3.561 ; inst4     ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.697      ;
+; -3.438 ; inst13    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.574      ;
+; -3.438 ; inst91    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.574      ;
+; -3.428 ; inst10    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.564      ;
+; -3.421 ; inst14    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.557      ;
+; -3.329 ; inst15    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.465      ;
+; -3.326 ; inst11    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 4.230      ;
+; -3.277 ; inst4     ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.121      ; 4.413      ;
+; -3.182 ; inst13    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.329      ;
+; -3.182 ; inst91    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.329      ;
+; -3.172 ; inst10    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.319      ;
+; -3.165 ; inst14    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.312      ;
+; -3.073 ; inst15    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.220      ;
+; -3.021 ; inst4     ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 4.168      ;
+; -2.948 ; inst12    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 3.839      ;
+; -2.939 ; inst12    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 3.830      ;
+; -2.655 ; inst12    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.124     ; 3.546      ;
+; -2.617 ; inst11    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 3.521      ;
+; -2.473 ; inst13    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.620      ;
+; -2.473 ; inst91    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.620      ;
+; -2.463 ; inst10    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.610      ;
+; -2.456 ; inst14    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.603      ;
+; -2.397 ; inst12    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 3.301      ;
+; -2.364 ; inst15    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.511      ;
+; -2.313 ; inst11    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.549     ; 2.779      ;
+; -2.312 ; inst4     ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.459      ;
+; -2.127 ; inst10    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.838      ;
+; -2.125 ; inst11    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 3.029      ;
+; -1.991 ; inst91    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.702      ;
+; -1.974 ; inst14    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.685      ;
+; -1.968 ; inst13    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.679      ;
+; -1.946 ; inst27    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.885      ;
+; -1.941 ; inst10    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 3.088      ;
+; -1.937 ; inst27    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.876      ;
+; -1.872 ; inst15    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.583      ;
+; -1.863 ; inst4     ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 2.574      ;
+; -1.834 ; inst30    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.773      ;
+; -1.825 ; inst30    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.764      ;
+; -1.805 ; inst91    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 2.952      ;
+; -1.788 ; inst14    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 2.935      ;
+; -1.782 ; inst13    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 2.929      ;
+; -1.688 ; inst12    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 2.592      ;
+; -1.686 ; inst15    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 2.833      ;
+; -1.677 ; inst4     ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.132      ; 2.824      ;
+; -1.653 ; inst27    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.592      ;
+; -1.541 ; inst30    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.076     ; 2.480      ;
+; -1.341 ; inst27    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 2.317      ;
+; -1.160 ; inst15    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.871      ;
+; -1.109 ; inst4     ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.820      ;
+; -1.030 ; inst13    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.741      ;
+; -0.986 ; inst12    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.111     ; 1.890      ;
+; -0.985 ; inst91    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.696      ;
+; -0.977 ; inst30    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 1.953      ;
+; -0.968 ; inst14    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.679      ;
+; -0.778 ; inst27    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 1.754      ;
+; -0.757 ; inst91    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.468      ;
+; -0.651 ; inst13    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.362      ;
+; -0.629 ; inst27    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.501     ; 1.143      ;
+; -0.576 ; inst10    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.287      ;
+; -0.480 ; inst4     ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.191      ;
+; -0.477 ; inst4     ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.188      ;
+; -0.456 ; inst14    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.167      ;
+; -0.384 ; inst13    ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.304     ; 1.095      ;
+; -0.362 ; inst27    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 1.338      ;
+; -0.336 ; inst30    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 1.312      ;
+; -0.186 ; inst30    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.039     ; 1.162      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLK'                                                                  ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.550 ; inst30    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 0.733      ;
+; 0.687 ; inst30    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 0.883      ;
+; 0.689 ; inst30    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 0.885      ;
+; 0.689 ; inst30    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 0.885      ;
+; 0.809 ; inst27    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 0.992      ;
+; 0.836 ; inst30    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 1.019      ;
+; 0.903 ; inst27    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 1.086      ;
+; 0.914 ; inst15    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.333      ;
+; 0.991 ; inst11    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.140      ;
+; 0.996 ; inst12    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.145      ;
+; 1.002 ; inst12    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.151      ;
+; 1.019 ; inst91    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.438      ;
+; 1.030 ; inst13    ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 0.995      ;
+; 1.045 ; inst30    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 1.228      ;
+; 1.078 ; inst10    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.497      ;
+; 1.095 ; inst10    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.514      ;
+; 1.096 ; inst4     ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.061      ;
+; 1.103 ; inst4     ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.068      ;
+; 1.128 ; inst14    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.093      ;
+; 1.133 ; inst4     ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.552      ;
+; 1.153 ; inst27    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 1.349      ;
+; 1.162 ; inst10    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.127      ;
+; 1.182 ; inst4     ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.147      ;
+; 1.191 ; inst4     ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.610      ;
+; 1.207 ; inst13    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.172      ;
+; 1.209 ; inst13    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.174      ;
+; 1.241 ; inst27    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 1.437      ;
+; 1.253 ; inst27    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.052      ; 1.449      ;
+; 1.253 ; inst11    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.402      ;
+; 1.263 ; inst11    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.412      ;
+; 1.263 ; inst12    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.005      ; 1.412      ;
+; 1.284 ; inst27    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.389     ; 1.039      ;
+; 1.284 ; inst15    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.703      ;
+; 1.319 ; inst27    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.039      ; 1.502      ;
+; 1.334 ; inst10    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.753      ;
+; 1.346 ; inst91    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.311      ;
+; 1.357 ; inst4     ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.322      ;
+; 1.370 ; inst15    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.789      ;
+; 1.371 ; inst91    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.790      ;
+; 1.461 ; inst13    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.880      ;
+; 1.487 ; inst12    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 1.647      ;
+; 1.513 ; inst91    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 1.932      ;
+; 1.522 ; inst11    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 1.682      ;
+; 1.544 ; inst10    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 1.950      ;
+; 1.573 ; inst91    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.538      ;
+; 1.591 ; inst4     ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.010      ;
+; 1.615 ; inst14    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.580      ;
+; 1.750 ; inst11    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 1.910      ;
+; 1.792 ; inst15    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.757      ;
+; 1.810 ; inst91    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.216      ;
+; 1.819 ; inst10    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.225      ;
+; 1.829 ; inst10    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.235      ;
+; 1.829 ; inst13    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.248      ;
+; 1.838 ; inst14    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.257      ;
+; 1.855 ; inst12    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 2.015      ;
+; 1.911 ; inst15    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.317      ;
+; 1.915 ; inst13    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.334      ;
+; 1.941 ; inst12    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 2.101      ;
+; 1.942 ; inst14    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.361      ;
+; 1.994 ; inst4     ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.400      ;
+; 2.016 ; inst10    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.981      ;
+; 2.033 ; inst13    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 1.998      ;
+; 2.073 ; inst14    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.479      ;
+; 2.085 ; inst91    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.491      ;
+; 2.089 ; inst11    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.016      ; 2.249      ;
+; 2.095 ; inst91    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.501      ;
+; 2.158 ; inst13    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.564      ;
+; 2.162 ; inst14    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.275      ; 2.581      ;
+; 2.165 ; inst14    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.571      ;
+; 2.177 ; inst14    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.583      ;
+; 2.186 ; inst15    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.592      ;
+; 2.196 ; inst15    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.602      ;
+; 2.210 ; inst91    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 2.175      ;
+; 2.250 ; inst13    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.656      ;
+; 2.259 ; inst14    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 2.224      ;
+; 2.262 ; inst13    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.668      ;
+; 2.269 ; inst4     ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.675      ;
+; 2.279 ; inst4     ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.262      ; 2.685      ;
+; 2.342 ; inst15    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.179     ; 2.307      ;
+; 2.749 ; inst11    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.436     ; 2.457      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'                                              ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst10      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst11      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst12      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst13      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst14      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst15      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst27      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst30      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst31      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst32      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst33      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst34      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst35      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst36      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst37      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst39      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst91      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst10      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst13      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst14      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst15      ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4       ;
+; 0.186  ; 0.370        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst91      ;
+; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst11      ;
+; 0.202  ; 0.386        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst12      ;
+; 0.206  ; 0.390        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst31      ;
+; 0.206  ; 0.390        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst32      ;
+; 0.206  ; 0.390        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst33      ;
+; 0.206  ; 0.390        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst34      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst27      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst30      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst35      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst36      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst37      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst39      ;
+; 0.212  ; 0.396        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40      ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst10|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst13|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst14|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst15|clk  ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk   ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst91|clk  ;
+; 0.362  ; 0.362        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst11|clk  ;
+; 0.362  ; 0.362        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst12|clk  ;
+; 0.366  ; 0.366        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst31|clk  ;
+; 0.366  ; 0.366        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst32|clk  ;
+; 0.366  ; 0.366        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst33|clk  ;
+; 0.366  ; 0.366        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst34|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst27|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst30|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst35|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst36|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst37|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst39|clk  ;
+; 0.372  ; 0.372        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk  ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst27      ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst30      ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst35      ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst36      ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst37      ;
+; 0.387  ; 0.603        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38      ;
+; 0.387  ; 0.603        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst39      ;
+; 0.387  ; 0.603        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40      ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst31      ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst32      ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst33      ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst34      ;
+; 0.396  ; 0.612        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst11      ;
+; 0.396  ; 0.612        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst12      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst10      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst13      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst14      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst15      ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4       ;
+; 0.413  ; 0.629        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst91      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst27|clk  ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst30|clk  ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst35|clk  ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst36|clk  ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst37|clk  ;
+; 0.627  ; 0.627        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk  ;
+; 0.627  ; 0.627        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst39|clk  ;
+; 0.627  ; 0.627        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk  ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst31|clk  ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst32|clk  ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst33|clk  ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst34|clk  ;
+; 0.636  ; 0.636        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst11|clk  ;
+; 0.636  ; 0.636        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst12|clk  ;
+; 0.653  ; 0.653        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst10|clk  ;
+; 0.653  ; 0.653        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst13|clk  ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; A[*]      ; CLK        ; 1.713 ; 2.050 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; 1.362 ; 1.709 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; 1.215 ; 1.563 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; 1.713 ; 2.050 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; 1.333 ; 1.658 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; 1.032 ; 1.356 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; 1.747 ; 2.104 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; 1.747 ; 2.104 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; 1.463 ; 1.827 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; 1.633 ; 1.953 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; 0.904 ; 1.245 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; 1.215 ; 1.545 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; A[*]      ; CLK        ; -0.713 ; -1.023 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; -1.050 ; -1.382 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; -0.919 ; -1.258 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; -1.398 ; -1.726 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; -1.003 ; -1.314 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; -0.713 ; -1.023 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; -0.593 ; -0.920 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; -1.430 ; -1.777 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; -1.157 ; -1.512 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; -1.321 ; -1.632 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; -0.593 ; -0.920 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; -0.893 ; -1.209 ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 5.957 ; 6.105 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 4.803 ; 4.851 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 4.790 ; 4.831 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 5.957 ; 6.105 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 4.780 ; 4.823 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 5.195 ; 5.222 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 5.201 ; 5.223 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 4.951 ; 4.968 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 5.139 ; 5.127 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 5.388 ; 5.366 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 5.302 ; 5.286 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 4.697 ; 4.737 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 4.718 ; 4.764 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 4.706 ; 4.744 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 5.874 ; 6.021 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 4.697 ; 4.737 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 5.095 ; 5.121 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 5.101 ; 5.122 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 4.861 ; 4.878 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 5.044 ; 5.032 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 5.283 ; 5.261 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 5.201 ; 5.185 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-------+--------+-------------------+
+; Clock ; Slack  ; End Point TNS     ;
++-------+--------+-------------------+
+; CLK   ; -2.060 ; -11.543           ;
++-------+--------+-------------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.332 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -25.072                         ;
++-------+--------+---------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLK'                                                                  ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -2.060 ; inst11    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.999      ;
+; -2.057 ; inst11    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.996      ;
+; -1.974 ; inst91    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.026      ;
+; -1.971 ; inst91    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.023      ;
+; -1.962 ; inst14    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.014      ;
+; -1.959 ; inst14    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.011      ;
+; -1.958 ; inst13    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.010      ;
+; -1.956 ; inst10    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.008      ;
+; -1.955 ; inst13    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.007      ;
+; -1.953 ; inst10    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 3.005      ;
+; -1.913 ; inst15    ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.965      ;
+; -1.910 ; inst15    ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.962      ;
+; -1.881 ; inst11    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.820      ;
+; -1.880 ; inst4     ; inst40  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.932      ;
+; -1.877 ; inst4     ; inst39  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.929      ;
+; -1.795 ; inst91    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.847      ;
+; -1.783 ; inst14    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.835      ;
+; -1.779 ; inst13    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.831      ;
+; -1.777 ; inst10    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.829      ;
+; -1.734 ; inst15    ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.786      ;
+; -1.707 ; inst11    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.658      ;
+; -1.701 ; inst4     ; inst38  ; CLK          ; CLK         ; 1.000        ; 0.045      ; 2.753      ;
+; -1.622 ; inst91    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.685      ;
+; -1.610 ; inst14    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.673      ;
+; -1.606 ; inst13    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.669      ;
+; -1.604 ; inst10    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.667      ;
+; -1.561 ; inst15    ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.624      ;
+; -1.528 ; inst4     ; inst37  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.591      ;
+; -1.432 ; inst12    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.371      ;
+; -1.429 ; inst12    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.368      ;
+; -1.278 ; inst11    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.229      ;
+; -1.253 ; inst12    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.068     ; 2.192      ;
+; -1.193 ; inst91    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.256      ;
+; -1.181 ; inst14    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.244      ;
+; -1.177 ; inst13    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.240      ;
+; -1.175 ; inst10    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.238      ;
+; -1.132 ; inst15    ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.195      ;
+; -1.099 ; inst4     ; inst36  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 2.162      ;
+; -1.079 ; inst12    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 2.030      ;
+; -1.066 ; inst11    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.325     ; 1.748      ;
+; -0.962 ; inst10    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.757      ;
+; -0.936 ; inst11    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 1.887      ;
+; -0.882 ; inst91    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.677      ;
+; -0.874 ; inst13    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.669      ;
+; -0.870 ; inst14    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.665      ;
+; -0.839 ; inst15    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.634      ;
+; -0.833 ; inst10    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.896      ;
+; -0.826 ; inst27    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.782      ;
+; -0.823 ; inst27    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.779      ;
+; -0.793 ; inst4     ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.588      ;
+; -0.766 ; inst30    ; inst40  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.722      ;
+; -0.763 ; inst30    ; inst39  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.719      ;
+; -0.759 ; inst91    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.822      ;
+; -0.747 ; inst14    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.810      ;
+; -0.745 ; inst13    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.808      ;
+; -0.710 ; inst15    ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.773      ;
+; -0.665 ; inst4     ; inst35  ; CLK          ; CLK         ; 1.000        ; 0.056      ; 1.728      ;
+; -0.650 ; inst12    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 1.601      ;
+; -0.647 ; inst27    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.603      ;
+; -0.587 ; inst30    ; inst38  ; CLK          ; CLK         ; 1.000        ; -0.051     ; 1.543      ;
+; -0.439 ; inst27    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 1.421      ;
+; -0.401 ; inst15    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.196      ;
+; -0.368 ; inst4     ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.163      ;
+; -0.292 ; inst91    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.087      ;
+; -0.280 ; inst14    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.075      ;
+; -0.264 ; inst13    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 1.059      ;
+; -0.234 ; inst30    ; inst37  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 1.216      ;
+; -0.216 ; inst12    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.056     ; 1.167      ;
+; -0.157 ; inst91    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.952      ;
+; -0.103 ; inst27    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 1.085      ;
+; -0.090 ; inst13    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.885      ;
+; -0.038 ; inst10    ; inst33  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.833      ;
+; -0.036 ; inst27    ; inst34  ; CLK          ; CLK         ; 1.000        ; -0.308     ; 0.735      ;
+; 0.033  ; inst4     ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.762      ;
+; 0.035  ; inst4     ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.760      ;
+; 0.035  ; inst14    ; inst32  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.760      ;
+; 0.080  ; inst13    ; inst31  ; CLK          ; CLK         ; 1.000        ; -0.212     ; 0.715      ;
+; 0.155  ; inst27    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 0.827      ;
+; 0.168  ; inst30    ; inst36  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 0.814      ;
+; 0.251  ; inst30    ; inst35  ; CLK          ; CLK         ; 1.000        ; -0.025     ; 0.731      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLK'                                                                  ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.332 ; inst30    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.441      ;
+; 0.406 ; inst30    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.518      ;
+; 0.406 ; inst30    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.518      ;
+; 0.409 ; inst30    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.521      ;
+; 0.474 ; inst30    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.583      ;
+; 0.485 ; inst27    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.594      ;
+; 0.541 ; inst15    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.774      ;
+; 0.547 ; inst27    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.656      ;
+; 0.579 ; inst11    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.675      ;
+; 0.581 ; inst12    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.677      ;
+; 0.585 ; inst12    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.681      ;
+; 0.612 ; inst91    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.845      ;
+; 0.624 ; inst30    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.733      ;
+; 0.639 ; inst10    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.872      ;
+; 0.648 ; inst13    ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.601      ;
+; 0.649 ; inst10    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.882      ;
+; 0.670 ; inst27    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.782      ;
+; 0.677 ; inst4     ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.910      ;
+; 0.683 ; inst4     ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.636      ;
+; 0.684 ; inst4     ; inst31  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.637      ;
+; 0.696 ; inst14    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.649      ;
+; 0.715 ; inst4     ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.948      ;
+; 0.716 ; inst10    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.669      ;
+; 0.727 ; inst27    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.839      ;
+; 0.728 ; inst27    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.028      ; 0.840      ;
+; 0.733 ; inst11    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.829      ;
+; 0.733 ; inst4     ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.686      ;
+; 0.734 ; inst11    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.830      ;
+; 0.737 ; inst12    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.012      ; 0.833      ;
+; 0.756 ; inst13    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.709      ;
+; 0.759 ; inst15    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 0.992      ;
+; 0.760 ; inst13    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.713      ;
+; 0.776 ; inst27    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.240     ; 0.620      ;
+; 0.778 ; inst27    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.025      ; 0.887      ;
+; 0.784 ; inst10    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.017      ;
+; 0.806 ; inst15    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.039      ;
+; 0.822 ; inst91    ; inst32  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.775      ;
+; 0.827 ; inst91    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.060      ;
+; 0.855 ; inst12    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 0.962      ;
+; 0.874 ; inst13    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.107      ;
+; 0.875 ; inst11    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 0.982      ;
+; 0.895 ; inst4     ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.848      ;
+; 0.898 ; inst91    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.131      ;
+; 0.931 ; inst10    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.152      ;
+; 0.944 ; inst4     ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.177      ;
+; 0.965 ; inst91    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.918      ;
+; 0.974 ; inst14    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 0.927      ;
+; 1.026 ; inst11    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 1.133      ;
+; 1.068 ; inst15    ; inst33  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.021      ;
+; 1.072 ; inst91    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.293      ;
+; 1.073 ; inst12    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 1.180      ;
+; 1.079 ; inst14    ; inst35  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.312      ;
+; 1.087 ; inst10    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.308      ;
+; 1.088 ; inst10    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.309      ;
+; 1.092 ; inst13    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.325      ;
+; 1.120 ; inst12    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 1.227      ;
+; 1.127 ; inst15    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.348      ;
+; 1.137 ; inst14    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.370      ;
+; 1.139 ; inst13    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.372      ;
+; 1.176 ; inst4     ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.397      ;
+; 1.204 ; inst11    ; inst36  ; CLK          ; CLK         ; 0.000        ; 0.023      ; 1.311      ;
+; 1.224 ; inst14    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.445      ;
+; 1.228 ; inst91    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.449      ;
+; 1.229 ; inst91    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.450      ;
+; 1.245 ; inst10    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.198      ;
+; 1.255 ; inst13    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.208      ;
+; 1.273 ; inst13    ; inst38  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.494      ;
+; 1.283 ; inst15    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.504      ;
+; 1.284 ; inst15    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.505      ;
+; 1.284 ; inst14    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.505      ;
+; 1.285 ; inst14    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.506      ;
+; 1.296 ; inst14    ; inst37  ; CLK          ; CLK         ; 0.000        ; 0.149      ; 1.529      ;
+; 1.332 ; inst4     ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.553      ;
+; 1.333 ; inst4     ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.554      ;
+; 1.333 ; inst13    ; inst39  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.554      ;
+; 1.334 ; inst13    ; inst40  ; CLK          ; CLK         ; 0.000        ; 0.137      ; 1.555      ;
+; 1.353 ; inst91    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.306      ;
+; 1.368 ; inst14    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.321      ;
+; 1.419 ; inst15    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.131     ; 1.372      ;
+; 1.615 ; inst11    ; inst34  ; CLK          ; CLK         ; 0.000        ; -0.256     ; 1.443      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'                                              ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target      ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK         ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst10      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst11      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst12      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst13      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst14      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst15      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst27      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst30      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst31      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst32      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst33      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst34      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst35      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst36      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst37      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst39      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst91      ;
+; -0.122 ; 0.062        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst11      ;
+; -0.122 ; 0.062        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst12      ;
+; -0.116 ; 0.068        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst27      ;
+; -0.116 ; 0.068        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst30      ;
+; -0.116 ; 0.068        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst35      ;
+; -0.116 ; 0.068        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst36      ;
+; -0.116 ; 0.068        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst37      ;
+; -0.110 ; 0.074        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst38      ;
+; -0.110 ; 0.074        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst39      ;
+; -0.110 ; 0.074        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst40      ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst10      ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst13      ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst14      ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst15      ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4       ;
+; -0.099 ; 0.085        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst91      ;
+; -0.081 ; 0.103        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst31      ;
+; -0.081 ; 0.103        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst32      ;
+; -0.081 ; 0.103        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst33      ;
+; -0.081 ; 0.103        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst34      ;
+; 0.058  ; 0.058        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst11|clk  ;
+; 0.058  ; 0.058        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst12|clk  ;
+; 0.064  ; 0.064        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst27|clk  ;
+; 0.064  ; 0.064        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst30|clk  ;
+; 0.064  ; 0.064        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst35|clk  ;
+; 0.064  ; 0.064        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst36|clk  ;
+; 0.064  ; 0.064        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst37|clk  ;
+; 0.070  ; 0.070        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst38|clk  ;
+; 0.070  ; 0.070        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst39|clk  ;
+; 0.070  ; 0.070        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst40|clk  ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst10|clk  ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst13|clk  ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst14|clk  ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst15|clk  ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk   ;
+; 0.081  ; 0.081        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst91|clk  ;
+; 0.098  ; 0.098        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst31|clk  ;
+; 0.098  ; 0.098        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst32|clk  ;
+; 0.098  ; 0.098        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst33|clk  ;
+; 0.098  ; 0.098        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst34|clk  ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i ;
+; 0.680  ; 0.896        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst31      ;
+; 0.680  ; 0.896        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst32      ;
+; 0.680  ; 0.896        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst33      ;
+; 0.680  ; 0.896        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst34      ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst10      ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst13      ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst14      ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst15      ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4       ;
+; 0.697  ; 0.913        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst91      ;
+; 0.708  ; 0.924        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst38      ;
+; 0.708  ; 0.924        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst39      ;
+; 0.708  ; 0.924        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst40      ;
+; 0.714  ; 0.930        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst27      ;
+; 0.714  ; 0.930        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst30      ;
+; 0.714  ; 0.930        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst35      ;
+; 0.714  ; 0.930        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst36      ;
+; 0.714  ; 0.930        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst37      ;
+; 0.720  ; 0.936        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst11      ;
+; 0.720  ; 0.936        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst12      ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o ;
+; 0.901  ; 0.901        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst31|clk  ;
+; 0.901  ; 0.901        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst32|clk  ;
+; 0.901  ; 0.901        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst33|clk  ;
+; 0.901  ; 0.901        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst34|clk  ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst10|clk  ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst13|clk  ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst14|clk  ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst15|clk  ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst4|clk   ;
+; 0.919  ; 0.919        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst91|clk  ;
+; 0.930  ; 0.930        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst38|clk  ;
+; 0.930  ; 0.930        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst39|clk  ;
+; 0.930  ; 0.930        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst40|clk  ;
+; 0.936  ; 0.936        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst27|clk  ;
+; 0.936  ; 0.936        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst30|clk  ;
++--------+--------------+----------------+------------------+-------+------------+-------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; A[*]      ; CLK        ; 1.157 ; 1.740 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; 0.967 ; 1.537 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; 0.860 ; 1.400 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; 1.157 ; 1.740 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; 0.966 ; 1.544 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; 0.780 ; 1.335 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; 1.204 ; 1.791 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; 1.204 ; 1.791 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; 1.028 ; 1.589 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; 1.102 ; 1.675 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; 0.703 ; 1.251 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; 0.904 ; 1.476 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; A[*]      ; CLK        ; -0.577 ; -1.120 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; -0.767 ; -1.324 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; -0.670 ; -1.205 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; -0.954 ; -1.531 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; -0.756 ; -1.321 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; -0.577 ; -1.120 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; -0.505 ; -1.042 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; -0.999 ; -1.580 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; -0.831 ; -1.386 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; -0.902 ; -1.469 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; -0.505 ; -1.042 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; -0.700 ; -1.259 ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 3.752 ; 3.959 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 2.980 ; 3.044 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 2.974 ; 3.030 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 3.752 ; 3.959 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 2.951 ; 3.022 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 3.222 ; 3.267 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 3.224 ; 3.269 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 3.066 ; 3.090 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 3.162 ; 3.193 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 3.312 ; 3.364 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 3.261 ; 3.313 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 2.899 ; 2.967 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 2.927 ; 2.987 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 2.921 ; 2.974 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 3.700 ; 3.905 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 2.899 ; 2.967 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 3.159 ; 3.201 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 3.161 ; 3.203 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 3.010 ; 3.031 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 3.102 ; 3.132 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 3.246 ; 3.296 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 3.198 ; 3.247 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+---------+-------+----------+---------+---------------------+
+; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -4.478  ; 0.332 ; N/A      ; N/A     ; -3.000              ;
+;  CLK             ; -4.478  ; 0.332 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -28.219 ; 0.0   ; 0.0      ; 0.0     ; -25.072             ;
+;  CLK             ; -28.219 ; 0.000 ; N/A      ; N/A     ; -25.072             ;
++------------------+---------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; A[*]      ; CLK        ; 2.043 ; 2.446 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; 1.665 ; 2.092 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; 1.505 ; 1.912 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; 2.043 ; 2.446 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; 1.631 ; 2.019 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; 1.305 ; 1.702 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; 2.083 ; 2.531 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; 2.083 ; 2.531 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; 1.777 ; 2.196 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; 1.951 ; 2.345 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; 1.172 ; 1.577 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; 1.511 ; 1.911 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; A[*]      ; CLK        ; -0.577 ; -1.023 ; Rise       ; CLK             ;
+;  A[0]     ; CLK        ; -0.767 ; -1.324 ; Rise       ; CLK             ;
+;  A[1]     ; CLK        ; -0.670 ; -1.205 ; Rise       ; CLK             ;
+;  A[2]     ; CLK        ; -0.954 ; -1.531 ; Rise       ; CLK             ;
+;  A[3]     ; CLK        ; -0.756 ; -1.314 ; Rise       ; CLK             ;
+;  A[4]     ; CLK        ; -0.577 ; -1.023 ; Rise       ; CLK             ;
+; B[*]      ; CLK        ; -0.505 ; -0.920 ; Rise       ; CLK             ;
+;  B[0]     ; CLK        ; -0.999 ; -1.580 ; Rise       ; CLK             ;
+;  B[1]     ; CLK        ; -0.831 ; -1.386 ; Rise       ; CLK             ;
+;  B[2]     ; CLK        ; -0.902 ; -1.469 ; Rise       ; CLK             ;
+;  B[3]     ; CLK        ; -0.505 ; -0.920 ; Rise       ; CLK             ;
+;  B[4]     ; CLK        ; -0.700 ; -1.209 ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Clock to Output Times                                                  ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 6.123 ; 6.296 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 4.974 ; 5.049 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 4.959 ; 5.024 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 6.123 ; 6.296 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 4.948 ; 5.015 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 5.392 ; 5.450 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 5.401 ; 5.434 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 5.127 ; 5.161 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 5.317 ; 5.338 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 5.587 ; 5.610 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 5.499 ; 5.513 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                          ;
++------------+------------+-------+-------+------------+-----------------+
+; Data Port  ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++------------+------------+-------+-------+------------+-----------------+
+; Output[*]  ; CLK        ; 2.899 ; 2.967 ; Rise       ; CLK             ;
+;  Output[0] ; CLK        ; 2.927 ; 2.987 ; Rise       ; CLK             ;
+;  Output[1] ; CLK        ; 2.921 ; 2.974 ; Rise       ; CLK             ;
+;  Output[2] ; CLK        ; 3.700 ; 3.905 ; Rise       ; CLK             ;
+;  Output[3] ; CLK        ; 2.899 ; 2.967 ; Rise       ; CLK             ;
+;  Output[4] ; CLK        ; 3.159 ; 3.201 ; Rise       ; CLK             ;
+;  Output[5] ; CLK        ; 3.161 ; 3.203 ; Rise       ; CLK             ;
+;  Output[6] ; CLK        ; 3.010 ; 3.031 ; Rise       ; CLK             ;
+;  Output[7] ; CLK        ; 3.102 ; 3.132 ; Rise       ; CLK             ;
+;  Output[8] ; CLK        ; 3.246 ; 3.296 ; Rise       ; CLK             ;
+;  Output[9] ; CLK        ; 3.198 ; 3.247 ; Rise       ; CLK             ;
++------------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Output[9]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[8]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[7]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[6]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[5]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[4]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[3]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[2]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[1]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Output[0]     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; CLK                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; B[4]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; A[4]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; A[2]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; A[3]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; B[3]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; B[1]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; B[0]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; A[1]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; A[0]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; B[2]                    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Output[9]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[8]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[7]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[6]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[5]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[4]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[3]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[2]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; Output[1]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; Output[0]     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 3621     ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 3621     ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 10    ; 10   ;
+; Unconstrained Output Ports      ; 10    ; 10   ;
+; Unconstrained Output Port Paths ; 10    ; 10   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:10:44 2016
+Info: Command: quartus_sta registered_multiply -c registered_multiply
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'registered_multiply.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLK CLK
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -4.478
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -4.478             -28.219 CLK 
+Info (332146): Worst-case hold slack is 0.617
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.617               0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -23.000 CLK 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.877
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.877             -24.107 CLK 
+Info (332146): Worst-case hold slack is 0.550
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.550               0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -23.000 CLK 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.060
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.060             -11.543 CLK 
+Info (332146): Worst-case hold slack is 0.332
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.332               0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -25.072 CLK 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 505 megabytes
+    Info: Processing ended: Fri Feb 19 16:10:46 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/registered_multiply/output_files/registered_multiply.sta.summary b/registered_multiply/output_files/registered_multiply.sta.summary
new file mode 100644
index 0000000..feadc88
--- /dev/null
+++ b/registered_multiply/output_files/registered_multiply.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'CLK'
+Slack : -4.478
+TNS   : -28.219
+
+Type  : Slow 1200mV 85C Model Hold 'CLK'
+Slack : 0.617
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLK'
+Slack : -3.877
+TNS   : -24.107
+
+Type  : Slow 1200mV 0C Model Hold 'CLK'
+Slack : 0.550
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLK'
+Slack : -2.060
+TNS   : -11.543
+
+Type  : Fast 1200mV 0C Model Hold 'CLK'
+Slack : 0.332
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -25.072
+
+------------------------------------------------------------
diff --git a/registered_multiply/registered_multiply.qpf b/registered_multiply/registered_multiply.qpf
new file mode 100644
index 0000000..7c1b077
--- /dev/null
+++ b/registered_multiply/registered_multiply.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 15:28:35  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "15:28:35  February 19, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "registered_multiply"
diff --git a/registered_multiply/registered_multiply.qsf b/registered_multiply/registered_multiply.qsf
new file mode 100644
index 0000000..74a50b8
--- /dev/null
+++ b/registered_multiply/registered_multiply.qsf
@@ -0,0 +1,81 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 15:28:35  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		registered_multiply_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY registered_multiply
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:28:35  FEBRUARY 19, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name BDF_FILE ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE ../comb_multiply/registered_multiply.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_G5 -to A[4]
+set_location_assignment PIN_G4 -to A[3]
+set_location_assignment PIN_H6 -to A[2]
+set_location_assignment PIN_H5 -to A[1]
+set_location_assignment PIN_J6 -to A[0]
+set_location_assignment PIN_D2 -to B[4]
+set_location_assignment PIN_E4 -to B[3]
+set_location_assignment PIN_E3 -to B[2]
+set_location_assignment PIN_H7 -to B[1]
+set_location_assignment PIN_J7 -to B[0]
+set_location_assignment PIN_F1 -to CLK
+set_location_assignment PIN_B1 -to Output[9]
+set_location_assignment PIN_B2 -to Output[8]
+set_location_assignment PIN_C2 -to Output[7]
+set_location_assignment PIN_C1 -to Output[6]
+set_location_assignment PIN_E1 -to Output[5]
+set_location_assignment PIN_F2 -to Output[4]
+set_location_assignment PIN_H1 -to Output[3]
+set_location_assignment PIN_J3 -to Output[2]
+set_location_assignment PIN_J2 -to Output[1]
+set_location_assignment PIN_J1 -to Output[0]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name CDF_FILE output_files/Chain3.cdf
\ No newline at end of file
diff --git a/registered_multiply/registered_multiply.qws b/registered_multiply/registered_multiply.qws
new file mode 100644
index 0000000..e1dbad3
--- /dev/null
+++ b/registered_multiply/registered_multiply.qws
diff --git a/registered_multiply/simulation/modelsim/registered_multiply.sft b/registered_multiply/simulation/modelsim/registered_multiply.sft
new file mode 100644
index 0000000..61c462d
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {registered_multiply_6_1200mv_85c_slow.vho registered_multiply_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {registered_multiply_6_1200mv_0c_slow.vho registered_multiply_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {registered_multiply_min_1200mv_0c_fast.vho registered_multiply_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/registered_multiply/simulation/modelsim/registered_multiply.vho b/registered_multiply/simulation/modelsim/registered_multiply.vho
new file mode 100644
index 0000000..19f2c44
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply.vho
@@ -0,0 +1,1670 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:10:48"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	registered_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	B : IN std_logic_vector(4 DOWNTO 0);
+	A : IN std_logic_vector(4 DOWNTO 0)
+	);
+END registered_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF registered_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_B : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_A : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \B[4]~input_o\ : std_logic;
+SIGNAL \inst30~feeder_combout\ : std_logic;
+SIGNAL \inst30~q\ : std_logic;
+SIGNAL \A[4]~input_o\ : std_logic;
+SIGNAL \inst12~feeder_combout\ : std_logic;
+SIGNAL \inst12~q\ : std_logic;
+SIGNAL \B[3]~input_o\ : std_logic;
+SIGNAL \inst27~feeder_combout\ : std_logic;
+SIGNAL \inst27~q\ : std_logic;
+SIGNAL \B[2]~input_o\ : std_logic;
+SIGNAL \inst15~q\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \B[1]~input_o\ : std_logic;
+SIGNAL \inst14~q\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \B[0]~input_o\ : std_logic;
+SIGNAL \inst13~q\ : std_logic;
+SIGNAL \A[3]~input_o\ : std_logic;
+SIGNAL \inst11~feeder_combout\ : std_logic;
+SIGNAL \inst11~q\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \A[2]~input_o\ : std_logic;
+SIGNAL \inst10~q\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \A[1]~input_o\ : std_logic;
+SIGNAL \inst91~q\ : std_logic;
+SIGNAL \A[0]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~1_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst|inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst18~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~1_combout\ : std_logic;
+SIGNAL \inst1|inst19~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~0_combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~1_combout\ : std_logic;
+SIGNAL \inst3|inst22~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst12|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst40~q\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst39~q\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst38~q\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst37~q\ : std_logic;
+SIGNAL \inst3|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst36~q\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst35~q\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst34~q\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst33~q\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst32~q\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+SIGNAL \inst31~q\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_CLK <= CLK;
+ww_B <= B;
+ww_A <= A;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst40~q\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst39~q\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst38~q\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst37~q\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst36~q\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst35~q\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst34~q\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst33~q\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~q\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst31~q\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\B[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(4),
+	o => \B[4]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N14
+\inst30~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~feeder_combout\ = \B[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[4]~input_o\,
+	combout => \inst30~feeder_combout\);
+
+-- Location: FF_X1_Y26_N15
+inst30 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst30~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst30~q\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\A[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(4),
+	o => \A[4]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N12
+\inst12~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst12~feeder_combout\ = \A[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[4]~input_o\,
+	combout => \inst12~feeder_combout\);
+
+-- Location: FF_X2_Y27_N13
+inst12 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst12~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst12~q\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\B[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(3),
+	o => \B[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N0
+\inst27~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst27~feeder_combout\ = \B[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[3]~input_o\,
+	combout => \inst27~feeder_combout\);
+
+-- Location: FF_X1_Y26_N1
+inst27 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst27~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst27~q\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\B[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(2),
+	o => \B[2]~input_o\);
+
+-- Location: FF_X1_Y27_N21
+inst15 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst15~q\);
+
+-- Location: LCCOMB_X2_Y26_N26
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\inst15~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datad => \inst12~q\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\B[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(1),
+	o => \B[1]~input_o\);
+
+-- Location: FF_X1_Y27_N11
+inst14 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst14~q\);
+
+-- Location: LCCOMB_X2_Y26_N20
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\inst14~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst12~q\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\B[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(0),
+	o => \B[0]~input_o\);
+
+-- Location: FF_X1_Y27_N13
+inst13 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[0]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst13~q\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\A[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(3),
+	o => \A[3]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N14
+\inst11~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst11~feeder_combout\ = \A[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[3]~input_o\,
+	combout => \inst11~feeder_combout\);
+
+-- Location: FF_X2_Y27_N15
+inst11 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst11~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst11~q\);
+
+-- Location: LCCOMB_X2_Y27_N20
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\inst11~q\ & \inst14~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst11~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst20~combout\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\A[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(2),
+	o => \A[2]~input_o\);
+
+-- Location: FF_X1_Y27_N25
+inst10 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst10~q\);
+
+-- Location: LCCOMB_X1_Y27_N26
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\inst14~q\ & \inst10~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst10~q\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\A[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(1),
+	o => \A[1]~input_o\);
+
+-- Location: FF_X1_Y27_N9
+inst91 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst91~q\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\A[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(0),
+	o => \A[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y27_N18
+\inst4~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \A[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[0]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X1_Y27_N19
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: LCCOMB_X1_Y27_N20
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst10~q\) # (\inst4~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst10~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N14
+\inst|inst10|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~1_combout\ = (\inst13~q\ & (\inst91~q\ & (\inst14~q\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst10|inst3~1_combout\);
+
+-- Location: LCCOMB_X2_Y27_N18
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~1_combout\) # ((\inst13~q\ & \inst11~q\)))) # (!\inst|inst19~combout\ & (\inst13~q\ & (\inst11~q\ & \inst|inst10|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~1_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y27_N0
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst20~combout\ & ((\inst|inst11|inst3~0_combout\) # ((\inst13~q\ & \inst12~q\)))) # (!\inst|inst20~combout\ & (\inst13~q\ & (\inst12~q\ & \inst|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst12~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N8
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\inst11~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst11~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X2_Y27_N30
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst20~combout\ $ (\inst|inst11|inst3~0_combout\ $ (((\inst12~q\ & \inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst12~q\,
+	datab => \inst13~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N22
+\inst|inst10|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~0_combout\ = (\inst91~q\ & (\inst14~q\ & ((!\inst4~q\) # (!\inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N10
+\inst1|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst18~combout\ = (\inst4~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst18~combout\);
+
+-- Location: LCCOMB_X1_Y27_N28
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\inst1|inst18~combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst18~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y27_N0
+\inst1|inst11|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~0_combout\ = (\inst4~q\ & (\inst91~q\ & \inst15~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datac => \inst91~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst11|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N4
+\inst1|inst11|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~1_combout\ = (\inst1|inst11|inst5~0_combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst11|inst5~0_combout\,
+	combout => \inst1|inst11|inst5~1_combout\);
+
+-- Location: LCCOMB_X1_Y27_N12
+\inst1|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst19~combout\ = (\inst15~q\ & \inst91~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst91~q\,
+	combout => \inst1|inst19~combout\);
+
+-- Location: LCCOMB_X1_Y27_N2
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst10|inst3~1_combout\ $ (\inst|inst19~combout\ $ (((\inst13~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst10|inst3~1_combout\,
+	datad => \inst|inst19~combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N30
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\inst1|inst11|inst5~1_combout\) # ((\inst|inst11|inst2~combout\ & ((\inst1|inst10|inst6~combout\) # (\inst1|inst19~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst10|inst6~combout\,
+	datab => \inst1|inst11|inst5~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N2
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~0_combout\) # ((\inst15~q\ & \inst10~q\)))) # (!\inst|inst12|inst2~combout\ & (\inst15~q\ & (\inst10~q\ & \inst1|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst1|inst11|inst3~0_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N0
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst21~combout\ & ((\inst1|inst12|inst3~0_combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst21~combout\ & (\inst1|inst12|inst3~0_combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst21~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N24
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst22~combout\ & ((\inst1|inst13|inst3~0_combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst22~combout\ & (\inst|inst21~combout\ & (\inst|inst12|inst3~0_combout\ & 
+-- \inst1|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N4
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst22~combout\ $ (\inst1|inst13|inst3~0_combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N24
+\inst|inst11|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~0_combout\ = (\inst13~q\ & (\inst11~q\ $ (((\inst10~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst10~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst10~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N16
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst|inst11|inst2~0_combout\ $ (\inst|inst10|inst3~1_combout\ $ (\inst1|inst19~combout\ $ (\inst1|inst10|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst2~0_combout\,
+	datab => \inst|inst10|inst3~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst1|inst10|inst6~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N6
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\inst4~q\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N12
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst1|inst11|inst3~0_combout\ $ (\inst|inst12|inst2~combout\ $ (((\inst10~q\ & \inst15~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst11|inst3~0_combout\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst15~q\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N26
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\inst27~q\ & ((\inst91~q\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\inst91~q\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y26_N18
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst1|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N28
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\inst10~q\ & \inst27~q\)))) # (!\inst2|inst12|inst3~1_combout\ & (\inst10~q\ & (\inst27~q\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst1|inst14|inst2~combout\ & ((\inst2|inst13|inst3~0_combout\) # ((\inst27~q\ & \inst11~q\)))) # (!\inst1|inst14|inst2~combout\ & (\inst27~q\ & (\inst11~q\ & \inst2|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N14
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\inst27~q\ & \inst12~q\)))) # (!\inst1|inst14|inst3~0_combout\ & (\inst27~q\ & (\inst12~q\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N10
+\inst3|inst13|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~0_combout\ = (\inst30~q\ & (\inst4~q\ & \inst91~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst30~q\,
+	datac => \inst4~q\,
+	datad => \inst91~q\,
+	combout => \inst3|inst13|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N8
+\inst2|inst12|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~0_combout\ = (\inst27~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst1|inst11|inst2~combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N16
+\inst3|inst13|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~1_combout\ = (\inst3|inst13|inst5~0_combout\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~0_combout\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst13|inst5~1_combout\);
+
+-- Location: LCCOMB_X2_Y26_N22
+\inst3|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst22~combout\ = (\inst10~q\ & \inst30~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst10~q\,
+	datad => \inst30~q\,
+	combout => \inst3|inst22~combout\);
+
+-- Location: LCCOMB_X2_Y26_N30
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst1|inst14|inst2~combout\ $ (\inst2|inst13|inst3~0_combout\ $ (((\inst27~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N30
+\inst3|inst12|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst6~combout\ = (\inst4~q\ & (\inst30~q\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datab => \inst30~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y26_N2
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\inst10~q\ & \inst27~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N24
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst13|inst2~combout\ & ((\inst3|inst12|inst6~combout\) # ((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N8
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst3|inst22~combout\ & ((\inst3|inst13|inst5~1_combout\) # ((\inst2|inst14|inst2~combout\) # (\inst3|inst13|inst3~0_combout\)))) # (!\inst3|inst22~combout\ & (\inst2|inst14|inst2~combout\ & 
+-- ((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~1_combout\,
+	datab => \inst3|inst22~combout\,
+	datac => \inst2|inst14|inst2~combout\,
+	datad => \inst3|inst13|inst3~0_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N18
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\inst27~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X2_Y26_N12
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst3|inst14|inst3~0_combout\ & ((\inst2|inst15|inst2~combout\) # ((\inst30~q\ & \inst11~q\)))) # (!\inst3|inst14|inst3~0_combout\ & (\inst30~q\ & (\inst11~q\ & \inst2|inst15|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N28
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst2|inst15|inst3~0_combout\ & ((\inst3|inst15|inst3~0_combout\) # ((\inst30~q\ & \inst12~q\)))) # (!\inst2|inst15|inst3~0_combout\ & (\inst30~q\ & (\inst12~q\ & \inst3|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: FF_X2_Y26_N29
+inst40 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst3~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst40~q\);
+
+-- Location: LCCOMB_X2_Y26_N10
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst2|inst15|inst3~0_combout\ $ (\inst3|inst15|inst3~0_combout\ $ (((\inst30~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: FF_X2_Y26_N11
+inst39 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst39~q\);
+
+-- Location: LCCOMB_X2_Y26_N16
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst3|inst14|inst3~0_combout\ $ (\inst2|inst15|inst2~combout\ $ (((\inst30~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: FF_X2_Y26_N17
+inst38 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst15|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst38~q\);
+
+-- Location: LCCOMB_X1_Y26_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst3|inst22~combout\ $ (\inst2|inst14|inst2~combout\ $ (((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100101010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst22~combout\,
+	datab => \inst3|inst13|inst5~1_combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \inst2|inst14|inst2~combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: FF_X1_Y26_N21
+inst37 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst14|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst37~q\);
+
+-- Location: LCCOMB_X1_Y26_N6
+\inst3|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~combout\ = \inst3|inst12|inst6~combout\ $ (\inst2|inst13|inst2~combout\ $ (((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst2~combout\);
+
+-- Location: FF_X1_Y26_N7
+inst36 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst13|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst36~q\);
+
+-- Location: LCCOMB_X1_Y26_N4
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\ $ (((\inst30~q\ & \inst4~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst4~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: FF_X1_Y26_N5
+inst35 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst12|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst35~q\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\inst4~q\ & \inst27~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datac => \inst27~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: FF_X1_Y23_N29
+inst34 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst2|inst11|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst34~q\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst1|inst18~combout\ $ (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst1|inst18~combout\,
+	datad => \inst|inst10|inst2~0_combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: FF_X1_Y23_N27
+inst33 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst1|inst10|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst33~q\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\inst13~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst4~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst4~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: FF_X1_Y23_N5
+inst32 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst|inst9|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst32~q\);
+
+-- Location: LCCOMB_X1_Y23_N10
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\inst4~q\ & \inst13~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst13~q\,
+	combout => \inst5~combout\);
+
+-- Location: FF_X1_Y23_N11
+inst31 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst5~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst31~q\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_slow.vho b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..19f2c44
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_slow.vho
@@ -0,0 +1,1670 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:10:48"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	registered_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	B : IN std_logic_vector(4 DOWNTO 0);
+	A : IN std_logic_vector(4 DOWNTO 0)
+	);
+END registered_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF registered_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_B : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_A : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \B[4]~input_o\ : std_logic;
+SIGNAL \inst30~feeder_combout\ : std_logic;
+SIGNAL \inst30~q\ : std_logic;
+SIGNAL \A[4]~input_o\ : std_logic;
+SIGNAL \inst12~feeder_combout\ : std_logic;
+SIGNAL \inst12~q\ : std_logic;
+SIGNAL \B[3]~input_o\ : std_logic;
+SIGNAL \inst27~feeder_combout\ : std_logic;
+SIGNAL \inst27~q\ : std_logic;
+SIGNAL \B[2]~input_o\ : std_logic;
+SIGNAL \inst15~q\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \B[1]~input_o\ : std_logic;
+SIGNAL \inst14~q\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \B[0]~input_o\ : std_logic;
+SIGNAL \inst13~q\ : std_logic;
+SIGNAL \A[3]~input_o\ : std_logic;
+SIGNAL \inst11~feeder_combout\ : std_logic;
+SIGNAL \inst11~q\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \A[2]~input_o\ : std_logic;
+SIGNAL \inst10~q\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \A[1]~input_o\ : std_logic;
+SIGNAL \inst91~q\ : std_logic;
+SIGNAL \A[0]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~1_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst|inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst18~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~1_combout\ : std_logic;
+SIGNAL \inst1|inst19~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~0_combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~1_combout\ : std_logic;
+SIGNAL \inst3|inst22~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst12|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst40~q\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst39~q\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst38~q\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst37~q\ : std_logic;
+SIGNAL \inst3|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst36~q\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst35~q\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst34~q\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst33~q\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst32~q\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+SIGNAL \inst31~q\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_CLK <= CLK;
+ww_B <= B;
+ww_A <= A;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst40~q\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst39~q\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst38~q\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst37~q\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst36~q\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst35~q\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst34~q\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst33~q\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~q\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst31~q\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\B[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(4),
+	o => \B[4]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N14
+\inst30~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~feeder_combout\ = \B[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[4]~input_o\,
+	combout => \inst30~feeder_combout\);
+
+-- Location: FF_X1_Y26_N15
+inst30 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst30~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst30~q\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\A[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(4),
+	o => \A[4]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N12
+\inst12~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst12~feeder_combout\ = \A[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[4]~input_o\,
+	combout => \inst12~feeder_combout\);
+
+-- Location: FF_X2_Y27_N13
+inst12 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst12~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst12~q\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\B[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(3),
+	o => \B[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N0
+\inst27~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst27~feeder_combout\ = \B[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[3]~input_o\,
+	combout => \inst27~feeder_combout\);
+
+-- Location: FF_X1_Y26_N1
+inst27 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst27~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst27~q\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\B[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(2),
+	o => \B[2]~input_o\);
+
+-- Location: FF_X1_Y27_N21
+inst15 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst15~q\);
+
+-- Location: LCCOMB_X2_Y26_N26
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\inst15~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datad => \inst12~q\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\B[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(1),
+	o => \B[1]~input_o\);
+
+-- Location: FF_X1_Y27_N11
+inst14 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst14~q\);
+
+-- Location: LCCOMB_X2_Y26_N20
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\inst14~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst12~q\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\B[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(0),
+	o => \B[0]~input_o\);
+
+-- Location: FF_X1_Y27_N13
+inst13 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[0]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst13~q\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\A[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(3),
+	o => \A[3]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N14
+\inst11~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst11~feeder_combout\ = \A[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[3]~input_o\,
+	combout => \inst11~feeder_combout\);
+
+-- Location: FF_X2_Y27_N15
+inst11 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst11~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst11~q\);
+
+-- Location: LCCOMB_X2_Y27_N20
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\inst11~q\ & \inst14~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst11~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst20~combout\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\A[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(2),
+	o => \A[2]~input_o\);
+
+-- Location: FF_X1_Y27_N25
+inst10 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst10~q\);
+
+-- Location: LCCOMB_X1_Y27_N26
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\inst14~q\ & \inst10~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst10~q\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\A[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(1),
+	o => \A[1]~input_o\);
+
+-- Location: FF_X1_Y27_N9
+inst91 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst91~q\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\A[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(0),
+	o => \A[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y27_N18
+\inst4~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \A[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[0]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X1_Y27_N19
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: LCCOMB_X1_Y27_N20
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst10~q\) # (\inst4~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst10~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N14
+\inst|inst10|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~1_combout\ = (\inst13~q\ & (\inst91~q\ & (\inst14~q\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst10|inst3~1_combout\);
+
+-- Location: LCCOMB_X2_Y27_N18
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~1_combout\) # ((\inst13~q\ & \inst11~q\)))) # (!\inst|inst19~combout\ & (\inst13~q\ & (\inst11~q\ & \inst|inst10|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~1_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y27_N0
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst20~combout\ & ((\inst|inst11|inst3~0_combout\) # ((\inst13~q\ & \inst12~q\)))) # (!\inst|inst20~combout\ & (\inst13~q\ & (\inst12~q\ & \inst|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst12~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N8
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\inst11~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst11~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X2_Y27_N30
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst20~combout\ $ (\inst|inst11|inst3~0_combout\ $ (((\inst12~q\ & \inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst12~q\,
+	datab => \inst13~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N22
+\inst|inst10|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~0_combout\ = (\inst91~q\ & (\inst14~q\ & ((!\inst4~q\) # (!\inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N10
+\inst1|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst18~combout\ = (\inst4~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst18~combout\);
+
+-- Location: LCCOMB_X1_Y27_N28
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\inst1|inst18~combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst18~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y27_N0
+\inst1|inst11|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~0_combout\ = (\inst4~q\ & (\inst91~q\ & \inst15~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datac => \inst91~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst11|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N4
+\inst1|inst11|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~1_combout\ = (\inst1|inst11|inst5~0_combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst11|inst5~0_combout\,
+	combout => \inst1|inst11|inst5~1_combout\);
+
+-- Location: LCCOMB_X1_Y27_N12
+\inst1|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst19~combout\ = (\inst15~q\ & \inst91~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst91~q\,
+	combout => \inst1|inst19~combout\);
+
+-- Location: LCCOMB_X1_Y27_N2
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst10|inst3~1_combout\ $ (\inst|inst19~combout\ $ (((\inst13~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst10|inst3~1_combout\,
+	datad => \inst|inst19~combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N30
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\inst1|inst11|inst5~1_combout\) # ((\inst|inst11|inst2~combout\ & ((\inst1|inst10|inst6~combout\) # (\inst1|inst19~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst10|inst6~combout\,
+	datab => \inst1|inst11|inst5~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N2
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~0_combout\) # ((\inst15~q\ & \inst10~q\)))) # (!\inst|inst12|inst2~combout\ & (\inst15~q\ & (\inst10~q\ & \inst1|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst1|inst11|inst3~0_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N0
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst21~combout\ & ((\inst1|inst12|inst3~0_combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst21~combout\ & (\inst1|inst12|inst3~0_combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst21~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N24
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst22~combout\ & ((\inst1|inst13|inst3~0_combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst22~combout\ & (\inst|inst21~combout\ & (\inst|inst12|inst3~0_combout\ & 
+-- \inst1|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N4
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst22~combout\ $ (\inst1|inst13|inst3~0_combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N24
+\inst|inst11|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~0_combout\ = (\inst13~q\ & (\inst11~q\ $ (((\inst10~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst10~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst10~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N16
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst|inst11|inst2~0_combout\ $ (\inst|inst10|inst3~1_combout\ $ (\inst1|inst19~combout\ $ (\inst1|inst10|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst2~0_combout\,
+	datab => \inst|inst10|inst3~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst1|inst10|inst6~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N6
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\inst4~q\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N12
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst1|inst11|inst3~0_combout\ $ (\inst|inst12|inst2~combout\ $ (((\inst10~q\ & \inst15~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst11|inst3~0_combout\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst15~q\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N26
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\inst27~q\ & ((\inst91~q\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\inst91~q\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y26_N18
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst1|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N28
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\inst10~q\ & \inst27~q\)))) # (!\inst2|inst12|inst3~1_combout\ & (\inst10~q\ & (\inst27~q\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst1|inst14|inst2~combout\ & ((\inst2|inst13|inst3~0_combout\) # ((\inst27~q\ & \inst11~q\)))) # (!\inst1|inst14|inst2~combout\ & (\inst27~q\ & (\inst11~q\ & \inst2|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N14
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\inst27~q\ & \inst12~q\)))) # (!\inst1|inst14|inst3~0_combout\ & (\inst27~q\ & (\inst12~q\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N10
+\inst3|inst13|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~0_combout\ = (\inst30~q\ & (\inst4~q\ & \inst91~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst30~q\,
+	datac => \inst4~q\,
+	datad => \inst91~q\,
+	combout => \inst3|inst13|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N8
+\inst2|inst12|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~0_combout\ = (\inst27~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst1|inst11|inst2~combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N16
+\inst3|inst13|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~1_combout\ = (\inst3|inst13|inst5~0_combout\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~0_combout\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst13|inst5~1_combout\);
+
+-- Location: LCCOMB_X2_Y26_N22
+\inst3|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst22~combout\ = (\inst10~q\ & \inst30~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst10~q\,
+	datad => \inst30~q\,
+	combout => \inst3|inst22~combout\);
+
+-- Location: LCCOMB_X2_Y26_N30
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst1|inst14|inst2~combout\ $ (\inst2|inst13|inst3~0_combout\ $ (((\inst27~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N30
+\inst3|inst12|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst6~combout\ = (\inst4~q\ & (\inst30~q\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datab => \inst30~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y26_N2
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\inst10~q\ & \inst27~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N24
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst13|inst2~combout\ & ((\inst3|inst12|inst6~combout\) # ((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N8
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst3|inst22~combout\ & ((\inst3|inst13|inst5~1_combout\) # ((\inst2|inst14|inst2~combout\) # (\inst3|inst13|inst3~0_combout\)))) # (!\inst3|inst22~combout\ & (\inst2|inst14|inst2~combout\ & 
+-- ((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~1_combout\,
+	datab => \inst3|inst22~combout\,
+	datac => \inst2|inst14|inst2~combout\,
+	datad => \inst3|inst13|inst3~0_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N18
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\inst27~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X2_Y26_N12
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst3|inst14|inst3~0_combout\ & ((\inst2|inst15|inst2~combout\) # ((\inst30~q\ & \inst11~q\)))) # (!\inst3|inst14|inst3~0_combout\ & (\inst30~q\ & (\inst11~q\ & \inst2|inst15|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N28
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst2|inst15|inst3~0_combout\ & ((\inst3|inst15|inst3~0_combout\) # ((\inst30~q\ & \inst12~q\)))) # (!\inst2|inst15|inst3~0_combout\ & (\inst30~q\ & (\inst12~q\ & \inst3|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: FF_X2_Y26_N29
+inst40 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst3~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst40~q\);
+
+-- Location: LCCOMB_X2_Y26_N10
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst2|inst15|inst3~0_combout\ $ (\inst3|inst15|inst3~0_combout\ $ (((\inst30~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: FF_X2_Y26_N11
+inst39 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst39~q\);
+
+-- Location: LCCOMB_X2_Y26_N16
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst3|inst14|inst3~0_combout\ $ (\inst2|inst15|inst2~combout\ $ (((\inst30~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: FF_X2_Y26_N17
+inst38 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst15|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst38~q\);
+
+-- Location: LCCOMB_X1_Y26_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst3|inst22~combout\ $ (\inst2|inst14|inst2~combout\ $ (((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100101010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst22~combout\,
+	datab => \inst3|inst13|inst5~1_combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \inst2|inst14|inst2~combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: FF_X1_Y26_N21
+inst37 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst14|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst37~q\);
+
+-- Location: LCCOMB_X1_Y26_N6
+\inst3|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~combout\ = \inst3|inst12|inst6~combout\ $ (\inst2|inst13|inst2~combout\ $ (((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst2~combout\);
+
+-- Location: FF_X1_Y26_N7
+inst36 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst13|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst36~q\);
+
+-- Location: LCCOMB_X1_Y26_N4
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\ $ (((\inst30~q\ & \inst4~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst4~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: FF_X1_Y26_N5
+inst35 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst12|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst35~q\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\inst4~q\ & \inst27~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datac => \inst27~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: FF_X1_Y23_N29
+inst34 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst2|inst11|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst34~q\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst1|inst18~combout\ $ (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst1|inst18~combout\,
+	datad => \inst|inst10|inst2~0_combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: FF_X1_Y23_N27
+inst33 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst1|inst10|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst33~q\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\inst13~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst4~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst4~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: FF_X1_Y23_N5
+inst32 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst|inst9|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst32~q\);
+
+-- Location: LCCOMB_X1_Y23_N10
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\inst4~q\ & \inst13~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst13~q\,
+	combout => \inst5~combout\);
+
+-- Location: FF_X1_Y23_N11
+inst31 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst5~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst31~q\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_vhd_slow.sdo b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..aac6195
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,1347 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "registered_multiply")
+  (DATE "02/19/2016 16:10:48")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (687:687:687) (683:683:683))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (773:773:773) (763:763:763))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (524:524:524) (524:524:524))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (333:333:333) (362:362:362))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (593:593:593) (627:627:627))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (587:587:587) (626:626:626))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (636:636:636) (691:691:691))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (613:613:613) (660:660:660))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (656:656:656) (709:709:709))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (669:669:669) (729:729:729))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2375:2375:2375) (2557:2557:2557))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst30)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1427:1427:1427) (1406:1406:1406))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst12\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2289:2289:2289) (2465:2465:2465))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst12)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1464:1464:1464))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst27\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2104:2104:2104) (2297:2297:2297))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst27)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1427:1427:1427) (1406:1406:1406))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst15)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT asdata (2820:2820:2820) (2979:2979:2979))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1011:1011:1011) (1003:1003:1003))
+        (PORT datad (649:649:649) (686:686:686))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst14)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT asdata (2660:2660:2660) (2863:2863:2863))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (844:844:844) (860:860:860))
+        (PORT datad (650:650:650) (690:690:690))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst13)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT asdata (2944:2944:2944) (3140:3140:3140))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst11\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2580:2580:2580) (2757:2757:2757))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst11)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1464:1464:1464))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (237:237:237) (310:310:310))
+        (PORT datad (538:538:538) (560:560:560))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst10)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT asdata (2910:2910:2910) (3086:3086:3086))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (359:359:359) (405:405:405))
+        (PORT datad (233:233:233) (301:301:301))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst91)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT asdata (2412:2412:2412) (2599:2599:2599))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2373:2373:2373) (2572:2572:2572))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1219:1219:1219) (1225:1225:1225))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (258:258:258) (338:338:338))
+        (PORT datad (235:235:235) (303:303:303))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (278:278:278) (374:374:374))
+        (PORT datab (258:258:258) (338:338:338))
+        (PORT datac (354:354:354) (403:403:403))
+        (PORT datad (159:159:159) (181:181:181))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (607:607:607) (638:638:638))
+        (PORT datab (264:264:264) (337:337:337))
+        (PORT datac (318:318:318) (329:329:329))
+        (PORT datad (320:320:320) (314:314:314))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (608:608:608) (635:635:635))
+        (PORT datab (539:539:539) (557:557:557))
+        (PORT datac (301:301:301) (307:307:307))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (443:443:443) (477:477:477))
+        (PORT datad (533:533:533) (551:551:551))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (315:315:315))
+        (PORT datab (571:571:571) (601:601:601))
+        (PORT datac (299:299:299) (304:304:304))
+        (PORT datad (166:166:166) (188:188:188))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (276:276:276) (370:370:370))
+        (PORT datab (257:257:257) (336:336:336))
+        (PORT datac (358:358:358) (403:403:403))
+        (PORT datad (233:233:233) (301:301:301))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (260:260:260) (338:338:338))
+        (PORT datad (530:530:530) (553:553:553))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (377:377:377))
+        (PORT datab (258:258:258) (335:335:335))
+        (PORT datac (181:181:181) (214:214:214))
+        (PORT datad (179:179:179) (201:201:201))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (260:260:260) (338:338:338))
+        (PORT datac (229:229:229) (308:308:308))
+        (PORT datad (533:533:533) (554:554:554))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (274:274:274) (369:369:369))
+        (PORT datab (256:256:256) (336:336:336))
+        (PORT datac (181:181:181) (215:215:215))
+        (PORT datad (158:158:158) (178:178:178))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (378:378:378) (422:422:422))
+        (PORT datab (258:258:258) (339:339:339))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (278:278:278) (370:370:370))
+        (PORT datab (443:443:443) (477:477:477))
+        (PORT datac (181:181:181) (215:215:215))
+        (PORT datad (305:305:305) (307:307:307))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (348:348:348))
+        (PORT datab (184:184:184) (218:218:218))
+        (PORT datac (305:305:305) (318:318:318))
+        (PORT datad (161:161:161) (183:183:183))
+        (IOPATH dataa combout (272:272:272) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1009:1009:1009) (1000:1000:1000))
+        (PORT datab (633:633:633) (659:659:659))
+        (PORT datac (332:332:332) (337:337:337))
+        (PORT datad (477:477:477) (459:459:459))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (609:609:609) (604:604:604))
+        (PORT datab (215:215:215) (258:258:258))
+        (PORT datac (560:560:560) (559:559:559))
+        (PORT datad (177:177:177) (198:198:198))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (190:190:190) (231:231:231))
+        (PORT datab (212:212:212) (253:253:253))
+        (PORT datac (556:556:556) (553:553:553))
+        (PORT datad (168:168:168) (192:192:192))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (191:191:191) (233:233:233))
+        (PORT datab (213:213:213) (255:255:255))
+        (PORT datac (560:560:560) (556:556:556))
+        (PORT datad (164:164:164) (187:187:187))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (370:370:370))
+        (PORT datab (444:444:444) (477:477:477))
+        (PORT datad (539:539:539) (554:554:554))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (320:320:320) (329:329:329))
+        (PORT datab (208:208:208) (244:244:244))
+        (PORT datac (304:304:304) (316:316:316))
+        (PORT datad (178:178:178) (200:200:200))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (362:362:362) (406:406:406))
+        (PORT datad (197:197:197) (218:218:218))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (364:364:364))
+        (PORT datab (768:768:768) (776:776:776))
+        (PORT datac (485:485:485) (463:463:463))
+        (PORT datad (745:745:745) (746:746:746))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1001:1001:1001))
+        (PORT datab (260:260:260) (343:343:343))
+        (PORT datac (585:585:585) (590:590:590))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (340:340:340) (353:353:353))
+        (PORT datab (577:577:577) (581:581:581))
+        (PORT datac (570:570:570) (562:562:562))
+        (PORT datad (321:321:321) (320:320:320))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (808:808:808) (822:822:822))
+        (PORT datab (261:261:261) (343:343:343))
+        (PORT datac (161:161:161) (193:193:193))
+        (PORT datad (165:165:165) (187:187:187))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (627:627:627) (665:665:665))
+        (PORT datab (682:682:682) (728:728:728))
+        (PORT datac (161:161:161) (194:194:194))
+        (PORT datad (316:316:316) (323:323:323))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (629:629:629) (669:669:669))
+        (PORT datab (693:693:693) (728:728:728))
+        (PORT datac (301:301:301) (307:307:307))
+        (PORT datad (166:166:166) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (258:258:258) (340:340:340))
+        (PORT datac (781:781:781) (805:805:805))
+        (PORT datad (793:793:793) (798:798:798))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (993:993:993) (1002:1002:1002))
+        (PORT datab (256:256:256) (337:337:337))
+        (PORT datac (783:783:783) (803:803:803))
+        (PORT datad (787:787:787) (749:749:749))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (184:184:184) (221:221:221))
+        (PORT datac (169:169:169) (205:205:205))
+        (PORT datad (179:179:179) (207:207:207))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (609:609:609) (635:635:635))
+        (PORT datad (396:396:396) (437:437:437))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (670:670:670))
+        (PORT datab (681:681:681) (728:728:728))
+        (PORT datac (164:164:164) (198:198:198))
+        (PORT datad (311:311:311) (320:320:320))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (808:808:808) (831:831:831))
+        (PORT datab (259:259:259) (341:341:341))
+        (PORT datac (170:170:170) (207:207:207))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (804:804:804) (817:817:817))
+        (PORT datab (254:254:254) (336:336:336))
+        (PORT datac (164:164:164) (198:198:198))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (995:995:995) (1001:1001:1001))
+        (PORT datab (257:257:257) (338:338:338))
+        (PORT datac (161:161:161) (194:194:194))
+        (PORT datad (168:168:168) (191:191:191))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (342:342:342) (352:352:352))
+        (PORT datab (333:333:333) (346:346:346))
+        (PORT datac (177:177:177) (208:208:208))
+        (PORT datad (327:327:327) (333:333:333))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (670:670:670))
+        (PORT datab (690:690:690) (727:727:727))
+        (PORT datac (300:300:300) (306:306:306))
+        (PORT datad (167:167:167) (191:191:191))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (419:419:419) (480:480:480))
+        (PORT datab (682:682:682) (733:733:733))
+        (PORT datac (162:162:162) (196:196:196))
+        (PORT datad (166:166:166) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (423:423:423) (483:483:483))
+        (PORT datab (690:690:690) (724:724:724))
+        (PORT datac (163:163:163) (197:197:197))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst40)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1414:1414:1414) (1394:1394:1394))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (420:420:420) (482:482:482))
+        (PORT datab (693:693:693) (729:729:729))
+        (PORT datac (163:163:163) (196:196:196))
+        (PORT datad (166:166:166) (189:189:189))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst39)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1414:1414:1414) (1394:1394:1394))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (422:422:422) (479:479:479))
+        (PORT datab (683:683:683) (733:733:733))
+        (PORT datac (163:163:163) (197:197:197))
+        (PORT datad (166:166:166) (190:190:190))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst38)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1414:1414:1414) (1394:1394:1394))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (488:488:488))
+        (PORT datab (202:202:202) (236:236:236))
+        (PORT datac (313:313:313) (314:314:314))
+        (PORT datad (463:463:463) (443:443:443))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst37)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1427:1427:1427) (1406:1406:1406))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (998:998:998) (1004:1004:1004))
+        (PORT datab (258:258:258) (339:339:339))
+        (PORT datac (163:163:163) (197:197:197))
+        (PORT datad (164:164:164) (188:188:188))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst36)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1427:1427:1427) (1406:1406:1406))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (581:581:581))
+        (PORT datab (1125:1125:1125) (1142:1142:1142))
+        (PORT datac (167:167:167) (203:203:203))
+        (PORT datad (177:177:177) (204:204:204))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst35)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1427:1427:1427) (1406:1406:1406))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (680:680:680) (744:744:744))
+        (PORT datac (631:631:631) (670:670:670))
+        (PORT datad (954:954:954) (920:920:920))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst34)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (957:957:957))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (723:723:723) (785:785:785))
+        (PORT datab (669:669:669) (705:705:705))
+        (PORT datac (755:755:755) (737:737:737))
+        (PORT datad (718:718:718) (697:697:697))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst33)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (957:957:957))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (722:722:722) (781:781:781))
+        (PORT datab (863:863:863) (886:886:886))
+        (PORT datac (654:654:654) (714:714:714))
+        (PORT datad (786:786:786) (804:804:804))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst32)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (957:957:957))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (652:652:652) (717:717:717))
+        (PORT datad (675:675:675) (742:742:742))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst31)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (957:957:957))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+)
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_slow.vho b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..19f2c44
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_slow.vho
@@ -0,0 +1,1670 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:10:48"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	registered_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	B : IN std_logic_vector(4 DOWNTO 0);
+	A : IN std_logic_vector(4 DOWNTO 0)
+	);
+END registered_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF registered_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_B : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_A : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \B[4]~input_o\ : std_logic;
+SIGNAL \inst30~feeder_combout\ : std_logic;
+SIGNAL \inst30~q\ : std_logic;
+SIGNAL \A[4]~input_o\ : std_logic;
+SIGNAL \inst12~feeder_combout\ : std_logic;
+SIGNAL \inst12~q\ : std_logic;
+SIGNAL \B[3]~input_o\ : std_logic;
+SIGNAL \inst27~feeder_combout\ : std_logic;
+SIGNAL \inst27~q\ : std_logic;
+SIGNAL \B[2]~input_o\ : std_logic;
+SIGNAL \inst15~q\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \B[1]~input_o\ : std_logic;
+SIGNAL \inst14~q\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \B[0]~input_o\ : std_logic;
+SIGNAL \inst13~q\ : std_logic;
+SIGNAL \A[3]~input_o\ : std_logic;
+SIGNAL \inst11~feeder_combout\ : std_logic;
+SIGNAL \inst11~q\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \A[2]~input_o\ : std_logic;
+SIGNAL \inst10~q\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \A[1]~input_o\ : std_logic;
+SIGNAL \inst91~q\ : std_logic;
+SIGNAL \A[0]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~1_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst|inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst18~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~1_combout\ : std_logic;
+SIGNAL \inst1|inst19~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~0_combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~1_combout\ : std_logic;
+SIGNAL \inst3|inst22~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst12|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst40~q\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst39~q\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst38~q\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst37~q\ : std_logic;
+SIGNAL \inst3|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst36~q\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst35~q\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst34~q\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst33~q\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst32~q\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+SIGNAL \inst31~q\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_CLK <= CLK;
+ww_B <= B;
+ww_A <= A;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst40~q\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst39~q\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst38~q\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst37~q\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst36~q\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst35~q\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst34~q\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst33~q\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~q\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst31~q\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\B[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(4),
+	o => \B[4]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N14
+\inst30~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~feeder_combout\ = \B[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[4]~input_o\,
+	combout => \inst30~feeder_combout\);
+
+-- Location: FF_X1_Y26_N15
+inst30 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst30~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst30~q\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\A[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(4),
+	o => \A[4]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N12
+\inst12~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst12~feeder_combout\ = \A[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[4]~input_o\,
+	combout => \inst12~feeder_combout\);
+
+-- Location: FF_X2_Y27_N13
+inst12 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst12~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst12~q\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\B[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(3),
+	o => \B[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N0
+\inst27~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst27~feeder_combout\ = \B[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[3]~input_o\,
+	combout => \inst27~feeder_combout\);
+
+-- Location: FF_X1_Y26_N1
+inst27 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst27~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst27~q\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\B[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(2),
+	o => \B[2]~input_o\);
+
+-- Location: FF_X1_Y27_N21
+inst15 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst15~q\);
+
+-- Location: LCCOMB_X2_Y26_N26
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\inst15~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datad => \inst12~q\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\B[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(1),
+	o => \B[1]~input_o\);
+
+-- Location: FF_X1_Y27_N11
+inst14 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst14~q\);
+
+-- Location: LCCOMB_X2_Y26_N20
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\inst14~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst12~q\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\B[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(0),
+	o => \B[0]~input_o\);
+
+-- Location: FF_X1_Y27_N13
+inst13 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[0]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst13~q\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\A[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(3),
+	o => \A[3]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N14
+\inst11~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst11~feeder_combout\ = \A[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[3]~input_o\,
+	combout => \inst11~feeder_combout\);
+
+-- Location: FF_X2_Y27_N15
+inst11 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst11~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst11~q\);
+
+-- Location: LCCOMB_X2_Y27_N20
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\inst11~q\ & \inst14~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst11~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst20~combout\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\A[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(2),
+	o => \A[2]~input_o\);
+
+-- Location: FF_X1_Y27_N25
+inst10 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst10~q\);
+
+-- Location: LCCOMB_X1_Y27_N26
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\inst14~q\ & \inst10~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst10~q\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\A[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(1),
+	o => \A[1]~input_o\);
+
+-- Location: FF_X1_Y27_N9
+inst91 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst91~q\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\A[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(0),
+	o => \A[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y27_N18
+\inst4~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \A[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[0]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X1_Y27_N19
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: LCCOMB_X1_Y27_N20
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst10~q\) # (\inst4~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst10~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N14
+\inst|inst10|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~1_combout\ = (\inst13~q\ & (\inst91~q\ & (\inst14~q\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst10|inst3~1_combout\);
+
+-- Location: LCCOMB_X2_Y27_N18
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~1_combout\) # ((\inst13~q\ & \inst11~q\)))) # (!\inst|inst19~combout\ & (\inst13~q\ & (\inst11~q\ & \inst|inst10|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~1_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y27_N0
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst20~combout\ & ((\inst|inst11|inst3~0_combout\) # ((\inst13~q\ & \inst12~q\)))) # (!\inst|inst20~combout\ & (\inst13~q\ & (\inst12~q\ & \inst|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst12~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N8
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\inst11~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst11~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X2_Y27_N30
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst20~combout\ $ (\inst|inst11|inst3~0_combout\ $ (((\inst12~q\ & \inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst12~q\,
+	datab => \inst13~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N22
+\inst|inst10|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~0_combout\ = (\inst91~q\ & (\inst14~q\ & ((!\inst4~q\) # (!\inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N10
+\inst1|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst18~combout\ = (\inst4~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst18~combout\);
+
+-- Location: LCCOMB_X1_Y27_N28
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\inst1|inst18~combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst18~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y27_N0
+\inst1|inst11|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~0_combout\ = (\inst4~q\ & (\inst91~q\ & \inst15~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datac => \inst91~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst11|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N4
+\inst1|inst11|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~1_combout\ = (\inst1|inst11|inst5~0_combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst11|inst5~0_combout\,
+	combout => \inst1|inst11|inst5~1_combout\);
+
+-- Location: LCCOMB_X1_Y27_N12
+\inst1|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst19~combout\ = (\inst15~q\ & \inst91~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst91~q\,
+	combout => \inst1|inst19~combout\);
+
+-- Location: LCCOMB_X1_Y27_N2
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst10|inst3~1_combout\ $ (\inst|inst19~combout\ $ (((\inst13~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst10|inst3~1_combout\,
+	datad => \inst|inst19~combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N30
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\inst1|inst11|inst5~1_combout\) # ((\inst|inst11|inst2~combout\ & ((\inst1|inst10|inst6~combout\) # (\inst1|inst19~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst10|inst6~combout\,
+	datab => \inst1|inst11|inst5~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N2
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~0_combout\) # ((\inst15~q\ & \inst10~q\)))) # (!\inst|inst12|inst2~combout\ & (\inst15~q\ & (\inst10~q\ & \inst1|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst1|inst11|inst3~0_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N0
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst21~combout\ & ((\inst1|inst12|inst3~0_combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst21~combout\ & (\inst1|inst12|inst3~0_combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst21~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N24
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst22~combout\ & ((\inst1|inst13|inst3~0_combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst22~combout\ & (\inst|inst21~combout\ & (\inst|inst12|inst3~0_combout\ & 
+-- \inst1|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N4
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst22~combout\ $ (\inst1|inst13|inst3~0_combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N24
+\inst|inst11|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~0_combout\ = (\inst13~q\ & (\inst11~q\ $ (((\inst10~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst10~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst10~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N16
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst|inst11|inst2~0_combout\ $ (\inst|inst10|inst3~1_combout\ $ (\inst1|inst19~combout\ $ (\inst1|inst10|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst2~0_combout\,
+	datab => \inst|inst10|inst3~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst1|inst10|inst6~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N6
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\inst4~q\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N12
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst1|inst11|inst3~0_combout\ $ (\inst|inst12|inst2~combout\ $ (((\inst10~q\ & \inst15~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst11|inst3~0_combout\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst15~q\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N26
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\inst27~q\ & ((\inst91~q\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\inst91~q\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y26_N18
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst1|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N28
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\inst10~q\ & \inst27~q\)))) # (!\inst2|inst12|inst3~1_combout\ & (\inst10~q\ & (\inst27~q\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst1|inst14|inst2~combout\ & ((\inst2|inst13|inst3~0_combout\) # ((\inst27~q\ & \inst11~q\)))) # (!\inst1|inst14|inst2~combout\ & (\inst27~q\ & (\inst11~q\ & \inst2|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N14
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\inst27~q\ & \inst12~q\)))) # (!\inst1|inst14|inst3~0_combout\ & (\inst27~q\ & (\inst12~q\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N10
+\inst3|inst13|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~0_combout\ = (\inst30~q\ & (\inst4~q\ & \inst91~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst30~q\,
+	datac => \inst4~q\,
+	datad => \inst91~q\,
+	combout => \inst3|inst13|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N8
+\inst2|inst12|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~0_combout\ = (\inst27~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst1|inst11|inst2~combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N16
+\inst3|inst13|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~1_combout\ = (\inst3|inst13|inst5~0_combout\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~0_combout\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst13|inst5~1_combout\);
+
+-- Location: LCCOMB_X2_Y26_N22
+\inst3|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst22~combout\ = (\inst10~q\ & \inst30~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst10~q\,
+	datad => \inst30~q\,
+	combout => \inst3|inst22~combout\);
+
+-- Location: LCCOMB_X2_Y26_N30
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst1|inst14|inst2~combout\ $ (\inst2|inst13|inst3~0_combout\ $ (((\inst27~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N30
+\inst3|inst12|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst6~combout\ = (\inst4~q\ & (\inst30~q\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datab => \inst30~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y26_N2
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\inst10~q\ & \inst27~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N24
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst13|inst2~combout\ & ((\inst3|inst12|inst6~combout\) # ((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N8
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst3|inst22~combout\ & ((\inst3|inst13|inst5~1_combout\) # ((\inst2|inst14|inst2~combout\) # (\inst3|inst13|inst3~0_combout\)))) # (!\inst3|inst22~combout\ & (\inst2|inst14|inst2~combout\ & 
+-- ((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~1_combout\,
+	datab => \inst3|inst22~combout\,
+	datac => \inst2|inst14|inst2~combout\,
+	datad => \inst3|inst13|inst3~0_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N18
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\inst27~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X2_Y26_N12
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst3|inst14|inst3~0_combout\ & ((\inst2|inst15|inst2~combout\) # ((\inst30~q\ & \inst11~q\)))) # (!\inst3|inst14|inst3~0_combout\ & (\inst30~q\ & (\inst11~q\ & \inst2|inst15|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N28
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst2|inst15|inst3~0_combout\ & ((\inst3|inst15|inst3~0_combout\) # ((\inst30~q\ & \inst12~q\)))) # (!\inst2|inst15|inst3~0_combout\ & (\inst30~q\ & (\inst12~q\ & \inst3|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: FF_X2_Y26_N29
+inst40 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst3~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst40~q\);
+
+-- Location: LCCOMB_X2_Y26_N10
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst2|inst15|inst3~0_combout\ $ (\inst3|inst15|inst3~0_combout\ $ (((\inst30~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: FF_X2_Y26_N11
+inst39 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst39~q\);
+
+-- Location: LCCOMB_X2_Y26_N16
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst3|inst14|inst3~0_combout\ $ (\inst2|inst15|inst2~combout\ $ (((\inst30~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: FF_X2_Y26_N17
+inst38 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst15|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst38~q\);
+
+-- Location: LCCOMB_X1_Y26_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst3|inst22~combout\ $ (\inst2|inst14|inst2~combout\ $ (((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100101010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst22~combout\,
+	datab => \inst3|inst13|inst5~1_combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \inst2|inst14|inst2~combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: FF_X1_Y26_N21
+inst37 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst14|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst37~q\);
+
+-- Location: LCCOMB_X1_Y26_N6
+\inst3|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~combout\ = \inst3|inst12|inst6~combout\ $ (\inst2|inst13|inst2~combout\ $ (((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst2~combout\);
+
+-- Location: FF_X1_Y26_N7
+inst36 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst13|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst36~q\);
+
+-- Location: LCCOMB_X1_Y26_N4
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\ $ (((\inst30~q\ & \inst4~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst4~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: FF_X1_Y26_N5
+inst35 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst12|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst35~q\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\inst4~q\ & \inst27~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datac => \inst27~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: FF_X1_Y23_N29
+inst34 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst2|inst11|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst34~q\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst1|inst18~combout\ $ (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst1|inst18~combout\,
+	datad => \inst|inst10|inst2~0_combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: FF_X1_Y23_N27
+inst33 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst1|inst10|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst33~q\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\inst13~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst4~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst4~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: FF_X1_Y23_N5
+inst32 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst|inst9|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst32~q\);
+
+-- Location: LCCOMB_X1_Y23_N10
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\inst4~q\ & \inst13~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst13~q\,
+	combout => \inst5~combout\);
+
+-- Location: FF_X1_Y23_N11
+inst31 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst5~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst31~q\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_vhd_slow.sdo b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..ab60ba5
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,1347 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "registered_multiply")
+  (DATE "02/19/2016 16:10:48")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (741:741:741) (767:767:767))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (829:829:829) (864:864:864))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (559:559:559) (592:592:592))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (365:365:365) (411:411:411))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (649:649:649) (694:694:694))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (640:640:640) (710:710:710))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (695:695:695) (774:774:774))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (670:670:670) (742:742:742))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (716:716:716) (793:793:793))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (731:731:731) (818:818:818))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2768:2768:2768) (3010:3010:3010))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst30)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst12\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2668:2668:2668) (2907:2907:2907))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst12)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1616:1616:1616) (1616:1616:1616))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst27\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2469:2469:2469) (2716:2716:2716))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst27)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst15)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3243:3243:3243) (3476:3476:3476))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1091:1091:1091) (1131:1131:1131))
+        (PORT datad (703:703:703) (773:773:773))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst14)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3079:3079:3079) (3337:3337:3337))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (917:917:917) (967:967:967))
+        (PORT datad (704:704:704) (778:778:778))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst13)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3385:3385:3385) (3672:3672:3672))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst11\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2984:2984:2984) (3214:3214:3214))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst11)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1616:1616:1616) (1616:1616:1616))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (264:264:264) (345:345:345))
+        (PORT datad (577:577:577) (635:635:635))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst10)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3345:3345:3345) (3587:3587:3587))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (389:389:389) (460:460:460))
+        (PORT datad (261:261:261) (338:338:338))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst91)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (2807:2807:2807) (3053:3053:3053))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2763:2763:2763) (3032:3032:3032))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (287:287:287) (379:379:379))
+        (PORT datad (261:261:261) (340:340:340))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (414:414:414))
+        (PORT datab (288:288:288) (379:379:379))
+        (PORT datac (387:387:387) (458:458:458))
+        (PORT datad (174:174:174) (200:200:200))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (658:658:658) (722:722:722))
+        (PORT datab (292:292:292) (378:378:378))
+        (PORT datac (341:341:341) (365:365:365))
+        (PORT datad (337:337:337) (349:349:349))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (659:659:659) (719:719:719))
+        (PORT datab (571:571:571) (627:627:627))
+        (PORT datac (326:326:326) (346:346:346))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (477:477:477) (542:542:542))
+        (PORT datad (565:565:565) (616:616:616))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (352:352:352))
+        (PORT datab (612:612:612) (682:682:682))
+        (PORT datac (323:323:323) (343:343:343))
+        (PORT datad (181:181:181) (208:208:208))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (410:410:410))
+        (PORT datab (287:287:287) (377:377:377))
+        (PORT datac (389:389:389) (458:458:458))
+        (PORT datad (259:259:259) (337:337:337))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (287:287:287) (378:378:378))
+        (PORT datad (563:563:563) (617:617:617))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (307:307:307) (416:416:416))
+        (PORT datab (287:287:287) (375:375:375))
+        (PORT datac (201:201:201) (236:236:236))
+        (PORT datad (196:196:196) (222:222:222))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (288:288:288) (378:378:378))
+        (PORT datac (259:259:259) (343:343:343))
+        (PORT datad (566:566:566) (619:619:619))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (409:409:409))
+        (PORT datab (285:285:285) (376:376:376))
+        (PORT datac (201:201:201) (238:238:238))
+        (PORT datad (172:172:172) (197:197:197))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (478:478:478))
+        (PORT datab (288:288:288) (380:380:380))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (410:410:410))
+        (PORT datab (477:477:477) (542:542:542))
+        (PORT datac (202:202:202) (237:237:237))
+        (PORT datad (321:321:321) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (393:393:393))
+        (PORT datab (201:201:201) (240:240:240))
+        (PORT datac (324:324:324) (356:356:356))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (303:303:303) (299:299:299))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1089:1089:1089) (1128:1128:1128))
+        (PORT datab (677:677:677) (740:740:740))
+        (PORT datac (359:359:359) (379:379:379))
+        (PORT datad (509:509:509) (520:520:520))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (659:659:659) (676:676:676))
+        (PORT datab (240:240:240) (285:285:285))
+        (PORT datac (609:609:609) (629:629:629))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (255:255:255))
+        (PORT datab (236:236:236) (281:281:281))
+        (PORT datac (601:601:601) (623:623:623))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (257:257:257))
+        (PORT datab (237:237:237) (282:282:282))
+        (PORT datac (608:608:608) (626:626:626))
+        (PORT datad (179:179:179) (207:207:207))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (410:410:410))
+        (PORT datab (478:478:478) (542:542:542))
+        (PORT datad (587:587:587) (628:628:628))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (373:373:373))
+        (PORT datab (229:229:229) (271:271:271))
+        (PORT datac (323:323:323) (354:354:354))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (386:386:386) (455:455:455))
+        (PORT datad (216:216:216) (241:241:241))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (409:409:409))
+        (PORT datab (816:816:816) (872:872:872))
+        (PORT datac (516:516:516) (516:516:516))
+        (PORT datad (797:797:797) (840:840:840))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1066:1066:1066) (1130:1130:1130))
+        (PORT datab (292:292:292) (384:384:384))
+        (PORT datac (638:638:638) (664:664:664))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (400:400:400))
+        (PORT datab (624:624:624) (646:646:646))
+        (PORT datac (613:613:613) (634:634:634))
+        (PORT datad (341:341:341) (361:361:361))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (866:866:866) (924:924:924))
+        (PORT datab (292:292:292) (384:384:384))
+        (PORT datac (178:178:178) (214:214:214))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (686:686:686) (748:748:748))
+        (PORT datab (747:747:747) (812:812:812))
+        (PORT datac (178:178:178) (215:215:215))
+        (PORT datad (339:339:339) (357:357:357))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (688:688:688) (752:752:752))
+        (PORT datab (746:746:746) (820:820:820))
+        (PORT datac (325:325:325) (347:347:347))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (289:289:289) (381:381:381))
+        (PORT datac (840:840:840) (902:902:902))
+        (PORT datad (857:857:857) (903:903:903))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1066:1066:1066) (1130:1130:1130))
+        (PORT datab (286:286:286) (378:378:378))
+        (PORT datac (842:842:842) (900:900:900))
+        (PORT datad (851:851:851) (846:846:846))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (245:245:245))
+        (PORT datac (188:188:188) (228:228:228))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (652:652:652) (710:710:710))
+        (PORT datad (423:423:423) (487:487:487))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (690:690:690) (754:754:754))
+        (PORT datab (746:746:746) (811:811:811))
+        (PORT datac (182:182:182) (219:219:219))
+        (PORT datad (335:335:335) (354:354:354))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (869:869:869) (936:936:936))
+        (PORT datab (290:290:290) (382:382:382))
+        (PORT datac (190:190:190) (230:230:230))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (861:861:861) (918:918:918))
+        (PORT datab (285:285:285) (377:377:377))
+        (PORT datac (182:182:182) (218:218:218))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1067:1067:1067) (1130:1130:1130))
+        (PORT datab (288:288:288) (379:379:379))
+        (PORT datac (178:178:178) (215:215:215))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (311:311:311))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (391:391:391))
+        (PORT datab (361:361:361) (388:388:388))
+        (PORT datac (195:195:195) (228:228:228))
+        (PORT datad (352:352:352) (367:367:367))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (690:690:690) (754:754:754))
+        (PORT datab (744:744:744) (819:819:819))
+        (PORT datac (324:324:324) (345:345:345))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (536:536:536))
+        (PORT datab (746:746:746) (817:817:817))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (451:451:451) (539:539:539))
+        (PORT datab (743:743:743) (816:816:816))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst40)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (451:451:451) (538:538:538))
+        (PORT datab (747:747:747) (821:821:821))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst39)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (536:536:536))
+        (PORT datab (747:747:747) (816:816:816))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst38)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (526:526:526) (546:546:546))
+        (PORT datab (221:221:221) (261:261:261))
+        (PORT datac (335:335:335) (353:353:353))
+        (PORT datad (492:492:492) (499:499:499))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst37)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1070:1070:1070) (1132:1132:1132))
+        (PORT datab (289:289:289) (380:380:380))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (179:179:179) (208:208:208))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst36)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (600:600:600) (655:655:655))
+        (PORT datab (1221:1221:1221) (1266:1266:1266))
+        (PORT datac (186:186:186) (225:225:225))
+        (PORT datad (193:193:193) (227:227:227))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst35)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (739:739:739) (836:836:836))
+        (PORT datac (676:676:676) (759:759:759))
+        (PORT datad (1021:1021:1021) (1038:1038:1038))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst34)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (789:789:789) (889:889:889))
+        (PORT datab (709:709:709) (797:797:797))
+        (PORT datac (803:803:803) (808:808:808))
+        (PORT datad (760:760:760) (781:781:781))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst33)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (788:788:788) (885:885:885))
+        (PORT datab (934:934:934) (1004:1004:1004))
+        (PORT datac (710:710:710) (799:799:799))
+        (PORT datad (845:845:845) (919:919:919))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst32)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (708:708:708) (802:802:802))
+        (PORT datad (745:745:745) (841:841:841))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst31)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_fast.vho b/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..19f2c44
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_fast.vho
@@ -0,0 +1,1670 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:10:48"
+
+-- 
+-- Device: Altera EP3C16F484C6 Package FBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	registered_multiply IS
+    PORT (
+	Output : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	B : IN std_logic_vector(4 DOWNTO 0);
+	A : IN std_logic_vector(4 DOWNTO 0)
+	);
+END registered_multiply;
+
+-- Design Ports Information
+-- Output[9]	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[8]	=>  Location: PIN_B2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[7]	=>  Location: PIN_C2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[6]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[5]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[4]	=>  Location: PIN_F2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[3]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[2]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[1]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Output[0]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[4]	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[4]	=>  Location: PIN_G5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[3]	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[1]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[0]	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[1]	=>  Location: PIN_H5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- A[0]	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- B[2]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF registered_multiply IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Output : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_B : std_logic_vector(4 DOWNTO 0);
+SIGNAL ww_A : std_logic_vector(4 DOWNTO 0);
+SIGNAL \Output[9]~output_o\ : std_logic;
+SIGNAL \Output[8]~output_o\ : std_logic;
+SIGNAL \Output[7]~output_o\ : std_logic;
+SIGNAL \Output[6]~output_o\ : std_logic;
+SIGNAL \Output[5]~output_o\ : std_logic;
+SIGNAL \Output[4]~output_o\ : std_logic;
+SIGNAL \Output[3]~output_o\ : std_logic;
+SIGNAL \Output[2]~output_o\ : std_logic;
+SIGNAL \Output[1]~output_o\ : std_logic;
+SIGNAL \Output[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \B[4]~input_o\ : std_logic;
+SIGNAL \inst30~feeder_combout\ : std_logic;
+SIGNAL \inst30~q\ : std_logic;
+SIGNAL \A[4]~input_o\ : std_logic;
+SIGNAL \inst12~feeder_combout\ : std_logic;
+SIGNAL \inst12~q\ : std_logic;
+SIGNAL \B[3]~input_o\ : std_logic;
+SIGNAL \inst27~feeder_combout\ : std_logic;
+SIGNAL \inst27~q\ : std_logic;
+SIGNAL \B[2]~input_o\ : std_logic;
+SIGNAL \inst15~q\ : std_logic;
+SIGNAL \inst1|inst22~combout\ : std_logic;
+SIGNAL \B[1]~input_o\ : std_logic;
+SIGNAL \inst14~q\ : std_logic;
+SIGNAL \inst|inst21~combout\ : std_logic;
+SIGNAL \B[0]~input_o\ : std_logic;
+SIGNAL \inst13~q\ : std_logic;
+SIGNAL \A[3]~input_o\ : std_logic;
+SIGNAL \inst11~feeder_combout\ : std_logic;
+SIGNAL \inst11~q\ : std_logic;
+SIGNAL \inst|inst20~combout\ : std_logic;
+SIGNAL \A[2]~input_o\ : std_logic;
+SIGNAL \inst10~q\ : std_logic;
+SIGNAL \inst|inst19~combout\ : std_logic;
+SIGNAL \A[1]~input_o\ : std_logic;
+SIGNAL \inst91~q\ : std_logic;
+SIGNAL \A[0]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \inst|inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst10|inst3~1_combout\ : std_logic;
+SIGNAL \inst|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst21~combout\ : std_logic;
+SIGNAL \inst|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst|inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst18~combout\ : std_logic;
+SIGNAL \inst1|inst10|inst6~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst5~1_combout\ : std_logic;
+SIGNAL \inst1|inst19~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst1|inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst|inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst1|inst11|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~0_combout\ : std_logic;
+SIGNAL \inst1|inst12|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst12|inst3~1_combout\ : std_logic;
+SIGNAL \inst1|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~0_combout\ : std_logic;
+SIGNAL \inst2|inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst3|inst13|inst5~1_combout\ : std_logic;
+SIGNAL \inst3|inst22~combout\ : std_logic;
+SIGNAL \inst2|inst14|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst12|inst6~combout\ : std_logic;
+SIGNAL \inst2|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst2|inst15|inst2~combout\ : std_logic;
+SIGNAL \inst3|inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst3|inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst40~q\ : std_logic;
+SIGNAL \inst3|inst16|inst2~combout\ : std_logic;
+SIGNAL \inst39~q\ : std_logic;
+SIGNAL \inst3|inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst38~q\ : std_logic;
+SIGNAL \inst3|inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst37~q\ : std_logic;
+SIGNAL \inst3|inst13|inst2~combout\ : std_logic;
+SIGNAL \inst36~q\ : std_logic;
+SIGNAL \inst3|inst12|inst~combout\ : std_logic;
+SIGNAL \inst35~q\ : std_logic;
+SIGNAL \inst2|inst11|inst~combout\ : std_logic;
+SIGNAL \inst34~q\ : std_logic;
+SIGNAL \inst1|inst10|inst~combout\ : std_logic;
+SIGNAL \inst33~q\ : std_logic;
+SIGNAL \inst|inst9|inst~combout\ : std_logic;
+SIGNAL \inst32~q\ : std_logic;
+SIGNAL \inst5~combout\ : std_logic;
+SIGNAL \inst31~q\ : std_logic;
+
+BEGIN
+
+Output <= ww_Output;
+ww_CLK <= CLK;
+ww_B <= B;
+ww_A <= A;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X0_Y27_N16
+\Output[9]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst40~q\,
+	devoe => ww_devoe,
+	o => \Output[9]~output_o\);
+
+-- Location: IOOBUF_X0_Y27_N9
+\Output[8]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst39~q\,
+	devoe => ww_devoe,
+	o => \Output[8]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N16
+\Output[7]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst38~q\,
+	devoe => ww_devoe,
+	o => \Output[7]~output_o\);
+
+-- Location: IOOBUF_X0_Y26_N23
+\Output[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst37~q\,
+	devoe => ww_devoe,
+	o => \Output[6]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N16
+\Output[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst36~q\,
+	devoe => ww_devoe,
+	o => \Output[5]~output_o\);
+
+-- Location: IOOBUF_X0_Y24_N23
+\Output[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst35~q\,
+	devoe => ww_devoe,
+	o => \Output[4]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N16
+\Output[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst34~q\,
+	devoe => ww_devoe,
+	o => \Output[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y21_N23
+\Output[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst33~q\,
+	devoe => ww_devoe,
+	o => \Output[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N2
+\Output[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst32~q\,
+	devoe => ww_devoe,
+	o => \Output[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y20_N9
+\Output[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst31~q\,
+	devoe => ww_devoe,
+	o => \Output[0]~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: IOIBUF_X0_Y25_N1
+\B[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(4),
+	o => \B[4]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N14
+\inst30~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst30~feeder_combout\ = \B[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[4]~input_o\,
+	combout => \inst30~feeder_combout\);
+
+-- Location: FF_X1_Y26_N15
+inst30 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst30~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst30~q\);
+
+-- Location: IOIBUF_X0_Y27_N22
+\A[4]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(4),
+	o => \A[4]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N12
+\inst12~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst12~feeder_combout\ = \A[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[4]~input_o\,
+	combout => \inst12~feeder_combout\);
+
+-- Location: FF_X2_Y27_N13
+inst12 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst12~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst12~q\);
+
+-- Location: IOIBUF_X0_Y26_N1
+\B[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(3),
+	o => \B[3]~input_o\);
+
+-- Location: LCCOMB_X1_Y26_N0
+\inst27~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst27~feeder_combout\ = \B[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \B[3]~input_o\,
+	combout => \inst27~feeder_combout\);
+
+-- Location: FF_X1_Y26_N1
+inst27 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst27~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst27~q\);
+
+-- Location: IOIBUF_X0_Y26_N8
+\B[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(2),
+	o => \B[2]~input_o\);
+
+-- Location: FF_X1_Y27_N21
+inst15 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst15~q\);
+
+-- Location: LCCOMB_X2_Y26_N26
+\inst1|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst22~combout\ = (\inst15~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datad => \inst12~q\,
+	combout => \inst1|inst22~combout\);
+
+-- Location: IOIBUF_X0_Y25_N15
+\B[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(1),
+	o => \B[1]~input_o\);
+
+-- Location: FF_X1_Y27_N11
+inst14 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst14~q\);
+
+-- Location: LCCOMB_X2_Y26_N20
+\inst|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst21~combout\ = (\inst14~q\ & \inst12~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst12~q\,
+	combout => \inst|inst21~combout\);
+
+-- Location: IOIBUF_X0_Y22_N15
+\B[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_B(0),
+	o => \B[0]~input_o\);
+
+-- Location: FF_X1_Y27_N13
+inst13 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \B[0]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst13~q\);
+
+-- Location: IOIBUF_X0_Y23_N8
+\A[3]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(3),
+	o => \A[3]~input_o\);
+
+-- Location: LCCOMB_X2_Y27_N14
+\inst11~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst11~feeder_combout\ = \A[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[3]~input_o\,
+	combout => \inst11~feeder_combout\);
+
+-- Location: FF_X2_Y27_N15
+inst11 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst11~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst11~q\);
+
+-- Location: LCCOMB_X2_Y27_N20
+\inst|inst20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst20~combout\ = (\inst11~q\ & \inst14~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst11~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst20~combout\);
+
+-- Location: IOIBUF_X0_Y25_N22
+\A[2]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(2),
+	o => \A[2]~input_o\);
+
+-- Location: FF_X1_Y27_N25
+inst10 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[2]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst10~q\);
+
+-- Location: LCCOMB_X1_Y27_N26
+\inst|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst19~combout\ = (\inst14~q\ & \inst10~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst14~q\,
+	datad => \inst10~q\,
+	combout => \inst|inst19~combout\);
+
+-- Location: IOIBUF_X0_Y27_N1
+\A[1]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(1),
+	o => \A[1]~input_o\);
+
+-- Location: FF_X1_Y27_N9
+inst91 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	asdata => \A[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst91~q\);
+
+-- Location: IOIBUF_X0_Y24_N1
+\A[0]~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_A(0),
+	o => \A[0]~input_o\);
+
+-- Location: LCCOMB_X1_Y27_N18
+\inst4~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \A[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \A[0]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X1_Y27_N19
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: LCCOMB_X1_Y27_N20
+\inst|inst10|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~0_combout\ = (\inst10~q\) # (\inst4~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst10~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N14
+\inst|inst10|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst3~1_combout\ = (\inst13~q\ & (\inst91~q\ & (\inst14~q\ & \inst|inst10|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst|inst10|inst3~0_combout\,
+	combout => \inst|inst10|inst3~1_combout\);
+
+-- Location: LCCOMB_X2_Y27_N18
+\inst|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst3~0_combout\ = (\inst|inst19~combout\ & ((\inst|inst10|inst3~1_combout\) # ((\inst13~q\ & \inst11~q\)))) # (!\inst|inst19~combout\ & (\inst13~q\ & (\inst11~q\ & \inst|inst10|inst3~1_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst19~combout\,
+	datad => \inst|inst10|inst3~1_combout\,
+	combout => \inst|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y27_N0
+\inst|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst3~0_combout\ = (\inst|inst20~combout\ & ((\inst|inst11|inst3~0_combout\) # ((\inst13~q\ & \inst12~q\)))) # (!\inst|inst20~combout\ & (\inst13~q\ & (\inst12~q\ & \inst|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst12~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N8
+\inst1|inst21\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst21~combout\ = (\inst11~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst11~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst21~combout\);
+
+-- Location: LCCOMB_X2_Y27_N30
+\inst|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst12|inst2~combout\ = \inst|inst20~combout\ $ (\inst|inst11|inst3~0_combout\ $ (((\inst12~q\ & \inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst12~q\,
+	datab => \inst13~q\,
+	datac => \inst|inst20~combout\,
+	datad => \inst|inst11|inst3~0_combout\,
+	combout => \inst|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N22
+\inst|inst10|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst10|inst2~0_combout\ = (\inst91~q\ & (\inst14~q\ & ((!\inst4~q\) # (!\inst13~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst14~q\,
+	datad => \inst4~q\,
+	combout => \inst|inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N10
+\inst1|inst18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst18~combout\ = (\inst4~q\ & \inst15~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst18~combout\);
+
+-- Location: LCCOMB_X1_Y27_N28
+\inst1|inst10|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst6~combout\ = (\inst1|inst18~combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst18~combout\,
+	combout => \inst1|inst10|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y27_N0
+\inst1|inst11|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~0_combout\ = (\inst4~q\ & (\inst91~q\ & \inst15~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst4~q\,
+	datac => \inst91~q\,
+	datad => \inst15~q\,
+	combout => \inst1|inst11|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N4
+\inst1|inst11|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst5~1_combout\ = (\inst1|inst11|inst5~0_combout\ & (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst10|inst2~0_combout\,
+	datad => \inst1|inst11|inst5~0_combout\,
+	combout => \inst1|inst11|inst5~1_combout\);
+
+-- Location: LCCOMB_X1_Y27_N12
+\inst1|inst19\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst19~combout\ = (\inst15~q\ & \inst91~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst91~q\,
+	combout => \inst1|inst19~combout\);
+
+-- Location: LCCOMB_X1_Y27_N2
+\inst|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~combout\ = \inst|inst10|inst3~1_combout\ $ (\inst|inst19~combout\ $ (((\inst13~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst|inst10|inst3~1_combout\,
+	datad => \inst|inst19~combout\,
+	combout => \inst|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N30
+\inst1|inst11|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst3~0_combout\ = (\inst1|inst11|inst5~1_combout\) # ((\inst|inst11|inst2~combout\ & ((\inst1|inst10|inst6~combout\) # (\inst1|inst19~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst10|inst6~combout\,
+	datab => \inst1|inst11|inst5~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst|inst11|inst2~combout\,
+	combout => \inst1|inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N2
+\inst1|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst3~0_combout\ = (\inst|inst12|inst2~combout\ & ((\inst1|inst11|inst3~0_combout\) # ((\inst15~q\ & \inst10~q\)))) # (!\inst|inst12|inst2~combout\ & (\inst15~q\ & (\inst10~q\ & \inst1|inst11|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst15~q\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst1|inst11|inst3~0_combout\,
+	combout => \inst1|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N0
+\inst1|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst3~0_combout\ = (\inst1|inst21~combout\ & ((\inst1|inst12|inst3~0_combout\) # (\inst|inst21~combout\ $ (\inst|inst12|inst3~0_combout\)))) # (!\inst1|inst21~combout\ & (\inst1|inst12|inst3~0_combout\ & (\inst|inst21~combout\ $ 
+-- (\inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst21~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N24
+\inst1|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst3~0_combout\ = (\inst1|inst22~combout\ & ((\inst1|inst13|inst3~0_combout\) # ((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\)))) # (!\inst1|inst22~combout\ & (\inst|inst21~combout\ & (\inst|inst12|inst3~0_combout\ & 
+-- \inst1|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N4
+\inst1|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst14|inst2~combout\ = \inst1|inst22~combout\ $ (\inst1|inst13|inst3~0_combout\ $ (((\inst|inst21~combout\ & \inst|inst12|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst22~combout\,
+	datab => \inst|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst13|inst3~0_combout\,
+	combout => \inst1|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N24
+\inst|inst11|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst11|inst2~0_combout\ = (\inst13~q\ & (\inst11~q\ $ (((\inst10~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst10~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst11~q\,
+	datac => \inst10~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y27_N16
+\inst1|inst11|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst11|inst2~combout\ = \inst|inst11|inst2~0_combout\ $ (\inst|inst10|inst3~1_combout\ $ (\inst1|inst19~combout\ $ (\inst1|inst10|inst6~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst11|inst2~0_combout\,
+	datab => \inst|inst10|inst3~1_combout\,
+	datac => \inst1|inst19~combout\,
+	datad => \inst1|inst10|inst6~combout\,
+	combout => \inst1|inst11|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y27_N6
+\inst2|inst12|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~0_combout\ = (\inst4~q\ & \inst1|inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N12
+\inst1|inst12|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst12|inst2~combout\ = \inst1|inst11|inst3~0_combout\ $ (\inst|inst12|inst2~combout\ $ (((\inst10~q\ & \inst15~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001011010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1|inst11|inst3~0_combout\,
+	datab => \inst10~q\,
+	datac => \inst|inst12|inst2~combout\,
+	datad => \inst15~q\,
+	combout => \inst1|inst12|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N26
+\inst2|inst12|inst3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst3~1_combout\ = (\inst27~q\ & ((\inst91~q\ & ((\inst2|inst12|inst3~0_combout\) # (\inst1|inst12|inst2~combout\))) # (!\inst91~q\ & (\inst2|inst12|inst3~0_combout\ & \inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst2|inst12|inst3~1_combout\);
+
+-- Location: LCCOMB_X1_Y26_N18
+\inst1|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst13|inst2~combout\ = \inst|inst21~combout\ $ (\inst1|inst21~combout\ $ (\inst|inst12|inst3~0_combout\ $ (\inst1|inst12|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110100110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst|inst21~combout\,
+	datab => \inst1|inst21~combout\,
+	datac => \inst|inst12|inst3~0_combout\,
+	datad => \inst1|inst12|inst3~0_combout\,
+	combout => \inst1|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N28
+\inst2|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst3~0_combout\ = (\inst2|inst12|inst3~1_combout\ & ((\inst1|inst13|inst2~combout\) # ((\inst10~q\ & \inst27~q\)))) # (!\inst2|inst12|inst3~1_combout\ & (\inst10~q\ & (\inst27~q\ & \inst1|inst13|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N6
+\inst2|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst3~0_combout\ = (\inst1|inst14|inst2~combout\ & ((\inst2|inst13|inst3~0_combout\) # ((\inst27~q\ & \inst11~q\)))) # (!\inst1|inst14|inst2~combout\ & (\inst27~q\ & (\inst11~q\ & \inst2|inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N14
+\inst2|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst3~0_combout\ = (\inst1|inst14|inst3~0_combout\ & ((\inst2|inst14|inst3~0_combout\) # ((\inst27~q\ & \inst12~q\)))) # (!\inst1|inst14|inst3~0_combout\ & (\inst27~q\ & (\inst12~q\ & \inst2|inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N10
+\inst3|inst13|inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~0_combout\ = (\inst30~q\ & (\inst4~q\ & \inst91~q\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst30~q\,
+	datac => \inst4~q\,
+	datad => \inst91~q\,
+	combout => \inst3|inst13|inst5~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N8
+\inst2|inst12|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst12|inst2~0_combout\ = (\inst27~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst1|inst11|inst2~combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst27~q\,
+	datac => \inst4~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X1_Y26_N16
+\inst3|inst13|inst5~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst5~1_combout\ = (\inst3|inst13|inst5~0_combout\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~0_combout\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst13|inst5~1_combout\);
+
+-- Location: LCCOMB_X2_Y26_N22
+\inst3|inst22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst22~combout\ = (\inst10~q\ & \inst30~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst10~q\,
+	datad => \inst30~q\,
+	combout => \inst3|inst22~combout\);
+
+-- Location: LCCOMB_X2_Y26_N30
+\inst2|inst14|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst14|inst2~combout\ = \inst1|inst14|inst2~combout\ $ (\inst2|inst13|inst3~0_combout\ $ (((\inst27~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst11~q\,
+	datac => \inst1|inst14|inst2~combout\,
+	datad => \inst2|inst13|inst3~0_combout\,
+	combout => \inst2|inst14|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N30
+\inst3|inst12|inst6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst6~combout\ = (\inst4~q\ & (\inst30~q\ & (\inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datab => \inst30~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst6~combout\);
+
+-- Location: LCCOMB_X1_Y26_N2
+\inst2|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst13|inst2~combout\ = \inst2|inst12|inst3~1_combout\ $ (\inst1|inst13|inst2~combout\ $ (((\inst10~q\ & \inst27~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst10~q\,
+	datab => \inst27~q\,
+	datac => \inst2|inst12|inst3~1_combout\,
+	datad => \inst1|inst13|inst2~combout\,
+	combout => \inst2|inst13|inst2~combout\);
+
+-- Location: LCCOMB_X1_Y26_N24
+\inst3|inst13|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst3~0_combout\ = (\inst2|inst13|inst2~combout\ & ((\inst3|inst12|inst6~combout\) # ((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N8
+\inst3|inst14|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst3~0_combout\ = (\inst3|inst22~combout\ & ((\inst3|inst13|inst5~1_combout\) # ((\inst2|inst14|inst2~combout\) # (\inst3|inst13|inst3~0_combout\)))) # (!\inst3|inst22~combout\ & (\inst2|inst14|inst2~combout\ & 
+-- ((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst13|inst5~1_combout\,
+	datab => \inst3|inst22~combout\,
+	datac => \inst2|inst14|inst2~combout\,
+	datad => \inst3|inst13|inst3~0_combout\,
+	combout => \inst3|inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N18
+\inst2|inst15|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst15|inst2~combout\ = \inst1|inst14|inst3~0_combout\ $ (\inst2|inst14|inst3~0_combout\ $ (((\inst27~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst27~q\,
+	datab => \inst12~q\,
+	datac => \inst1|inst14|inst3~0_combout\,
+	datad => \inst2|inst14|inst3~0_combout\,
+	combout => \inst2|inst15|inst2~combout\);
+
+-- Location: LCCOMB_X2_Y26_N12
+\inst3|inst15|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst3~0_combout\ = (\inst3|inst14|inst3~0_combout\ & ((\inst2|inst15|inst2~combout\) # ((\inst30~q\ & \inst11~q\)))) # (!\inst3|inst14|inst3~0_combout\ & (\inst30~q\ & (\inst11~q\ & \inst2|inst15|inst2~combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X2_Y26_N28
+\inst3|inst16|inst3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst3~0_combout\ = (\inst2|inst15|inst3~0_combout\ & ((\inst3|inst15|inst3~0_combout\) # ((\inst30~q\ & \inst12~q\)))) # (!\inst2|inst15|inst3~0_combout\ & (\inst30~q\ & (\inst12~q\ & \inst3|inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst3~0_combout\);
+
+-- Location: FF_X2_Y26_N29
+inst40 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst3~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst40~q\);
+
+-- Location: LCCOMB_X2_Y26_N10
+\inst3|inst16|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst16|inst2~combout\ = \inst2|inst15|inst3~0_combout\ $ (\inst3|inst15|inst3~0_combout\ $ (((\inst30~q\ & \inst12~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst12~q\,
+	datac => \inst2|inst15|inst3~0_combout\,
+	datad => \inst3|inst15|inst3~0_combout\,
+	combout => \inst3|inst16|inst2~combout\);
+
+-- Location: FF_X2_Y26_N11
+inst39 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst16|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst39~q\);
+
+-- Location: LCCOMB_X2_Y26_N16
+\inst3|inst15|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst15|inst2~0_combout\ = \inst3|inst14|inst3~0_combout\ $ (\inst2|inst15|inst2~combout\ $ (((\inst30~q\ & \inst11~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst11~q\,
+	datac => \inst3|inst14|inst3~0_combout\,
+	datad => \inst2|inst15|inst2~combout\,
+	combout => \inst3|inst15|inst2~0_combout\);
+
+-- Location: FF_X2_Y26_N17
+inst38 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst15|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst38~q\);
+
+-- Location: LCCOMB_X1_Y26_N20
+\inst3|inst14|inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst14|inst2~0_combout\ = \inst3|inst22~combout\ $ (\inst2|inst14|inst2~combout\ $ (((\inst3|inst13|inst5~1_combout\) # (\inst3|inst13|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010100101010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst3|inst22~combout\,
+	datab => \inst3|inst13|inst5~1_combout\,
+	datac => \inst3|inst13|inst3~0_combout\,
+	datad => \inst2|inst14|inst2~combout\,
+	combout => \inst3|inst14|inst2~0_combout\);
+
+-- Location: FF_X1_Y26_N21
+inst37 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst14|inst2~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst37~q\);
+
+-- Location: LCCOMB_X1_Y26_N6
+\inst3|inst13|inst2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst13|inst2~combout\ = \inst3|inst12|inst6~combout\ $ (\inst2|inst13|inst2~combout\ $ (((\inst91~q\ & \inst30~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst91~q\,
+	datab => \inst30~q\,
+	datac => \inst3|inst12|inst6~combout\,
+	datad => \inst2|inst13|inst2~combout\,
+	combout => \inst3|inst13|inst2~combout\);
+
+-- Location: FF_X1_Y26_N7
+inst36 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst13|inst2~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst36~q\);
+
+-- Location: LCCOMB_X1_Y26_N4
+\inst3|inst12|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst3|inst12|inst~combout\ = \inst2|inst12|inst2~0_combout\ $ (\inst1|inst12|inst2~combout\ $ (((\inst30~q\ & \inst4~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst30~q\,
+	datab => \inst4~q\,
+	datac => \inst2|inst12|inst2~0_combout\,
+	datad => \inst1|inst12|inst2~combout\,
+	combout => \inst3|inst12|inst~combout\);
+
+-- Location: FF_X1_Y26_N5
+inst35 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst3|inst12|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst35~q\);
+
+-- Location: LCCOMB_X1_Y23_N28
+\inst2|inst11|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2|inst11|inst~combout\ = \inst1|inst11|inst2~combout\ $ (((\inst4~q\ & \inst27~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst4~q\,
+	datac => \inst27~q\,
+	datad => \inst1|inst11|inst2~combout\,
+	combout => \inst2|inst11|inst~combout\);
+
+-- Location: FF_X1_Y23_N29
+inst34 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst2|inst11|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst34~q\);
+
+-- Location: LCCOMB_X1_Y23_N26
+\inst1|inst10|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst1|inst10|inst~combout\ = \inst1|inst18~combout\ $ (\inst|inst10|inst2~0_combout\ $ (((\inst13~q\ & \inst10~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst10~q\,
+	datac => \inst1|inst18~combout\,
+	datad => \inst|inst10|inst2~0_combout\,
+	combout => \inst1|inst10|inst~combout\);
+
+-- Location: FF_X1_Y23_N27
+inst33 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst1|inst10|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst33~q\);
+
+-- Location: LCCOMB_X1_Y23_N4
+\inst|inst9|inst\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst|inst9|inst~combout\ = (\inst13~q\ & (\inst91~q\ $ (((\inst4~q\ & \inst14~q\))))) # (!\inst13~q\ & (((\inst4~q\ & \inst14~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13~q\,
+	datab => \inst91~q\,
+	datac => \inst4~q\,
+	datad => \inst14~q\,
+	combout => \inst|inst9|inst~combout\);
+
+-- Location: FF_X1_Y23_N5
+inst32 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst|inst9|inst~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst32~q\);
+
+-- Location: LCCOMB_X1_Y23_N10
+inst5 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~combout\ = (\inst4~q\ & \inst13~q\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst4~q\,
+	datad => \inst13~q\,
+	combout => \inst5~combout\);
+
+-- Location: FF_X1_Y23_N11
+inst31 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~input_o\,
+	d => \inst5~combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst31~q\);
+
+ww_Output(9) <= \Output[9]~output_o\;
+
+ww_Output(8) <= \Output[8]~output_o\;
+
+ww_Output(7) <= \Output[7]~output_o\;
+
+ww_Output(6) <= \Output[6]~output_o\;
+
+ww_Output(5) <= \Output[5]~output_o\;
+
+ww_Output(4) <= \Output[4]~output_o\;
+
+ww_Output(3) <= \Output[3]~output_o\;
+
+ww_Output(2) <= \Output[2]~output_o\;
+
+ww_Output(1) <= \Output[1]~output_o\;
+
+ww_Output(0) <= \Output[0]~output_o\;
+END structure;
+
+
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_vhd_fast.sdo b/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..e42acde
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,1347 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16F484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "registered_multiply")
+  (DATE "02/19/2016 16:10:48")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (385:385:385) (453:453:453))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (436:436:436) (504:504:504))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (286:286:286) (333:333:333))
+        (IOPATH i o (1506:1506:1506) (1490:1490:1490))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (188:188:188) (228:228:228))
+        (IOPATH i o (1496:1496:1496) (1480:1480:1480))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (356:356:356) (417:417:417))
+        (IOPATH i o (1486:1486:1486) (1470:1470:1470))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (354:354:354) (415:415:415))
+        (IOPATH i o (1486:1486:1486) (1470:1470:1470))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (373:373:373) (460:460:460))
+        (IOPATH i o (1476:1476:1476) (1460:1460:1460))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (362:362:362) (440:440:440))
+        (IOPATH i o (2288:2288:2288) (2417:2417:2417))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (406:406:406) (478:478:478))
+        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (412:412:412) (492:492:492))
+        (IOPATH i o (1466:1466:1466) (1450:1450:1450))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (411:411:411) (793:793:793))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (431:431:431) (813:813:813))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1603:1603:1603) (1785:1785:1785))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst30)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (866:866:866) (916:916:916))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst12\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1545:1545:1545) (1710:1710:1710))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst12)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (939:939:939))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst27\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1442:1442:1442) (1600:1600:1600))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst27)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (866:866:866) (916:916:916))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst15)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT asdata (1846:1846:1846) (2037:2037:2037))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (574:574:574) (666:666:666))
+        (PORT datad (383:383:383) (461:461:461))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst14)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT asdata (1782:1782:1782) (1961:1961:1961))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (486:486:486) (564:564:564))
+        (PORT datad (383:383:383) (461:461:461))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst13)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT asdata (1958:1958:1958) (2163:2163:2163))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst11\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1721:1721:1721) (1909:1909:1909))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst11)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (939:939:939))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (144:144:144) (186:186:186))
+        (PORT datad (304:304:304) (366:366:366))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst10)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT asdata (1911:1911:1911) (2112:2112:2112))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (207:207:207) (261:261:261))
+        (PORT datad (142:142:142) (183:183:183))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst91)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT asdata (1614:1614:1614) (1772:1772:1772))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1616:1616:1616) (1796:1796:1796))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (761:761:761) (794:794:794))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (155:155:155) (208:208:208))
+        (PORT datad (142:142:142) (183:183:183))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (168:168:168) (229:229:229))
+        (PORT datab (157:157:157) (209:209:209))
+        (PORT datac (204:204:204) (259:259:259))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (346:346:346) (412:412:412))
+        (PORT datab (158:158:158) (209:209:209))
+        (PORT datac (172:172:172) (207:207:207))
+        (PORT datad (175:175:175) (197:197:197))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (411:411:411))
+        (PORT datab (296:296:296) (356:356:356))
+        (PORT datac (167:167:167) (196:196:196))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (249:249:249) (307:307:307))
+        (PORT datad (295:295:295) (352:352:352))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (195:195:195))
+        (PORT datab (325:325:325) (390:390:390))
+        (PORT datac (165:165:165) (193:193:193))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (172:172:172) (231:231:231))
+        (PORT datab (158:158:158) (210:210:210))
+        (PORT datac (205:205:205) (258:258:258))
+        (PORT datad (141:141:141) (182:182:182))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (154:154:154) (209:209:209))
+        (PORT datad (295:295:295) (355:355:355))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (168:168:168) (237:237:237))
+        (PORT datab (155:155:155) (207:207:207))
+        (PORT datac (106:106:106) (128:128:128))
+        (PORT datad (103:103:103) (122:122:122))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (158:158:158) (211:211:211))
+        (PORT datac (141:141:141) (187:187:187))
+        (PORT datad (296:296:296) (356:356:356))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (167:167:167) (228:228:228))
+        (PORT datab (158:158:158) (209:209:209))
+        (PORT datac (109:109:109) (131:131:131))
+        (PORT datad (89:89:89) (106:106:106))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (268:268:268))
+        (PORT datab (156:156:156) (211:211:211))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (169:169:169) (230:230:230))
+        (PORT datab (249:249:249) (307:307:307))
+        (PORT datac (107:107:107) (130:130:130))
+        (PORT datad (165:165:165) (195:195:195))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (187:187:187) (222:222:222))
+        (PORT datab (106:106:106) (135:135:135))
+        (PORT datac (169:169:169) (203:203:203))
+        (PORT datad (93:93:93) (111:111:111))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (572:572:572) (664:664:664))
+        (PORT datab (370:370:370) (438:438:438))
+        (PORT datac (183:183:183) (214:214:214))
+        (PORT datad (265:265:265) (297:297:297))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (407:407:407))
+        (PORT datab (128:128:128) (162:162:162))
+        (PORT datac (330:330:330) (378:378:378))
+        (PORT datad (102:102:102) (118:118:118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (108:108:108) (141:141:141))
+        (PORT datab (124:124:124) (155:155:155))
+        (PORT datac (325:325:325) (372:372:372))
+        (PORT datad (97:97:97) (116:116:116))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (112:112:112) (144:144:144))
+        (PORT datab (128:128:128) (158:158:158))
+        (PORT datac (329:329:329) (375:375:375))
+        (PORT datad (93:93:93) (112:112:112))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (172:172:172) (231:231:231))
+        (PORT datab (249:249:249) (307:307:307))
+        (PORT datad (305:305:305) (353:353:353))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (211:211:211))
+        (PORT datab (119:119:119) (149:149:149))
+        (PORT datac (166:166:166) (199:199:199))
+        (PORT datad (103:103:103) (120:120:120))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (203:203:203) (255:255:255))
+        (PORT datad (116:116:116) (132:132:132))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (195:195:195) (233:233:233))
+        (PORT datab (436:436:436) (518:518:518))
+        (PORT datac (260:260:260) (295:295:295))
+        (PORT datad (428:428:428) (499:499:499))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (675:675:675))
+        (PORT datab (161:161:161) (216:216:216))
+        (PORT datac (340:340:340) (400:400:400))
+        (PORT datad (102:102:102) (128:128:128))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (187:187:187) (225:225:225))
+        (PORT datab (329:329:329) (390:390:390))
+        (PORT datac (327:327:327) (382:382:382))
+        (PORT datad (176:176:176) (203:203:203))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (460:460:460) (549:549:549))
+        (PORT datab (161:161:161) (216:216:216))
+        (PORT datac (93:93:93) (115:115:115))
+        (PORT datad (94:94:94) (111:111:111))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (348:348:348) (424:424:424))
+        (PORT datab (401:401:401) (485:485:485))
+        (PORT datac (93:93:93) (115:115:115))
+        (PORT datad (173:173:173) (203:203:203))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (428:428:428))
+        (PORT datab (402:402:402) (486:486:486))
+        (PORT datac (166:166:166) (195:195:195))
+        (PORT datad (95:95:95) (112:112:112))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (156:156:156) (209:209:209))
+        (PORT datac (451:451:451) (536:536:536))
+        (PORT datad (461:461:461) (535:535:535))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (578:578:578) (676:676:676))
+        (PORT datab (156:156:156) (210:210:210))
+        (PORT datac (450:450:450) (534:534:534))
+        (PORT datad (452:452:452) (496:496:496))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datac (98:98:98) (124:124:124))
+        (PORT datad (101:101:101) (123:123:123))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (358:358:358) (419:419:419))
+        (PORT datad (226:226:226) (276:276:276))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (353:353:353) (430:430:430))
+        (PORT datab (401:401:401) (485:485:485))
+        (PORT datac (97:97:97) (121:121:121))
+        (PORT datad (170:170:170) (200:200:200))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (462:462:462) (555:555:555))
+        (PORT datab (156:156:156) (214:214:214))
+        (PORT datac (102:102:102) (128:128:128))
+        (PORT datad (102:102:102) (128:128:128))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (456:456:456) (543:543:543))
+        (PORT datab (155:155:155) (208:208:208))
+        (PORT datac (97:97:97) (120:120:120))
+        (PORT datad (96:96:96) (115:115:115))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (577:577:577) (675:675:675))
+        (PORT datab (159:159:159) (211:211:211))
+        (PORT datac (93:93:93) (116:116:116))
+        (PORT datad (97:97:97) (116:116:116))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (187:187:187) (223:223:223))
+        (PORT datab (187:187:187) (222:222:222))
+        (PORT datac (104:104:104) (125:125:125))
+        (PORT datad (181:181:181) (208:208:208))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (429:429:429))
+        (PORT datab (403:403:403) (487:487:487))
+        (PORT datac (165:165:165) (193:193:193))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (239:239:239) (306:306:306))
+        (PORT datab (400:400:400) (485:485:485))
+        (PORT datac (94:94:94) (118:118:118))
+        (PORT datad (94:94:94) (113:113:113))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (308:308:308))
+        (PORT datab (404:404:404) (488:488:488))
+        (PORT datac (94:94:94) (119:119:119))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst40)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (854:854:854) (898:898:898))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (239:239:239) (306:306:306))
+        (PORT datab (406:406:406) (492:492:492))
+        (PORT datac (94:94:94) (116:116:116))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst39)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (854:854:854) (898:898:898))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (238:238:238) (301:301:301))
+        (PORT datab (400:400:400) (485:485:485))
+        (PORT datac (94:94:94) (117:117:117))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst38)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (854:854:854) (898:898:898))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (316:316:316))
+        (PORT datab (115:115:115) (144:144:144))
+        (PORT datac (172:172:172) (197:197:197))
+        (PORT datad (251:251:251) (283:283:283))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst37)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (866:866:866) (916:916:916))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (579:579:579) (678:678:678))
+        (PORT datab (156:156:156) (211:211:211))
+        (PORT datac (97:97:97) (119:119:119))
+        (PORT datad (94:94:94) (112:112:112))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst36)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (866:866:866) (916:916:916))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (307:307:307) (372:372:372))
+        (PORT datab (661:661:661) (757:757:757))
+        (PORT datac (97:97:97) (122:122:122))
+        (PORT datad (101:101:101) (122:122:122))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst35)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (866:866:866) (916:916:916))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (405:405:405) (495:495:495))
+        (PORT datac (374:374:374) (447:447:447))
+        (PORT datad (552:552:552) (612:612:612))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst34)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (586:586:586) (601:601:601))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (442:442:442) (530:530:530))
+        (PORT datab (394:394:394) (471:471:471))
+        (PORT datac (429:429:429) (490:490:490))
+        (PORT datad (421:421:421) (466:466:466))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst33)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (586:586:586) (601:601:601))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (439:439:439) (526:526:526))
+        (PORT datab (505:505:505) (590:590:590))
+        (PORT datac (391:391:391) (472:472:472))
+        (PORT datad (466:466:466) (542:542:542))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst32)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (586:586:586) (601:601:601))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (392:392:392) (474:474:474))
+        (PORT datad (417:417:417) (497:497:497))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst31)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (586:586:586) (601:601:601))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_modelsim.xrf b/registered_multiply/simulation/modelsim/registered_multiply_modelsim.xrf
new file mode 100644
index 0000000..2704c99
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_modelsim.xrf
@@ -0,0 +1,83 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/comb_multiply/registered_multiply.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/registered_multiply/db/registered_multiply.cbx.xml
+design_name = registered_multiply
+instance = comp, \Output[9]~output\, Output[9]~output, registered_multiply, 1
+instance = comp, \Output[8]~output\, Output[8]~output, registered_multiply, 1
+instance = comp, \Output[7]~output\, Output[7]~output, registered_multiply, 1
+instance = comp, \Output[6]~output\, Output[6]~output, registered_multiply, 1
+instance = comp, \Output[5]~output\, Output[5]~output, registered_multiply, 1
+instance = comp, \Output[4]~output\, Output[4]~output, registered_multiply, 1
+instance = comp, \Output[3]~output\, Output[3]~output, registered_multiply, 1
+instance = comp, \Output[2]~output\, Output[2]~output, registered_multiply, 1
+instance = comp, \Output[1]~output\, Output[1]~output, registered_multiply, 1
+instance = comp, \Output[0]~output\, Output[0]~output, registered_multiply, 1
+instance = comp, \CLK~input\, CLK~input, registered_multiply, 1
+instance = comp, \B[4]~input\, B[4]~input, registered_multiply, 1
+instance = comp, \inst30~feeder\, inst30~feeder, registered_multiply, 1
+instance = comp, \A[4]~input\, A[4]~input, registered_multiply, 1
+instance = comp, \inst12~feeder\, inst12~feeder, registered_multiply, 1
+instance = comp, \B[3]~input\, B[3]~input, registered_multiply, 1
+instance = comp, \inst27~feeder\, inst27~feeder, registered_multiply, 1
+instance = comp, \B[2]~input\, B[2]~input, registered_multiply, 1
+instance = comp, \inst1|inst22\, inst1|inst22, registered_multiply, 1
+instance = comp, \B[1]~input\, B[1]~input, registered_multiply, 1
+instance = comp, \inst|inst21\, inst|inst21, registered_multiply, 1
+instance = comp, \B[0]~input\, B[0]~input, registered_multiply, 1
+instance = comp, \A[3]~input\, A[3]~input, registered_multiply, 1
+instance = comp, \inst11~feeder\, inst11~feeder, registered_multiply, 1
+instance = comp, \inst|inst20\, inst|inst20, registered_multiply, 1
+instance = comp, \A[2]~input\, A[2]~input, registered_multiply, 1
+instance = comp, \inst|inst19\, inst|inst19, registered_multiply, 1
+instance = comp, \A[1]~input\, A[1]~input, registered_multiply, 1
+instance = comp, \A[0]~input\, A[0]~input, registered_multiply, 1
+instance = comp, \inst4~feeder\, inst4~feeder, registered_multiply, 1
+instance = comp, \inst|inst10|inst3~0\, inst|inst10|inst3~0, registered_multiply, 1
+instance = comp, \inst|inst10|inst3~1\, inst|inst10|inst3~1, registered_multiply, 1
+instance = comp, \inst|inst11|inst3~0\, inst|inst11|inst3~0, registered_multiply, 1
+instance = comp, \inst|inst12|inst3~0\, inst|inst12|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst21\, inst1|inst21, registered_multiply, 1
+instance = comp, \inst|inst12|inst2\, inst|inst12|inst2, registered_multiply, 1
+instance = comp, \inst|inst10|inst2~0\, inst|inst10|inst2~0, registered_multiply, 1
+instance = comp, \inst1|inst18\, inst1|inst18, registered_multiply, 1
+instance = comp, \inst1|inst10|inst6\, inst1|inst10|inst6, registered_multiply, 1
+instance = comp, \inst1|inst11|inst5~0\, inst1|inst11|inst5~0, registered_multiply, 1
+instance = comp, \inst1|inst11|inst5~1\, inst1|inst11|inst5~1, registered_multiply, 1
+instance = comp, \inst1|inst19\, inst1|inst19, registered_multiply, 1
+instance = comp, \inst|inst11|inst2\, inst|inst11|inst2, registered_multiply, 1
+instance = comp, \inst1|inst11|inst3~0\, inst1|inst11|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst12|inst3~0\, inst1|inst12|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst13|inst3~0\, inst1|inst13|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst14|inst3~0\, inst1|inst14|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst14|inst2\, inst1|inst14|inst2, registered_multiply, 1
+instance = comp, \inst|inst11|inst2~0\, inst|inst11|inst2~0, registered_multiply, 1
+instance = comp, \inst1|inst11|inst2\, inst1|inst11|inst2, registered_multiply, 1
+instance = comp, \inst2|inst12|inst3~0\, inst2|inst12|inst3~0, registered_multiply, 1
+instance = comp, \inst1|inst12|inst2\, inst1|inst12|inst2, registered_multiply, 1
+instance = comp, \inst2|inst12|inst3~1\, inst2|inst12|inst3~1, registered_multiply, 1
+instance = comp, \inst1|inst13|inst2\, inst1|inst13|inst2, registered_multiply, 1
+instance = comp, \inst2|inst13|inst3~0\, inst2|inst13|inst3~0, registered_multiply, 1
+instance = comp, \inst2|inst14|inst3~0\, inst2|inst14|inst3~0, registered_multiply, 1
+instance = comp, \inst2|inst15|inst3~0\, inst2|inst15|inst3~0, registered_multiply, 1
+instance = comp, \inst3|inst13|inst5~0\, inst3|inst13|inst5~0, registered_multiply, 1
+instance = comp, \inst2|inst12|inst2~0\, inst2|inst12|inst2~0, registered_multiply, 1
+instance = comp, \inst3|inst13|inst5~1\, inst3|inst13|inst5~1, registered_multiply, 1
+instance = comp, \inst3|inst22\, inst3|inst22, registered_multiply, 1
+instance = comp, \inst2|inst14|inst2\, inst2|inst14|inst2, registered_multiply, 1
+instance = comp, \inst3|inst12|inst6\, inst3|inst12|inst6, registered_multiply, 1
+instance = comp, \inst2|inst13|inst2\, inst2|inst13|inst2, registered_multiply, 1
+instance = comp, \inst3|inst13|inst3~0\, inst3|inst13|inst3~0, registered_multiply, 1
+instance = comp, \inst3|inst14|inst3~0\, inst3|inst14|inst3~0, registered_multiply, 1
+instance = comp, \inst2|inst15|inst2\, inst2|inst15|inst2, registered_multiply, 1
+instance = comp, \inst3|inst15|inst3~0\, inst3|inst15|inst3~0, registered_multiply, 1
+instance = comp, \inst3|inst16|inst3~0\, inst3|inst16|inst3~0, registered_multiply, 1
+instance = comp, \inst3|inst16|inst2\, inst3|inst16|inst2, registered_multiply, 1
+instance = comp, \inst3|inst15|inst2~0\, inst3|inst15|inst2~0, registered_multiply, 1
+instance = comp, \inst3|inst14|inst2~0\, inst3|inst14|inst2~0, registered_multiply, 1
+instance = comp, \inst3|inst13|inst2\, inst3|inst13|inst2, registered_multiply, 1
+instance = comp, \inst3|inst12|inst\, inst3|inst12|inst, registered_multiply, 1
+instance = comp, \inst2|inst11|inst\, inst2|inst11|inst, registered_multiply, 1
+instance = comp, \inst1|inst10|inst\, inst1|inst10|inst, registered_multiply, 1
+instance = comp, \inst|inst9|inst\, inst|inst9|inst, registered_multiply, 1
diff --git a/registered_multiply/simulation/modelsim/registered_multiply_vhd.sdo b/registered_multiply/simulation/modelsim/registered_multiply_vhd.sdo
new file mode 100644
index 0000000..ab60ba5
--- /dev/null
+++ b/registered_multiply/simulation/modelsim/registered_multiply_vhd.sdo
@@ -0,0 +1,1347 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "registered_multiply")
+  (DATE "02/19/2016 16:10:48")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (741:741:741) (767:767:767))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (829:829:829) (864:864:864))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (559:559:559) (592:592:592))
+        (IOPATH i o (2266:2266:2266) (2254:2254:2254))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (365:365:365) (411:411:411))
+        (IOPATH i o (2256:2256:2256) (2244:2244:2244))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (649:649:649) (694:694:694))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (640:640:640) (710:710:710))
+        (IOPATH i o (2246:2246:2246) (2234:2234:2234))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (695:695:695) (774:774:774))
+        (IOPATH i o (2236:2236:2236) (2224:2224:2224))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (670:670:670) (742:742:742))
+        (IOPATH i o (3436:3436:3436) (3537:3537:3537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (716:716:716) (793:793:793))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\Output\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (731:731:731) (818:818:818))
+        (IOPATH i o (2226:2226:2226) (2214:2214:2214))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (775:775:775) (936:936:936))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst30\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2768:2768:2768) (3010:3010:3010))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst30)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst12\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2668:2668:2668) (2907:2907:2907))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst12)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1616:1616:1616) (1616:1616:1616))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst27\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2469:2469:2469) (2716:2716:2716))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst27)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst15)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3243:3243:3243) (3476:3476:3476))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1091:1091:1091) (1131:1131:1131))
+        (PORT datad (703:703:703) (773:773:773))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst14)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3079:3079:3079) (3337:3337:3337))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (917:917:917) (967:967:967))
+        (PORT datad (704:704:704) (778:778:778))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\B\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst13)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3385:3385:3385) (3672:3672:3672))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst11\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2984:2984:2984) (3214:3214:3214))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst11)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1616:1616:1616) (1616:1616:1616))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (264:264:264) (345:345:345))
+        (PORT datad (577:577:577) (635:635:635))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst10)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (3345:3345:3345) (3587:3587:3587))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (389:389:389) (460:460:460))
+        (PORT datad (261:261:261) (338:338:338))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst91)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT asdata (2807:2807:2807) (3053:3053:3053))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\A\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2763:2763:2763) (3032:3032:3032))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1340:1340:1340) (1375:1375:1375))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (287:287:287) (379:379:379))
+        (PORT datad (261:261:261) (340:340:340))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (414:414:414))
+        (PORT datab (288:288:288) (379:379:379))
+        (PORT datac (387:387:387) (458:458:458))
+        (PORT datad (174:174:174) (200:200:200))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (658:658:658) (722:722:722))
+        (PORT datab (292:292:292) (378:378:378))
+        (PORT datac (341:341:341) (365:365:365))
+        (PORT datad (337:337:337) (349:349:349))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (659:659:659) (719:719:719))
+        (PORT datab (571:571:571) (627:627:627))
+        (PORT datac (326:326:326) (346:346:346))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst21\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (477:477:477) (542:542:542))
+        (PORT datad (565:565:565) (616:616:616))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (352:352:352))
+        (PORT datab (612:612:612) (682:682:682))
+        (PORT datac (323:323:323) (343:343:343))
+        (PORT datad (181:181:181) (208:208:208))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (410:410:410))
+        (PORT datab (287:287:287) (377:377:377))
+        (PORT datac (389:389:389) (458:458:458))
+        (PORT datad (259:259:259) (337:337:337))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (287:287:287) (378:378:378))
+        (PORT datad (563:563:563) (617:617:617))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (307:307:307) (416:416:416))
+        (PORT datab (287:287:287) (375:375:375))
+        (PORT datac (201:201:201) (236:236:236))
+        (PORT datad (196:196:196) (222:222:222))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (288:288:288) (378:378:378))
+        (PORT datac (259:259:259) (343:343:343))
+        (PORT datad (566:566:566) (619:619:619))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (409:409:409))
+        (PORT datab (285:285:285) (376:376:376))
+        (PORT datac (201:201:201) (238:238:238))
+        (PORT datad (172:172:172) (197:197:197))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst19\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (478:478:478))
+        (PORT datab (288:288:288) (380:380:380))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (410:410:410))
+        (PORT datab (477:477:477) (542:542:542))
+        (PORT datac (202:202:202) (237:237:237))
+        (PORT datad (321:321:321) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (393:393:393))
+        (PORT datab (201:201:201) (240:240:240))
+        (PORT datac (324:324:324) (356:356:356))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (303:303:303) (299:299:299))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1089:1089:1089) (1128:1128:1128))
+        (PORT datab (677:677:677) (740:740:740))
+        (PORT datac (359:359:359) (379:379:379))
+        (PORT datad (509:509:509) (520:520:520))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (659:659:659) (676:676:676))
+        (PORT datab (240:240:240) (285:285:285))
+        (PORT datac (609:609:609) (629:629:629))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (255:255:255))
+        (PORT datab (236:236:236) (281:281:281))
+        (PORT datac (601:601:601) (623:623:623))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (257:257:257))
+        (PORT datab (237:237:237) (282:282:282))
+        (PORT datac (608:608:608) (626:626:626))
+        (PORT datad (179:179:179) (207:207:207))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (410:410:410))
+        (PORT datab (478:478:478) (542:542:542))
+        (PORT datad (587:587:587) (628:628:628))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (373:373:373))
+        (PORT datab (229:229:229) (271:271:271))
+        (PORT datac (323:323:323) (354:354:354))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (386:386:386) (455:455:455))
+        (PORT datad (216:216:216) (241:241:241))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst12\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (384:384:384) (409:409:409))
+        (PORT datab (816:816:816) (872:872:872))
+        (PORT datac (516:516:516) (516:516:516))
+        (PORT datad (797:797:797) (840:840:840))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1066:1066:1066) (1130:1130:1130))
+        (PORT datab (292:292:292) (384:384:384))
+        (PORT datac (638:638:638) (664:664:664))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (400:400:400))
+        (PORT datab (624:624:624) (646:646:646))
+        (PORT datac (613:613:613) (634:634:634))
+        (PORT datad (341:341:341) (361:361:361))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (866:866:866) (924:924:924))
+        (PORT datab (292:292:292) (384:384:384))
+        (PORT datac (178:178:178) (214:214:214))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (686:686:686) (748:748:748))
+        (PORT datab (747:747:747) (812:812:812))
+        (PORT datac (178:178:178) (215:215:215))
+        (PORT datad (339:339:339) (357:357:357))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (688:688:688) (752:752:752))
+        (PORT datab (746:746:746) (820:820:820))
+        (PORT datac (325:325:325) (347:347:347))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (289:289:289) (381:381:381))
+        (PORT datac (840:840:840) (902:902:902))
+        (PORT datad (857:857:857) (903:903:903))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1066:1066:1066) (1130:1130:1130))
+        (PORT datab (286:286:286) (378:378:378))
+        (PORT datac (842:842:842) (900:900:900))
+        (PORT datad (851:851:851) (846:846:846))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst5\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (245:245:245))
+        (PORT datac (188:188:188) (228:228:228))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (652:652:652) (710:710:710))
+        (PORT datad (423:423:423) (487:487:487))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst14\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (690:690:690) (754:754:754))
+        (PORT datab (746:746:746) (811:811:811))
+        (PORT datac (182:182:182) (219:219:219))
+        (PORT datad (335:335:335) (354:354:354))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (869:869:869) (936:936:936))
+        (PORT datab (290:290:290) (382:382:382))
+        (PORT datac (190:190:190) (230:230:230))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (861:861:861) (918:918:918))
+        (PORT datab (285:285:285) (377:377:377))
+        (PORT datac (182:182:182) (218:218:218))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1067:1067:1067) (1130:1130:1130))
+        (PORT datab (288:288:288) (379:379:379))
+        (PORT datac (178:178:178) (215:215:215))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (311:311:311))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (391:391:391))
+        (PORT datab (361:361:361) (388:388:388))
+        (PORT datac (195:195:195) (228:228:228))
+        (PORT datad (352:352:352) (367:367:367))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst15\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (690:690:690) (754:754:754))
+        (PORT datab (744:744:744) (819:819:819))
+        (PORT datac (324:324:324) (345:345:345))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (536:536:536))
+        (PORT datab (746:746:746) (817:817:817))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (451:451:451) (539:539:539))
+        (PORT datab (743:743:743) (816:816:816))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst40)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst16\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (451:451:451) (538:538:538))
+        (PORT datab (747:747:747) (821:821:821))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst39)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (536:536:536))
+        (PORT datab (747:747:747) (816:816:816))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst38)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1544:1544:1544) (1543:1543:1543))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (526:526:526) (546:546:546))
+        (PORT datab (221:221:221) (261:261:261))
+        (PORT datac (335:335:335) (353:353:353))
+        (PORT datad (492:492:492) (499:499:499))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst37)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst13\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1070:1070:1070) (1132:1132:1132))
+        (PORT datab (289:289:289) (380:380:380))
+        (PORT datac (180:180:180) (217:217:217))
+        (PORT datad (179:179:179) (208:208:208))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst36)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst3\|inst12\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (600:600:600) (655:655:655))
+        (PORT datab (1221:1221:1221) (1266:1266:1266))
+        (PORT datac (186:186:186) (225:225:225))
+        (PORT datad (193:193:193) (227:227:227))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst35)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1558:1558:1558) (1585:1585:1585))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\|inst11\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (739:739:739) (836:836:836))
+        (PORT datac (676:676:676) (759:759:759))
+        (PORT datad (1021:1021:1021) (1038:1038:1038))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst34)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst1\|inst10\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (789:789:789) (889:889:889))
+        (PORT datab (709:709:709) (797:797:797))
+        (PORT datac (803:803:803) (808:808:808))
+        (PORT datad (760:760:760) (781:781:781))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst33)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\|inst9\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (788:788:788) (885:885:885))
+        (PORT datab (934:934:934) (1004:1004:1004))
+        (PORT datac (710:710:710) (799:799:799))
+        (PORT datad (845:845:845) (919:919:919))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst32)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (708:708:708) (802:802:802))
+        (PORT datad (745:745:745) (841:841:841))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst31)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1069:1069:1069) (1069:1069:1069))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/stopwatch/db/logic_util_heursitic.dat b/stopwatch/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..8ba8243
--- /dev/null
+++ b/stopwatch/db/logic_util_heursitic.dat
diff --git a/stopwatch/db/prev_cmp_stopwatch.qmsg b/stopwatch/db/prev_cmp_stopwatch.qmsg
new file mode 100644
index 0000000..c229a4a
--- /dev/null
+++ b/stopwatch/db/prev_cmp_stopwatch.qmsg
@@ -0,0 +1,14 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503902567 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503902568 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:25:02 2016 " "Processing started: Fri Feb 26 16:25:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503902568 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503902568 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch " "Command: quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503902568 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456503902791 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/ten_counter/ten_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/ten_counter/ten_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_counter " "Found entity 1: ten_counter" {  } { { "../ten_counter/ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503902827 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503902827 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/one_hertz_clock/one_hertz_clock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/one_hertz_clock/one_hertz_clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 one_hertz_clock " "Found entity 1: one_hertz_clock" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503902829 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503902829 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/bcd_to_display/bcd_to_display.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/bcd_to_display/bcd_to_display.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bcd_to_display " "Found entity 1: bcd_to_display" {  } { { "../bcd_to_display/bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503902830 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503902830 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Git/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503902831 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503902831 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopwatch.bdf 1 1 " "Found 1 design units, including 1 entities, in source file stopwatch.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stopwatch " "Found entity 1: stopwatch" {  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503902833 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503902833 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "stopwatch " "Elaborating entity \"stopwatch\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456503902851 ""}
+{ "Error" "EGDFX_SYMBOL_OR_BLOCK_ALREADY_DEFINED" "GND inst27 " "Logic function of type GND and instance \"inst27\" is already defined as a signal name or another logic function" {  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 792 872 904 824 "inst27" "" } { 416 856 1040 512 "inst27" "" } } } }  } 0 275062 "Logic function of type %1!s! and instance \"%2!s!\" is already defined as a signal name or another logic function" 0 0 "Quartus II" 0 -1 1456503902854 ""}
+{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" {  } {  } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1456503902854 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503902893 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Feb 26 16:25:02 2016 " "Processing ended: Fri Feb 26 16:25:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503902893 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503902893 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503902893 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503902893 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 0 s " "Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503903488 ""}
diff --git a/stopwatch/db/stopwatch.(0).cnf.cdb b/stopwatch/db/stopwatch.(0).cnf.cdb
new file mode 100644
index 0000000..ebce4b2
--- /dev/null
+++ b/stopwatch/db/stopwatch.(0).cnf.cdb
diff --git a/stopwatch/db/stopwatch.(0).cnf.hdb b/stopwatch/db/stopwatch.(0).cnf.hdb
new file mode 100644
index 0000000..7967881
--- /dev/null
+++ b/stopwatch/db/stopwatch.(0).cnf.hdb
diff --git a/stopwatch/db/stopwatch.(1).cnf.cdb b/stopwatch/db/stopwatch.(1).cnf.cdb
new file mode 100644
index 0000000..77ebcd9
--- /dev/null
+++ b/stopwatch/db/stopwatch.(1).cnf.cdb
diff --git a/stopwatch/db/stopwatch.(1).cnf.hdb b/stopwatch/db/stopwatch.(1).cnf.hdb
new file mode 100644
index 0000000..a3a2992
--- /dev/null
+++ b/stopwatch/db/stopwatch.(1).cnf.hdb
diff --git a/stopwatch/db/stopwatch.(2).cnf.cdb b/stopwatch/db/stopwatch.(2).cnf.cdb
new file mode 100644
index 0000000..4498dcc
--- /dev/null
+++ b/stopwatch/db/stopwatch.(2).cnf.cdb
diff --git a/stopwatch/db/stopwatch.(2).cnf.hdb b/stopwatch/db/stopwatch.(2).cnf.hdb
new file mode 100644
index 0000000..4716d23
--- /dev/null
+++ b/stopwatch/db/stopwatch.(2).cnf.hdb
diff --git a/stopwatch/db/stopwatch.(3).cnf.cdb b/stopwatch/db/stopwatch.(3).cnf.cdb
new file mode 100644
index 0000000..f118235
--- /dev/null
+++ b/stopwatch/db/stopwatch.(3).cnf.cdb
diff --git a/stopwatch/db/stopwatch.(3).cnf.hdb b/stopwatch/db/stopwatch.(3).cnf.hdb
new file mode 100644
index 0000000..9f15acd
--- /dev/null
+++ b/stopwatch/db/stopwatch.(3).cnf.hdb
diff --git a/stopwatch/db/stopwatch.(4).cnf.cdb b/stopwatch/db/stopwatch.(4).cnf.cdb
new file mode 100644
index 0000000..5545262
--- /dev/null
+++ b/stopwatch/db/stopwatch.(4).cnf.cdb
diff --git a/stopwatch/db/stopwatch.(4).cnf.hdb b/stopwatch/db/stopwatch.(4).cnf.hdb
new file mode 100644
index 0000000..4483151
--- /dev/null
+++ b/stopwatch/db/stopwatch.(4).cnf.hdb
diff --git a/stopwatch/db/stopwatch.asm.qmsg b/stopwatch/db/stopwatch.asm.qmsg
new file mode 100644
index 0000000..f386940
--- /dev/null
+++ b/stopwatch/db/stopwatch.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504673583 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504673584 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:53 2016 " "Processing started: Fri Feb 26 16:37:53 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504673584 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456504673584 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch " "Command: quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456504673585 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456504674224 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456504674242 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "424 " "Peak virtual memory: 424 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504674473 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:54 2016 " "Processing ended: Fri Feb 26 16:37:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504674473 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504674473 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504674473 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456504674473 ""}
diff --git a/stopwatch/db/stopwatch.asm.rdb b/stopwatch/db/stopwatch.asm.rdb
new file mode 100644
index 0000000..e79730f
--- /dev/null
+++ b/stopwatch/db/stopwatch.asm.rdb
diff --git a/stopwatch/db/stopwatch.asm_labs.ddb b/stopwatch/db/stopwatch.asm_labs.ddb
new file mode 100644
index 0000000..05ca717
--- /dev/null
+++ b/stopwatch/db/stopwatch.asm_labs.ddb
diff --git a/stopwatch/db/stopwatch.cbx.xml b/stopwatch/db/stopwatch.cbx.xml
new file mode 100644
index 0000000..87e847e
--- /dev/null
+++ b/stopwatch/db/stopwatch.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="stopwatch">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/stopwatch/db/stopwatch.cmp.bpm b/stopwatch/db/stopwatch.cmp.bpm
new file mode 100644
index 0000000..055bce5
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.bpm
diff --git a/stopwatch/db/stopwatch.cmp.cdb b/stopwatch/db/stopwatch.cmp.cdb
new file mode 100644
index 0000000..38c2cce
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.cdb
diff --git a/stopwatch/db/stopwatch.cmp.hdb b/stopwatch/db/stopwatch.cmp.hdb
new file mode 100644
index 0000000..d695711
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.hdb
diff --git a/stopwatch/db/stopwatch.cmp.idb b/stopwatch/db/stopwatch.cmp.idb
new file mode 100644
index 0000000..9859f0e
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.idb
diff --git a/stopwatch/db/stopwatch.cmp.kpt b/stopwatch/db/stopwatch.cmp.kpt
new file mode 100644
index 0000000..8746ad7
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.kpt
diff --git a/stopwatch/db/stopwatch.cmp.logdb b/stopwatch/db/stopwatch.cmp.logdb
new file mode 100644
index 0000000..334d57a
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.logdb
@@ -0,0 +1,75 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,33;0;33;0;0;33;33;0;33;33;0;29;0;0;4;0;29;4;0;0;0;29;0;0;0;0;0;33;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;33;0;33;33;0;0;33;0;0;33;4;33;33;29;33;4;29;33;33;33;4;33;33;33;33;33;0;33;33,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Point,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DIG3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Split,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Start,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Reset,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DE0CLOCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/stopwatch/db/stopwatch.cmp.rdb b/stopwatch/db/stopwatch.cmp.rdb
new file mode 100644
index 0000000..f9feecf
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp.rdb
diff --git a/stopwatch/db/stopwatch.cmp_merge.kpt b/stopwatch/db/stopwatch.cmp_merge.kpt
new file mode 100644
index 0000000..d4d0bcf
--- /dev/null
+++ b/stopwatch/db/stopwatch.cmp_merge.kpt
diff --git a/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..c86ea3e
--- /dev/null
+++ b/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..ab8d5bc
--- /dev/null
+++ b/stopwatch/db/stopwatch.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/stopwatch/db/stopwatch.db_info b/stopwatch/db/stopwatch.db_info
new file mode 100644
index 0000000..f679447
--- /dev/null
+++ b/stopwatch/db/stopwatch.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 16:37:39 2016
diff --git a/stopwatch/db/stopwatch.fit.qmsg b/stopwatch/db/stopwatch.fit.qmsg
new file mode 100644
index 0000000..e4d935d
--- /dev/null
+++ b/stopwatch/db/stopwatch.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456504666492 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "stopwatch EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"stopwatch\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456504666717 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504666762 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504666762 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456504666762 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456504666833 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504667022 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504667022 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456504667022 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456504667022 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 298 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504667024 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 300 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504667024 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 302 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504667024 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 304 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504667024 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 306 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456504667024 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456504667024 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456504667025 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "17 " "TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1456504667866 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopwatch.sdc " "Synopsys Design Constraints File file not found: 'stopwatch.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456504667866 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456504667866 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456504667868 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1456504667869 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456504667869 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ten_counter:inst6\|inst23  " "Automatically promoted node ten_counter:inst6\|inst23 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456504667877 ""}  } { { "../ten_counter/ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { { 360 1088 1152 440 "inst23" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ten_counter:inst6|inst23 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/stopwatch/" { { 0 { 0 ""} 0 136 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456504667877 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456504668015 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456504668015 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456504668015 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456504668016 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456504668016 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456504668016 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456504668016 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456504668016 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456504668017 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456504668017 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456504668017 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504668037 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456504668522 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504668589 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456504668596 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456504668944 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504668944 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456504669124 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y20 X30_Y29 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29" {  } { { "loc" "" { Generic "C:/Git/stopwatch/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} 21 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456504669622 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456504669622 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504670790 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456504670792 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456504670792 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456504670800 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456504670829 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456504671066 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456504671093 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456504671182 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456504671688 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Git/stopwatch/output_files/stopwatch.fit.smsg " "Generated suppressed messages file C:/Git/stopwatch/output_files/stopwatch.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456504672391 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1094 " "Peak virtual memory: 1094 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504672570 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:52 2016 " "Processing ended: Fri Feb 26 16:37:52 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504672570 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504672570 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504672570 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456504672570 ""}
diff --git a/stopwatch/db/stopwatch.hier_info b/stopwatch/db/stopwatch.hier_info
new file mode 100644
index 0000000..62e166a
--- /dev/null
+++ b/stopwatch/db/stopwatch.hier_info
@@ -0,0 +1,570 @@
+|stopwatch
+Point <= <GND>
+DIG0[0] <= Out0[0].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[1] <= Out0[1].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[2] <= Out0[2].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[3] <= Out0[3].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[4] <= Out0[4].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[5] <= Out0[5].DB_MAX_OUTPUT_PORT_TYPE
+DIG0[6] <= Out0[6].DB_MAX_OUTPUT_PORT_TYPE
+DE0CLOCK => one_hertz_clock:inst9.CLK
+Reset => inst30.IN0
+Reset => inst29.IN0
+Start => inst31.IN1
+Start => inst29.IN1
+Split => inst7.LATCH_ENABLE
+Split => inst13.LATCH_ENABLE
+Split => inst17.LATCH_ENABLE
+Split => inst21.LATCH_ENABLE
+Split => inst10.LATCH_ENABLE
+Split => inst14.LATCH_ENABLE
+Split => inst18.LATCH_ENABLE
+Split => inst22.LATCH_ENABLE
+Split => inst11.LATCH_ENABLE
+Split => inst15.LATCH_ENABLE
+Split => inst19.LATCH_ENABLE
+Split => inst23.LATCH_ENABLE
+Split => inst12.LATCH_ENABLE
+Split => inst16.LATCH_ENABLE
+Split => inst20.LATCH_ENABLE
+Split => inst24.LATCH_ENABLE
+DIG1[0] <= Out1[0].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[1] <= Out1[1].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[2] <= Out1[2].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[3] <= Out1[3].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[4] <= Out1[4].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[5] <= Out1[5].DB_MAX_OUTPUT_PORT_TYPE
+DIG1[6] <= Out1[6].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[0] <= Out2[0].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[1] <= Out2[1].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[2] <= Out2[2].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[3] <= Out2[3].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[4] <= Out2[4].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[5] <= Out2[5].DB_MAX_OUTPUT_PORT_TYPE
+DIG2[6] <= Out2[6].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[0] <= Out3[0].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[1] <= Out3[1].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[2] <= Out3[2].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[3] <= Out3[3].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[4] <= Out3[4].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[5] <= Out3[5].DB_MAX_OUTPUT_PORT_TYPE
+DIG3[6] <= Out3[6].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|bcd_to_display:inst
+DISPout[0] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[2] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[3] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[4] <= inst12.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[5] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[6] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+BCDin[0] => inst4.IN0
+BCDin[0] => inst16.IN1
+BCDin[0] => inst9.IN0
+BCDin[0] => inst19.IN0
+BCDin[0] => inst6.IN3
+BCDin[0] => inst14.IN0
+BCDin[0] => inst26.IN0
+BCDin[0] => inst36.IN0
+BCDin[0] => inst37.IN0
+BCDin[1] => inst8.IN0
+BCDin[1] => inst10.IN0
+BCDin[1] => inst19.IN1
+BCDin[1] => inst13.IN0
+BCDin[1] => inst25.IN0
+BCDin[1] => inst24.IN0
+BCDin[1] => inst28.IN0
+BCDin[1] => inst31.IN0
+BCDin[1] => inst34.IN0
+BCDin[1] => inst40.IN0
+BCDin[1] => inst41.IN0
+BCDin[2] => inst3.IN0
+BCDin[2] => inst16.IN0
+BCDin[2] => inst11.IN0
+BCDin[2] => inst6.IN2
+BCDin[2] => inst15.IN0
+BCDin[2] => inst26.IN2
+BCDin[2] => inst33.IN1
+BCDin[2] => inst39.IN1
+BCDin[2] => inst38.IN0
+BCDin[3] => inst8.IN3
+BCDin[3] => inst6.IN0
+BCDin[3] => inst5.IN0
+BCDin[3] => inst2.IN0
+BCDin[3] => inst1.IN0
+
+
+|stopwatch|ten_counter:inst1
+cout <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+CLR => inst22.IN0
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst3.CLK
+CLK => inst2.CLK
+count[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9
+1_Hz <= inst30.DB_MAX_OUTPUT_PORT_TYPE
+CLK => inst77.CLK
+CLK => inst72.CLK
+CLK => inst67.CLK
+CLK => inst63.CLK
+CLK => inst58.CLK
+CLK => inst48.CLK
+CLK => inst43.CLK
+CLK => inst389.CLK
+CLK => inst50.CLK
+CLK => inst459.CLK
+CLK => inst40.CLK
+CLK => inst38.CLK
+CLK => inst3799999.CLK
+CLK => inst82.CLK
+CLK => inst97.CLK
+CLK => inst92.CLK
+CLK => inst87.CLK
+CLK => inst102.CLK
+CLK => inst107.CLK
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst78
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst73
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst68
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst37
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst59
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst49
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst449
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst369
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst51
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst46
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst41
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst36
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst999
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst83
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst98
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst93
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst88
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst103
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|one_hertz_clock:inst9|full_adder:inst108
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|bcd_to_display:inst3
+DISPout[0] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[2] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[3] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[4] <= inst12.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[5] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[6] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+BCDin[0] => inst4.IN0
+BCDin[0] => inst16.IN1
+BCDin[0] => inst9.IN0
+BCDin[0] => inst19.IN0
+BCDin[0] => inst6.IN3
+BCDin[0] => inst14.IN0
+BCDin[0] => inst26.IN0
+BCDin[0] => inst36.IN0
+BCDin[0] => inst37.IN0
+BCDin[1] => inst8.IN0
+BCDin[1] => inst10.IN0
+BCDin[1] => inst19.IN1
+BCDin[1] => inst13.IN0
+BCDin[1] => inst25.IN0
+BCDin[1] => inst24.IN0
+BCDin[1] => inst28.IN0
+BCDin[1] => inst31.IN0
+BCDin[1] => inst34.IN0
+BCDin[1] => inst40.IN0
+BCDin[1] => inst41.IN0
+BCDin[2] => inst3.IN0
+BCDin[2] => inst16.IN0
+BCDin[2] => inst11.IN0
+BCDin[2] => inst6.IN2
+BCDin[2] => inst15.IN0
+BCDin[2] => inst26.IN2
+BCDin[2] => inst33.IN1
+BCDin[2] => inst39.IN1
+BCDin[2] => inst38.IN0
+BCDin[3] => inst8.IN3
+BCDin[3] => inst6.IN0
+BCDin[3] => inst5.IN0
+BCDin[3] => inst2.IN0
+BCDin[3] => inst1.IN0
+
+
+|stopwatch|ten_counter:inst2
+cout <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+CLR => inst22.IN0
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst3.CLK
+CLK => inst2.CLK
+count[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|bcd_to_display:inst4
+DISPout[0] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[2] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[3] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[4] <= inst12.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[5] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[6] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+BCDin[0] => inst4.IN0
+BCDin[0] => inst16.IN1
+BCDin[0] => inst9.IN0
+BCDin[0] => inst19.IN0
+BCDin[0] => inst6.IN3
+BCDin[0] => inst14.IN0
+BCDin[0] => inst26.IN0
+BCDin[0] => inst36.IN0
+BCDin[0] => inst37.IN0
+BCDin[1] => inst8.IN0
+BCDin[1] => inst10.IN0
+BCDin[1] => inst19.IN1
+BCDin[1] => inst13.IN0
+BCDin[1] => inst25.IN0
+BCDin[1] => inst24.IN0
+BCDin[1] => inst28.IN0
+BCDin[1] => inst31.IN0
+BCDin[1] => inst34.IN0
+BCDin[1] => inst40.IN0
+BCDin[1] => inst41.IN0
+BCDin[2] => inst3.IN0
+BCDin[2] => inst16.IN0
+BCDin[2] => inst11.IN0
+BCDin[2] => inst6.IN2
+BCDin[2] => inst15.IN0
+BCDin[2] => inst26.IN2
+BCDin[2] => inst33.IN1
+BCDin[2] => inst39.IN1
+BCDin[2] => inst38.IN0
+BCDin[3] => inst8.IN3
+BCDin[3] => inst6.IN0
+BCDin[3] => inst5.IN0
+BCDin[3] => inst2.IN0
+BCDin[3] => inst1.IN0
+
+
+|stopwatch|ten_counter:inst6
+cout <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+CLR => inst22.IN0
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst3.CLK
+CLK => inst2.CLK
+count[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopwatch|bcd_to_display:inst5
+DISPout[0] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[2] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[3] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[4] <= inst12.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[5] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+DISPout[6] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+BCDin[0] => inst4.IN0
+BCDin[0] => inst16.IN1
+BCDin[0] => inst9.IN0
+BCDin[0] => inst19.IN0
+BCDin[0] => inst6.IN3
+BCDin[0] => inst14.IN0
+BCDin[0] => inst26.IN0
+BCDin[0] => inst36.IN0
+BCDin[0] => inst37.IN0
+BCDin[1] => inst8.IN0
+BCDin[1] => inst10.IN0
+BCDin[1] => inst19.IN1
+BCDin[1] => inst13.IN0
+BCDin[1] => inst25.IN0
+BCDin[1] => inst24.IN0
+BCDin[1] => inst28.IN0
+BCDin[1] => inst31.IN0
+BCDin[1] => inst34.IN0
+BCDin[1] => inst40.IN0
+BCDin[1] => inst41.IN0
+BCDin[2] => inst3.IN0
+BCDin[2] => inst16.IN0
+BCDin[2] => inst11.IN0
+BCDin[2] => inst6.IN2
+BCDin[2] => inst15.IN0
+BCDin[2] => inst26.IN2
+BCDin[2] => inst33.IN1
+BCDin[2] => inst39.IN1
+BCDin[2] => inst38.IN0
+BCDin[3] => inst8.IN3
+BCDin[3] => inst6.IN0
+BCDin[3] => inst5.IN0
+BCDin[3] => inst2.IN0
+BCDin[3] => inst1.IN0
+
+
+|stopwatch|ten_counter:inst8
+cout <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+CLR => inst22.IN0
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst3.CLK
+CLK => inst2.CLK
+count[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/stopwatch/db/stopwatch.hif b/stopwatch/db/stopwatch.hif
new file mode 100644
index 0000000..43df4af
--- /dev/null
+++ b/stopwatch/db/stopwatch.hif
diff --git a/stopwatch/db/stopwatch.ipinfo b/stopwatch/db/stopwatch.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/stopwatch/db/stopwatch.ipinfo
diff --git a/stopwatch/db/stopwatch.lpc.html b/stopwatch/db/stopwatch.lpc.html
new file mode 100644
index 0000000..2132e63
--- /dev/null
+++ b/stopwatch/db/stopwatch.lpc.html
@@ -0,0 +1,466 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst8</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >5</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst108</TD>
+<TD >3</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst103</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst88</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst93</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst98</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst83</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst999</TD>
+<TD >3</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst36</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst41</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst46</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst51</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst369</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst449</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst49</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst59</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst37</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst68</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst73</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9|inst78</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/stopwatch/db/stopwatch.lpc.rdb b/stopwatch/db/stopwatch.lpc.rdb
new file mode 100644
index 0000000..4434f8f
--- /dev/null
+++ b/stopwatch/db/stopwatch.lpc.rdb
diff --git a/stopwatch/db/stopwatch.lpc.txt b/stopwatch/db/stopwatch.lpc.txt
new file mode 100644
index 0000000..7e04f64
--- /dev/null
+++ b/stopwatch/db/stopwatch.lpc.txt
@@ -0,0 +1,34 @@
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                         ;
++---------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy     ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++---------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst8         ; 2     ; 1              ; 0            ; 1              ; 5      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst5         ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6         ; 2     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst4         ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst2         ; 2     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst3         ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst108 ; 3     ; 2              ; 0            ; 2              ; 2      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst103 ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst88  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst93  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst98  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst83  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst999 ; 3     ; 2              ; 0            ; 2              ; 2      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst36  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst41  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst46  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst51  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst369 ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst449 ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst49  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst59  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst37  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst68  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst73  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9|inst78  ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9         ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst1         ; 2     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst          ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++---------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/stopwatch/db/stopwatch.map.ammdb b/stopwatch/db/stopwatch.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.ammdb
diff --git a/stopwatch/db/stopwatch.map.bpm b/stopwatch/db/stopwatch.map.bpm
new file mode 100644
index 0000000..1b9cd6b
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.bpm
diff --git a/stopwatch/db/stopwatch.map.cdb b/stopwatch/db/stopwatch.map.cdb
new file mode 100644
index 0000000..fc04273
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.cdb
diff --git a/stopwatch/db/stopwatch.map.hdb b/stopwatch/db/stopwatch.map.hdb
new file mode 100644
index 0000000..e180255
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.hdb
diff --git a/stopwatch/db/stopwatch.map.kpt b/stopwatch/db/stopwatch.map.kpt
new file mode 100644
index 0000000..6b586e2
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.kpt
diff --git a/stopwatch/db/stopwatch.map.logdb b/stopwatch/db/stopwatch.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopwatch/db/stopwatch.map.qmsg b/stopwatch/db/stopwatch.map.qmsg
new file mode 100644
index 0000000..de3726d
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.qmsg
@@ -0,0 +1,22 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504664168 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504664170 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:43 2016 " "Processing started: Fri Feb 26 16:37:43 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504664170 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456504664170 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch " "Command: quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456504664170 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456504664412 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/ten_counter/ten_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/ten_counter/ten_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_counter " "Found entity 1: ten_counter" {  } { { "../ten_counter/ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504664447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504664447 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/one_hertz_clock/one_hertz_clock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/one_hertz_clock/one_hertz_clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 one_hertz_clock " "Found entity 1: one_hertz_clock" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504664449 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504664449 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/bcd_to_display/bcd_to_display.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/bcd_to_display/bcd_to_display.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 bcd_to_display " "Found entity 1: bcd_to_display" {  } { { "../bcd_to_display/bcd_to_display.bdf" "" { Schematic "C:/Git/bcd_to_display/bcd_to_display.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504664450 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504664450 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/git/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /git/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Git/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504664451 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504664451 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopwatch.bdf 1 1 " "Found 1 design units, including 1 entities, in source file stopwatch.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stopwatch " "Found entity 1: stopwatch" {  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456504664453 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456504664453 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "stopwatch " "Elaborating entity \"stopwatch\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456504664472 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd_to_display bcd_to_display:inst " "Elaborating entity \"bcd_to_display\" for hierarchy \"bcd_to_display:inst\"" {  } { { "stopwatch.bdf" "inst" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 176 856 1040 272 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664474 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ten_counter ten_counter:inst1 " "Elaborating entity \"ten_counter\" for hierarchy \"ten_counter:inst1\"" {  } { { "stopwatch.bdf" "inst1" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 176 640 776 272 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664483 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "one_hertz_clock one_hertz_clock:inst9 " "Elaborating entity \"one_hertz_clock\" for hierarchy \"one_hertz_clock:inst9\"" {  } { { "stopwatch.bdf" "inst9" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 352 368 464 448 "inst9" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664484 ""}
+{ "Warning" "WGDFX_NOT_ALL_BITS_USED" "N\[14..5\] " "Not all bits in bus \"N\[14..5\]\" are used" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } { 480 312 336 496 "N\[6\]" "" } { 496 312 336 512 "N\[7\]" "" } { 472 496 521 488 "N\[9\]" "" } { 488 496 526 504 "N\[10\]" "" } { 504 496 526 520 "N\[11\]" "" } { 520 496 526 536 "N\[12\]" "" } { 552 496 523 568 "N\[14\]" "" } { 1288 968 997 1304 "N\[5\]" "" } { 1408 968 997 1424 "N\[6\]" "" } { 1528 968 997 1544 "N\[7\]" "" } { 1768 968 997 1784 "N\[9\]" "" } { 1888 968 1003 1904 "N\[10\]" "" } { 2008 968 1003 2024 "N\[11\]" "" } { 2128 968 1003 2144 "N\[12\]" "" } { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275089 "Not all bits in bus \"%1!s!\" are used" 0 0 "Quartus II" 0 -1 1456504664485 ""}
+{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "N " "Converted elements in bus name \"N\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[5\] N5 " "Converted element name(s) from \"N\[5\]\" to \"N5\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[6\] N6 " "Converted element name(s) from \"N\[6\]\" to \"N6\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 480 312 336 496 "N\[6\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[7\] N7 " "Converted element name(s) from \"N\[7\]\" to \"N7\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 496 312 336 512 "N\[7\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[9\] N9 " "Converted element name(s) from \"N\[9\]\" to \"N9\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 472 496 521 488 "N\[9\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[10\] N10 " "Converted element name(s) from \"N\[10\]\" to \"N10\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 488 496 526 504 "N\[10\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[11\] N11 " "Converted element name(s) from \"N\[11\]\" to \"N11\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 504 496 526 520 "N\[11\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[12\] N12 " "Converted element name(s) from \"N\[12\]\" to \"N12\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 520 496 526 536 "N\[12\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[14\] N14 " "Converted element name(s) from \"N\[14\]\" to \"N14\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 552 496 523 568 "N\[14\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[5\] N5 " "Converted element name(s) from \"N\[5\]\" to \"N5\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 1288 968 997 1304 "N\[5\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[6\] N6 " "Converted element name(s) from \"N\[6\]\" to \"N6\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 1408 968 997 1424 "N\[6\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[7\] N7 " "Converted element name(s) from \"N\[7\]\" to \"N7\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 1528 968 997 1544 "N\[7\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[9\] N9 " "Converted element name(s) from \"N\[9\]\" to \"N9\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 1768 968 997 1784 "N\[9\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[10\] N10 " "Converted element name(s) from \"N\[10\]\" to \"N10\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 1888 968 1003 1904 "N\[10\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[11\] N11 " "Converted element name(s) from \"N\[11\]\" to \"N11\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 2008 968 1003 2024 "N\[11\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[12\] N12 " "Converted element name(s) from \"N\[12\]\" to \"N12\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 2128 968 1003 2144 "N\[12\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "N\[14\] N14 " "Converted element name(s) from \"N\[14\]\" to \"N14\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275081 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664485 ""}  } { { "../one_hertz_clock/one_hertz_clock.bdf" "" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 464 312 341 480 "N\[5\]" "" } { 480 312 336 496 "N\[6\]" "" } { 496 312 336 512 "N\[7\]" "" } { 472 496 521 488 "N\[9\]" "" } { 488 496 526 504 "N\[10\]" "" } { 504 496 526 520 "N\[11\]" "" } { 520 496 526 536 "N\[12\]" "" } { 552 496 523 568 "N\[14\]" "" } { 1288 968 997 1304 "N\[5\]" "" } { 1408 968 997 1424 "N\[6\]" "" } { 1528 968 997 1544 "N\[7\]" "" } { 1768 968 997 1784 "N\[9\]" "" } { 1888 968 1003 1904 "N\[10\]" "" } { 2008 968 1003 2024 "N\[11\]" "" } { 2128 968 1003 2144 "N\[12\]" "" } { 2368 968 1003 2384 "N\[14\]" "" } } } }  } 0 275080 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "Quartus II" 0 -1 1456504664485 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder one_hertz_clock:inst9\|full_adder:inst78 " "Elaborating entity \"full_adder\" for hierarchy \"one_hertz_clock:inst9\|full_adder:inst78\"" {  } { { "../one_hertz_clock/one_hertz_clock.bdf" "inst78" { Schematic "C:/Git/one_hertz_clock/one_hertz_clock.bdf" { { 2120 488 584 2216 "inst78" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456504664487 ""}
+{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "inst28 " "Latch inst28 has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA Reset " "Ports D and ENA on the latch are fed by the same signal Reset" {  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 528 128 296 544 "Reset" "" } } } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Quartus II" 0 -1 1456504664848 ""}  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 512 504 568 592 "inst28" "" } } } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Quartus II" 0 -1 1456504664848 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "Point GND " "Pin \"Point\" is stuck at GND" {  } { { "stopwatch.bdf" "" { Schematic "C:/Git/stopwatch/stopwatch.bdf" { { 800 920 1096 816 "Point" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456504664878 "|stopwatch|Point"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456504664878 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456504664973 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456504665182 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456504665182 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "130 " "Implemented 130 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456504665212 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456504665212 ""} { "Info" "ICUT_CUT_TM_LCELLS" "97 " "Implemented 97 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456504665212 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456504665212 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "463 " "Peak virtual memory: 463 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504665224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:45 2016 " "Processing ended: Fri Feb 26 16:37:45 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504665224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504665224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504665224 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456504665224 ""}
diff --git a/stopwatch/db/stopwatch.map.rdb b/stopwatch/db/stopwatch.map.rdb
new file mode 100644
index 0000000..90f8016
--- /dev/null
+++ b/stopwatch/db/stopwatch.map.rdb
diff --git a/stopwatch/db/stopwatch.map_bb.cdb b/stopwatch/db/stopwatch.map_bb.cdb
new file mode 100644
index 0000000..57a96f8
--- /dev/null
+++ b/stopwatch/db/stopwatch.map_bb.cdb
diff --git a/stopwatch/db/stopwatch.map_bb.hdb b/stopwatch/db/stopwatch.map_bb.hdb
new file mode 100644
index 0000000..758909f
--- /dev/null
+++ b/stopwatch/db/stopwatch.map_bb.hdb
diff --git a/stopwatch/db/stopwatch.map_bb.logdb b/stopwatch/db/stopwatch.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopwatch/db/stopwatch.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopwatch/db/stopwatch.pplq.rdb b/stopwatch/db/stopwatch.pplq.rdb
new file mode 100644
index 0000000..8502917
--- /dev/null
+++ b/stopwatch/db/stopwatch.pplq.rdb
diff --git a/stopwatch/db/stopwatch.pre_map.hdb b/stopwatch/db/stopwatch.pre_map.hdb
new file mode 100644
index 0000000..d429505
--- /dev/null
+++ b/stopwatch/db/stopwatch.pre_map.hdb
diff --git a/stopwatch/db/stopwatch.pti_db_list.ddb b/stopwatch/db/stopwatch.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/stopwatch/db/stopwatch.pti_db_list.ddb
diff --git a/stopwatch/db/stopwatch.root_partition.map.reg_db.cdb b/stopwatch/db/stopwatch.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..546fd89
--- /dev/null
+++ b/stopwatch/db/stopwatch.root_partition.map.reg_db.cdb
diff --git a/stopwatch/db/stopwatch.routing.rdb b/stopwatch/db/stopwatch.routing.rdb
new file mode 100644
index 0000000..06ab9ab
--- /dev/null
+++ b/stopwatch/db/stopwatch.routing.rdb
diff --git a/stopwatch/db/stopwatch.rtlv.hdb b/stopwatch/db/stopwatch.rtlv.hdb
new file mode 100644
index 0000000..86fe913
--- /dev/null
+++ b/stopwatch/db/stopwatch.rtlv.hdb
diff --git a/stopwatch/db/stopwatch.rtlv_sg.cdb b/stopwatch/db/stopwatch.rtlv_sg.cdb
new file mode 100644
index 0000000..44694f3
--- /dev/null
+++ b/stopwatch/db/stopwatch.rtlv_sg.cdb
diff --git a/stopwatch/db/stopwatch.rtlv_sg_swap.cdb b/stopwatch/db/stopwatch.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..fa38e56
--- /dev/null
+++ b/stopwatch/db/stopwatch.rtlv_sg_swap.cdb
diff --git a/stopwatch/db/stopwatch.sgdiff.cdb b/stopwatch/db/stopwatch.sgdiff.cdb
new file mode 100644
index 0000000..456a903
--- /dev/null
+++ b/stopwatch/db/stopwatch.sgdiff.cdb
diff --git a/stopwatch/db/stopwatch.sgdiff.hdb b/stopwatch/db/stopwatch.sgdiff.hdb
new file mode 100644
index 0000000..095c4f1
--- /dev/null
+++ b/stopwatch/db/stopwatch.sgdiff.hdb
diff --git a/stopwatch/db/stopwatch.sld_design_entry.sci b/stopwatch/db/stopwatch.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/stopwatch/db/stopwatch.sld_design_entry.sci
diff --git a/stopwatch/db/stopwatch.sld_design_entry_dsc.sci b/stopwatch/db/stopwatch.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/stopwatch/db/stopwatch.sld_design_entry_dsc.sci
diff --git a/stopwatch/db/stopwatch.smart_action.txt b/stopwatch/db/stopwatch.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/stopwatch/db/stopwatch.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/stopwatch/db/stopwatch.sta.qmsg b/stopwatch/db/stopwatch.sta.qmsg
new file mode 100644
index 0000000..7d410ec
--- /dev/null
+++ b/stopwatch/db/stopwatch.sta.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456504675683 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456504675684 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:37:55 2016 " "Processing started: Fri Feb 26 16:37:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456504675684 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456504675684 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta stopwatch -c stopwatch " "Command: quartus_sta stopwatch -c stopwatch" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456504675684 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456504675743 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456504675844 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504675844 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504675890 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456504675890 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "17 " "TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1456504675997 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopwatch.sdc " "Synopsys Design Constraints File file not found: 'stopwatch.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456504676027 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456504676028 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DE0CLOCK DE0CLOCK " "create_clock -period 1.000 -name DE0CLOCK DE0CLOCK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name Reset Reset " "create_clock -period 1.000 -name Reset Reset" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name one_hertz_clock:inst9\|inst102 one_hertz_clock:inst9\|inst102 " "create_clock -period 1.000 -name one_hertz_clock:inst9\|inst102 one_hertz_clock:inst9\|inst102" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name Split Split " "create_clock -period 1.000 -name Split Split" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ten_counter:inst1\|inst ten_counter:inst1\|inst " "create_clock -period 1.000 -name ten_counter:inst1\|inst ten_counter:inst1\|inst" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ten_counter:inst2\|inst ten_counter:inst2\|inst " "create_clock -period 1.000 -name ten_counter:inst2\|inst ten_counter:inst2\|inst" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ten_counter:inst6\|inst ten_counter:inst6\|inst " "create_clock -period 1.000 -name ten_counter:inst6\|inst ten_counter:inst6\|inst" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676029 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456504676130 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676131 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456504676131 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456504676139 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456504676156 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456504676156 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.370 " "Worst-case setup slack is -2.370" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.370       -44.235 DE0CLOCK  " "   -2.370       -44.235 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.031        -8.373 Split  " "   -1.031        -8.373 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.923        -0.923 Reset  " "   -0.923        -0.923 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.518        -1.429 ten_counter:inst1\|inst  " "   -0.518        -1.429 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.505        -1.341 ten_counter:inst2\|inst  " "   -0.505        -1.341 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.481        -1.435 one_hertz_clock:inst9\|inst102  " "   -0.481        -1.435 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.054        -0.121 ten_counter:inst6\|inst  " "   -0.054        -0.121 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676158 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.545 " "Worst-case hold slack is -0.545" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.545        -1.713 one_hertz_clock:inst9\|inst102  " "   -0.545        -1.713 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.440        -1.046 Split  " "   -0.440        -1.046 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.401        -1.418 ten_counter:inst2\|inst  " "   -0.401        -1.418 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.349        -6.211 DE0CLOCK  " "   -0.349        -6.211 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.245        -0.692 ten_counter:inst1\|inst  " "   -0.245        -0.692 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.160         0.000 Reset  " "    0.160         0.000 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359         0.000 ten_counter:inst6\|inst  " "    0.359         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676162 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.180 " "Worst-case recovery slack is -2.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.180        -8.720 ten_counter:inst1\|inst  " "   -2.180        -8.720 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.948        -7.792 ten_counter:inst2\|inst  " "   -1.948        -7.792 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.679        -2.716 ten_counter:inst6\|inst  " "   -0.679        -2.716 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.465        -1.860 one_hertz_clock:inst9\|inst102  " "   -0.465        -1.860 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676164 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.969 " "Worst-case removal slack is 0.969" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.969         0.000 one_hertz_clock:inst9\|inst102  " "    0.969         0.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.155         0.000 ten_counter:inst6\|inst  " "    1.155         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.492         0.000 ten_counter:inst2\|inst  " "    2.492         0.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.734         0.000 ten_counter:inst1\|inst  " "    2.734         0.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676166 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 DE0CLOCK  " "   -3.000       -22.000 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 Reset  " "   -3.000        -3.000 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 Split  " "   -3.000        -3.000 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 one_hertz_clock:inst9\|inst102  " "   -1.000        -4.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst1\|inst  " "   -1.000        -4.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst2\|inst  " "   -1.000        -4.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst6\|inst  " "   -1.000        -4.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676168 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456504676278 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456504676298 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456504676617 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676645 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456504676654 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456504676654 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.050 " "Worst-case setup slack is -2.050" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.050       -38.014 DE0CLOCK  " "   -2.050       -38.014 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.772        -5.372 Split  " "   -0.772        -5.372 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.770        -0.770 Reset  " "   -0.770        -0.770 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.355        -0.961 ten_counter:inst1\|inst  " "   -0.355        -0.961 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.347        -0.891 ten_counter:inst2\|inst  " "   -0.347        -0.891 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.325        -0.962 one_hertz_clock:inst9\|inst102  " "   -0.325        -0.962 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.057         0.000 ten_counter:inst6\|inst  " "    0.057         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676657 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.493 " "Worst-case hold slack is -0.493" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.493        -1.569 one_hertz_clock:inst9\|inst102  " "   -0.493        -1.569 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.486        -1.250 Split  " "   -0.486        -1.250 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.386        -1.354 ten_counter:inst2\|inst  " "   -0.386        -1.354 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.361        -6.640 DE0CLOCK  " "   -0.361        -6.640 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.230        -0.633 ten_counter:inst1\|inst  " "   -0.230        -0.633 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104         0.000 Reset  " "    0.104         0.000 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.313         0.000 ten_counter:inst6\|inst  " "    0.313         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676662 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.039 " "Worst-case recovery slack is -2.039" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.039        -8.156 ten_counter:inst1\|inst  " "   -2.039        -8.156 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.819        -7.276 ten_counter:inst2\|inst  " "   -1.819        -7.276 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.688        -2.752 ten_counter:inst6\|inst  " "   -0.688        -2.752 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.412        -1.648 one_hertz_clock:inst9\|inst102  " "   -0.412        -1.648 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676666 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.953 " "Worst-case removal slack is 0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.953         0.000 one_hertz_clock:inst9\|inst102  " "    0.953         0.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.218         0.000 ten_counter:inst6\|inst  " "    1.218         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.412         0.000 ten_counter:inst2\|inst  " "    2.412         0.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.625         0.000 ten_counter:inst1\|inst  " "    2.625         0.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676670 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.000 DE0CLOCK  " "   -3.000       -22.000 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 Reset  " "   -3.000        -3.000 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 Split  " "   -3.000        -3.000 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 one_hertz_clock:inst9\|inst102  " "   -1.000        -4.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst1\|inst  " "   -1.000        -4.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst2\|inst  " "   -1.000        -4.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst6\|inst  " "   -1.000        -4.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676673 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456504676845 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676917 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456504676919 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456504676919 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.896 " "Worst-case setup slack is -0.896" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.896       -16.354 DE0CLOCK  " "   -0.896       -16.354 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.696        -0.696 Reset  " "   -0.696        -0.696 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.125         0.000 Split  " "    0.125         0.000 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.176         0.000 ten_counter:inst1\|inst  " "    0.176         0.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180         0.000 ten_counter:inst2\|inst  " "    0.180         0.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.192         0.000 one_hertz_clock:inst9\|inst102  " "    0.192         0.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.408         0.000 ten_counter:inst6\|inst  " "    0.408         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676924 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.502 " "Worst-case hold slack is -0.502" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.502        -3.342 Split  " "   -0.502        -3.342 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.309        -1.019 one_hertz_clock:inst9\|inst102  " "   -0.309        -1.019 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.283        -5.149 DE0CLOCK  " "   -0.283        -5.149 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.229        -0.830 ten_counter:inst2\|inst  " "   -0.229        -0.830 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.143        -0.438 ten_counter:inst1\|inst  " "   -0.143        -0.438 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.171         0.000 Reset  " "    0.171         0.000 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 ten_counter:inst6\|inst  " "    0.187         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676932 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.972 " "Worst-case recovery slack is -0.972" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.972        -3.888 ten_counter:inst1\|inst  " "   -0.972        -3.888 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.847        -3.388 ten_counter:inst2\|inst  " "   -0.847        -3.388 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.097        -0.388 ten_counter:inst6\|inst  " "   -0.097        -0.388 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.214         0.000 one_hertz_clock:inst9\|inst102  " "    0.214         0.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676938 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.489 " "Worst-case removal slack is 0.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.489         0.000 one_hertz_clock:inst9\|inst102  " "    0.489         0.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.759         0.000 ten_counter:inst6\|inst  " "    0.759         0.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.560         0.000 ten_counter:inst2\|inst  " "    1.560         0.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.702         0.000 ten_counter:inst1\|inst  " "    1.702         0.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676945 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -22.400 DE0CLOCK  " "   -3.000       -22.400 DE0CLOCK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.097 Split  " "   -3.000        -3.097 Split " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.008 Reset  " "   -3.000        -3.008 Reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 one_hertz_clock:inst9\|inst102  " "   -1.000        -4.000 one_hertz_clock:inst9\|inst102 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst1\|inst  " "   -1.000        -4.000 ten_counter:inst1\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst2\|inst  " "   -1.000        -4.000 ten_counter:inst2\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000        -4.000 ten_counter:inst6\|inst  " "   -1.000        -4.000 ten_counter:inst6\|inst " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456504676950 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456504677318 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456504677318 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "488 " "Peak virtual memory: 488 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456504677397 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:37:57 2016 " "Processing ended: Fri Feb 26 16:37:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456504677397 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456504677397 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456504677397 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456504677397 ""}
diff --git a/stopwatch/db/stopwatch.sta.rdb b/stopwatch/db/stopwatch.sta.rdb
new file mode 100644
index 0000000..48c8f6c
--- /dev/null
+++ b/stopwatch/db/stopwatch.sta.rdb
diff --git a/stopwatch/db/stopwatch.sta_cmp.6_slow_1200mv_85c.tdb b/stopwatch/db/stopwatch.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..1524182
--- /dev/null
+++ b/stopwatch/db/stopwatch.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/stopwatch/db/stopwatch.syn_hier_info b/stopwatch/db/stopwatch.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/stopwatch/db/stopwatch.syn_hier_info
diff --git a/stopwatch/db/stopwatch.tis_db_list.ddb b/stopwatch/db/stopwatch.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/stopwatch/db/stopwatch.tis_db_list.ddb
diff --git a/stopwatch/db/stopwatch.tiscmp.fast_1200mv_0c.ddb b/stopwatch/db/stopwatch.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..c555750
--- /dev/null
+++ b/stopwatch/db/stopwatch.tiscmp.fast_1200mv_0c.ddb
diff --git a/stopwatch/db/stopwatch.tiscmp.slow_1200mv_0c.ddb b/stopwatch/db/stopwatch.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..6fca3cc
--- /dev/null
+++ b/stopwatch/db/stopwatch.tiscmp.slow_1200mv_0c.ddb
diff --git a/stopwatch/db/stopwatch.tiscmp.slow_1200mv_85c.ddb b/stopwatch/db/stopwatch.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..29b4429
--- /dev/null
+++ b/stopwatch/db/stopwatch.tiscmp.slow_1200mv_85c.ddb
diff --git a/stopwatch/db/stopwatch.tmw_info b/stopwatch/db/stopwatch.tmw_info
new file mode 100644
index 0000000..bf648b6
--- /dev/null
+++ b/stopwatch/db/stopwatch.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:15
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:08-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
diff --git a/stopwatch/db/stopwatch.vpr.ammdb b/stopwatch/db/stopwatch.vpr.ammdb
new file mode 100644
index 0000000..b92a939
--- /dev/null
+++ b/stopwatch/db/stopwatch.vpr.ammdb
diff --git a/stopwatch/incremental_db/README b/stopwatch/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/stopwatch/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.db_info b/stopwatch/incremental_db/compiled_partitions/stopwatch.db_info
new file mode 100644
index 0000000..69702de
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 15:13:42 2016
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.ammdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.ammdb
new file mode 100644
index 0000000..f2ea3c8
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.ammdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.cdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.cdb
new file mode 100644
index 0000000..ffbd3c4
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.cdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.dfp b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.dfp
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.hdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.hdb
new file mode 100644
index 0000000..c84c8fb
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.hdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.kpt b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.kpt
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.logdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.rcfdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..a31da53
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.cmp.rcfdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.cdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.cdb
new file mode 100644
index 0000000..6d0ad91
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.cdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.dpi b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.dpi
new file mode 100644
index 0000000..58606e5
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.dpi
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.cdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..b4a58b2
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.cdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hb_info b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hb_info
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..861be90
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.hdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.sig b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hdb b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hdb
new file mode 100644
index 0000000..38bf687
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.hdb
diff --git a/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.kpt b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.kpt
new file mode 100644
index 0000000..19f1797
--- /dev/null
+++ b/stopwatch/incremental_db/compiled_partitions/stopwatch.root_partition.map.kpt
diff --git a/stopwatch/output_files/stopwatch.asm.rpt b/stopwatch/output_files/stopwatch.asm.rpt
new file mode 100644
index 0000000..f79748d
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for stopwatch
+Fri Feb 26 16:37:54 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Git/stopwatch/output_files/stopwatch.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 26 16:37:54 2016 ;
+; Revision Name         ; stopwatch                             ;
+; Top-level Entity Name ; stopwatch                             ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------+
+; Assembler Generated Files                   ;
++---------------------------------------------+
+; File Name                                   ;
++---------------------------------------------+
+; C:/Git/stopwatch/output_files/stopwatch.sof ;
++---------------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Assembler Device Options: C:/Git/stopwatch/output_files/stopwatch.sof ;
++----------------+------------------------------------------------------+
+; Option         ; Setting                                              ;
++----------------+------------------------------------------------------+
+; Device         ; EP3C16F484C6                                         ;
+; JTAG usercode  ; 0x000DA3AE                                           ;
+; Checksum       ; 0x000DA3AE                                           ;
++----------------+------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:53 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 424 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:54 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/stopwatch/output_files/stopwatch.done b/stopwatch/output_files/stopwatch.done
new file mode 100644
index 0000000..0f57e05
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.done
@@ -0,0 +1 @@
+Fri Feb 26 16:37:58 2016
diff --git a/stopwatch/output_files/stopwatch.fit.rpt b/stopwatch/output_files/stopwatch.fit.rpt
new file mode 100644
index 0000000..b9c63b7
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.fit.rpt
@@ -0,0 +1,1626 @@
+Fitter report for stopwatch
+Fri Feb 26 16:37:52 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Other Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Estimated Delay Added for Hold Timing Summary
+ 35. Estimated Delay Added for Hold Timing Details
+ 36. Fitter Messages
+ 37. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 26 16:37:52 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; stopwatch                                        ;
+; Top-level Entity Name              ; stopwatch                                        ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 97 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 97 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 35 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 35                                               ;
+; Total pins                         ; 33 / 347 ( 10 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.50        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  16.7%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; Point    ; Missing drive strength and slew rate ;
+; DIG0[6]  ; Missing drive strength and slew rate ;
+; DIG0[5]  ; Missing drive strength and slew rate ;
+; DIG0[4]  ; Missing drive strength and slew rate ;
+; DIG0[3]  ; Missing drive strength and slew rate ;
+; DIG0[2]  ; Missing drive strength and slew rate ;
+; DIG0[1]  ; Missing drive strength and slew rate ;
+; DIG0[0]  ; Missing drive strength and slew rate ;
+; DIG1[6]  ; Missing drive strength and slew rate ;
+; DIG1[5]  ; Missing drive strength and slew rate ;
+; DIG1[4]  ; Missing drive strength and slew rate ;
+; DIG1[3]  ; Missing drive strength and slew rate ;
+; DIG1[2]  ; Missing drive strength and slew rate ;
+; DIG1[1]  ; Missing drive strength and slew rate ;
+; DIG1[0]  ; Missing drive strength and slew rate ;
+; DIG2[6]  ; Missing drive strength and slew rate ;
+; DIG2[5]  ; Missing drive strength and slew rate ;
+; DIG2[4]  ; Missing drive strength and slew rate ;
+; DIG2[3]  ; Missing drive strength and slew rate ;
+; DIG2[2]  ; Missing drive strength and slew rate ;
+; DIG2[1]  ; Missing drive strength and slew rate ;
+; DIG2[0]  ; Missing drive strength and slew rate ;
+; DIG3[6]  ; Missing drive strength and slew rate ;
+; DIG3[5]  ; Missing drive strength and slew rate ;
+; DIG3[4]  ; Missing drive strength and slew rate ;
+; DIG3[3]  ; Missing drive strength and slew rate ;
+; DIG3[2]  ; Missing drive strength and slew rate ;
+; DIG3[1]  ; Missing drive strength and slew rate ;
+; DIG3[0]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 210 ( 0.00 % )     ;
+;     -- Achieved     ; 0 / 210 ( 0.00 % )     ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 200     ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Git/stopwatch/output_files/stopwatch.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 97 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 62                    ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 35                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 42                    ;
+;     -- 3 input functions                    ; 40                    ;
+;     -- <=2 input functions                  ; 15                    ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 97                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 35 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 35 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 8 / 963 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 33 / 347 ( 10 % )     ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 1% / 1% / 1%          ;
+; Maximum fan-out                             ; 23                    ;
+; Highest non-global fan-out                  ; 23                    ;
+; Total fan-out                               ; 485                   ;
+; Average fan-out                             ; 2.32                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 97 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 62                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 35                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 42                   ; 0                              ;
+;     -- 3 input functions                    ; 40                   ; 0                              ;
+;     -- <=2 input functions                  ; 15                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 97                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 35                   ; 0                              ;
+;     -- Dedicated logic registers            ; 35 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 8 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 33                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+; Clock control block                         ; 1 / 24 ( 4 % )       ; 0 / 24 ( 0 % )                 ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 480                  ; 5                              ;
+;     -- Registered Connections               ; 144                  ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 4                    ; 0                              ;
+;     -- Output Ports                         ; 29                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                    ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; DE0CLOCK ; G21   ; 6        ; 41           ; 15           ; 0            ; 19                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Reset    ; H2    ; 1        ; 0            ; 21           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Split    ; F1    ; 1        ; 0            ; 23           ; 0            ; 16                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; Start    ; G3    ; 1        ; 0            ; 23           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DIG0[0] ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[1] ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[2] ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[3] ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[4] ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[5] ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG0[6] ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[0] ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[1] ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[2] ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[3] ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[4] ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[5] ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG1[6] ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[0] ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[1] ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[2] ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[3] ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[4] ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[5] ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG2[6] ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[0] ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[1] ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[2] ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[3] ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[4] ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[5] ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DIG3[6] ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; Point   ; A18   ; 7        ; 32           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                    ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                               ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO                ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO            ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                   ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                  ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                              ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO                      ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                     ; Use as regular IO        ; DIG3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                     ; Use as regular IO        ; DIG2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                     ; Use as regular IO        ; DIG2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                     ; Use as regular IO        ; DIG1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8  ; Use as regular IO        ; DIG0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                     ; Use as regular IO        ; DIG1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                     ; Use as regular IO        ; DIG1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                     ; Use as regular IO        ; DIG1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                    ; Use as regular IO        ; DIG1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                    ; Use as regular IO        ; DIG1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO        ; DIG1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                    ; Use as regular IO        ; DIG0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                    ; Use as regular IO        ; DIG0[1]                 ; Dual Purpose Pin          ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 7 / 33 ( 21 % )  ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
+; 7        ; 29 / 47 ( 62 % ) ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; DIG1[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; DIG1[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; DIG1[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; DIG2[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; DIG2[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; Point                                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A19      ; 290        ; 7        ; DIG3[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; DIG1[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; DIG1[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; DIG2[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; DIG2[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; DIG3[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; DIG3[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; DIG1[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; DIG3[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; DIG2[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; DIG3[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; DIG0[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; DIG1[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; DIG2[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; Split                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; DIG0[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; DIG0[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; DIG0[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; DIG2[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; DIG3[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; Start                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; DIG0[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; DIG3[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; DE0CLOCK                                                  ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H2       ; 25         ; 1        ; Reset                                                     ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; DIG0[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; DIG0[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                 ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------+--------------+
+; |stopwatch                 ; 97 (15)     ; 35 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 33   ; 0            ; 62 (15)      ; 0 (0)             ; 35 (4)           ; |stopwatch                                          ; work         ;
+;    |bcd_to_display:inst3|  ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |stopwatch|bcd_to_display:inst3                     ; work         ;
+;    |bcd_to_display:inst4|  ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 2 (2)            ; |stopwatch|bcd_to_display:inst4                     ; work         ;
+;    |bcd_to_display:inst5|  ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |stopwatch|bcd_to_display:inst5                     ; work         ;
+;    |bcd_to_display:inst|   ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |stopwatch|bcd_to_display:inst                      ; work         ;
+;    |one_hertz_clock:inst9| ; 31 (25)     ; 19 (19)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (6)       ; 0 (0)             ; 19 (2)           ; |stopwatch|one_hertz_clock:inst9                    ; work         ;
+;       |full_adder:inst103| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst103 ; work         ;
+;       |full_adder:inst108| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst108 ; work         ;
+;       |full_adder:inst369| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst369 ; work         ;
+;       |full_adder:inst36|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst36  ; work         ;
+;       |full_adder:inst37|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst37  ; work         ;
+;       |full_adder:inst41|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst41  ; work         ;
+;       |full_adder:inst449| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst449 ; work         ;
+;       |full_adder:inst46|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst46  ; work         ;
+;       |full_adder:inst49|  ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst49  ; work         ;
+;       |full_adder:inst51|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst51  ; work         ;
+;       |full_adder:inst59|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst59  ; work         ;
+;       |full_adder:inst68|  ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst68  ; work         ;
+;       |full_adder:inst73|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst73  ; work         ;
+;       |full_adder:inst78|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst78  ; work         ;
+;       |full_adder:inst83|  ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst83  ; work         ;
+;       |full_adder:inst88|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst88  ; work         ;
+;       |full_adder:inst93|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst93  ; work         ;
+;       |full_adder:inst98|  ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 1 (1)            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst98  ; work         ;
+;    |ten_counter:inst1|     ; 8 (8)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |stopwatch|ten_counter:inst1                        ; work         ;
+;    |ten_counter:inst2|     ; 8 (8)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |stopwatch|ten_counter:inst2                        ; work         ;
+;    |ten_counter:inst6|     ; 7 (7)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; |stopwatch|ten_counter:inst6                        ; work         ;
+;    |ten_counter:inst8|     ; 4 (4)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; |stopwatch|ten_counter:inst8                        ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                      ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name     ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+; Point    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG0[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG1[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG2[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DIG3[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Split    ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; Start    ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Reset    ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --  ; --   ;
+; DE0CLOCK ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; Split               ;                   ;         ;
+;      - inst21       ; 0                 ; 0       ;
+;      - inst13       ; 0                 ; 0       ;
+;      - inst17       ; 0                 ; 0       ;
+;      - inst7        ; 0                 ; 0       ;
+;      - inst22       ; 0                 ; 0       ;
+;      - inst14       ; 0                 ; 0       ;
+;      - inst18       ; 0                 ; 0       ;
+;      - inst10       ; 0                 ; 0       ;
+;      - inst23       ; 0                 ; 0       ;
+;      - inst15       ; 0                 ; 0       ;
+;      - inst19       ; 0                 ; 0       ;
+;      - inst11       ; 0                 ; 0       ;
+;      - inst24       ; 0                 ; 0       ;
+;      - inst16       ; 0                 ; 0       ;
+;      - inst20       ; 0                 ; 0       ;
+;      - inst12       ; 0                 ; 0       ;
+; Start               ;                   ;         ;
+;      - inst31       ; 0                 ; 6       ;
+;      - inst29       ; 0                 ; 6       ;
+; Reset               ;                   ;         ;
+;      - inst31       ; 1                 ; 0       ;
+;      - inst29       ; 0                 ; 0       ;
+; DE0CLOCK            ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                 ;
++------------------------------+--------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
+; Name                         ; Location           ; Fan-Out ; Usage              ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------------------------------+--------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
+; DE0CLOCK                     ; PIN_G21            ; 19      ; Clock              ; no     ; --                   ; --               ; --                        ;
+; Split                        ; PIN_F1             ; 16      ; Latch enable       ; no     ; --                   ; --               ; --                        ;
+; inst28                       ; LCCOMB_X28_Y28_N6  ; 17      ; Async. clear       ; no     ; --                   ; --               ; --                        ;
+; inst29                       ; LCCOMB_X28_Y28_N18 ; 1       ; Latch enable       ; no     ; --                   ; --               ; --                        ;
+; one_hertz_clock:inst9|inst30 ; LCCOMB_X39_Y16_N0  ; 23      ; Clock, Sync. clear ; no     ; --                   ; --               ; --                        ;
+; ten_counter:inst1|inst23     ; LCCOMB_X28_Y28_N2  ; 4       ; Clock              ; no     ; --                   ; --               ; --                        ;
+; ten_counter:inst2|inst23     ; LCCOMB_X28_Y28_N10 ; 4       ; Clock              ; no     ; --                   ; --               ; --                        ;
+; ten_counter:inst6|inst23     ; LCCOMB_X27_Y28_N28 ; 4       ; Clock              ; yes    ; Global Clock         ; GCLK14           ; --                        ;
++------------------------------+--------------------+---------+--------------------+--------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                          ;
++--------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                     ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; ten_counter:inst6|inst23 ; LCCOMB_X27_Y28_N28 ; 4       ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
++--------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------+
+; Non-Global High Fan-Out Signals                           ;
++-------------------------------------------------+---------+
+; Name                                            ; Fan-Out ;
++-------------------------------------------------+---------+
+; one_hertz_clock:inst9|inst30                    ; 23      ;
+; DE0CLOCK~input                                  ; 19      ;
+; inst28                                          ; 17      ;
+; Split~input                                     ; 16      ;
+; inst12                                          ; 8       ;
+; inst20                                          ; 8       ;
+; inst16                                          ; 8       ;
+; inst11                                          ; 8       ;
+; inst19                                          ; 8       ;
+; inst15                                          ; 8       ;
+; inst10                                          ; 8       ;
+; inst18                                          ; 8       ;
+; inst14                                          ; 8       ;
+; inst7                                           ; 8       ;
+; inst17                                          ; 8       ;
+; inst13                                          ; 8       ;
+; inst24                                          ; 6       ;
+; inst23                                          ; 6       ;
+; inst22                                          ; 6       ;
+; inst21                                          ; 6       ;
+; ten_counter:inst6|inst                          ; 6       ;
+; ten_counter:inst2|inst                          ; 6       ;
+; ten_counter:inst1|inst                          ; 6       ;
+; one_hertz_clock:inst9|inst30~0                  ; 5       ;
+; one_hertz_clock:inst9|inst3799999               ; 5       ;
+; ten_counter:inst8|inst                          ; 5       ;
+; ten_counter:inst6|inst1                         ; 5       ;
+; ten_counter:inst2|inst1                         ; 5       ;
+; ten_counter:inst1|inst1                         ; 5       ;
+; one_hertz_clock:inst9|inst87                    ; 5       ;
+; one_hertz_clock:inst9|inst72                    ; 5       ;
+; one_hertz_clock:inst9|inst389                   ; 5       ;
+; one_hertz_clock:inst9|inst58                    ; 5       ;
+; one_hertz_clock:inst9|inst50                    ; 5       ;
+; one_hertz_clock:inst9|full_adder:inst83|inst6   ; 4       ;
+; one_hertz_clock:inst9|full_adder:inst68|inst6   ; 4       ;
+; one_hertz_clock:inst9|full_adder:inst49|inst6   ; 4       ;
+; ten_counter:inst2|inst23                        ; 4       ;
+; ten_counter:inst1|inst23                        ; 4       ;
+; ten_counter:inst8|inst1                         ; 4       ;
+; ten_counter:inst6|inst2                         ; 4       ;
+; ten_counter:inst6|inst3                         ; 4       ;
+; ten_counter:inst2|inst2                         ; 4       ;
+; ten_counter:inst2|inst3                         ; 4       ;
+; ten_counter:inst1|inst2                         ; 4       ;
+; ten_counter:inst1|inst3                         ; 4       ;
+; one_hertz_clock:inst9|inst43                    ; 4       ;
+; one_hertz_clock:inst9|inst92                    ; 4       ;
+; one_hertz_clock:inst9|inst63                    ; 4       ;
+; one_hertz_clock:inst9|inst77                    ; 4       ;
+; one_hertz_clock:inst9|inst38                    ; 4       ;
+; ten_counter:inst8|inst2                         ; 3       ;
+; ten_counter:inst8|inst3                         ; 3       ;
+; one_hertz_clock:inst9|inst97                    ; 3       ;
+; one_hertz_clock:inst9|inst48                    ; 3       ;
+; one_hertz_clock:inst9|inst67                    ; 3       ;
+; one_hertz_clock:inst9|inst82                    ; 3       ;
+; one_hertz_clock:inst9|inst102                   ; 3       ;
+; one_hertz_clock:inst9|inst40                    ; 3       ;
+; Reset~input                                     ; 2       ;
+; Start~input                                     ; 2       ;
+; one_hertz_clock:inst9|full_adder:inst98|inst6   ; 2       ;
+; one_hertz_clock:inst9|inst30~1                  ; 2       ;
+; one_hertz_clock:inst9|inst107                   ; 2       ;
+; one_hertz_clock:inst9|inst459                   ; 2       ;
+; ten_counter:inst8|inst~0                        ; 1       ;
+; ten_counter:inst6|inst~0                        ; 1       ;
+; ten_counter:inst2|inst~0                        ; 1       ;
+; ten_counter:inst1|inst~0                        ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst88|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst98|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst73|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst108|inst   ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst369|inst   ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst449|inst   ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst49|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst59|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst68|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst93|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst83|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst37|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst78|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst103|inst   ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst49|inst6~0 ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst36|inst    ; 1       ;
+; one_hertz_clock:inst9|inst29                    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst41|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst46|inst    ; 1       ;
+; one_hertz_clock:inst9|full_adder:inst51|inst    ; 1       ;
+; inst29                                          ; 1       ;
+; inst31                                          ; 1       ;
+; one_hertz_clock:inst9|inst30~5                  ; 1       ;
+; one_hertz_clock:inst9|inst30~4                  ; 1       ;
+; one_hertz_clock:inst9|inst30~3                  ; 1       ;
+; one_hertz_clock:inst9|inst30~2                  ; 1       ;
+; ten_counter:inst8|inst2~0                       ; 1       ;
+; ten_counter:inst8|inst5~0                       ; 1       ;
+; ten_counter:inst8|inst17                        ; 1       ;
+; ten_counter:inst6|inst2~0                       ; 1       ;
+; ten_counter:inst6|inst5~0                       ; 1       ;
+; ten_counter:inst6|inst17                        ; 1       ;
+; ten_counter:inst2|inst2~0                       ; 1       ;
+; ten_counter:inst2|inst5~0                       ; 1       ;
+; ten_counter:inst2|inst17                        ; 1       ;
+; ten_counter:inst1|inst2~0                       ; 1       ;
+; ten_counter:inst1|inst5~0                       ; 1       ;
+; ten_counter:inst1|inst17                        ; 1       ;
+; bcd_to_display:inst5|inst8~0                    ; 1       ;
+; bcd_to_display:inst5|inst7~0                    ; 1       ;
+; bcd_to_display:inst5|inst6~0                    ; 1       ;
+; bcd_to_display:inst5|inst5~0                    ; 1       ;
+; bcd_to_display:inst5|inst12~0                   ; 1       ;
+; bcd_to_display:inst5|inst2~0                    ; 1       ;
+; bcd_to_display:inst5|inst1~0                    ; 1       ;
+; bcd_to_display:inst4|inst8~0                    ; 1       ;
+; bcd_to_display:inst4|inst7~0                    ; 1       ;
+; bcd_to_display:inst4|inst6~0                    ; 1       ;
+; bcd_to_display:inst4|inst5~0                    ; 1       ;
+; bcd_to_display:inst4|inst12~0                   ; 1       ;
+; bcd_to_display:inst4|inst2~0                    ; 1       ;
+; bcd_to_display:inst4|inst1~0                    ; 1       ;
+; bcd_to_display:inst3|inst8~0                    ; 1       ;
+; bcd_to_display:inst3|inst7~0                    ; 1       ;
+; bcd_to_display:inst3|inst6~0                    ; 1       ;
+; bcd_to_display:inst3|inst5~0                    ; 1       ;
+; bcd_to_display:inst3|inst12~0                   ; 1       ;
+; bcd_to_display:inst3|inst2~0                    ; 1       ;
+; bcd_to_display:inst3|inst1~0                    ; 1       ;
+; bcd_to_display:inst|inst8~0                     ; 1       ;
+; bcd_to_display:inst|inst7~0                     ; 1       ;
+; bcd_to_display:inst|inst6~0                     ; 1       ;
+; bcd_to_display:inst|inst5~0                     ; 1       ;
+; bcd_to_display:inst|inst12~0                    ; 1       ;
+; bcd_to_display:inst|inst2~0                     ; 1       ;
+; bcd_to_display:inst|inst1~0                     ; 1       ;
++-------------------------------------------------+---------+
+
+
++------------------------------------------------------+
+; Other Routing Usage Summary                          ;
++-----------------------------+------------------------+
+; Other Routing Resource Type ; Usage                  ;
++-----------------------------+------------------------+
+; Block interconnects         ; 119 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 2 / 1,804 ( < 1 % )    ;
+; C4 interconnects            ; 96 / 31,272 ( < 1 % )  ;
+; Direct links                ; 36 / 47,787 ( < 1 % )  ;
+; Global clocks               ; 1 / 20 ( 5 % )         ;
+; Local interconnects         ; 61 / 15,408 ( < 1 % )  ;
+; R24 interconnects           ; 15 / 1,775 ( < 1 % )   ;
+; R4 interconnects            ; 82 / 41,310 ( < 1 % )  ;
++-----------------------------+------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 12.13) ; Number of LABs  (Total = 8) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 1                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 1                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 1                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 2                           ;
+; 16                                          ; 3                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 8) ;
++------------------------------------+-----------------------------+
+; 1 Async. clear                     ; 2                           ;
+; 1 Clock                            ; 5                           ;
+; 1 Sync. clear                      ; 1                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 16.50) ; Number of LABs  (Total = 8) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 1                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 1                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 1                           ;
+; 20                                           ; 1                           ;
+; 21                                           ; 0                           ;
+; 22                                           ; 1                           ;
+; 23                                           ; 0                           ;
+; 24                                           ; 1                           ;
+; 25                                           ; 0                           ;
+; 26                                           ; 0                           ;
+; 27                                           ; 0                           ;
+; 28                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 8.00) ; Number of LABs  (Total = 8) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 1                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 3                           ;
+; 8                                               ; 1                           ;
+; 9                                               ; 1                           ;
+; 10                                              ; 1                           ;
+; 11                                              ; 0                           ;
+; 12                                              ; 0                           ;
+; 13                                              ; 0                           ;
+; 14                                              ; 0                           ;
+; 15                                              ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 6.13) ; Number of LABs  (Total = 8) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 1                           ;
+; 3                                           ; 2                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 3                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 1                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 0                           ;
+; 16                                          ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 33        ; 0            ; 33        ; 0            ; 0            ; 33        ; 33        ; 0            ; 33        ; 33        ; 0            ; 29           ; 0            ; 0            ; 4            ; 0            ; 29           ; 4            ; 0            ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 33        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 33           ; 0         ; 33           ; 33           ; 0         ; 0         ; 33           ; 0         ; 0         ; 33           ; 4            ; 33           ; 33           ; 29           ; 33           ; 4            ; 29           ; 33           ; 33           ; 33           ; 4            ; 33           ; 33           ; 33           ; 33           ; 33           ; 0         ; 33           ; 33           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Point              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DIG3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Split              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Start              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Reset              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DE0CLOCK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                     ;
++-------------------------------+-------------------------------+-------------------+
+; Source Clock(s)               ; Destination Clock(s)          ; Delay Added in ns ;
++-------------------------------+-------------------------------+-------------------+
+; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 6.5               ;
+; ten_counter:inst2|inst        ; Split                         ; 6.0               ;
+; DE0CLOCK                      ; DE0CLOCK                      ; 5.8               ;
+; ten_counter:inst1|inst        ; Split                         ; 5.0               ;
+; ten_counter:inst2|inst        ; ten_counter:inst2|inst        ; 2.5               ;
+; one_hertz_clock:inst9|inst102 ; Split                         ; 1.8               ;
+; ten_counter:inst1|inst        ; ten_counter:inst1|inst        ; 1.6               ;
++-------------------------------+-------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+
+
++-------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                             ;
++-----------------------------------+-----------------------------------+-------------------+
+; Source Register                   ; Destination Register              ; Delay Added in ns ;
++-----------------------------------+-----------------------------------+-------------------+
+; ten_counter:inst6|inst            ; inst11                            ; 2.340             ;
+; ten_counter:inst1|inst            ; DIG0[0]                           ; 1.768             ;
+; ten_counter:inst2|inst            ; inst10                            ; 1.696             ;
+; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; 1.643             ;
+; ten_counter:inst2|inst2           ; inst18                            ; 1.538             ;
+; ten_counter:inst6|inst3           ; inst23                            ; 1.263             ;
+; ten_counter:inst6|inst2           ; inst19                            ; 1.203             ;
+; ten_counter:inst6|inst1           ; inst15                            ; 1.203             ;
+; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst3799999 ; 1.122             ;
+; ten_counter:inst2|inst3           ; inst22                            ; 0.905             ;
+; ten_counter:inst2|inst1           ; inst14                            ; 0.845             ;
+; Split                             ; inst24                            ; 0.050             ;
++-----------------------------------+-----------------------------------+-------------------+
+Note: This table only shows the top 29 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "stopwatch"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Warning (335093): TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'stopwatch.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node ten_counter:inst6|inst23 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.36 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Git/stopwatch/output_files/stopwatch.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 1094 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:52 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:07
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Git/stopwatch/output_files/stopwatch.fit.smsg.
+
+
diff --git a/stopwatch/output_files/stopwatch.fit.smsg b/stopwatch/output_files/stopwatch.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/stopwatch/output_files/stopwatch.fit.summary b/stopwatch/output_files/stopwatch.fit.summary
new file mode 100644
index 0000000..a094673
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Fri Feb 26 16:37:52 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : stopwatch
+Top-level Entity Name : stopwatch
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 97 / 15,408 ( < 1 % )
+    Total combinational functions : 97 / 15,408 ( < 1 % )
+    Dedicated logic registers : 35 / 15,408 ( < 1 % )
+Total registers : 35
+Total pins : 33 / 347 ( 10 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/stopwatch/output_files/stopwatch.flow.rpt b/stopwatch/output_files/stopwatch.flow.rpt
new file mode 100644
index 0000000..802fec7
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.flow.rpt
@@ -0,0 +1,123 @@
+Flow report for stopwatch
+Fri Feb 26 16:37:57 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 26 16:37:54 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; stopwatch                                        ;
+; Top-level Entity Name              ; stopwatch                                        ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 97 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 97 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 35 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 35                                               ;
+; Total pins                         ; 33 / 347 ( 10 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/26/2016 16:37:44 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; stopwatch           ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                 ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297093.145650466407624 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top        ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 463 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:07     ; 1.5                     ; 1094 MB             ; 00:00:07                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 424 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 488 MB              ; 00:00:02                           ;
+; Total                     ; 00:00:12     ; --                      ; --                  ; 00:00:11                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch
+quartus_fit --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch
+quartus_asm --read_settings_files=off --write_settings_files=off stopwatch -c stopwatch
+quartus_sta stopwatch -c stopwatch
+
+
+
diff --git a/stopwatch/output_files/stopwatch.jdi b/stopwatch/output_files/stopwatch.jdi
new file mode 100644
index 0000000..fe7e652
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="55db7546f2e1aaef59ef"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="stopwatch.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/stopwatch/output_files/stopwatch.map.rpt b/stopwatch/output_files/stopwatch.map.rpt
new file mode 100644
index 0000000..b0c1513
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.map.rpt
@@ -0,0 +1,356 @@
+Analysis & Synthesis report for stopwatch
+Fri Feb 26 16:37:45 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. User-Specified and Inferred Latches
+  9. General Register Statistics
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 26 16:37:45 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; stopwatch                                        ;
+; Top-level Entity Name              ; stopwatch                                        ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 97                                               ;
+;     Total combinational functions  ; 97                                               ;
+;     Dedicated logic registers      ; 35                                               ;
+; Total registers                    ; 35                                               ;
+; Total pins                         ; 33                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; stopwatch          ; stopwatch          ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                               ;
++----------------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+
+; File Name with User-Entered Path       ; Used in Netlist ; File Type                          ; File Name with Absolute Path               ; Library ;
++----------------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+
+; ../ten_counter/ten_counter.bdf         ; yes             ; User Block Diagram/Schematic File  ; C:/Git/ten_counter/ten_counter.bdf         ;         ;
+; ../one_hertz_clock/one_hertz_clock.bdf ; yes             ; User Block Diagram/Schematic File  ; C:/Git/one_hertz_clock/one_hertz_clock.bdf ;         ;
+; ../bcd_to_display/bcd_to_display.bdf   ; yes             ; User Block Diagram/Schematic File  ; C:/Git/bcd_to_display/bcd_to_display.bdf   ;         ;
+; ../adder/full_adder.bdf                ; yes             ; User Block Diagram/Schematic File  ; C:/Git/adder/full_adder.bdf                ;         ;
+; stopwatch.bdf                          ; yes             ; User Block Diagram/Schematic File  ; C:/Git/stopwatch/stopwatch.bdf             ;         ;
++----------------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+
+
+
++----------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                ;
++---------------------------------------------+------------------------------+
+; Resource                                    ; Usage                        ;
++---------------------------------------------+------------------------------+
+; Estimated Total logic elements              ; 97                           ;
+;                                             ;                              ;
+; Total combinational functions               ; 97                           ;
+; Logic element usage by number of LUT inputs ;                              ;
+;     -- 4 input functions                    ; 42                           ;
+;     -- 3 input functions                    ; 40                           ;
+;     -- <=2 input functions                  ; 15                           ;
+;                                             ;                              ;
+; Logic elements by mode                      ;                              ;
+;     -- normal mode                          ; 97                           ;
+;     -- arithmetic mode                      ; 0                            ;
+;                                             ;                              ;
+; Total registers                             ; 35                           ;
+;     -- Dedicated logic registers            ; 35                           ;
+;     -- I/O registers                        ; 0                            ;
+;                                             ;                              ;
+; I/O pins                                    ; 33                           ;
+; Embedded Multiplier 9-bit elements          ; 0                            ;
+; Maximum fan-out node                        ; one_hertz_clock:inst9|inst30 ;
+; Maximum fan-out                             ; 23                           ;
+; Total fan-out                               ; 479                          ;
+; Average fan-out                             ; 2.42                         ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                 ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
+; |stopwatch                 ; 97 (19)           ; 35 (0)       ; 0           ; 0            ; 0       ; 0         ; 33   ; 0            ; |stopwatch                                          ; work         ;
+;    |bcd_to_display:inst3|  ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|bcd_to_display:inst3                     ; work         ;
+;    |bcd_to_display:inst4|  ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|bcd_to_display:inst4                     ; work         ;
+;    |bcd_to_display:inst5|  ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|bcd_to_display:inst5                     ; work         ;
+;    |bcd_to_display:inst|   ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|bcd_to_display:inst                      ; work         ;
+;    |one_hertz_clock:inst9| ; 31 (8)            ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9                    ; work         ;
+;       |full_adder:inst103| ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst103 ; work         ;
+;       |full_adder:inst108| ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst108 ; work         ;
+;       |full_adder:inst369| ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst369 ; work         ;
+;       |full_adder:inst36|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst36  ; work         ;
+;       |full_adder:inst37|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst37  ; work         ;
+;       |full_adder:inst41|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst41  ; work         ;
+;       |full_adder:inst449| ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst449 ; work         ;
+;       |full_adder:inst46|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst46  ; work         ;
+;       |full_adder:inst49|  ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst49  ; work         ;
+;       |full_adder:inst51|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst51  ; work         ;
+;       |full_adder:inst59|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst59  ; work         ;
+;       |full_adder:inst68|  ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst68  ; work         ;
+;       |full_adder:inst73|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst73  ; work         ;
+;       |full_adder:inst78|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst78  ; work         ;
+;       |full_adder:inst83|  ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst83  ; work         ;
+;       |full_adder:inst88|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst88  ; work         ;
+;       |full_adder:inst93|  ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst93  ; work         ;
+;       |full_adder:inst98|  ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|one_hertz_clock:inst9|full_adder:inst98  ; work         ;
+;    |ten_counter:inst1|     ; 5 (5)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|ten_counter:inst1                        ; work         ;
+;    |ten_counter:inst2|     ; 5 (5)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|ten_counter:inst2                        ; work         ;
+;    |ten_counter:inst6|     ; 5 (5)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|ten_counter:inst6                        ; work         ;
+;    |ten_counter:inst8|     ; 4 (4)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopwatch|ten_counter:inst8                        ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                ;
++-----------------------------------------------------+---------------------+------------------------+
+; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
++-----------------------------------------------------+---------------------+------------------------+
+; inst21                                              ; Split               ; yes                    ;
+; inst13                                              ; Split               ; yes                    ;
+; inst17                                              ; Split               ; yes                    ;
+; inst7                                               ; Split               ; yes                    ;
+; inst22                                              ; Split               ; yes                    ;
+; inst14                                              ; Split               ; yes                    ;
+; inst18                                              ; Split               ; yes                    ;
+; inst10                                              ; Split               ; yes                    ;
+; inst23                                              ; Split               ; yes                    ;
+; inst15                                              ; Split               ; yes                    ;
+; inst19                                              ; Split               ; yes                    ;
+; inst11                                              ; Split               ; yes                    ;
+; inst24                                              ; Split               ; yes                    ;
+; inst16                                              ; Split               ; yes                    ;
+; inst20                                              ; Split               ; yes                    ;
+; inst12                                              ; Split               ; yes                    ;
+; inst28                                              ; inst29              ; yes                    ;
+; Number of user-specified and inferred latches = 17  ;                     ;                        ;
++-----------------------------------------------------+---------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 35    ;
+; Number of registers using Synchronous Clear  ; 18    ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 16    ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:43 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopwatch -c stopwatch
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file /git/ten_counter/ten_counter.bdf
+    Info (12023): Found entity 1: ten_counter
+Info (12021): Found 1 design units, including 1 entities, in source file /git/one_hertz_clock/one_hertz_clock.bdf
+    Info (12023): Found entity 1: one_hertz_clock
+Info (12021): Found 1 design units, including 1 entities, in source file /git/bcd_to_display/bcd_to_display.bdf
+    Info (12023): Found entity 1: bcd_to_display
+Info (12021): Found 1 design units, including 1 entities, in source file /git/adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file stopwatch.bdf
+    Info (12023): Found entity 1: stopwatch
+Info (12127): Elaborating entity "stopwatch" for the top level hierarchy
+Info (12128): Elaborating entity "bcd_to_display" for hierarchy "bcd_to_display:inst"
+Info (12128): Elaborating entity "ten_counter" for hierarchy "ten_counter:inst1"
+Info (12128): Elaborating entity "one_hertz_clock" for hierarchy "one_hertz_clock:inst9"
+Warning (275089): Not all bits in bus "N[14..5]" are used
+Warning (275080): Converted elements in bus name "N" using legacy naming rules. Make any assignments on the new names, not on the original names.
+    Warning (275081): Converted element name(s) from "N[5]" to "N5"
+    Warning (275081): Converted element name(s) from "N[6]" to "N6"
+    Warning (275081): Converted element name(s) from "N[7]" to "N7"
+    Warning (275081): Converted element name(s) from "N[9]" to "N9"
+    Warning (275081): Converted element name(s) from "N[10]" to "N10"
+    Warning (275081): Converted element name(s) from "N[11]" to "N11"
+    Warning (275081): Converted element name(s) from "N[12]" to "N12"
+    Warning (275081): Converted element name(s) from "N[14]" to "N14"
+    Warning (275081): Converted element name(s) from "N[5]" to "N5"
+    Warning (275081): Converted element name(s) from "N[6]" to "N6"
+    Warning (275081): Converted element name(s) from "N[7]" to "N7"
+    Warning (275081): Converted element name(s) from "N[9]" to "N9"
+    Warning (275081): Converted element name(s) from "N[10]" to "N10"
+    Warning (275081): Converted element name(s) from "N[11]" to "N11"
+    Warning (275081): Converted element name(s) from "N[12]" to "N12"
+    Warning (275081): Converted element name(s) from "N[14]" to "N14"
+Info (12128): Elaborating entity "full_adder" for hierarchy "one_hertz_clock:inst9|full_adder:inst78"
+Warning (13012): Latch inst28 has unsafe behavior
+    Warning (13013): Ports D and ENA on the latch are fed by the same signal Reset
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "Point" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 130 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 4 input pins
+    Info (21059): Implemented 29 output pins
+    Info (21061): Implemented 97 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 22 warnings
+    Info: Peak virtual memory: 463 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:45 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/stopwatch/output_files/stopwatch.map.summary b/stopwatch/output_files/stopwatch.map.summary
new file mode 100644
index 0000000..9cfbae1
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Fri Feb 26 16:37:45 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : stopwatch
+Top-level Entity Name : stopwatch
+Family : Cyclone III
+Total logic elements : 97
+    Total combinational functions : 97
+    Dedicated logic registers : 35
+Total registers : 35
+Total pins : 33
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/stopwatch/output_files/stopwatch.pin b/stopwatch/output_files/stopwatch.pin
new file mode 100644
index 0000000..814a425
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "stopwatch"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+DIG1[0]                      : A13       : output : 2.5 V             :         : 7         : Y              
+DIG1[3]                      : A14       : output : 2.5 V             :         : 7         : Y              
+DIG1[6]                      : A15       : output : 2.5 V             :         : 7         : Y              
+DIG2[1]                      : A16       : output : 2.5 V             :         : 7         : Y              
+DIG2[4]                      : A17       : output : 2.5 V             :         : 7         : Y              
+Point                        : A18       : output : 2.5 V             :         : 7         : Y              
+DIG3[2]                      : A19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+DIG1[1]                      : B13       : output : 2.5 V             :         : 7         : Y              
+DIG1[4]                      : B14       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+DIG2[2]                      : B16       : output : 2.5 V             :         : 7         : Y              
+DIG2[5]                      : B17       : output : 2.5 V             :         : 7         : Y              
+DIG3[0]                      : B18       : output : 2.5 V             :         : 7         : Y              
+DIG3[3]                      : B19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+DIG1[2]                      : C13       : output : 2.5 V             :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+DIG3[4]                      : C19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+DIG2[0]                      : D15       : output : 2.5 V             :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+DIG3[5]                      : D19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+DIG0[0]                      : E11       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+DIG1[5]                      : E14       : output : 2.5 V             :         : 7         : Y              
+DIG2[3]                      : E15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+Split                        : F1        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+DIG0[1]                      : F11       : output : 2.5 V             :         : 7         : Y              
+DIG0[5]                      : F12       : output : 2.5 V             :         : 7         : Y              
+DIG0[6]                      : F13       : output : 2.5 V             :         : 7         : Y              
+DIG2[6]                      : F14       : output : 2.5 V             :         : 7         : Y              
+DIG3[1]                      : F15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+Start                        : G3        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+DIG0[4]                      : G12       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+DIG3[6]                      : G15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+DE0CLOCK                     : G21       : input  : 2.5 V             :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
+Reset                        : H2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+DIG0[2]                      : H12       : output : 2.5 V             :         : 7         : Y              
+DIG0[3]                      : H13       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/stopwatch/output_files/stopwatch.sof b/stopwatch/output_files/stopwatch.sof
new file mode 100644
index 0000000..52cba46
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.sof
diff --git a/stopwatch/output_files/stopwatch.sta.rpt b/stopwatch/output_files/stopwatch.sta.rpt
new file mode 100644
index 0000000..f8123a6
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.sta.rpt
@@ -0,0 +1,4037 @@
+TimeQuest Timing Analyzer report for stopwatch
+Fri Feb 26 16:37:57 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'DE0CLOCK'
+ 13. Slow 1200mV 85C Model Setup: 'Split'
+ 14. Slow 1200mV 85C Model Setup: 'Reset'
+ 15. Slow 1200mV 85C Model Setup: 'ten_counter:inst1|inst'
+ 16. Slow 1200mV 85C Model Setup: 'ten_counter:inst2|inst'
+ 17. Slow 1200mV 85C Model Setup: 'one_hertz_clock:inst9|inst102'
+ 18. Slow 1200mV 85C Model Setup: 'ten_counter:inst6|inst'
+ 19. Slow 1200mV 85C Model Hold: 'one_hertz_clock:inst9|inst102'
+ 20. Slow 1200mV 85C Model Hold: 'Split'
+ 21. Slow 1200mV 85C Model Hold: 'ten_counter:inst2|inst'
+ 22. Slow 1200mV 85C Model Hold: 'DE0CLOCK'
+ 23. Slow 1200mV 85C Model Hold: 'ten_counter:inst1|inst'
+ 24. Slow 1200mV 85C Model Hold: 'Reset'
+ 25. Slow 1200mV 85C Model Hold: 'ten_counter:inst6|inst'
+ 26. Slow 1200mV 85C Model Recovery: 'ten_counter:inst1|inst'
+ 27. Slow 1200mV 85C Model Recovery: 'ten_counter:inst2|inst'
+ 28. Slow 1200mV 85C Model Recovery: 'ten_counter:inst6|inst'
+ 29. Slow 1200mV 85C Model Recovery: 'one_hertz_clock:inst9|inst102'
+ 30. Slow 1200mV 85C Model Removal: 'one_hertz_clock:inst9|inst102'
+ 31. Slow 1200mV 85C Model Removal: 'ten_counter:inst6|inst'
+ 32. Slow 1200mV 85C Model Removal: 'ten_counter:inst2|inst'
+ 33. Slow 1200mV 85C Model Removal: 'ten_counter:inst1|inst'
+ 34. Slow 1200mV 85C Model Minimum Pulse Width: 'DE0CLOCK'
+ 35. Slow 1200mV 85C Model Minimum Pulse Width: 'Reset'
+ 36. Slow 1200mV 85C Model Minimum Pulse Width: 'Split'
+ 37. Slow 1200mV 85C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'
+ 38. Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst1|inst'
+ 39. Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst2|inst'
+ 40. Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst6|inst'
+ 41. Setup Times
+ 42. Hold Times
+ 43. Clock to Output Times
+ 44. Minimum Clock to Output Times
+ 45. Slow 1200mV 85C Model Metastability Report
+ 46. Slow 1200mV 0C Model Fmax Summary
+ 47. Slow 1200mV 0C Model Setup Summary
+ 48. Slow 1200mV 0C Model Hold Summary
+ 49. Slow 1200mV 0C Model Recovery Summary
+ 50. Slow 1200mV 0C Model Removal Summary
+ 51. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 52. Slow 1200mV 0C Model Setup: 'DE0CLOCK'
+ 53. Slow 1200mV 0C Model Setup: 'Split'
+ 54. Slow 1200mV 0C Model Setup: 'Reset'
+ 55. Slow 1200mV 0C Model Setup: 'ten_counter:inst1|inst'
+ 56. Slow 1200mV 0C Model Setup: 'ten_counter:inst2|inst'
+ 57. Slow 1200mV 0C Model Setup: 'one_hertz_clock:inst9|inst102'
+ 58. Slow 1200mV 0C Model Setup: 'ten_counter:inst6|inst'
+ 59. Slow 1200mV 0C Model Hold: 'one_hertz_clock:inst9|inst102'
+ 60. Slow 1200mV 0C Model Hold: 'Split'
+ 61. Slow 1200mV 0C Model Hold: 'ten_counter:inst2|inst'
+ 62. Slow 1200mV 0C Model Hold: 'DE0CLOCK'
+ 63. Slow 1200mV 0C Model Hold: 'ten_counter:inst1|inst'
+ 64. Slow 1200mV 0C Model Hold: 'Reset'
+ 65. Slow 1200mV 0C Model Hold: 'ten_counter:inst6|inst'
+ 66. Slow 1200mV 0C Model Recovery: 'ten_counter:inst1|inst'
+ 67. Slow 1200mV 0C Model Recovery: 'ten_counter:inst2|inst'
+ 68. Slow 1200mV 0C Model Recovery: 'ten_counter:inst6|inst'
+ 69. Slow 1200mV 0C Model Recovery: 'one_hertz_clock:inst9|inst102'
+ 70. Slow 1200mV 0C Model Removal: 'one_hertz_clock:inst9|inst102'
+ 71. Slow 1200mV 0C Model Removal: 'ten_counter:inst6|inst'
+ 72. Slow 1200mV 0C Model Removal: 'ten_counter:inst2|inst'
+ 73. Slow 1200mV 0C Model Removal: 'ten_counter:inst1|inst'
+ 74. Slow 1200mV 0C Model Minimum Pulse Width: 'DE0CLOCK'
+ 75. Slow 1200mV 0C Model Minimum Pulse Width: 'Reset'
+ 76. Slow 1200mV 0C Model Minimum Pulse Width: 'Split'
+ 77. Slow 1200mV 0C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'
+ 78. Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst1|inst'
+ 79. Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst2|inst'
+ 80. Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst6|inst'
+ 81. Setup Times
+ 82. Hold Times
+ 83. Clock to Output Times
+ 84. Minimum Clock to Output Times
+ 85. Slow 1200mV 0C Model Metastability Report
+ 86. Fast 1200mV 0C Model Setup Summary
+ 87. Fast 1200mV 0C Model Hold Summary
+ 88. Fast 1200mV 0C Model Recovery Summary
+ 89. Fast 1200mV 0C Model Removal Summary
+ 90. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 91. Fast 1200mV 0C Model Setup: 'DE0CLOCK'
+ 92. Fast 1200mV 0C Model Setup: 'Reset'
+ 93. Fast 1200mV 0C Model Setup: 'Split'
+ 94. Fast 1200mV 0C Model Setup: 'ten_counter:inst1|inst'
+ 95. Fast 1200mV 0C Model Setup: 'ten_counter:inst2|inst'
+ 96. Fast 1200mV 0C Model Setup: 'one_hertz_clock:inst9|inst102'
+ 97. Fast 1200mV 0C Model Setup: 'ten_counter:inst6|inst'
+ 98. Fast 1200mV 0C Model Hold: 'Split'
+ 99. Fast 1200mV 0C Model Hold: 'one_hertz_clock:inst9|inst102'
+100. Fast 1200mV 0C Model Hold: 'DE0CLOCK'
+101. Fast 1200mV 0C Model Hold: 'ten_counter:inst2|inst'
+102. Fast 1200mV 0C Model Hold: 'ten_counter:inst1|inst'
+103. Fast 1200mV 0C Model Hold: 'Reset'
+104. Fast 1200mV 0C Model Hold: 'ten_counter:inst6|inst'
+105. Fast 1200mV 0C Model Recovery: 'ten_counter:inst1|inst'
+106. Fast 1200mV 0C Model Recovery: 'ten_counter:inst2|inst'
+107. Fast 1200mV 0C Model Recovery: 'ten_counter:inst6|inst'
+108. Fast 1200mV 0C Model Recovery: 'one_hertz_clock:inst9|inst102'
+109. Fast 1200mV 0C Model Removal: 'one_hertz_clock:inst9|inst102'
+110. Fast 1200mV 0C Model Removal: 'ten_counter:inst6|inst'
+111. Fast 1200mV 0C Model Removal: 'ten_counter:inst2|inst'
+112. Fast 1200mV 0C Model Removal: 'ten_counter:inst1|inst'
+113. Fast 1200mV 0C Model Minimum Pulse Width: 'DE0CLOCK'
+114. Fast 1200mV 0C Model Minimum Pulse Width: 'Split'
+115. Fast 1200mV 0C Model Minimum Pulse Width: 'Reset'
+116. Fast 1200mV 0C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'
+117. Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst1|inst'
+118. Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst2|inst'
+119. Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst6|inst'
+120. Setup Times
+121. Hold Times
+122. Clock to Output Times
+123. Minimum Clock to Output Times
+124. Fast 1200mV 0C Model Metastability Report
+125. Multicorner Timing Analysis Summary
+126. Setup Times
+127. Hold Times
+128. Clock to Output Times
+129. Minimum Clock to Output Times
+130. Board Trace Model Assignments
+131. Input Transition Times
+132. Slow Corner Signal Integrity Metrics
+133. Fast Corner Signal Integrity Metrics
+134. Setup Transfers
+135. Hold Transfers
+136. Recovery Transfers
+137. Removal Transfers
+138. Report TCCS
+139. Report RSKM
+140. Unconstrained Paths
+141. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; stopwatch                                                          ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                       ;
++-------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------+
+; Clock Name                    ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                           ;
++-------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------+
+; DE0CLOCK                      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { DE0CLOCK }                      ;
+; one_hertz_clock:inst9|inst102 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { one_hertz_clock:inst9|inst102 } ;
+; Reset                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Reset }                         ;
+; Split                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { Split }                         ;
+; ten_counter:inst1|inst        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ten_counter:inst1|inst }        ;
+; ten_counter:inst2|inst        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ten_counter:inst2|inst }        ;
+; ten_counter:inst6|inst        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ten_counter:inst6|inst }        ;
++-------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                                           ;
++------------+-----------------+-------------------------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name                    ; Note                                                          ;
++------------+-----------------+-------------------------------+---------------------------------------------------------------+
+; 296.74 MHz ; 250.0 MHz       ; DE0CLOCK                      ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 351.37 MHz ; 250.0 MHz       ; Reset                         ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 658.76 MHz ; 500.0 MHz       ; ten_counter:inst1|inst        ; limit due to minimum period restriction (tmin)                ;
+; 664.45 MHz ; 500.0 MHz       ; ten_counter:inst2|inst        ; limit due to minimum period restriction (tmin)                ;
+; 675.22 MHz ; 500.0 MHz       ; one_hertz_clock:inst9|inst102 ; limit due to minimum period restriction (tmin)                ;
+; 948.77 MHz ; 500.0 MHz       ; ten_counter:inst6|inst        ; limit due to minimum period restriction (tmin)                ;
++------------+-----------------+-------------------------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                    ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -2.370 ; -44.235       ;
+; Split                         ; -1.031 ; -8.373        ;
+; Reset                         ; -0.923 ; -0.923        ;
+; ten_counter:inst1|inst        ; -0.518 ; -1.429        ;
+; ten_counter:inst2|inst        ; -0.505 ; -1.341        ;
+; one_hertz_clock:inst9|inst102 ; -0.481 ; -1.435        ;
+; ten_counter:inst6|inst        ; -0.054 ; -0.121        ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                     ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; one_hertz_clock:inst9|inst102 ; -0.545 ; -1.713        ;
+; Split                         ; -0.440 ; -1.046        ;
+; ten_counter:inst2|inst        ; -0.401 ; -1.418        ;
+; DE0CLOCK                      ; -0.349 ; -6.211        ;
+; ten_counter:inst1|inst        ; -0.245 ; -0.692        ;
+; Reset                         ; 0.160  ; 0.000         ;
+; ten_counter:inst6|inst        ; 0.359  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                 ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; ten_counter:inst1|inst        ; -2.180 ; -8.720        ;
+; ten_counter:inst2|inst        ; -1.948 ; -7.792        ;
+; ten_counter:inst6|inst        ; -0.679 ; -2.716        ;
+; one_hertz_clock:inst9|inst102 ; -0.465 ; -1.860        ;
++-------------------------------+--------+---------------+
+
+
++-------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                 ;
++-------------------------------+-------+---------------+
+; Clock                         ; Slack ; End Point TNS ;
++-------------------------------+-------+---------------+
+; one_hertz_clock:inst9|inst102 ; 0.969 ; 0.000         ;
+; ten_counter:inst6|inst        ; 1.155 ; 0.000         ;
+; ten_counter:inst2|inst        ; 2.492 ; 0.000         ;
+; ten_counter:inst1|inst        ; 2.734 ; 0.000         ;
++-------------------------------+-------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary      ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -3.000 ; -22.000       ;
+; Reset                         ; -3.000 ; -3.000        ;
+; Split                         ; -3.000 ; -3.000        ;
+; one_hertz_clock:inst9|inst102 ; -1.000 ; -4.000        ;
+; ten_counter:inst1|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst2|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst6|inst        ; -1.000 ; -4.000        ;
++-------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'DE0CLOCK'                                                                                                              ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; -2.370 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.455      ;
+; -2.370 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.455      ;
+; -2.370 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.455      ;
+; -2.370 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.455      ;
+; -2.370 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.455      ;
+; -2.342 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.427      ;
+; -2.342 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.427      ;
+; -2.342 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.427      ;
+; -2.342 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.427      ;
+; -2.342 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.427      ;
+; -2.336 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.421      ;
+; -2.319 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.404      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.312 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.282      ;
+; -2.305 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.038     ; 3.282      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.283 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.253      ;
+; -2.276 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.038     ; 3.253      ;
+; -2.174 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.259      ;
+; -2.174 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.259      ;
+; -2.174 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.259      ;
+; -2.174 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.259      ;
+; -2.174 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.259      ;
+; -2.165 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.250      ;
+; -2.151 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.236      ;
+; -2.145 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.230      ;
+; -2.145 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.230      ;
+; -2.145 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.230      ;
+; -2.145 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.230      ;
+; -2.145 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.230      ;
+; -2.143 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.228      ;
+; -2.143 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.228      ;
+; -2.143 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.228      ;
+; -2.143 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.228      ;
+; -2.138 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.223      ;
+; -2.138 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.223      ;
+; -2.138 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.223      ;
+; -2.138 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.223      ;
+; -2.138 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.223      ;
+; -2.120 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.205      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.115 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.085      ;
+; -2.114 ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.084      ;
+; -2.111 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.196      ;
+; -2.108 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.038     ; 3.085      ;
+; -2.105 ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.075      ;
+; -2.104 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.189      ;
+; -2.095 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.180      ;
+; -2.095 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.180      ;
+; -2.095 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.180      ;
+; -2.095 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.180      ;
+; -2.095 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.070      ; 3.180      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.087 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.057      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
+; -2.084 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.045     ; 3.054      ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'Split'                                                                                              ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; -1.031 ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.386      ; 2.053      ;
+; -0.893 ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.357     ; 0.745      ;
+; -0.835 ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.117      ; 0.548      ;
+; -0.834 ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.120      ; 0.548      ;
+; -0.787 ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.204     ; 0.623      ;
+; -0.779 ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.203     ; 0.606      ;
+; -0.777 ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.204     ; 0.616      ;
+; -0.759 ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.254      ; 0.626      ;
+; -0.645 ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.102      ; 1.818      ;
+; -0.294 ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.243      ; 1.887      ;
+; -0.234 ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.105      ; 1.702      ;
+; -0.225 ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.105      ; 1.716      ;
+; -0.166 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.500        ; 2.461      ; 2.520      ;
+; -0.114 ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.243      ; 1.720      ;
+; 0.090  ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.500        ; 2.845      ; 2.788      ;
+; 0.094  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.500        ; 2.611      ; 2.553      ;
+; 0.239  ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 2.461      ; 2.615      ;
+; 0.453  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 2.611      ; 2.694      ;
+; 0.493  ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 2.845      ; 2.885      ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'Reset'                                                               ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.923 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.500        ; 2.886      ; 3.418      ;
+; -0.254 ; Reset     ; inst28  ; Reset        ; Reset       ; 1.000        ; 2.886      ; 3.249      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'ten_counter:inst1|inst'                                                                                                 ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.518 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.041     ; 1.492      ;
+; -0.496 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.038     ; 1.473      ;
+; -0.445 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.041     ; 1.419      ;
+; -0.415 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.041     ; 1.389      ;
+; -0.220 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.041     ; 1.194      ;
+; -0.217 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.038     ; 1.194      ;
+; -0.197 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.038     ; 1.174      ;
+; 0.370  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.295      ; 1.639      ;
+; 0.389  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.295      ; 1.620      ;
+; 0.504  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.295      ; 1.505      ;
+; 0.505  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.295      ; 1.504      ;
+; 0.807  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.295      ; 1.702      ;
+; 0.819  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.295      ; 1.690      ;
+; 0.880  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.295      ; 1.629      ;
+; 0.882  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.295      ; 1.627      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'ten_counter:inst2|inst'                                                                                                 ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.505 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.041     ; 1.479      ;
+; -0.490 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.041     ; 1.464      ;
+; -0.351 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.041     ; 1.325      ;
+; -0.346 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.038     ; 1.323      ;
+; -0.225 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.038     ; 1.202      ;
+; -0.222 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.041     ; 1.196      ;
+; -0.212 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.038     ; 1.189      ;
+; 0.466  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.654      ; 1.892      ;
+; 0.594  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.654      ; 1.764      ;
+; 0.599  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.654      ; 1.759      ;
+; 0.614  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.654      ; 1.744      ;
+; 0.896  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.654      ; 1.962      ;
+; 1.010  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.654      ; 1.848      ;
+; 1.017  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.654      ; 1.841      ;
+; 1.048  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.654      ; 1.810      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'one_hertz_clock:inst9|inst102'                                                                                                        ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; -0.481 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.458      ;
+; -0.479 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.044     ; 1.450      ;
+; -0.478 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.044     ; 1.449      ;
+; -0.475 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.044     ; 1.446      ;
+; -0.199 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.176      ;
+; -0.194 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.171      ;
+; -0.192 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.044     ; 1.163      ;
+; 0.313  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.510      ; 2.911      ;
+; 0.443  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.510      ; 2.781      ;
+; 0.446  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.510      ; 2.778      ;
+; 0.529  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.510      ; 2.695      ;
+; 0.882  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.510      ; 2.842      ;
+; 1.038  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.510      ; 2.686      ;
+; 1.042  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.510      ; 2.682      ;
+; 1.121  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.510      ; 2.603      ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'ten_counter:inst6|inst'                                                                                                 ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.054 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.988      ;
+; -0.043 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.977      ;
+; -0.024 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.958      ;
+; -0.009 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.943      ;
+; 0.212  ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.722      ;
+; 0.213  ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.721      ;
+; 0.214  ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.720      ;
+; 0.275  ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.659      ;
+; 0.275  ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.659      ;
+; 0.275  ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.659      ;
+; 0.297  ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.061     ; 0.637      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'one_hertz_clock:inst9|inst102'                                                                                                         ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; -0.545 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.632      ; 2.443      ;
+; -0.426 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.632      ; 2.562      ;
+; -0.420 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.632      ; 2.568      ;
+; -0.322 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.632      ; 2.666      ;
+; 0.078  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.632      ; 2.566      ;
+; 0.137  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.632      ; 2.625      ;
+; 0.140  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.632      ; 2.628      ;
+; 0.237  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.632      ; 2.725      ;
+; 0.851  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.046      ;
+; 0.855  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.050      ;
+; 0.871  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.044      ; 1.072      ;
+; 1.022  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.044      ; 1.223      ;
+; 1.034  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.044      ; 1.235      ;
+; 1.069  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.044      ; 1.270      ;
+; 1.087  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.282      ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'Split'                                                                                               ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; -0.440 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 2.929      ; 2.718      ;
+; -0.375 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 2.686      ; 2.530      ;
+; -0.231 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 2.530      ; 2.518      ;
+; -0.020 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; -0.500       ; 2.929      ; 2.638      ;
+; 0.003  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; -0.500       ; 2.686      ; 2.408      ;
+; 0.132  ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.390      ; 1.542      ;
+; 0.178  ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; -0.500       ; 2.530      ; 2.427      ;
+; 0.227  ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.277      ; 1.524      ;
+; 0.252  ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.277      ; 1.549      ;
+; 0.272  ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.390      ; 1.682      ;
+; 0.310  ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.275      ; 1.605      ;
+; 0.349  ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.539      ; 1.908      ;
+; 0.473  ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.037      ; 0.540      ;
+; 0.481  ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.036      ; 0.547      ;
+; 0.486  ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.036      ; 0.552      ;
+; 0.571  ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.463      ; 0.554      ;
+; 0.669  ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.323      ; 0.512      ;
+; 0.672  ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.320      ; 0.512      ;
+; 0.738  ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; -0.123     ; 0.645      ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'ten_counter:inst2|inst'                                                                                                  ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.401 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.741      ; 1.706      ;
+; -0.401 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.741      ; 1.706      ;
+; -0.400 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.741      ; 1.707      ;
+; -0.216 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.741      ; 1.891      ;
+; 0.027  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.741      ; 1.634      ;
+; 0.029  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.741      ; 1.636      ;
+; 0.074  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.741      ; 1.681      ;
+; 0.217  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.741      ; 1.824      ;
+; 0.869  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.038      ; 1.064      ;
+; 0.870  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.041      ; 1.068      ;
+; 0.877  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.038      ; 1.072      ;
+; 0.971  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.041      ; 1.169      ;
+; 0.972  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.038      ; 1.167      ;
+; 1.052  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.041      ; 1.250      ;
+; 1.088  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.041      ; 1.286      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'DE0CLOCK'                                                                                                                                ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; -0.349 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.115      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.334 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.950      ; 1.992      ;
+; -0.304 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.160      ;
+; -0.304 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.160      ;
+; -0.304 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.160      ;
+; -0.304 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.160      ;
+; -0.304 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 2.088      ; 2.160      ;
+; 0.235  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.199      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.253  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.950      ; 2.079      ;
+; 0.281  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.245      ;
+; 0.281  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.245      ;
+; 0.281  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.245      ;
+; 0.281  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.245      ;
+; 0.281  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 2.088      ; 2.245      ;
+; 0.382  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.415  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.617      ;
+; 0.421  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.623      ;
+; 0.422  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.624      ;
+; 0.434  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.636      ;
+; 0.596  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.798      ;
+; 0.596  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.798      ;
+; 0.597  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.799      ;
+; 0.600  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.802      ;
+; 0.699  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.901      ;
+; 0.728  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.930      ;
+; 0.737  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 0.939      ;
+; 0.878  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 0.965      ;
+; 0.881  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 0.968      ;
+; 0.893  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.095      ;
+; 0.973  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.175      ;
+; 1.001  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.088      ;
+; 1.104  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.306      ;
+; 1.111  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.198      ;
+; 1.134  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.336      ;
+; 1.135  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.337      ;
+; 1.135  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.337      ;
+; 1.136  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 1.331      ;
+; 1.162  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 1.357      ;
+; 1.184  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.271      ;
+; 1.187  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.274      ;
+; 1.194  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.396      ;
+; 1.194  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.281      ;
+; 1.195  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.282      ;
+; 1.234  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.436      ;
+; 1.300  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.387      ;
+; 1.304  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.391      ;
+; 1.305  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.392      ;
+; 1.325  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.038      ; 1.520      ;
+; 1.347  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.549      ;
+; 1.351  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.553      ;
+; 1.351  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.553      ;
+; 1.351  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.553      ;
+; 1.364  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.566      ;
+; 1.364  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.566      ;
+; 1.365  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.567      ;
+; 1.366  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.200      ; 1.723      ;
+; 1.377  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.464      ;
+; 1.378  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.465      ;
+; 1.380  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.467      ;
+; 1.381  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.070     ; 1.468      ;
+; 1.404  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.606      ;
+; 1.404  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.606      ;
+; 1.405  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.045      ; 1.607      ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'ten_counter:inst1|inst'                                                                                                  ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.245 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.367      ; 1.478      ;
+; -0.224 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.367      ; 1.499      ;
+; -0.142 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.367      ; 1.581      ;
+; -0.081 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.367      ; 1.642      ;
+; 0.199  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.367      ; 1.422      ;
+; 0.213  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.367      ; 1.436      ;
+; 0.322  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.367      ; 1.545      ;
+; 0.358  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.367      ; 1.581      ;
+; 0.859  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.038      ; 1.054      ;
+; 0.872  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.041      ; 1.070      ;
+; 0.874  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.038      ; 1.069      ;
+; 1.038  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.041      ; 1.236      ;
+; 1.089  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.041      ; 1.287      ;
+; 1.091  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.038      ; 1.286      ;
+; 1.116  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.041      ; 1.314      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'Reset'                                                               ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.160 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.000        ; 2.981      ; 3.141      ;
+; 0.833 ; Reset     ; inst28  ; Reset        ; Reset       ; -0.500       ; 2.981      ; 3.314      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'ten_counter:inst6|inst'                                                                                                 ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.359 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.577      ;
+; 0.362 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.580      ;
+; 0.392 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.610      ;
+; 0.392 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.610      ;
+; 0.394 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.612      ;
+; 0.560 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.778      ;
+; 0.571 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.789      ;
+; 0.572 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.790      ;
+; 0.587 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.061      ; 0.805      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'ten_counter:inst1|inst'                                                                      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -2.180 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.686     ; 0.989      ;
+; -2.180 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.686     ; 0.989      ;
+; -2.180 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.686     ; 0.989      ;
+; -2.180 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.686     ; 0.989      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'ten_counter:inst2|inst'                                                                      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -1.948 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.327     ; 1.116      ;
+; -1.948 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.327     ; 1.116      ;
+; -1.948 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.327     ; 1.116      ;
+; -1.948 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.327     ; 1.116      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'ten_counter:inst6|inst'                                                                      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -0.679 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.077     ; 1.087      ;
+; -0.679 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.077     ; 1.087      ;
+; -0.679 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.077     ; 1.087      ;
+; -0.679 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.077     ; 1.087      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'one_hertz_clock:inst9|inst102'                                                                      ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; -0.465 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.471     ; 0.989      ;
+; -0.465 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.471     ; 0.989      ;
+; -0.465 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.471     ; 0.989      ;
+; -0.465 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.471     ; 0.989      ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'one_hertz_clock:inst9|inst102'                                                                      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; 0.969 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.254     ; 0.892      ;
+; 0.969 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.254     ; 0.892      ;
+; 0.969 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.254     ; 0.892      ;
+; 0.969 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.254     ; 0.892      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'ten_counter:inst6|inst'                                                                      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 1.155 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.173      ; 1.015      ;
+; 1.155 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.173      ; 1.015      ;
+; 1.155 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.173      ; 1.015      ;
+; 1.155 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.173      ; 1.015      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'ten_counter:inst2|inst'                                                                      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 2.492 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.145     ; 1.024      ;
+; 2.492 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.145     ; 1.024      ;
+; 2.492 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.145     ; 1.024      ;
+; 2.492 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.145     ; 1.024      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'ten_counter:inst1|inst'                                                                      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 2.734 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.519     ; 0.892      ;
+; 2.734 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.519     ; 0.892      ;
+; 2.734 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.519     ; 0.892      ;
+; 2.734 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.519     ; 0.892      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'DE0CLOCK'                                                                 ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                            ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; DE0CLOCK ; Rise       ; DE0CLOCK                          ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; 0.162  ; 0.346        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; 0.166  ; 0.350        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.324  ; 0.324        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; 0.432  ; 0.648        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; 0.435  ; 0.651        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.672  ; 0.672        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.675  ; 0.675        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'Reset'                                              ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target         ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Reset ; Rise       ; Reset          ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28|datac   ;
+; 0.308  ; 0.308        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|datad   ;
+; 0.313  ; 0.313        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28         ;
+; 0.328  ; 0.328        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|combout ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|o  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|i  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|i  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|o  ;
+; 0.671  ; 0.671        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|combout ;
+; 0.687  ; 0.687        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28         ;
+; 0.691  ; 0.691        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|datad   ;
+; 0.697  ; 0.697        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28|datac   ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'Split'                                             ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Split ; Rise       ; Split         ;
+; 0.270  ; 0.270        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst7|datad   ;
+; 0.273  ; 0.273        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst21        ;
+; 0.274  ; 0.274        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst21|datac  ;
+; 0.277  ; 0.277        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst19|datac  ;
+; 0.278  ; 0.278        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst15|datac  ;
+; 0.279  ; 0.279        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst19        ;
+; 0.280  ; 0.280        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst15        ;
+; 0.280  ; 0.280        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst18|datad  ;
+; 0.280  ; 0.280        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst23        ;
+; 0.280  ; 0.280        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst23|datac  ;
+; 0.281  ; 0.281        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst11|datac  ;
+; 0.281  ; 0.281        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst17|datad  ;
+; 0.283  ; 0.283        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst11        ;
+; 0.283  ; 0.283        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst12        ;
+; 0.283  ; 0.283        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst16        ;
+; 0.283  ; 0.283        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst20        ;
+; 0.284  ; 0.284        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst12|datac  ;
+; 0.284  ; 0.284        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst13|datad  ;
+; 0.284  ; 0.284        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst16|datac  ;
+; 0.284  ; 0.284        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst20|datac  ;
+; 0.284  ; 0.284        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst24|datad  ;
+; 0.290  ; 0.290        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst7         ;
+; 0.300  ; 0.300        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst18        ;
+; 0.301  ; 0.301        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst17        ;
+; 0.304  ; 0.304        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst13        ;
+; 0.304  ; 0.304        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst24        ;
+; 0.321  ; 0.321        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst10|datac  ;
+; 0.321  ; 0.321        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst14|datac  ;
+; 0.322  ; 0.322        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst22|datac  ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst10        ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst14        ;
+; 0.324  ; 0.324        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst22        ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|o ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|i ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|o ;
+; 0.675  ; 0.675        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst14        ;
+; 0.675  ; 0.675        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst22        ;
+; 0.676  ; 0.676        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst10        ;
+; 0.677  ; 0.677        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst14|datac  ;
+; 0.677  ; 0.677        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst22|datac  ;
+; 0.678  ; 0.678        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst10|datac  ;
+; 0.696  ; 0.696        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst13        ;
+; 0.696  ; 0.696        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst24        ;
+; 0.699  ; 0.699        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst17        ;
+; 0.700  ; 0.700        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst18        ;
+; 0.709  ; 0.709        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst7         ;
+; 0.716  ; 0.716        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst12|datac  ;
+; 0.716  ; 0.716        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst13|datad  ;
+; 0.716  ; 0.716        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst16|datac  ;
+; 0.716  ; 0.716        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst20|datac  ;
+; 0.716  ; 0.716        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst24|datad  ;
+; 0.717  ; 0.717        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst11        ;
+; 0.717  ; 0.717        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst12        ;
+; 0.717  ; 0.717        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst16        ;
+; 0.717  ; 0.717        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst20        ;
+; 0.719  ; 0.719        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst11|datac  ;
+; 0.719  ; 0.719        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst17|datad  ;
+; 0.719  ; 0.719        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst23        ;
+; 0.720  ; 0.720        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst15        ;
+; 0.720  ; 0.720        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst18|datad  ;
+; 0.720  ; 0.720        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst19        ;
+; 0.720  ; 0.720        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst23|datac  ;
+; 0.722  ; 0.722        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst15|datac  ;
+; 0.722  ; 0.722        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst19|datac  ;
+; 0.725  ; 0.725        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst21|datac  ;
+; 0.726  ; 0.726        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst21        ;
+; 0.729  ; 0.729        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst7|datad   ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'                                                       ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                         ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.291  ; 0.291        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.291  ; 0.291        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.291  ; 0.291        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.291  ; 0.291        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
+; 0.393  ; 0.393        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.412  ; 0.412        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.584  ; 0.584        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.601  ; 0.601        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst1|inst'                                                       ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.218  ; 0.434        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.218  ; 0.434        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.218  ; 0.434        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.218  ; 0.434        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.382  ; 0.566        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.382  ; 0.566        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.382  ; 0.566        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.382  ; 0.566        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.433  ; 0.433        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
+; 0.439  ; 0.439        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.456  ; 0.456        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.542  ; 0.542        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.558  ; 0.558        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.564  ; 0.564        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst2|inst'                                                       ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.217  ; 0.433        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.383  ; 0.567        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.414  ; 0.414        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
+; 0.430  ; 0.430        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
+; 0.455  ; 0.455        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.455  ; 0.455        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.455  ; 0.455        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.455  ; 0.455        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.543  ; 0.543        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.543  ; 0.543        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.543  ; 0.543        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.543  ; 0.543        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.567  ; 0.567        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
+; 0.583  ; 0.583        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'ten_counter:inst6|inst'                                                             ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.271  ; 0.487        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.271  ; 0.487        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.271  ; 0.487        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.271  ; 0.487        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.321  ; 0.505        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.321  ; 0.505        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.321  ; 0.505        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.321  ; 0.505        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.483  ; 0.483        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.483  ; 0.483        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.483  ; 0.483        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.483  ; 0.483        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
+; 0.484  ; 0.484        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
+; 0.490  ; 0.490        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.490  ; 0.490        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.505  ; 0.505        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.505  ; 0.505        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
+; 0.511  ; 0.511        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.511  ; 0.511        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.511  ; 0.511        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.511  ; 0.511        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
+; 0.512  ; 0.512        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Reset     ; Reset      ; 1.254 ; 1.423 ; Rise       ; Reset           ;
+; Start     ; Reset      ; 3.420 ; 3.904 ; Rise       ; Reset           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Reset     ; Reset      ; -0.160 ; -0.333 ; Rise       ; Reset           ;
+; Start     ; Reset      ; -2.241 ; -2.710 ; Rise       ; Reset           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 7.291 ; 7.387 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 7.291 ; 7.376 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 7.286 ; 7.387 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 6.893 ; 6.900 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 6.855 ; 6.920 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 6.874 ; 6.936 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 6.900 ; 6.909 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 6.841 ; 6.887 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 7.009 ; 7.059 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 6.743 ; 6.823 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 6.472 ; 6.566 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 6.520 ; 6.576 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 6.565 ; 6.648 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 6.291 ; 6.381 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 7.009 ; 7.059 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 6.809 ; 6.858 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 6.722 ; 6.772 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 6.659 ; 6.733 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 6.474 ; 6.590 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 6.498 ; 6.556 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 6.481 ; 6.543 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 6.722 ; 6.716 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 6.502 ; 6.576 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 6.717 ; 6.772 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 6.698 ; 6.781 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 6.338 ; 6.396 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 6.613 ; 6.747 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 6.327 ; 6.360 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 6.369 ; 6.431 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 6.483 ; 6.616 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 6.698 ; 6.781 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 6.542 ; 6.606 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 5.394 ; 5.478 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 5.824 ; 5.916 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 5.916 ; 5.920 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 5.430 ; 5.485 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 5.406 ; 5.478 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 5.476 ; 5.582 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 5.425 ; 5.514 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 5.394 ; 5.480 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 5.401 ; 5.445 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 5.571 ; 5.644 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 5.769 ; 5.823 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 5.403 ; 5.445 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 5.401 ; 5.474 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 5.613 ; 5.655 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 5.845 ; 5.953 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 5.621 ; 5.748 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 5.836 ; 5.918 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 6.007 ; 6.100 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 5.894 ; 5.969 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 5.884 ; 5.927 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 5.836 ; 5.918 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 6.094 ; 6.220 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 5.859 ; 5.989 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 6.061 ; 6.171 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 5.860 ; 5.934 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 5.860 ; 5.934 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 6.264 ; 6.364 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 5.898 ; 5.971 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 5.892 ; 5.958 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 6.229 ; 6.255 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 6.209 ; 6.296 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 6.054 ; 6.128 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                                             ;
++-------------+-----------------+-------------------------------+---------------------------------------------------------------+
+; Fmax        ; Restricted Fmax ; Clock Name                    ; Note                                                          ;
++-------------+-----------------+-------------------------------+---------------------------------------------------------------+
+; 327.87 MHz  ; 250.0 MHz       ; DE0CLOCK                      ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 393.7 MHz   ; 250.0 MHz       ; Reset                         ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 738.01 MHz  ; 500.0 MHz       ; ten_counter:inst1|inst        ; limit due to minimum period restriction (tmin)                ;
+; 742.39 MHz  ; 500.0 MHz       ; ten_counter:inst2|inst        ; limit due to minimum period restriction (tmin)                ;
+; 754.72 MHz  ; 500.0 MHz       ; one_hertz_clock:inst9|inst102 ; limit due to minimum period restriction (tmin)                ;
+; 1060.45 MHz ; 500.0 MHz       ; ten_counter:inst6|inst        ; limit due to minimum period restriction (tmin)                ;
++-------------+-----------------+-------------------------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                     ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -2.050 ; -38.014       ;
+; Split                         ; -0.772 ; -5.372        ;
+; Reset                         ; -0.770 ; -0.770        ;
+; ten_counter:inst1|inst        ; -0.355 ; -0.961        ;
+; ten_counter:inst2|inst        ; -0.347 ; -0.891        ;
+; one_hertz_clock:inst9|inst102 ; -0.325 ; -0.962        ;
+; ten_counter:inst6|inst        ; 0.057  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                      ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; one_hertz_clock:inst9|inst102 ; -0.493 ; -1.569        ;
+; Split                         ; -0.486 ; -1.250        ;
+; ten_counter:inst2|inst        ; -0.386 ; -1.354        ;
+; DE0CLOCK                      ; -0.361 ; -6.640        ;
+; ten_counter:inst1|inst        ; -0.230 ; -0.633        ;
+; Reset                         ; 0.104  ; 0.000         ;
+; ten_counter:inst6|inst        ; 0.313  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                  ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; ten_counter:inst1|inst        ; -2.039 ; -8.156        ;
+; ten_counter:inst2|inst        ; -1.819 ; -7.276        ;
+; ten_counter:inst6|inst        ; -0.688 ; -2.752        ;
+; one_hertz_clock:inst9|inst102 ; -0.412 ; -1.648        ;
++-------------------------------+--------+---------------+
+
+
++-------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                  ;
++-------------------------------+-------+---------------+
+; Clock                         ; Slack ; End Point TNS ;
++-------------------------------+-------+---------------+
+; one_hertz_clock:inst9|inst102 ; 0.953 ; 0.000         ;
+; ten_counter:inst6|inst        ; 1.218 ; 0.000         ;
+; ten_counter:inst2|inst        ; 2.412 ; 0.000         ;
+; ten_counter:inst1|inst        ; 2.625 ; 0.000         ;
++-------------------------------+-------+---------------+
+
+
++--------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary       ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -3.000 ; -22.000       ;
+; Reset                         ; -3.000 ; -3.000        ;
+; Split                         ; -3.000 ; -3.000        ;
+; one_hertz_clock:inst9|inst102 ; -1.000 ; -4.000        ;
+; ten_counter:inst1|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst2|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst6|inst        ; -1.000 ; -4.000        ;
++-------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'DE0CLOCK'                                                                                                               ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; -2.050 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.123      ;
+; -2.050 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.123      ;
+; -2.050 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.123      ;
+; -2.050 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.123      ;
+; -2.050 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.123      ;
+; -2.029 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.102      ;
+; -2.020 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.093      ;
+; -2.020 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.093      ;
+; -2.020 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.093      ;
+; -2.020 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.093      ;
+; -2.020 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.093      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.980 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.956      ;
+; -1.976 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 3.049      ;
+; -1.975 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.034     ; 2.956      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.965 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.941      ;
+; -1.960 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.034     ; 2.941      ;
+; -1.882 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.955      ;
+; -1.882 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.955      ;
+; -1.882 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.955      ;
+; -1.882 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.955      ;
+; -1.882 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.955      ;
+; -1.879 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.952      ;
+; -1.879 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.952      ;
+; -1.879 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.952      ;
+; -1.879 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.952      ;
+; -1.879 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.952      ;
+; -1.861 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.934      ;
+; -1.858 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.931      ;
+; -1.815 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.888      ;
+; -1.815 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.888      ;
+; -1.815 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.888      ;
+; -1.815 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.888      ;
+; -1.815 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.888      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.788      ;
+; -1.812 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.885      ;
+; -1.812 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.885      ;
+; -1.812 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.885      ;
+; -1.812 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.885      ;
+; -1.812 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.885      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.809 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.785      ;
+; -1.807 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.034     ; 2.788      ;
+; -1.806 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.879      ;
+; -1.806 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.879      ;
+; -1.806 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.879      ;
+; -1.806 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.879      ;
+; -1.806 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.879      ;
+; -1.804 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.034     ; 2.785      ;
+; -1.794 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.867      ;
+; -1.775 ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.751      ;
+; -1.769 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.842      ;
+; -1.769 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.842      ;
+; -1.769 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.842      ;
+; -1.769 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.842      ;
+; -1.769 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.842      ;
+; -1.768 ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.039     ; 2.744      ;
+; -1.768 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.058      ; 2.841      ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'Split'                                                                                               ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; -0.772 ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.316      ; 1.849      ;
+; -0.658 ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.143      ; 0.491      ;
+; -0.657 ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.140      ; 0.491      ;
+; -0.618 ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.240     ; 0.668      ;
+; -0.590 ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.262      ; 0.558      ;
+; -0.518 ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.102     ; 0.541      ;
+; -0.517 ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.103     ; 0.555      ;
+; -0.503 ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; -0.103     ; 0.549      ;
+; -0.369 ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.066      ; 1.604      ;
+; -0.084 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.500        ; 2.283      ; 2.324      ;
+; -0.052 ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.212      ; 1.673      ;
+; -0.017 ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.070      ; 1.507      ;
+; -0.017 ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.070      ; 1.528      ;
+; 0.098  ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.213      ; 1.535      ;
+; 0.160  ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.500        ; 2.640      ; 2.554      ;
+; 0.170  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.500        ; 2.445      ; 2.351      ;
+; 0.393  ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 2.283      ; 2.347      ;
+; 0.627  ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 2.640      ; 2.587      ;
+; 0.645  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 2.445      ; 2.376      ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'Reset'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.770 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.500        ; 2.722      ; 3.193      ;
+; -0.084 ; Reset     ; inst28  ; Reset        ; Reset       ; 1.000        ; 2.722      ; 3.007      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'ten_counter:inst1|inst'                                                                                                  ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.355 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.036     ; 1.334      ;
+; -0.336 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.034     ; 1.317      ;
+; -0.290 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.036     ; 1.269      ;
+; -0.270 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.036     ; 1.249      ;
+; -0.090 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.036     ; 1.069      ;
+; -0.089 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.034     ; 1.070      ;
+; -0.072 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.034     ; 1.053      ;
+; 0.375  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.166      ; 1.486      ;
+; 0.389  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.166      ; 1.472      ;
+; 0.488  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.166      ; 1.373      ;
+; 0.495  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 1.166      ; 1.366      ;
+; 0.806  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.166      ; 1.555      ;
+; 0.850  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.166      ; 1.511      ;
+; 0.904  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.166      ; 1.457      ;
+; 0.906  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 1.166      ; 1.455      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'ten_counter:inst2|inst'                                                                                                  ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.347 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.037     ; 1.325      ;
+; -0.336 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.037     ; 1.314      ;
+; -0.213 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.037     ; 1.191      ;
+; -0.208 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.034     ; 1.189      ;
+; -0.099 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.034     ; 1.080      ;
+; -0.096 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.037     ; 1.074      ;
+; -0.086 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.034     ; 1.067      ;
+; 0.475  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.494      ; 1.704      ;
+; 0.580  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.494      ; 1.599      ;
+; 0.582  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.494      ; 1.597      ;
+; 0.600  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 1.494      ; 1.579      ;
+; 0.907  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.494      ; 1.772      ;
+; 1.033  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.494      ; 1.646      ;
+; 1.041  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.494      ; 1.638      ;
+; 1.069  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 1.494      ; 1.610      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'one_hertz_clock:inst9|inst102'                                                                                                         ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; -0.325 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.034     ; 1.306      ;
+; -0.321 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.298      ;
+; -0.319 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.296      ;
+; -0.316 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.293      ;
+; -0.073 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.034     ; 1.054      ;
+; -0.071 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.038     ; 1.048      ;
+; -0.070 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.034     ; 1.051      ;
+; 0.362  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.293      ; 2.626      ;
+; 0.471  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.293      ; 2.517      ;
+; 0.473  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.293      ; 2.515      ;
+; 0.587  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 2.293      ; 2.401      ;
+; 0.922  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.293      ; 2.566      ;
+; 1.037  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.293      ; 2.451      ;
+; 1.040  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.293      ; 2.448      ;
+; 1.117  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 2.293      ; 2.371      ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'ten_counter:inst6|inst'                                                                                                 ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.057 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.884      ;
+; 0.067 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.874      ;
+; 0.085 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.856      ;
+; 0.107 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.834      ;
+; 0.292 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.649      ;
+; 0.294 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.647      ;
+; 0.294 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.647      ;
+; 0.358 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.583      ;
+; 0.358 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.583      ;
+; 0.358 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.583      ;
+; 0.379 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.054     ; 0.562      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'one_hertz_clock:inst9|inst102'                                                                                                          ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; -0.493 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.403      ; 2.234      ;
+; -0.383 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.403      ; 2.344      ;
+; -0.377 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.403      ; 2.350      ;
+; -0.316 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 2.403      ; 2.411      ;
+; 0.059  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.403      ; 2.286      ;
+; 0.155  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.403      ; 2.382      ;
+; 0.158  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.403      ; 2.385      ;
+; 0.234  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 2.403      ; 2.461      ;
+; 0.771  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.034      ; 0.949      ;
+; 0.773  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.034      ; 0.951      ;
+; 0.783  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 0.965      ;
+; 0.922  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.104      ;
+; 0.931  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.113      ;
+; 0.962  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.038      ; 1.144      ;
+; 0.979  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.034      ; 1.157      ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'Split'                                                                                                ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; -0.486 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 2.715      ; 2.439      ;
+; -0.482 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 2.512      ; 2.230      ;
+; -0.282 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 2.342      ; 2.260      ;
+; -0.010 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; -0.500       ; 2.715      ; 2.415      ;
+; 0.005  ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; -0.500       ; 2.512      ; 2.217      ;
+; 0.053  ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.344      ; 1.417      ;
+; 0.149  ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.224      ; 1.393      ;
+; 0.168  ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.224      ; 1.412      ;
+; 0.182  ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.344      ; 1.546      ;
+; 0.196  ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; -0.500       ; 2.342      ; 2.238      ;
+; 0.237  ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.221      ; 1.478      ;
+; 0.281  ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.450      ; 1.751      ;
+; 0.349  ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.112      ; 0.491      ;
+; 0.353  ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.111      ; 0.494      ;
+; 0.361  ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.112      ; 0.503      ;
+; 0.535  ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.448      ; 0.503      ;
+; 0.584  ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; -0.032     ; 0.582      ;
+; 0.611  ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.323      ; 0.454      ;
+; 0.614  ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.320      ; 0.454      ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'ten_counter:inst2|inst'                                                                                                   ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.386 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.573      ; 1.521      ;
+; -0.386 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.573      ; 1.521      ;
+; -0.382 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.573      ; 1.525      ;
+; -0.200 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 1.573      ; 1.707      ;
+; 0.077  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.573      ; 1.484      ;
+; 0.079  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.573      ; 1.486      ;
+; 0.117  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.573      ; 1.524      ;
+; 0.234  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 1.573      ; 1.641      ;
+; 0.788  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.034      ; 0.966      ;
+; 0.789  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.037      ; 0.970      ;
+; 0.795  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.034      ; 0.973      ;
+; 0.874  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.037      ; 1.055      ;
+; 0.876  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.034      ; 1.054      ;
+; 0.948  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.037      ; 1.129      ;
+; 0.979  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.037      ; 1.160      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'DE0CLOCK'                                                                                                                                 ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.361 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.829      ; 1.812      ;
+; -0.357 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.934      ;
+; -0.318 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.973      ;
+; -0.318 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.973      ;
+; -0.318 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.973      ;
+; -0.318 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.973      ;
+; -0.318 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.947      ; 1.973      ;
+; 0.166  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 1.957      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.192  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.829      ; 1.865      ;
+; 0.220  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 2.011      ;
+; 0.220  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 2.011      ;
+; 0.220  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 2.011      ;
+; 0.220  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 2.011      ;
+; 0.220  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.947      ; 2.011      ;
+; 0.333  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.341  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.371  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.554      ;
+; 0.376  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.559      ;
+; 0.377  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.560      ;
+; 0.388  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.571      ;
+; 0.536  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.719      ;
+; 0.536  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.719      ;
+; 0.536  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.719      ;
+; 0.538  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.721      ;
+; 0.641  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.824      ;
+; 0.668  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.851      ;
+; 0.678  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 0.861      ;
+; 0.793  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 0.879      ;
+; 0.796  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 0.882      ;
+; 0.824  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.007      ;
+; 0.874  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.057      ;
+; 0.895  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 0.981      ;
+; 0.994  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.080      ;
+; 1.008  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.191      ;
+; 1.031  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 1.209      ;
+; 1.039  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 1.217      ;
+; 1.043  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.226      ;
+; 1.043  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.226      ;
+; 1.044  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.227      ;
+; 1.057  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.143      ;
+; 1.060  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.146      ;
+; 1.079  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.165      ;
+; 1.080  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.263      ;
+; 1.080  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.166      ;
+; 1.128  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.311      ;
+; 1.173  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.259      ;
+; 1.178  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.264      ;
+; 1.179  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.265      ;
+; 1.211  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.034      ; 1.389      ;
+; 1.228  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.411      ;
+; 1.228  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.411      ;
+; 1.235  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.418      ;
+; 1.237  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.420      ;
+; 1.241  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.327      ;
+; 1.242  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.328      ;
+; 1.244  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.330      ;
+; 1.245  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.331      ;
+; 1.245  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.428      ;
+; 1.245  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.428      ;
+; 1.246  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.429      ;
+; 1.254  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.173      ; 1.571      ;
+; 1.272  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.058     ; 1.358      ;
+; 1.286  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.469      ;
+; 1.286  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.039      ; 1.469      ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'ten_counter:inst1|inst'                                                                                                   ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.230 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.231      ; 1.325      ;
+; -0.211 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.231      ; 1.344      ;
+; -0.136 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.231      ; 1.419      ;
+; -0.056 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 1.231      ; 1.499      ;
+; 0.240  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.231      ; 1.295      ;
+; 0.252  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.231      ; 1.307      ;
+; 0.355  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.231      ; 1.410      ;
+; 0.376  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 1.231      ; 1.431      ;
+; 0.778  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.034      ; 0.956      ;
+; 0.789  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.036      ; 0.969      ;
+; 0.790  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.034      ; 0.968      ;
+; 0.936  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.036      ; 1.116      ;
+; 0.980  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.034      ; 1.158      ;
+; 0.983  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.036      ; 1.163      ;
+; 1.012  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.036      ; 1.192      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'Reset'                                                                ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.104 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.000        ; 2.809      ; 2.913      ;
+; 0.790 ; Reset     ; inst28  ; Reset        ; Reset       ; -0.500       ; 2.809      ; 3.099      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'ten_counter:inst6|inst'                                                                                                  ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.313 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.511      ;
+; 0.321 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.519      ;
+; 0.350 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.548      ;
+; 0.351 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.549      ;
+; 0.352 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.550      ;
+; 0.503 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.701      ;
+; 0.512 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.710      ;
+; 0.513 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.711      ;
+; 0.524 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.054      ; 0.722      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'ten_counter:inst1|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -2.039 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.643     ; 0.891      ;
+; -2.039 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.643     ; 0.891      ;
+; -2.039 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.643     ; 0.891      ;
+; -2.039 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -1.643     ; 0.891      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'ten_counter:inst2|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -1.819 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.315     ; 0.999      ;
+; -1.819 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.315     ; 0.999      ;
+; -1.819 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.315     ; 0.999      ;
+; -1.819 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -1.315     ; 0.999      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'ten_counter:inst6|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -0.688 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.196     ; 0.977      ;
+; -0.688 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.196     ; 0.977      ;
+; -0.688 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.196     ; 0.977      ;
+; -0.688 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; -0.196     ; 0.977      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'one_hertz_clock:inst9|inst102'                                                                       ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; -0.412 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.516     ; 0.891      ;
+; -0.412 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.516     ; 0.891      ;
+; -0.412 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.516     ; 0.891      ;
+; -0.412 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.516     ; 0.891      ;
++--------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'one_hertz_clock:inst9|inst102'                                                                       ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; 0.953 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.319     ; 0.798      ;
+; 0.953 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.319     ; 0.798      ;
+; 0.953 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.319     ; 0.798      ;
+; 0.953 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.319     ; 0.798      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'ten_counter:inst6|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 1.218 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.030      ; 0.922      ;
+; 1.218 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.030      ; 0.922      ;
+; 1.218 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.030      ; 0.922      ;
+; 1.218 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.030      ; 0.922      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'ten_counter:inst2|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 2.412 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.149     ; 0.927      ;
+; 2.412 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.149     ; 0.927      ;
+; 2.412 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.149     ; 0.927      ;
+; 2.412 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -1.149     ; 0.927      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'ten_counter:inst1|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 2.625 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.491     ; 0.798      ;
+; 2.625 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.491     ; 0.798      ;
+; 2.625 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.491     ; 0.798      ;
+; 2.625 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -1.491     ; 0.798      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'DE0CLOCK'                                                                  ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                            ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; DE0CLOCK ; Rise       ; DE0CLOCK                          ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; 0.129  ; 0.313        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; 0.146  ; 0.330        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.289  ; 0.289        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.306  ; 0.306        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; 0.452  ; 0.668        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; 0.469  ; 0.685        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.692  ; 0.692        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.709  ; 0.709        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'Reset'                                               ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target         ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Reset ; Rise       ; Reset          ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|o  ;
+; 0.366  ; 0.366        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|datad   ;
+; 0.379  ; 0.379        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28|datac   ;
+; 0.382  ; 0.382        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28         ;
+; 0.388  ; 0.388        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|combout ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|i  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|i  ;
+; 0.608  ; 0.608        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|combout ;
+; 0.612  ; 0.612        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28         ;
+; 0.617  ; 0.617        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28|datac   ;
+; 0.632  ; 0.632        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|datad   ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|o  ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'Split'                                              ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Split ; Rise       ; Split         ;
+; 0.326  ; 0.326        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst15|datac  ;
+; 0.326  ; 0.326        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst19|datac  ;
+; 0.329  ; 0.329        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst23|datac  ;
+; 0.331  ; 0.331        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst11|datac  ;
+; 0.331  ; 0.331        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst15        ;
+; 0.331  ; 0.331        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst19        ;
+; 0.332  ; 0.332        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst23        ;
+; 0.336  ; 0.336        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst11        ;
+; 0.336  ; 0.336        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst12|datac  ;
+; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst16|datac  ;
+; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst20|datac  ;
+; 0.338  ; 0.338        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst12        ;
+; 0.338  ; 0.338        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst24|datad  ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|o ;
+; 0.339  ; 0.339        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst16        ;
+; 0.339  ; 0.339        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst20        ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst7|datad   ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst21|datac  ;
+; 0.347  ; 0.347        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst18|datad  ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst17|datad  ;
+; 0.348  ; 0.348        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst21        ;
+; 0.349  ; 0.349        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst10|datac  ;
+; 0.349  ; 0.349        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst14|datac  ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst13|datad  ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst22|datac  ;
+; 0.354  ; 0.354        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst10        ;
+; 0.354  ; 0.354        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst14        ;
+; 0.356  ; 0.356        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst22        ;
+; 0.360  ; 0.360        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst24        ;
+; 0.366  ; 0.366        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst7         ;
+; 0.369  ; 0.369        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst18        ;
+; 0.370  ; 0.370        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst17        ;
+; 0.373  ; 0.373        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst13        ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|i ;
+; 0.625  ; 0.625        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst13        ;
+; 0.628  ; 0.628        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst17        ;
+; 0.628  ; 0.628        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst18        ;
+; 0.631  ; 0.631        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst7         ;
+; 0.638  ; 0.638        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst24        ;
+; 0.644  ; 0.644        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst14        ;
+; 0.644  ; 0.644        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst22        ;
+; 0.646  ; 0.646        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst10        ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst13|datad  ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst14|datac  ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst22|datac  ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst10|datac  ;
+; 0.651  ; 0.651        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst21        ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst17|datad  ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst18|datad  ;
+; 0.653  ; 0.653        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst21|datac  ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst7|datad   ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|o ;
+; 0.661  ; 0.661        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst16        ;
+; 0.661  ; 0.661        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst20        ;
+; 0.662  ; 0.662        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst12        ;
+; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst24|datad  ;
+; 0.663  ; 0.663        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst16|datac  ;
+; 0.663  ; 0.663        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst20|datac  ;
+; 0.664  ; 0.664        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst11        ;
+; 0.664  ; 0.664        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst12|datac  ;
+; 0.667  ; 0.667        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst23        ;
+; 0.669  ; 0.669        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst11|datac  ;
+; 0.669  ; 0.669        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst15        ;
+; 0.669  ; 0.669        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst19        ;
+; 0.671  ; 0.671        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst23|datac  ;
+; 0.674  ; 0.674        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst15|datac  ;
+; 0.674  ; 0.674        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst19|datac  ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'                                                        ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                         ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.414  ; 0.414        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.426  ; 0.426        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.571  ; 0.571        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.582  ; 0.582        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.626  ; 0.626        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst1|inst'                                                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.231  ; 0.447        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.368  ; 0.552        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.454  ; 0.454        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
+; 0.455  ; 0.455        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.471  ; 0.471        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.471  ; 0.471        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.471  ; 0.471        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.471  ; 0.471        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.528  ; 0.528        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.528  ; 0.528        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.528  ; 0.528        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.528  ; 0.528        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.544  ; 0.544        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.544  ; 0.544        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst2|inst'                                                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.225  ; 0.441        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.225  ; 0.441        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.225  ; 0.441        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.225  ; 0.441        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.373  ; 0.557        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.373  ; 0.557        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.373  ; 0.557        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.373  ; 0.557        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.442  ; 0.442        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
+; 0.459  ; 0.459        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.538  ; 0.538        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
+; 0.555  ; 0.555        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst6|inst'                                                              ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.244  ; 0.460        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.244  ; 0.460        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.244  ; 0.460        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.244  ; 0.460        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.478  ; 0.478        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.478  ; 0.478        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
+; 0.484  ; 0.484        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.484  ; 0.484        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.484  ; 0.484        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.484  ; 0.484        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
+; 0.487  ; 0.487        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.509  ; 0.509        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
+; 0.513  ; 0.513        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.513  ; 0.513        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.513  ; 0.513        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.513  ; 0.513        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
+; 0.519  ; 0.519        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.519  ; 0.519        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Reset     ; Reset      ; 1.084 ; 1.270 ; Rise       ; Reset           ;
+; Start     ; Reset      ; 2.956 ; 3.317 ; Rise       ; Reset           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Reset     ; Reset      ; -0.104 ; -0.290 ; Rise       ; Reset           ;
+; Start     ; Reset      ; -1.901 ; -2.253 ; Rise       ; Reset           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 6.834 ; 6.953 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 6.834 ; 6.951 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 6.828 ; 6.953 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 6.465 ; 6.501 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 6.445 ; 6.516 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 6.461 ; 6.522 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 6.474 ; 6.516 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 6.418 ; 6.493 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 6.548 ; 6.681 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 6.357 ; 6.429 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 6.117 ; 6.209 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 6.124 ; 6.237 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 6.198 ; 6.259 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 5.956 ; 6.027 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 6.548 ; 6.681 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 6.389 ; 6.498 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 6.327 ; 6.412 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 6.265 ; 6.381 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 6.116 ; 6.234 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 6.114 ; 6.215 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 6.107 ; 6.207 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 6.327 ; 6.369 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 6.131 ; 6.239 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 6.302 ; 6.412 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 6.309 ; 6.416 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 5.994 ; 6.064 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 6.217 ; 6.387 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 5.988 ; 6.028 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 6.025 ; 6.094 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 6.117 ; 6.267 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 6.309 ; 6.416 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 6.160 ; 6.261 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 5.124 ; 5.209 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 5.506 ; 5.647 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 5.583 ; 5.637 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 5.145 ; 5.229 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 5.133 ; 5.228 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 5.194 ; 5.304 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 5.156 ; 5.248 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 5.124 ; 5.209 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 5.155 ; 5.221 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 5.306 ; 5.411 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 5.482 ; 5.567 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 5.156 ; 5.221 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 5.155 ; 5.246 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 5.340 ; 5.404 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 5.541 ; 5.684 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 5.362 ; 5.499 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 5.536 ; 5.642 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 5.688 ; 5.809 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 5.585 ; 5.681 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 5.570 ; 5.647 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 5.536 ; 5.642 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 5.759 ; 5.908 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 5.560 ; 5.704 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 5.718 ; 5.862 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 5.559 ; 5.659 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 5.559 ; 5.659 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 5.904 ; 6.037 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 5.597 ; 5.690 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 5.590 ; 5.680 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 5.888 ; 5.942 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 5.866 ; 5.992 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 5.718 ; 5.835 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                     ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -0.896 ; -16.354       ;
+; Reset                         ; -0.696 ; -0.696        ;
+; Split                         ; 0.125  ; 0.000         ;
+; ten_counter:inst1|inst        ; 0.176  ; 0.000         ;
+; ten_counter:inst2|inst        ; 0.180  ; 0.000         ;
+; one_hertz_clock:inst9|inst102 ; 0.192  ; 0.000         ;
+; ten_counter:inst6|inst        ; 0.408  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                      ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; Split                         ; -0.502 ; -3.342        ;
+; one_hertz_clock:inst9|inst102 ; -0.309 ; -1.019        ;
+; DE0CLOCK                      ; -0.283 ; -5.149        ;
+; ten_counter:inst2|inst        ; -0.229 ; -0.830        ;
+; ten_counter:inst1|inst        ; -0.143 ; -0.438        ;
+; Reset                         ; 0.171  ; 0.000         ;
+; ten_counter:inst6|inst        ; 0.187  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++--------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                  ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; ten_counter:inst1|inst        ; -0.972 ; -3.888        ;
+; ten_counter:inst2|inst        ; -0.847 ; -3.388        ;
+; ten_counter:inst6|inst        ; -0.097 ; -0.388        ;
+; one_hertz_clock:inst9|inst102 ; 0.214  ; 0.000         ;
++-------------------------------+--------+---------------+
+
+
++-------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                  ;
++-------------------------------+-------+---------------+
+; Clock                         ; Slack ; End Point TNS ;
++-------------------------------+-------+---------------+
+; one_hertz_clock:inst9|inst102 ; 0.489 ; 0.000         ;
+; ten_counter:inst6|inst        ; 0.759 ; 0.000         ;
+; ten_counter:inst2|inst        ; 1.560 ; 0.000         ;
+; ten_counter:inst1|inst        ; 1.702 ; 0.000         ;
++-------------------------------+-------+---------------+
+
+
++--------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary       ;
++-------------------------------+--------+---------------+
+; Clock                         ; Slack  ; End Point TNS ;
++-------------------------------+--------+---------------+
+; DE0CLOCK                      ; -3.000 ; -22.400       ;
+; Split                         ; -3.000 ; -3.097        ;
+; Reset                         ; -3.000 ; -3.008        ;
+; one_hertz_clock:inst9|inst102 ; -1.000 ; -4.000        ;
+; ten_counter:inst1|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst2|inst        ; -1.000 ; -4.000        ;
+; ten_counter:inst6|inst        ; -1.000 ; -4.000        ;
++-------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'DE0CLOCK'                                                                                                               ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+; -0.896 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.947      ;
+; -0.880 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.931      ;
+; -0.880 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.931      ;
+; -0.880 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.931      ;
+; -0.880 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.931      ;
+; -0.880 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.931      ;
+; -0.854 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.905      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.851 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.831      ;
+; -0.846 ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.022     ; 1.831      ;
+; -0.838 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.889      ;
+; -0.838 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.889      ;
+; -0.838 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.889      ;
+; -0.838 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.889      ;
+; -0.838 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.889      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.809 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.789      ;
+; -0.804 ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.022     ; 1.789      ;
+; -0.791 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.842      ;
+; -0.785 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.836      ;
+; -0.775 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.826      ;
+; -0.775 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.826      ;
+; -0.775 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.826      ;
+; -0.775 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.826      ;
+; -0.775 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.826      ;
+; -0.769 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.820      ;
+; -0.769 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.820      ;
+; -0.769 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.820      ;
+; -0.769 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.820      ;
+; -0.769 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.820      ;
+; -0.753 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.804      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.746 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.726      ;
+; -0.742 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.793      ;
+; -0.741 ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.022     ; 1.726      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.740 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.720      ;
+; -0.737 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.788      ;
+; -0.737 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.788      ;
+; -0.737 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.788      ;
+; -0.737 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.788      ;
+; -0.737 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.788      ;
+; -0.735 ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.022     ; 1.720      ;
+; -0.731 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.782      ;
+; -0.726 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.777      ;
+; -0.726 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.777      ;
+; -0.726 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.777      ;
+; -0.726 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.777      ;
+; -0.726 ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.777      ;
+; -0.715 ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.695      ;
+; -0.715 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.766      ;
+; -0.715 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.766      ;
+; -0.715 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.766      ;
+; -0.715 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst72      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.766      ;
+; -0.715 ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.766      ;
+; -0.712 ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.022     ; 1.697      ;
+; -0.711 ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; 0.044      ; 1.762      ;
+; -0.708 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.688      ;
+; -0.708 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.688      ;
+; -0.708 ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK     ; DE0CLOCK    ; 1.000        ; -0.027     ; 1.688      ;
++--------+-----------------------------------+-----------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'Reset'                                                                ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.696 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.500        ; 1.563      ; 2.266      ;
+; 0.222  ; Reset     ; inst28  ; Reset        ; Reset       ; 1.000        ; 1.563      ; 1.848      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'Split'                                                                                              ;
++-------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; 0.125 ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.442      ; 0.300      ;
+; 0.126 ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.444      ; 0.300      ;
+; 0.130 ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.155      ; 1.238      ;
+; 0.174 ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; 0.500        ; 0.517      ; 0.341      ;
+; 0.295 ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 0.151      ; 0.404      ;
+; 0.339 ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 0.228      ; 0.339      ;
+; 0.344 ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 0.227      ; 0.335      ;
+; 0.348 ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 0.228      ; 0.329      ;
+; 0.427 ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.006      ; 1.054      ;
+; 0.484 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.500        ; 1.737      ; 1.403      ;
+; 0.600 ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.083      ; 1.120      ;
+; 0.617 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.500        ; 1.845      ; 1.462      ;
+; 0.636 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.500        ; 1.973      ; 1.568      ;
+; 0.675 ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.011      ; 0.983      ;
+; 0.691 ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.011      ; 0.980      ;
+; 0.720 ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.083      ; 1.010      ;
+; 0.802 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 1.000        ; 1.737      ; 1.585      ;
+; 0.946 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 1.000        ; 1.973      ; 1.758      ;
+; 0.950 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 1.000        ; 1.845      ; 1.629      ;
++-------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'ten_counter:inst1|inst'                                                                                                 ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.176 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.024     ; 0.807      ;
+; 0.190 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.022     ; 0.795      ;
+; 0.216 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.024     ; 0.767      ;
+; 0.240 ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.024     ; 0.743      ;
+; 0.345 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.024     ; 0.638      ;
+; 0.348 ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.022     ; 0.637      ;
+; 0.359 ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 1.000        ; -0.022     ; 0.626      ;
+; 0.436 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 0.718      ; 0.894      ;
+; 0.480 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 0.718      ; 0.850      ;
+; 0.532 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 0.718      ; 0.798      ;
+; 0.533 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.500        ; 0.718      ; 0.797      ;
+; 0.910 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 0.718      ; 0.920      ;
+; 0.925 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 0.718      ; 0.905      ;
+; 0.941 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 0.718      ; 0.889      ;
+; 0.944 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 1.000        ; 0.718      ; 0.886      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'ten_counter:inst2|inst'                                                                                                 ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.180 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.026     ; 0.801      ;
+; 0.185 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.026     ; 0.796      ;
+; 0.270 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.026     ; 0.711      ;
+; 0.279 ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.022     ; 0.706      ;
+; 0.339 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.022     ; 0.646      ;
+; 0.342 ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.026     ; 0.639      ;
+; 0.346 ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 1.000        ; -0.022     ; 0.639      ;
+; 0.506 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 0.917      ; 1.013      ;
+; 0.592 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 0.917      ; 0.927      ;
+; 0.596 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 0.917      ; 0.923      ;
+; 0.605 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.500        ; 0.917      ; 0.914      ;
+; 0.961 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 0.917      ; 1.058      ;
+; 1.004 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 0.917      ; 1.015      ;
+; 1.005 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 0.917      ; 1.014      ;
+; 1.023 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 1.000        ; 0.917      ; 0.996      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'one_hertz_clock:inst9|inst102'                                                                                                        ;
++-------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; 0.192 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.022     ; 0.793      ;
+; 0.199 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.025     ; 0.783      ;
+; 0.199 ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.025     ; 0.783      ;
+; 0.204 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.025     ; 0.778      ;
+; 0.356 ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.022     ; 0.629      ;
+; 0.361 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.022     ; 0.624      ;
+; 0.363 ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.025     ; 0.619      ;
+; 0.382 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 1.404      ; 1.634      ;
+; 0.389 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 1.404      ; 1.627      ;
+; 0.431 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 1.404      ; 1.585      ;
+; 0.449 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.500        ; 1.404      ; 1.567      ;
+; 0.946 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 1.404      ; 1.570      ;
+; 1.043 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 1.404      ; 1.473      ;
+; 1.050 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 1.404      ; 1.466      ;
+; 1.073 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 1.000        ; 1.404      ; 1.443      ;
++-------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'ten_counter:inst6|inst'                                                                                                 ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.408 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.543      ;
+; 0.414 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.537      ;
+; 0.425 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.526      ;
+; 0.436 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.515      ;
+; 0.560 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.391      ;
+; 0.563 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.388      ;
+; 0.563 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.388      ;
+; 0.592 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.359      ;
+; 0.592 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.359      ;
+; 0.592 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.359      ;
+; 0.601 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 1.000        ; -0.036     ; 0.350      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'Split'                                                                                                ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+; -0.502 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 2.024      ; 1.657      ;
+; -0.482 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.891      ; 1.534      ;
+; -0.376 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.778      ; 1.527      ;
+; -0.344 ; ten_counter:inst2|inst1 ; inst14  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.170      ; 0.846      ;
+; -0.309 ; ten_counter:inst6|inst2 ; inst19  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.110      ; 0.821      ;
+; -0.306 ; ten_counter:inst6|inst1 ; inst15  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.110      ; 0.824      ;
+; -0.248 ; ten_counter:inst2|inst3 ; inst22  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.169      ; 0.941      ;
+; -0.238 ; ten_counter:inst6|inst3 ; inst23  ; ten_counter:inst2|inst        ; Split       ; 0.000        ; 1.105      ; 0.887      ;
+; -0.213 ; ten_counter:inst2|inst2 ; inst18  ; ten_counter:inst1|inst        ; Split       ; 0.000        ; 1.245      ; 1.052      ;
+; -0.175 ; ten_counter:inst6|inst  ; inst11  ; ten_counter:inst6|inst        ; Split       ; -0.500       ; 2.024      ; 1.484      ;
+; -0.136 ; ten_counter:inst2|inst  ; inst10  ; ten_counter:inst2|inst        ; Split       ; -0.500       ; 1.891      ; 1.380      ;
+; -0.112 ; ten_counter:inst8|inst2 ; inst20  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.370      ; 0.288      ;
+; -0.107 ; ten_counter:inst8|inst1 ; inst16  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.368      ; 0.291      ;
+; -0.105 ; ten_counter:inst8|inst  ; inst12  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.369      ; 0.294      ;
+; -0.052 ; ten_counter:inst1|inst  ; inst7   ; ten_counter:inst1|inst        ; Split       ; -0.500       ; 1.778      ; 1.351      ;
+; 0.027  ; ten_counter:inst8|inst3 ; inst24  ; ten_counter:inst6|inst        ; Split       ; 0.000        ; 0.289      ; 0.346      ;
+; 0.140  ; ten_counter:inst1|inst3 ; inst21  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.636      ; 0.296      ;
+; 0.195  ; ten_counter:inst1|inst2 ; inst17  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.561      ; 0.276      ;
+; 0.198  ; ten_counter:inst1|inst1 ; inst13  ; one_hertz_clock:inst9|inst102 ; Split       ; -0.500       ; 0.558      ; 0.276      ;
++--------+-------------------------+---------+-------------------------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'one_hertz_clock:inst9|inst102'                                                                                                          ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                  ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+; -0.309 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 1.472      ; 1.352      ;
+; -0.262 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 1.472      ; 1.399      ;
+; -0.258 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 1.472      ; 1.403      ;
+; -0.190 ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 0.000        ; 1.472      ; 1.471      ;
+; 0.315  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 1.472      ; 1.476      ;
+; 0.333  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 1.472      ; 1.494      ;
+; 0.374  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 1.472      ; 1.535      ;
+; 0.378  ; ten_counter:inst1|inst  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; -0.500       ; 1.472      ; 1.539      ;
+; 0.444  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.022      ; 0.550      ;
+; 0.445  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.022      ; 0.551      ;
+; 0.463  ; ten_counter:inst1|inst3 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.025      ; 0.572      ;
+; 0.540  ; ten_counter:inst1|inst2 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.025      ; 0.649      ;
+; 0.546  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst3 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.025      ; 0.655      ;
+; 0.566  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst2 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.025      ; 0.675      ;
+; 0.580  ; ten_counter:inst1|inst1 ; ten_counter:inst1|inst1 ; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 0.000        ; 0.022      ; 0.686      ;
++--------+-------------------------+-------------------------+-------------------------------+-------------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'DE0CLOCK'                                                                                                                                 ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                         ; To Node                           ; Launch Clock                  ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+; -0.283 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.136      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.272 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.125      ; 1.062      ;
+; -0.266 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.153      ;
+; -0.266 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.153      ;
+; -0.266 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.153      ;
+; -0.266 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.153      ;
+; -0.266 ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; 0.000        ; 1.210      ; 1.153      ;
+; 0.201  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.208  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst3799999 ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.218  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.329      ;
+; 0.222  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.333      ;
+; 0.223  ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.334      ;
+; 0.229  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.340      ;
+; 0.319  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.430      ;
+; 0.320  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.431      ;
+; 0.320  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.431      ;
+; 0.320  ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.431      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst48      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst58      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst82      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst92      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst97      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst107     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.330  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.125      ; 1.164      ;
+; 0.341  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.260      ;
+; 0.341  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.260      ;
+; 0.341  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.260      ;
+; 0.341  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.260      ;
+; 0.341  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.260      ;
+; 0.351  ; one_hertz_clock:inst9|inst102     ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst102 ; DE0CLOCK    ; -0.500       ; 1.210      ; 1.270      ;
+; 0.360  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.471      ;
+; 0.384  ; one_hertz_clock:inst9|inst63      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.495      ;
+; 0.389  ; one_hertz_clock:inst9|inst389     ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.500      ;
+; 0.466  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.577      ;
+; 0.470  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.510      ;
+; 0.473  ; one_hertz_clock:inst9|inst72      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.513      ;
+; 0.500  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.611      ;
+; 0.531  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.571      ;
+; 0.576  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.687      ;
+; 0.586  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.692      ;
+; 0.591  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst87      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.702      ;
+; 0.591  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst97      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.702      ;
+; 0.592  ; one_hertz_clock:inst9|inst77      ; one_hertz_clock:inst9|inst92      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.703      ;
+; 0.594  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.634      ;
+; 0.607  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst38      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.713      ;
+; 0.626  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst40      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.737      ;
+; 0.634  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.674      ;
+; 0.636  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst50      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.676      ;
+; 0.639  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.679      ;
+; 0.640  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.680      ;
+; 0.646  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst107     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.757      ;
+; 0.688  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.022      ; 0.794      ;
+; 0.688  ; one_hertz_clock:inst9|inst38      ; one_hertz_clock:inst9|inst48      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.728      ;
+; 0.692  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.803      ;
+; 0.701  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst459     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.812      ;
+; 0.702  ; one_hertz_clock:inst9|inst87      ; one_hertz_clock:inst9|inst102     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.122      ; 0.908      ;
+; 0.702  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.742      ;
+; 0.703  ; one_hertz_clock:inst9|inst40      ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.743      ;
+; 0.714  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst77      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.825      ;
+; 0.714  ; one_hertz_clock:inst9|inst67      ; one_hertz_clock:inst9|inst82      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.825      ;
+; 0.723  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.834      ;
+; 0.723  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.834      ;
+; 0.723  ; one_hertz_clock:inst9|inst50      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.834      ;
+; 0.739  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst58      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.850      ;
+; 0.739  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst63      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.850      ;
+; 0.739  ; one_hertz_clock:inst9|inst43      ; one_hertz_clock:inst9|inst67      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; 0.027      ; 0.850      ;
+; 0.742  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.782      ;
+; 0.743  ; one_hertz_clock:inst9|inst3799999 ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.783      ;
+; 0.744  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst43      ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.784      ;
+; 0.745  ; one_hertz_clock:inst9|inst459     ; one_hertz_clock:inst9|inst389     ; DE0CLOCK                      ; DE0CLOCK    ; 0.000        ; -0.044     ; 0.785      ;
++--------+-----------------------------------+-----------------------------------+-------------------------------+-------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'ten_counter:inst2|inst'                                                                                                   ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.229 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 0.965      ; 0.935      ;
+; -0.229 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 0.965      ; 0.935      ;
+; -0.228 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 0.965      ; 0.936      ;
+; -0.144 ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; 0.000        ; 0.965      ; 1.020      ;
+; 0.191  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 0.965      ; 0.855      ;
+; 0.194  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 0.965      ; 0.858      ;
+; 0.219  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 0.965      ; 0.883      ;
+; 0.314  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst  ; ten_counter:inst6|inst ; ten_counter:inst2|inst ; -0.500       ; 0.965      ; 0.978      ;
+; 0.452  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.026      ; 0.562      ;
+; 0.456  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.022      ; 0.562      ;
+; 0.464  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.022      ; 0.570      ;
+; 0.513  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst2 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.022      ; 0.619      ;
+; 0.513  ; ten_counter:inst6|inst2 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.026      ; 0.623      ;
+; 0.557  ; ten_counter:inst6|inst1 ; ten_counter:inst6|inst3 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.026      ; 0.667      ;
+; 0.578  ; ten_counter:inst6|inst3 ; ten_counter:inst6|inst1 ; ten_counter:inst2|inst ; ten_counter:inst2|inst ; 0.000        ; 0.026      ; 0.688      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'ten_counter:inst1|inst'                                                                                                   ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; -0.143 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 0.759      ; 0.805      ;
+; -0.128 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 0.759      ; 0.820      ;
+; -0.091 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 0.759      ; 0.857      ;
+; -0.076 ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; 0.000        ; 0.759      ; 0.872      ;
+; 0.306  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 0.759      ; 0.754      ;
+; 0.311  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 0.759      ; 0.759      ;
+; 0.360  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 0.759      ; 0.808      ;
+; 0.415  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst  ; ten_counter:inst2|inst ; ten_counter:inst1|inst ; -0.500       ; 0.759      ; 0.863      ;
+; 0.449  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.022      ; 0.555      ;
+; 0.455  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.024      ; 0.563      ;
+; 0.456  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.022      ; 0.562      ;
+; 0.549  ; ten_counter:inst2|inst2 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.024      ; 0.657      ;
+; 0.580  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst3 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.022      ; 0.686      ;
+; 0.581  ; ten_counter:inst2|inst1 ; ten_counter:inst2|inst2 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.024      ; 0.689      ;
+; 0.586  ; ten_counter:inst2|inst3 ; ten_counter:inst2|inst1 ; ten_counter:inst1|inst ; ten_counter:inst1|inst ; 0.000        ; 0.024      ; 0.694      ;
++--------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'Reset'                                                                ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.171 ; Reset     ; inst28  ; Reset        ; Reset       ; 0.000        ; 1.616      ; 1.787      ;
+; 1.087 ; Reset     ; inst28  ; Reset        ; Reset       ; -0.500       ; 1.616      ; 2.203      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'ten_counter:inst6|inst'                                                                                                  ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock           ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+; 0.187 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.307      ;
+; 0.194 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst  ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.314      ;
+; 0.205 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.325      ;
+; 0.205 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.325      ;
+; 0.206 ; ten_counter:inst8|inst  ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.326      ;
+; 0.298 ; ten_counter:inst8|inst2 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.418      ;
+; 0.303 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst2 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.423      ;
+; 0.303 ; ten_counter:inst8|inst1 ; ten_counter:inst8|inst3 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.423      ;
+; 0.311 ; ten_counter:inst8|inst3 ; ten_counter:inst8|inst1 ; ten_counter:inst6|inst ; ten_counter:inst6|inst ; 0.000        ; 0.036      ; 0.431      ;
++-------+-------------------------+-------------------------+------------------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'ten_counter:inst1|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -0.972 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -0.898     ; 0.561      ;
+; -0.972 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -0.898     ; 0.561      ;
+; -0.972 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -0.898     ; 0.561      ;
+; -0.972 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; 0.500        ; -0.898     ; 0.561      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'ten_counter:inst2|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -0.847 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -0.699     ; 0.635      ;
+; -0.847 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -0.699     ; 0.635      ;
+; -0.847 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -0.699     ; 0.635      ;
+; -0.847 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; 0.500        ; -0.699     ; 0.635      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'ten_counter:inst6|inst'                                                                       ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; -0.097 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; 0.500        ; 0.045      ; 0.619      ;
+; -0.097 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; 0.045      ; 0.619      ;
+; -0.097 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; 0.045      ; 0.619      ;
+; -0.097 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; 0.500        ; 0.045      ; 0.619      ;
++--------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'one_hertz_clock:inst9|inst102'                                                                      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; 0.214 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.212     ; 0.561      ;
+; 0.214 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.212     ; 0.561      ;
+; 0.214 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.212     ; 0.561      ;
+; 0.214 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 1.000        ; -0.212     ; 0.561      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'one_hertz_clock:inst9|inst102'                                                                       ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+; 0.489 ; inst28    ; ten_counter:inst1|inst  ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.091     ; 0.502      ;
+; 0.489 ; inst28    ; ten_counter:inst1|inst1 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.091     ; 0.502      ;
+; 0.489 ; inst28    ; ten_counter:inst1|inst2 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.091     ; 0.502      ;
+; 0.489 ; inst28    ; ten_counter:inst1|inst3 ; Reset        ; one_hertz_clock:inst9|inst102 ; 0.000        ; -0.091     ; 0.502      ;
++-------+-----------+-------------------------+--------------+-------------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'ten_counter:inst6|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 0.759 ; inst28    ; ten_counter:inst8|inst  ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.188      ; 0.561      ;
+; 0.759 ; inst28    ; ten_counter:inst8|inst1 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.188      ; 0.561      ;
+; 0.759 ; inst28    ; ten_counter:inst8|inst2 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.188      ; 0.561      ;
+; 0.759 ; inst28    ; ten_counter:inst8|inst3 ; Reset        ; ten_counter:inst6|inst ; -0.500       ; 0.188      ; 0.561      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'ten_counter:inst2|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 1.560 ; inst28    ; ten_counter:inst6|inst  ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -0.598     ; 0.566      ;
+; 1.560 ; inst28    ; ten_counter:inst6|inst3 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -0.598     ; 0.566      ;
+; 1.560 ; inst28    ; ten_counter:inst6|inst1 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -0.598     ; 0.566      ;
+; 1.560 ; inst28    ; ten_counter:inst6|inst2 ; Reset        ; ten_counter:inst2|inst ; -0.500       ; -0.598     ; 0.566      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'ten_counter:inst1|inst'                                                                       ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; Slack ; From Node ; To Node                 ; Launch Clock ; Latch Clock            ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+; 1.702 ; inst28    ; ten_counter:inst2|inst  ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -0.804     ; 0.502      ;
+; 1.702 ; inst28    ; ten_counter:inst2|inst2 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -0.804     ; 0.502      ;
+; 1.702 ; inst28    ; ten_counter:inst2|inst3 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -0.804     ; 0.502      ;
+; 1.702 ; inst28    ; ten_counter:inst2|inst1 ; Reset        ; ten_counter:inst1|inst ; -0.500       ; -0.804     ; 0.502      ;
++-------+-----------+-------------------------+--------------+------------------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'DE0CLOCK'                                                                  ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                            ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; DE0CLOCK ; Rise       ; DE0CLOCK                          ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; -0.022 ; 0.162        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; -0.019 ; 0.165        ; 0.184          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.156  ; 0.156        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.159  ; 0.159        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; DE0CLOCK ; Rise       ; DE0CLOCK~input|i                  ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst102     ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst3799999 ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst38      ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst40      ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst459     ;
+; 0.619  ; 0.835        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst72      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst107     ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst389     ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst43      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst48      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst50      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst58      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst63      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst67      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst77      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst82      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst87      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst92      ;
+; 0.622  ; 0.838        ; 0.216          ; High Pulse Width ; DE0CLOCK ; Rise       ; one_hertz_clock:inst9|inst97      ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst102|clk                 ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst3799999|clk             ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst38|clk                  ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst40|clk                  ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst459|clk                 ;
+; 0.839  ; 0.839        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst72|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst107|clk                 ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst389|clk                 ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst43|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst48|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst50|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst58|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst63|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst67|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst77|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst82|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst87|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst92|clk                  ;
+; 0.842  ; 0.842        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; inst9|inst97|clk                  ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; DE0CLOCK ; Rise       ; DE0CLOCK~input|o                  ;
++--------+--------------+----------------+------------------+----------+------------+-----------------------------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'Split'                                              ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Split ; Rise       ; Split         ;
+; -0.011 ; -0.011       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst15        ;
+; -0.011 ; -0.011       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst19        ;
+; -0.008 ; -0.008       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst11        ;
+; -0.008 ; -0.008       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst15|datac  ;
+; -0.008 ; -0.008       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst19|datac  ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst21        ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst23        ;
+; -0.005 ; -0.005       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst11|datac  ;
+; -0.005 ; -0.005       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst20        ;
+; -0.004 ; -0.004       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst12        ;
+; -0.004 ; -0.004       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst21|datac  ;
+; -0.004 ; -0.004       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst23|datac  ;
+; -0.003 ; -0.003       ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst16        ;
+; -0.003 ; -0.003       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst17|datad  ;
+; -0.002 ; -0.002       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst13|datad  ;
+; -0.002 ; -0.002       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst18|datad  ;
+; -0.002 ; -0.002       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst20|datac  ;
+; -0.002 ; -0.002       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst24|datad  ;
+; -0.001 ; -0.001       ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst12|datac  ;
+; 0.000  ; 0.000        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst16|datac  ;
+; 0.002  ; 0.002        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst17        ;
+; 0.003  ; 0.003        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst13        ;
+; 0.003  ; 0.003        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst18        ;
+; 0.003  ; 0.003        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst24        ;
+; 0.004  ; 0.004        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst10        ;
+; 0.004  ; 0.004        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst14        ;
+; 0.005  ; 0.005        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst22        ;
+; 0.007  ; 0.007        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst10|datac  ;
+; 0.007  ; 0.007        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst14|datac  ;
+; 0.008  ; 0.008        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst22|datac  ;
+; 0.025  ; 0.025        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; inst7|datad   ;
+; 0.030  ; 0.030        ; 0.000          ; High Pulse Width ; Split ; Fall       ; inst7         ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|o ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|i ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Split ; Rise       ; Split~input|i ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; Split ; Rise       ; Split~input|o ;
+; 0.969  ; 0.969        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst7         ;
+; 0.973  ; 0.973        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst7|datad   ;
+; 0.990  ; 0.990        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst10|datac  ;
+; 0.990  ; 0.990        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst14|datac  ;
+; 0.990  ; 0.990        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst22|datac  ;
+; 0.993  ; 0.993        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst10        ;
+; 0.993  ; 0.993        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst14        ;
+; 0.993  ; 0.993        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst22        ;
+; 0.995  ; 0.995        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst13        ;
+; 0.995  ; 0.995        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst17        ;
+; 0.995  ; 0.995        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst18        ;
+; 0.995  ; 0.995        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst24        ;
+; 0.998  ; 0.998        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst12|datac  ;
+; 0.998  ; 0.998        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst16|datac  ;
+; 0.998  ; 0.998        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst20|datac  ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst13|datad  ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst17|datad  ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst18|datad  ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst24|datad  ;
+; 1.001  ; 1.001        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst12        ;
+; 1.001  ; 1.001        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst16        ;
+; 1.001  ; 1.001        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst20        ;
+; 1.001  ; 1.001        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst23|datac  ;
+; 1.002  ; 1.002        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst11|datac  ;
+; 1.002  ; 1.002        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst21|datac  ;
+; 1.004  ; 1.004        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst23        ;
+; 1.005  ; 1.005        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst11        ;
+; 1.005  ; 1.005        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst15|datac  ;
+; 1.005  ; 1.005        ; 0.000          ; High Pulse Width ; Split ; Rise       ; inst19|datac  ;
+; 1.005  ; 1.005        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst21        ;
+; 1.008  ; 1.008        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst15        ;
+; 1.008  ; 1.008        ; 0.000          ; Low Pulse Width  ; Split ; Fall       ; inst19        ;
++--------+--------------+----------------+------------------+-------+------------+---------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'Reset'                                               ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target         ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; Reset ; Rise       ; Reset          ;
+; -0.007 ; -0.007       ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28|datac   ;
+; -0.001 ; -0.001       ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst28         ;
+; 0.020  ; 0.020        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|datad   ;
+; 0.025  ; 0.025        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; inst29|combout ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|o  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|i  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; Reset ; Rise       ; Reset~input|i  ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; Reset~input|o  ;
+; 0.974  ; 0.974        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|combout ;
+; 0.978  ; 0.978        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst29|datad   ;
+; 0.998  ; 0.998        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28         ;
+; 1.004  ; 1.004        ; 0.000          ; High Pulse Width ; Reset ; Rise       ; inst28|datac   ;
++--------+--------------+----------------+------------------+-------+------------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'one_hertz_clock:inst9|inst102'                                                        ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                         ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.123  ; 0.307        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.123  ; 0.307        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.123  ; 0.307        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.123  ; 0.307        ; 0.184          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
+; 0.434  ; 0.434        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.466  ; 0.682        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst  ;
+; 0.466  ; 0.682        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst1 ;
+; 0.466  ; 0.682        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst2 ;
+; 0.466  ; 0.682        ; 0.216          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; ten_counter:inst1|inst3 ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst102|q         ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|dataa      ;
+; 0.562  ; 0.562        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst9|inst30|combout    ;
+; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst1|clk         ;
+; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst2|clk         ;
+; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst3|clk         ;
+; 0.688  ; 0.688        ; 0.000          ; High Pulse Width ; one_hertz_clock:inst9|inst102 ; Rise       ; inst1|inst|clk          ;
++--------+--------------+----------------+------------------+-------------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst1|inst'                                                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.245  ; 0.461        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.245  ; 0.461        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.245  ; 0.461        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.245  ; 0.461        ; 0.216          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.355  ; 0.539        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst  ;
+; 0.355  ; 0.539        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst1 ;
+; 0.355  ; 0.539        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst2 ;
+; 0.355  ; 0.539        ; 0.184          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; ten_counter:inst2|inst3 ;
+; 0.450  ; 0.450        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
+; 0.454  ; 0.454        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.465  ; 0.465        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Rise       ; inst1|inst|q            ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst1|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst2|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst3|clk         ;
+; 0.533  ; 0.533        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst2|inst|clk          ;
+; 0.544  ; 0.544        ; 0.000          ; Low Pulse Width  ; ten_counter:inst1|inst ; Fall       ; inst1|inst23|combout    ;
+; 0.548  ; 0.548        ; 0.000          ; High Pulse Width ; ten_counter:inst1|inst ; Rise       ; inst1|inst23|datac      ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst2|inst'                                                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                  ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.247  ; 0.463        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.247  ; 0.463        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.247  ; 0.463        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.247  ; 0.463        ; 0.216          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst  ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst1 ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst2 ;
+; 0.353  ; 0.537        ; 0.184          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; ten_counter:inst6|inst3 ;
+; 0.435  ; 0.435        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
+; 0.437  ; 0.437        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
+; 0.467  ; 0.467        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.467  ; 0.467        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.467  ; 0.467        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.467  ; 0.467        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Rise       ; inst2|inst|q            ;
+; 0.531  ; 0.531        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst1|clk         ;
+; 0.531  ; 0.531        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst2|clk         ;
+; 0.531  ; 0.531        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst3|clk         ;
+; 0.531  ; 0.531        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst6|inst|clk          ;
+; 0.561  ; 0.561        ; 0.000          ; High Pulse Width ; ten_counter:inst2|inst ; Rise       ; inst2|inst23|dataa      ;
+; 0.563  ; 0.563        ; 0.000          ; Low Pulse Width  ; ten_counter:inst2|inst ; Fall       ; inst2|inst23|combout    ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'ten_counter:inst6|inst'                                                              ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                  ; Clock Edge ; Target                        ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.252  ; 0.436        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.252  ; 0.436        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.252  ; 0.436        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.252  ; 0.436        ; 0.184          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.338  ; 0.554        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst        ;
+; 0.338  ; 0.554        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst1       ;
+; 0.338  ; 0.554        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst2       ;
+; 0.338  ; 0.554        ; 0.216          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; ten_counter:inst8|inst3       ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.432  ; 0.432        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
+; 0.440  ; 0.440        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.440  ; 0.440        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
+; 0.492  ; 0.492        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst23|datac            ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; ten_counter:inst6|inst ; Rise       ; inst6|inst|q                  ;
+; 0.504  ; 0.504        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23|combout          ;
+; 0.553  ; 0.553        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|inclk[0] ;
+; 0.553  ; 0.553        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst6|inst23~clkctrl|outclk   ;
+; 0.560  ; 0.560        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst1|clk               ;
+; 0.560  ; 0.560        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst2|clk               ;
+; 0.560  ; 0.560        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst3|clk               ;
+; 0.560  ; 0.560        ; 0.000          ; High Pulse Width ; ten_counter:inst6|inst ; Fall       ; inst8|inst|clk                ;
++--------+--------------+----------------+------------------+------------------------+------------+-------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Reset     ; Reset      ; 0.778 ; 1.196 ; Rise       ; Reset           ;
+; Start     ; Reset      ; 2.001 ; 2.699 ; Rise       ; Reset           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Reset     ; Reset      ; -0.171 ; -0.587 ; Rise       ; Reset           ;
+; Start     ; Reset      ; -1.342 ; -2.031 ; Rise       ; Reset           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 4.689 ; 4.702 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 4.689 ; 4.687 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 4.645 ; 4.702 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 4.470 ; 4.350 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 4.416 ; 4.439 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 4.380 ; 4.446 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 4.471 ; 4.351 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 4.435 ; 4.418 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 4.519 ; 4.423 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 4.347 ; 4.363 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 4.170 ; 4.212 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 4.239 ; 4.164 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 4.243 ; 4.269 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 4.061 ; 4.116 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 4.519 ; 4.423 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 4.433 ; 4.378 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 4.360 ; 4.286 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 4.306 ; 4.262 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 4.210 ; 4.229 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 4.214 ; 4.169 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 4.207 ; 4.174 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 4.360 ; 4.257 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 4.236 ; 4.193 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 4.336 ; 4.286 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 4.352 ; 4.316 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 4.146 ; 4.115 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 4.298 ; 4.291 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 4.144 ; 4.079 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 4.170 ; 4.144 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 4.219 ; 4.232 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 4.352 ; 4.316 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 4.241 ; 4.212 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 3.538 ; 3.538 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 3.812 ; 3.775 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 3.873 ; 3.793 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 3.581 ; 3.543 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 3.551 ; 3.538 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 3.594 ; 3.615 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 3.558 ; 3.574 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 3.538 ; 3.555 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 3.582 ; 3.550 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 3.683 ; 3.661 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 3.786 ; 3.758 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 3.583 ; 3.550 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 3.582 ; 3.572 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 3.698 ; 3.667 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 3.831 ; 3.832 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 3.734 ; 3.732 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 3.827 ; 3.809 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 3.927 ; 3.899 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 3.870 ; 3.851 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 3.861 ; 3.813 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 3.827 ; 3.809 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 3.988 ; 3.987 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 3.862 ; 3.867 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 3.952 ; 3.949 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 3.885 ; 3.837 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 3.885 ; 3.837 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 4.087 ; 4.053 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 3.909 ; 3.856 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 3.905 ; 3.853 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 4.085 ; 4.008 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 4.080 ; 4.020 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 3.978 ; 3.925 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                           ;
++--------------------------------+---------+---------+----------+---------+---------------------+
+; Clock                          ; Setup   ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------+---------+---------+----------+---------+---------------------+
+; Worst-case Slack               ; -2.370  ; -0.545  ; -2.180   ; 0.489   ; -3.000              ;
+;  DE0CLOCK                      ; -2.370  ; -0.361  ; N/A      ; N/A     ; -3.000              ;
+;  Reset                         ; -0.923  ; 0.104   ; N/A      ; N/A     ; -3.000              ;
+;  Split                         ; -1.031  ; -0.502  ; N/A      ; N/A     ; -3.000              ;
+;  one_hertz_clock:inst9|inst102 ; -0.481  ; -0.545  ; -0.465   ; 0.489   ; -1.000              ;
+;  ten_counter:inst1|inst        ; -0.518  ; -0.245  ; -2.180   ; 1.702   ; -1.000              ;
+;  ten_counter:inst2|inst        ; -0.505  ; -0.401  ; -1.948   ; 1.560   ; -1.000              ;
+;  ten_counter:inst6|inst        ; -0.054  ; 0.187   ; -0.688   ; 0.759   ; -1.000              ;
+; Design-wide TNS                ; -57.857 ; -11.446 ; -21.088  ; 0.0     ; -44.505             ;
+;  DE0CLOCK                      ; -44.235 ; -6.640  ; N/A      ; N/A     ; -22.400             ;
+;  Reset                         ; -0.923  ; 0.000   ; N/A      ; N/A     ; -3.008              ;
+;  Split                         ; -8.373  ; -3.342  ; N/A      ; N/A     ; -3.097              ;
+;  one_hertz_clock:inst9|inst102 ; -1.435  ; -1.713  ; -1.860   ; 0.000   ; -4.000              ;
+;  ten_counter:inst1|inst        ; -1.429  ; -0.692  ; -8.720   ; 0.000   ; -4.000              ;
+;  ten_counter:inst2|inst        ; -1.341  ; -1.418  ; -7.792   ; 0.000   ; -4.000              ;
+;  ten_counter:inst6|inst        ; -0.121  ; 0.000   ; -2.752   ; 0.000   ; -4.000              ;
++--------------------------------+---------+---------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Reset     ; Reset      ; 1.254 ; 1.423 ; Rise       ; Reset           ;
+; Start     ; Reset      ; 3.420 ; 3.904 ; Rise       ; Reset           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Reset     ; Reset      ; -0.104 ; -0.290 ; Rise       ; Reset           ;
+; Start     ; Reset      ; -1.342 ; -2.031 ; Rise       ; Reset           ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 7.291 ; 7.387 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 7.291 ; 7.376 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 7.286 ; 7.387 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 6.893 ; 6.900 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 6.855 ; 6.920 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 6.874 ; 6.936 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 6.900 ; 6.909 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 6.841 ; 6.887 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 7.009 ; 7.059 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 6.743 ; 6.823 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 6.472 ; 6.566 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 6.520 ; 6.576 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 6.565 ; 6.648 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 6.291 ; 6.381 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 7.009 ; 7.059 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 6.809 ; 6.858 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 6.722 ; 6.772 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 6.659 ; 6.733 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 6.474 ; 6.590 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 6.498 ; 6.556 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 6.481 ; 6.543 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 6.722 ; 6.716 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 6.502 ; 6.576 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 6.717 ; 6.772 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 6.698 ; 6.781 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 6.338 ; 6.396 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 6.613 ; 6.747 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 6.327 ; 6.360 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 6.369 ; 6.431 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 6.483 ; 6.616 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 6.698 ; 6.781 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 6.542 ; 6.606 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; DIG0[*]   ; Split      ; 3.538 ; 3.538 ; Fall       ; Split           ;
+;  DIG0[0]  ; Split      ; 3.812 ; 3.775 ; Fall       ; Split           ;
+;  DIG0[1]  ; Split      ; 3.873 ; 3.793 ; Fall       ; Split           ;
+;  DIG0[2]  ; Split      ; 3.581 ; 3.543 ; Fall       ; Split           ;
+;  DIG0[3]  ; Split      ; 3.551 ; 3.538 ; Fall       ; Split           ;
+;  DIG0[4]  ; Split      ; 3.594 ; 3.615 ; Fall       ; Split           ;
+;  DIG0[5]  ; Split      ; 3.558 ; 3.574 ; Fall       ; Split           ;
+;  DIG0[6]  ; Split      ; 3.538 ; 3.555 ; Fall       ; Split           ;
+; DIG1[*]   ; Split      ; 3.582 ; 3.550 ; Fall       ; Split           ;
+;  DIG1[0]  ; Split      ; 3.683 ; 3.661 ; Fall       ; Split           ;
+;  DIG1[1]  ; Split      ; 3.786 ; 3.758 ; Fall       ; Split           ;
+;  DIG1[2]  ; Split      ; 3.583 ; 3.550 ; Fall       ; Split           ;
+;  DIG1[3]  ; Split      ; 3.582 ; 3.572 ; Fall       ; Split           ;
+;  DIG1[4]  ; Split      ; 3.698 ; 3.667 ; Fall       ; Split           ;
+;  DIG1[5]  ; Split      ; 3.831 ; 3.832 ; Fall       ; Split           ;
+;  DIG1[6]  ; Split      ; 3.734 ; 3.732 ; Fall       ; Split           ;
+; DIG2[*]   ; Split      ; 3.827 ; 3.809 ; Fall       ; Split           ;
+;  DIG2[0]  ; Split      ; 3.927 ; 3.899 ; Fall       ; Split           ;
+;  DIG2[1]  ; Split      ; 3.870 ; 3.851 ; Fall       ; Split           ;
+;  DIG2[2]  ; Split      ; 3.861 ; 3.813 ; Fall       ; Split           ;
+;  DIG2[3]  ; Split      ; 3.827 ; 3.809 ; Fall       ; Split           ;
+;  DIG2[4]  ; Split      ; 3.988 ; 3.987 ; Fall       ; Split           ;
+;  DIG2[5]  ; Split      ; 3.862 ; 3.867 ; Fall       ; Split           ;
+;  DIG2[6]  ; Split      ; 3.952 ; 3.949 ; Fall       ; Split           ;
+; DIG3[*]   ; Split      ; 3.885 ; 3.837 ; Fall       ; Split           ;
+;  DIG3[0]  ; Split      ; 3.885 ; 3.837 ; Fall       ; Split           ;
+;  DIG3[1]  ; Split      ; 4.087 ; 4.053 ; Fall       ; Split           ;
+;  DIG3[2]  ; Split      ; 3.909 ; 3.856 ; Fall       ; Split           ;
+;  DIG3[3]  ; Split      ; 3.905 ; 3.853 ; Fall       ; Split           ;
+;  DIG3[4]  ; Split      ; 4.085 ; 4.008 ; Fall       ; Split           ;
+;  DIG3[5]  ; Split      ; 4.080 ; 4.020 ; Fall       ; Split           ;
+;  DIG3[6]  ; Split      ; 3.978 ; 3.925 ; Fall       ; Split           ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Point         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG0[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG1[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG2[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DIG3[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; Split                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Start                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Reset                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; DE0CLOCK                ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Point         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Point         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG0[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG1[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG2[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; DIG3[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                           ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+; From Clock                    ; To Clock                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+; DE0CLOCK                      ; DE0CLOCK                      ; 530      ; 0        ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; DE0CLOCK                      ; 21       ; 21       ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 7        ; 0        ; 0        ; 0        ;
+; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 4        ; 4        ; 0        ; 0        ;
+; Reset                         ; Reset                         ; 1        ; 1        ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; Split                         ; 0        ; 0        ; 3        ; 0        ;
+; ten_counter:inst1|inst        ; Split                         ; 0        ; 0        ; 1        ; 4        ;
+; ten_counter:inst2|inst        ; Split                         ; 0        ; 0        ; 1        ; 4        ;
+; ten_counter:inst6|inst        ; Split                         ; 0        ; 0        ; 1        ; 5        ;
+; ten_counter:inst1|inst        ; ten_counter:inst1|inst        ; 0        ; 0        ; 0        ; 7        ;
+; ten_counter:inst2|inst        ; ten_counter:inst1|inst        ; 0        ; 0        ; 4        ; 4        ;
+; ten_counter:inst2|inst        ; ten_counter:inst2|inst        ; 0        ; 0        ; 0        ; 7        ;
+; ten_counter:inst6|inst        ; ten_counter:inst2|inst        ; 0        ; 0        ; 4        ; 4        ;
+; ten_counter:inst6|inst        ; ten_counter:inst6|inst        ; 0        ; 0        ; 0        ; 11       ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                            ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+; From Clock                    ; To Clock                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+; DE0CLOCK                      ; DE0CLOCK                      ; 530      ; 0        ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; DE0CLOCK                      ; 21       ; 21       ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; one_hertz_clock:inst9|inst102 ; 7        ; 0        ; 0        ; 0        ;
+; ten_counter:inst1|inst        ; one_hertz_clock:inst9|inst102 ; 4        ; 4        ; 0        ; 0        ;
+; Reset                         ; Reset                         ; 1        ; 1        ; 0        ; 0        ;
+; one_hertz_clock:inst9|inst102 ; Split                         ; 0        ; 0        ; 3        ; 0        ;
+; ten_counter:inst1|inst        ; Split                         ; 0        ; 0        ; 1        ; 4        ;
+; ten_counter:inst2|inst        ; Split                         ; 0        ; 0        ; 1        ; 4        ;
+; ten_counter:inst6|inst        ; Split                         ; 0        ; 0        ; 1        ; 5        ;
+; ten_counter:inst1|inst        ; ten_counter:inst1|inst        ; 0        ; 0        ; 0        ; 7        ;
+; ten_counter:inst2|inst        ; ten_counter:inst1|inst        ; 0        ; 0        ; 4        ; 4        ;
+; ten_counter:inst2|inst        ; ten_counter:inst2|inst        ; 0        ; 0        ; 0        ; 7        ;
+; ten_counter:inst6|inst        ; ten_counter:inst2|inst        ; 0        ; 0        ; 4        ; 4        ;
+; ten_counter:inst6|inst        ; ten_counter:inst6|inst        ; 0        ; 0        ; 0        ; 11       ;
++-------------------------------+-------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++----------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                     ;
++------------+-------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-------------------------------+----------+----------+----------+----------+
+; Reset      ; one_hertz_clock:inst9|inst102 ; 4        ; 0        ; 0        ; 0        ;
+; Reset      ; ten_counter:inst1|inst        ; 0        ; 0        ; 4        ; 0        ;
+; Reset      ; ten_counter:inst2|inst        ; 0        ; 0        ; 4        ; 0        ;
+; Reset      ; ten_counter:inst6|inst        ; 0        ; 0        ; 4        ; 0        ;
++------------+-------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++----------------------------------------------------------------------------------------+
+; Removal Transfers                                                                      ;
++------------+-------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                      ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-------------------------------+----------+----------+----------+----------+
+; Reset      ; one_hertz_clock:inst9|inst102 ; 4        ; 0        ; 0        ; 0        ;
+; Reset      ; ten_counter:inst1|inst        ; 0        ; 0        ; 4        ; 0        ;
+; Reset      ; ten_counter:inst2|inst        ; 0        ; 0        ; 4        ; 0        ;
+; Reset      ; ten_counter:inst6|inst        ; 0        ; 0        ; 4        ; 0        ;
++------------+-------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 1     ; 1    ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 104   ; 104  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:37:55 2016
+Info: Command: quartus_sta stopwatch -c stopwatch
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 17 combinational loops as latches.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'stopwatch.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name DE0CLOCK DE0CLOCK
+    Info (332105): create_clock -period 1.000 -name Reset Reset
+    Info (332105): create_clock -period 1.000 -name one_hertz_clock:inst9|inst102 one_hertz_clock:inst9|inst102
+    Info (332105): create_clock -period 1.000 -name Split Split
+    Info (332105): create_clock -period 1.000 -name ten_counter:inst1|inst ten_counter:inst1|inst
+    Info (332105): create_clock -period 1.000 -name ten_counter:inst2|inst ten_counter:inst2|inst
+    Info (332105): create_clock -period 1.000 -name ten_counter:inst6|inst ten_counter:inst6|inst
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.370
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.370       -44.235 DE0CLOCK 
+    Info (332119):    -1.031        -8.373 Split 
+    Info (332119):    -0.923        -0.923 Reset 
+    Info (332119):    -0.518        -1.429 ten_counter:inst1|inst 
+    Info (332119):    -0.505        -1.341 ten_counter:inst2|inst 
+    Info (332119):    -0.481        -1.435 one_hertz_clock:inst9|inst102 
+    Info (332119):    -0.054        -0.121 ten_counter:inst6|inst 
+Info (332146): Worst-case hold slack is -0.545
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.545        -1.713 one_hertz_clock:inst9|inst102 
+    Info (332119):    -0.440        -1.046 Split 
+    Info (332119):    -0.401        -1.418 ten_counter:inst2|inst 
+    Info (332119):    -0.349        -6.211 DE0CLOCK 
+    Info (332119):    -0.245        -0.692 ten_counter:inst1|inst 
+    Info (332119):     0.160         0.000 Reset 
+    Info (332119):     0.359         0.000 ten_counter:inst6|inst 
+Info (332146): Worst-case recovery slack is -2.180
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.180        -8.720 ten_counter:inst1|inst 
+    Info (332119):    -1.948        -7.792 ten_counter:inst2|inst 
+    Info (332119):    -0.679        -2.716 ten_counter:inst6|inst 
+    Info (332119):    -0.465        -1.860 one_hertz_clock:inst9|inst102 
+Info (332146): Worst-case removal slack is 0.969
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.969         0.000 one_hertz_clock:inst9|inst102 
+    Info (332119):     1.155         0.000 ten_counter:inst6|inst 
+    Info (332119):     2.492         0.000 ten_counter:inst2|inst 
+    Info (332119):     2.734         0.000 ten_counter:inst1|inst 
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -22.000 DE0CLOCK 
+    Info (332119):    -3.000        -3.000 Reset 
+    Info (332119):    -3.000        -3.000 Split 
+    Info (332119):    -1.000        -4.000 one_hertz_clock:inst9|inst102 
+    Info (332119):    -1.000        -4.000 ten_counter:inst1|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst2|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst6|inst 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.050
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.050       -38.014 DE0CLOCK 
+    Info (332119):    -0.772        -5.372 Split 
+    Info (332119):    -0.770        -0.770 Reset 
+    Info (332119):    -0.355        -0.961 ten_counter:inst1|inst 
+    Info (332119):    -0.347        -0.891 ten_counter:inst2|inst 
+    Info (332119):    -0.325        -0.962 one_hertz_clock:inst9|inst102 
+    Info (332119):     0.057         0.000 ten_counter:inst6|inst 
+Info (332146): Worst-case hold slack is -0.493
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.493        -1.569 one_hertz_clock:inst9|inst102 
+    Info (332119):    -0.486        -1.250 Split 
+    Info (332119):    -0.386        -1.354 ten_counter:inst2|inst 
+    Info (332119):    -0.361        -6.640 DE0CLOCK 
+    Info (332119):    -0.230        -0.633 ten_counter:inst1|inst 
+    Info (332119):     0.104         0.000 Reset 
+    Info (332119):     0.313         0.000 ten_counter:inst6|inst 
+Info (332146): Worst-case recovery slack is -2.039
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.039        -8.156 ten_counter:inst1|inst 
+    Info (332119):    -1.819        -7.276 ten_counter:inst2|inst 
+    Info (332119):    -0.688        -2.752 ten_counter:inst6|inst 
+    Info (332119):    -0.412        -1.648 one_hertz_clock:inst9|inst102 
+Info (332146): Worst-case removal slack is 0.953
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.953         0.000 one_hertz_clock:inst9|inst102 
+    Info (332119):     1.218         0.000 ten_counter:inst6|inst 
+    Info (332119):     2.412         0.000 ten_counter:inst2|inst 
+    Info (332119):     2.625         0.000 ten_counter:inst1|inst 
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -22.000 DE0CLOCK 
+    Info (332119):    -3.000        -3.000 Reset 
+    Info (332119):    -3.000        -3.000 Split 
+    Info (332119):    -1.000        -4.000 one_hertz_clock:inst9|inst102 
+    Info (332119):    -1.000        -4.000 ten_counter:inst1|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst2|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst6|inst 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.896
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.896       -16.354 DE0CLOCK 
+    Info (332119):    -0.696        -0.696 Reset 
+    Info (332119):     0.125         0.000 Split 
+    Info (332119):     0.176         0.000 ten_counter:inst1|inst 
+    Info (332119):     0.180         0.000 ten_counter:inst2|inst 
+    Info (332119):     0.192         0.000 one_hertz_clock:inst9|inst102 
+    Info (332119):     0.408         0.000 ten_counter:inst6|inst 
+Info (332146): Worst-case hold slack is -0.502
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.502        -3.342 Split 
+    Info (332119):    -0.309        -1.019 one_hertz_clock:inst9|inst102 
+    Info (332119):    -0.283        -5.149 DE0CLOCK 
+    Info (332119):    -0.229        -0.830 ten_counter:inst2|inst 
+    Info (332119):    -0.143        -0.438 ten_counter:inst1|inst 
+    Info (332119):     0.171         0.000 Reset 
+    Info (332119):     0.187         0.000 ten_counter:inst6|inst 
+Info (332146): Worst-case recovery slack is -0.972
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.972        -3.888 ten_counter:inst1|inst 
+    Info (332119):    -0.847        -3.388 ten_counter:inst2|inst 
+    Info (332119):    -0.097        -0.388 ten_counter:inst6|inst 
+    Info (332119):     0.214         0.000 one_hertz_clock:inst9|inst102 
+Info (332146): Worst-case removal slack is 0.489
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.489         0.000 one_hertz_clock:inst9|inst102 
+    Info (332119):     0.759         0.000 ten_counter:inst6|inst 
+    Info (332119):     1.560         0.000 ten_counter:inst2|inst 
+    Info (332119):     1.702         0.000 ten_counter:inst1|inst 
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -22.400 DE0CLOCK 
+    Info (332119):    -3.000        -3.097 Split 
+    Info (332119):    -3.000        -3.008 Reset 
+    Info (332119):    -1.000        -4.000 one_hertz_clock:inst9|inst102 
+    Info (332119):    -1.000        -4.000 ten_counter:inst1|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst2|inst 
+    Info (332119):    -1.000        -4.000 ten_counter:inst6|inst 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 488 megabytes
+    Info: Processing ended: Fri Feb 26 16:37:57 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/stopwatch/output_files/stopwatch.sta.summary b/stopwatch/output_files/stopwatch.sta.summary
new file mode 100644
index 0000000..7e1fd63
--- /dev/null
+++ b/stopwatch/output_files/stopwatch.sta.summary
@@ -0,0 +1,353 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'DE0CLOCK'
+Slack : -2.370
+TNS   : -44.235
+
+Type  : Slow 1200mV 85C Model Setup 'Split'
+Slack : -1.031
+TNS   : -8.373
+
+Type  : Slow 1200mV 85C Model Setup 'Reset'
+Slack : -0.923
+TNS   : -0.923
+
+Type  : Slow 1200mV 85C Model Setup 'ten_counter:inst1|inst'
+Slack : -0.518
+TNS   : -1.429
+
+Type  : Slow 1200mV 85C Model Setup 'ten_counter:inst2|inst'
+Slack : -0.505
+TNS   : -1.341
+
+Type  : Slow 1200mV 85C Model Setup 'one_hertz_clock:inst9|inst102'
+Slack : -0.481
+TNS   : -1.435
+
+Type  : Slow 1200mV 85C Model Setup 'ten_counter:inst6|inst'
+Slack : -0.054
+TNS   : -0.121
+
+Type  : Slow 1200mV 85C Model Hold 'one_hertz_clock:inst9|inst102'
+Slack : -0.545
+TNS   : -1.713
+
+Type  : Slow 1200mV 85C Model Hold 'Split'
+Slack : -0.440
+TNS   : -1.046
+
+Type  : Slow 1200mV 85C Model Hold 'ten_counter:inst2|inst'
+Slack : -0.401
+TNS   : -1.418
+
+Type  : Slow 1200mV 85C Model Hold 'DE0CLOCK'
+Slack : -0.349
+TNS   : -6.211
+
+Type  : Slow 1200mV 85C Model Hold 'ten_counter:inst1|inst'
+Slack : -0.245
+TNS   : -0.692
+
+Type  : Slow 1200mV 85C Model Hold 'Reset'
+Slack : 0.160
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'ten_counter:inst6|inst'
+Slack : 0.359
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'ten_counter:inst1|inst'
+Slack : -2.180
+TNS   : -8.720
+
+Type  : Slow 1200mV 85C Model Recovery 'ten_counter:inst2|inst'
+Slack : -1.948
+TNS   : -7.792
+
+Type  : Slow 1200mV 85C Model Recovery 'ten_counter:inst6|inst'
+Slack : -0.679
+TNS   : -2.716
+
+Type  : Slow 1200mV 85C Model Recovery 'one_hertz_clock:inst9|inst102'
+Slack : -0.465
+TNS   : -1.860
+
+Type  : Slow 1200mV 85C Model Removal 'one_hertz_clock:inst9|inst102'
+Slack : 0.969
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'ten_counter:inst6|inst'
+Slack : 1.155
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'ten_counter:inst2|inst'
+Slack : 2.492
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'ten_counter:inst1|inst'
+Slack : 2.734
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'DE0CLOCK'
+Slack : -3.000
+TNS   : -22.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Reset'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Split'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'one_hertz_clock:inst9|inst102'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ten_counter:inst1|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ten_counter:inst2|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'ten_counter:inst6|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Setup 'DE0CLOCK'
+Slack : -2.050
+TNS   : -38.014
+
+Type  : Slow 1200mV 0C Model Setup 'Split'
+Slack : -0.772
+TNS   : -5.372
+
+Type  : Slow 1200mV 0C Model Setup 'Reset'
+Slack : -0.770
+TNS   : -0.770
+
+Type  : Slow 1200mV 0C Model Setup 'ten_counter:inst1|inst'
+Slack : -0.355
+TNS   : -0.961
+
+Type  : Slow 1200mV 0C Model Setup 'ten_counter:inst2|inst'
+Slack : -0.347
+TNS   : -0.891
+
+Type  : Slow 1200mV 0C Model Setup 'one_hertz_clock:inst9|inst102'
+Slack : -0.325
+TNS   : -0.962
+
+Type  : Slow 1200mV 0C Model Setup 'ten_counter:inst6|inst'
+Slack : 0.057
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'one_hertz_clock:inst9|inst102'
+Slack : -0.493
+TNS   : -1.569
+
+Type  : Slow 1200mV 0C Model Hold 'Split'
+Slack : -0.486
+TNS   : -1.250
+
+Type  : Slow 1200mV 0C Model Hold 'ten_counter:inst2|inst'
+Slack : -0.386
+TNS   : -1.354
+
+Type  : Slow 1200mV 0C Model Hold 'DE0CLOCK'
+Slack : -0.361
+TNS   : -6.640
+
+Type  : Slow 1200mV 0C Model Hold 'ten_counter:inst1|inst'
+Slack : -0.230
+TNS   : -0.633
+
+Type  : Slow 1200mV 0C Model Hold 'Reset'
+Slack : 0.104
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'ten_counter:inst6|inst'
+Slack : 0.313
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'ten_counter:inst1|inst'
+Slack : -2.039
+TNS   : -8.156
+
+Type  : Slow 1200mV 0C Model Recovery 'ten_counter:inst2|inst'
+Slack : -1.819
+TNS   : -7.276
+
+Type  : Slow 1200mV 0C Model Recovery 'ten_counter:inst6|inst'
+Slack : -0.688
+TNS   : -2.752
+
+Type  : Slow 1200mV 0C Model Recovery 'one_hertz_clock:inst9|inst102'
+Slack : -0.412
+TNS   : -1.648
+
+Type  : Slow 1200mV 0C Model Removal 'one_hertz_clock:inst9|inst102'
+Slack : 0.953
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'ten_counter:inst6|inst'
+Slack : 1.218
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'ten_counter:inst2|inst'
+Slack : 2.412
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'ten_counter:inst1|inst'
+Slack : 2.625
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'DE0CLOCK'
+Slack : -3.000
+TNS   : -22.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Reset'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Split'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'one_hertz_clock:inst9|inst102'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst1|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst2|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst6|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Fast 1200mV 0C Model Setup 'DE0CLOCK'
+Slack : -0.896
+TNS   : -16.354
+
+Type  : Fast 1200mV 0C Model Setup 'Reset'
+Slack : -0.696
+TNS   : -0.696
+
+Type  : Fast 1200mV 0C Model Setup 'Split'
+Slack : 0.125
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'ten_counter:inst1|inst'
+Slack : 0.176
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'ten_counter:inst2|inst'
+Slack : 0.180
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'one_hertz_clock:inst9|inst102'
+Slack : 0.192
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'ten_counter:inst6|inst'
+Slack : 0.408
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'Split'
+Slack : -0.502
+TNS   : -3.342
+
+Type  : Fast 1200mV 0C Model Hold 'one_hertz_clock:inst9|inst102'
+Slack : -0.309
+TNS   : -1.019
+
+Type  : Fast 1200mV 0C Model Hold 'DE0CLOCK'
+Slack : -0.283
+TNS   : -5.149
+
+Type  : Fast 1200mV 0C Model Hold 'ten_counter:inst2|inst'
+Slack : -0.229
+TNS   : -0.830
+
+Type  : Fast 1200mV 0C Model Hold 'ten_counter:inst1|inst'
+Slack : -0.143
+TNS   : -0.438
+
+Type  : Fast 1200mV 0C Model Hold 'Reset'
+Slack : 0.171
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'ten_counter:inst6|inst'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'ten_counter:inst1|inst'
+Slack : -0.972
+TNS   : -3.888
+
+Type  : Fast 1200mV 0C Model Recovery 'ten_counter:inst2|inst'
+Slack : -0.847
+TNS   : -3.388
+
+Type  : Fast 1200mV 0C Model Recovery 'ten_counter:inst6|inst'
+Slack : -0.097
+TNS   : -0.388
+
+Type  : Fast 1200mV 0C Model Recovery 'one_hertz_clock:inst9|inst102'
+Slack : 0.214
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'one_hertz_clock:inst9|inst102'
+Slack : 0.489
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'ten_counter:inst6|inst'
+Slack : 0.759
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'ten_counter:inst2|inst'
+Slack : 1.560
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'ten_counter:inst1|inst'
+Slack : 1.702
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'DE0CLOCK'
+Slack : -3.000
+TNS   : -22.400
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Split'
+Slack : -3.000
+TNS   : -3.097
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Reset'
+Slack : -3.000
+TNS   : -3.008
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'one_hertz_clock:inst9|inst102'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst1|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst2|inst'
+Slack : -1.000
+TNS   : -4.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'ten_counter:inst6|inst'
+Slack : -1.000
+TNS   : -4.000
+
+------------------------------------------------------------
diff --git a/stopwatch/stopwatch.bdf b/stopwatch/stopwatch.bdf
new file mode 100644
index 0000000..79adb71
--- /dev/null
+++ b/stopwatch/stopwatch.bdf
@@ -0,0 +1,1603 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 128 512 296 528)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Start" (rect 5 0 28 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 72 528 128 544))
+)
+(pin
+	(input)
+	(rect 128 528 296 544)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Reset" (rect 5 0 34 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 72 544 128 560))
+)
+(pin
+	(input)
+	(rect 192 624 360 640)
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+	(pt 1272 248)
+	(pt 1312 248)
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+	(text "Q1[1]" (rect 1291 328 1318 340)(font "Arial" ))
+	(pt 1272 344)
+	(pt 1312 344)
+)
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+	(text "Q2[1]" (rect 1291 424 1318 436)(font "Arial" ))
+	(pt 1272 440)
+	(pt 1312 440)
+)
+(connector
+	(text "Q3[1]" (rect 1291 520 1318 532)(font "Arial" ))
+	(pt 1272 536)
+	(pt 1312 536)
+)
+(connector
+	(text "M1[0]" (rect 1216 336 1243 348)(font "Arial" ))
+	(pt 1208 352)
+	(pt 1232 352)
+)
+(connector
+	(text "M2[0]" (rect 1216 432 1243 444)(font "Arial" ))
+	(pt 1208 448)
+	(pt 1232 448)
+)
+(connector
+	(text "M3[0]" (rect 1216 528 1243 540)(font "Arial" ))
+	(pt 1208 544)
+	(pt 1232 544)
+)
+(connector
+	(text "M0[1]" (rect 1384 240 1411 252)(font "Arial" ))
+	(pt 1376 256)
+	(pt 1400 256)
+)
+(connector
+	(text "M1[1]" (rect 1384 336 1411 348)(font "Arial" ))
+	(pt 1376 352)
+	(pt 1400 352)
+)
+(connector
+	(text "M2[1]" (rect 1384 432 1411 444)(font "Arial" ))
+	(pt 1376 448)
+	(pt 1400 448)
+)
+(connector
+	(text "M3[1]" (rect 1384 528 1411 540)(font "Arial" ))
+	(pt 1376 544)
+	(pt 1400 544)
+)
+(connector
+	(text "Q0[2]" (rect 1459 232 1486 244)(font "Arial" ))
+	(pt 1440 248)
+	(pt 1480 248)
+)
+(connector
+	(text "Q1[2]" (rect 1459 328 1486 340)(font "Arial" ))
+	(pt 1440 344)
+	(pt 1480 344)
+)
+(connector
+	(text "Q2[2]" (rect 1459 424 1486 436)(font "Arial" ))
+	(pt 1440 440)
+	(pt 1480 440)
+)
+(connector
+	(text "Q3[2]" (rect 1459 520 1486 532)(font "Arial" ))
+	(pt 1440 536)
+	(pt 1480 536)
+)
+(connector
+	(text "M0[2]" (rect 1552 240 1579 252)(font "Arial" ))
+	(pt 1544 256)
+	(pt 1568 256)
+)
+(connector
+	(text "M1[2]" (rect 1552 336 1579 348)(font "Arial" ))
+	(pt 1544 352)
+	(pt 1568 352)
+)
+(connector
+	(text "M2[2]" (rect 1552 432 1579 444)(font "Arial" ))
+	(pt 1544 448)
+	(pt 1568 448)
+)
+(connector
+	(text "M3[2]" (rect 1552 528 1579 540)(font "Arial" ))
+	(pt 1544 544)
+	(pt 1568 544)
+)
+(connector
+	(text "Q0[3]" (rect 1635 232 1662 244)(font "Arial" ))
+	(pt 1616 248)
+	(pt 1656 248)
+)
+(connector
+	(text "Q1[3]" (rect 1635 328 1662 340)(font "Arial" ))
+	(pt 1616 344)
+	(pt 1656 344)
+)
+(connector
+	(text "Q2[3]" (rect 1635 424 1662 436)(font "Arial" ))
+	(pt 1616 440)
+	(pt 1656 440)
+)
+(connector
+	(text "Q3[3]" (rect 1635 520 1662 532)(font "Arial" ))
+	(pt 1616 536)
+	(pt 1656 536)
+)
+(connector
+	(text "M0[3]" (rect 1728 240 1755 252)(font "Arial" ))
+	(pt 1720 256)
+	(pt 1744 256)
+)
+(connector
+	(text "M1[3]" (rect 1728 336 1755 348)(font "Arial" ))
+	(pt 1720 352)
+	(pt 1744 352)
+)
+(connector
+	(text "M2[3]" (rect 1728 432 1755 444)(font "Arial" ))
+	(pt 1720 448)
+	(pt 1744 448)
+)
+(connector
+	(text "M3[3]" (rect 1728 528 1755 540)(font "Arial" ))
+	(pt 1720 544)
+	(pt 1744 544)
+)
+(connector
+	(text "M0[3..0]" (rect 824 184 864 196)(font "Arial" ))
+	(pt 856 208)
+	(pt 840 208)
+	(bus)
+)
+(connector
+	(text "M2[3..0]" (rect 824 424 864 436)(font "Arial" ))
+	(pt 856 448)
+	(pt 840 448)
+	(bus)
+)
+(connector
+	(text "M1[3..0]" (rect 821 312 861 324)(font "Arial" ))
+	(pt 856 328)
+	(pt 840 328)
+	(bus)
+)
+(connector
+	(text "M3[3..0]" (rect 823 552 863 564)(font "Arial" ))
+	(pt 856 568)
+	(pt 840 568)
+	(bus)
+)
+(connector
+	(text "Out0[6..0]" (rect 1047 192 1096 204)(font "Arial" ))
+	(pt 1040 208)
+	(pt 1064 208)
+	(bus)
+)
+(connector
+	(text "Out1[6..0]" (rect 1051 312 1100 324)(font "Arial" ))
+	(pt 1040 328)
+	(pt 1064 328)
+	(bus)
+)
+(connector
+	(text "Out2[6..0]" (rect 1052 432 1101 444)(font "Arial" ))
+	(pt 1040 448)
+	(pt 1064 448)
+	(bus)
+)
+(connector
+	(text "Out3[6..0]" (rect 1047 552 1096 564)(font "Arial" ))
+	(pt 1064 568)
+	(pt 1040 568)
+	(bus)
+)
+(connector
+	(pt 592 464)
+	(pt 640 464)
+)
+(connector
+	(pt 592 344)
+	(pt 592 464)
+)
+(connector
+	(pt 568 544)
+	(pt 592 544)
+)
+(connector
+	(pt 592 464)
+	(pt 592 544)
+)
+(connector
+	(pt 592 544)
+	(pt 592 584)
+)
+(connector
+	(text "Out0[6..0]" (rect 905 648 954 660)(font "Arial" ))
+	(pt 920 664)
+	(pt 896 664)
+	(bus)
+)
+(connector
+	(text "Out1[6..0]" (rect 903 680 952 692)(font "Arial" ))
+	(pt 920 696)
+	(pt 896 696)
+	(bus)
+)
+(connector
+	(text "Out2[6..0]" (rect 910 712 959 724)(font "Arial" ))
+	(pt 920 728)
+	(pt 896 728)
+	(bus)
+)
+(connector
+	(text "Out3[6..0]" (rect 911 744 960 756)(font "Arial" ))
+	(pt 920 760)
+	(pt 896 760)
+	(bus)
+)
+(connector
+	(pt 920 808)
+	(pt 904 808)
+)
+(connector
+	(pt 504 552)
+	(pt 496 552)
+)
+(connector
+	(pt 376 568)
+	(pt 344 568)
+)
+(connector
+	(pt 376 584)
+	(pt 320 584)
+)
+(connector
+	(pt 320 584)
+	(pt 320 536)
+)
+(connector
+	(pt 440 576)
+	(pt 496 576)
+)
+(connector
+	(pt 496 552)
+	(pt 496 576)
+)
+(connector
+	(pt 496 536)
+	(pt 496 528)
+)
+(connector
+	(pt 504 536)
+	(pt 496 536)
+)
+(connector
+	(pt 496 528)
+	(pt 488 528)
+)
+(connector
+	(pt 344 520)
+	(pt 344 568)
+)
+(connector
+	(text "EN" (rect 396 616 411 628)(font "Arial" ))
+	(pt 400 632)
+	(pt 360 632)
+)
+(connector
+	(pt 416 536)
+	(pt 424 536)
+)
+(connector
+	(pt 296 536)
+	(pt 320 536)
+)
+(connector
+	(pt 320 536)
+	(pt 368 536)
+)
+(connector
+	(pt 296 520)
+	(pt 344 520)
+)
+(connector
+	(pt 344 520)
+	(pt 424 520)
+)
+(junction (pt 592 344))
+(junction (pt 592 464))
+(junction (pt 592 544))
+(junction (pt 344 520))
+(junction (pt 320 536))
diff --git a/stopwatch/stopwatch.qpf b/stopwatch/stopwatch.qpf
new file mode 100644
index 0000000..ee98bd0
--- /dev/null
+++ b/stopwatch/stopwatch.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:12:21  February 26, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:12:21  February 26, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "stopwatch"
diff --git a/stopwatch/stopwatch.qsf b/stopwatch/stopwatch.qsf
new file mode 100644
index 0000000..7653276
--- /dev/null
+++ b/stopwatch/stopwatch.qsf
@@ -0,0 +1,92 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:12:21  February 26, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		stopwatch_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY stopwatch
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:12:21  FEBRUARY 26, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name BDF_FILE ../ten_counter/ten_counter.bdf
+set_global_assignment -name BDF_FILE ../one_hertz_clock/one_hertz_clock.bdf
+set_global_assignment -name BDF_FILE ../bcd_to_display/bcd_to_display.bdf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name BDF_FILE stopwatch.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_G21 -to DE0CLOCK
+set_location_assignment PIN_F13 -to DIG0[6]
+set_location_assignment PIN_A18 -to Point
+set_location_assignment PIN_H2 -to Reset
+set_location_assignment PIN_F1 -to Split
+set_location_assignment PIN_G3 -to Start
+set_location_assignment PIN_E11 -to DIG0[0]
+set_location_assignment PIN_F11 -to DIG0[1]
+set_location_assignment PIN_H12 -to DIG0[2]
+set_location_assignment PIN_H13 -to DIG0[3]
+set_location_assignment PIN_G12 -to DIG0[4]
+set_location_assignment PIN_F12 -to DIG0[5]
+set_location_assignment PIN_A13 -to DIG1[0]
+set_location_assignment PIN_B13 -to DIG1[1]
+set_location_assignment PIN_C13 -to DIG1[2]
+set_location_assignment PIN_A14 -to DIG1[3]
+set_location_assignment PIN_B14 -to DIG1[4]
+set_location_assignment PIN_E14 -to DIG1[5]
+set_location_assignment PIN_A15 -to DIG1[6]
+set_location_assignment PIN_D15 -to DIG2[0]
+set_location_assignment PIN_A16 -to DIG2[1]
+set_location_assignment PIN_B16 -to DIG2[2]
+set_location_assignment PIN_E15 -to DIG2[3]
+set_location_assignment PIN_A17 -to DIG2[4]
+set_location_assignment PIN_B17 -to DIG2[5]
+set_location_assignment PIN_F14 -to DIG2[6]
+set_location_assignment PIN_B18 -to DIG3[0]
+set_location_assignment PIN_F15 -to DIG3[1]
+set_location_assignment PIN_A19 -to DIG3[2]
+set_location_assignment PIN_B19 -to DIG3[3]
+set_location_assignment PIN_C19 -to DIG3[4]
+set_location_assignment PIN_D19 -to DIG3[5]
+set_location_assignment PIN_G15 -to DIG3[6]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/stopwatch/stopwatch.qws b/stopwatch/stopwatch.qws
new file mode 100644
index 0000000..99dfcaa
--- /dev/null
+++ b/stopwatch/stopwatch.qws
diff --git a/ten_bit_adder/db/.cmp.kpt b/ten_bit_adder/db/.cmp.kpt
new file mode 100644
index 0000000..6d65ceb
--- /dev/null
+++ b/ten_bit_adder/db/.cmp.kpt
diff --git a/ten_bit_adder/db/logic_util_heursitic.dat b/ten_bit_adder/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..a67f360
--- /dev/null
+++ b/ten_bit_adder/db/logic_util_heursitic.dat
diff --git a/ten_bit_adder/db/prev_cmp_ten_bit_adder.qmsg b/ten_bit_adder/db/prev_cmp_ten_bit_adder.qmsg
new file mode 100644
index 0000000..91a2961
--- /dev/null
+++ b/ten_bit_adder/db/prev_cmp_ten_bit_adder.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455821845789 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455821845790 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 18:57:25 2016 " "Processing started: Thu Feb 18 18:57:25 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455821845790 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455821845790 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455821845790 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455821846421 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455821846487 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455821846487 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/10_bit_adder/ten_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/10_bit_adder/ten_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder " "Found entity 1: ten_bit_adder" {  } { { "../10_bit_adder/ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/10_bit_adder/ten_bit_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455821846493 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455821846493 ""}
+{ "Error" "ESGN_DUPLICATE_ENTITY" "ten_bit_adder work " "Can't compile duplicate declarations of entity \"ten_bit_adder\" into library \"work\"" { { "Error" "ESGN_AMBIGUOUS_ENTITY_SUB" "ten_bit_adder ../10_bit_adder/ten_bit_adder.bdf work " "Instance could be entity \"ten_bit_adder\" in file ../10_bit_adder/ten_bit_adder.bdf compiled in library work" {  } { { "../10_bit_adder/ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/10_bit_adder/ten_bit_adder.bdf" { } } }  } 0 12180 "Instance could be entity \"%1!s!\" in file %2!s! compiled in library %3!s!" 0 0 "Quartus II" 0 -1 1455821846497 ""} { "Error" "ESGN_AMBIGUOUS_ENTITY_SUB" "ten_bit_adder ten_bit_adder.bdf work " "Instance could be entity \"ten_bit_adder\" in file ten_bit_adder.bdf compiled in library work" {  } { { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { } } }  } 0 12180 "Instance could be entity \"%1!s!\" in file %2!s! compiled in library %3!s!" 0 0 "Quartus II" 0 -1 1455821846497 ""}  } { { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { } } }  } 0 12049 "Can't compile duplicate declarations of entity \"%1!s!\" into library \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455821846497 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_bit_adder.bdf" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455821846497 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "541 " "Peak virtual memory: 541 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455821846565 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Feb 18 18:57:26 2016 " "Processing ended: Thu Feb 18 18:57:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455821846565 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455821846565 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455821846565 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455821846565 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1  " "Quartus II Full Compilation was unsuccessful. 5 errors, 1 warning" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455821847195 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.(0).cnf.cdb b/ten_bit_adder/db/ten_bit_adder.(0).cnf.cdb
new file mode 100644
index 0000000..d4652cb
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.(0).cnf.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.(0).cnf.hdb b/ten_bit_adder/db/ten_bit_adder.(0).cnf.hdb
new file mode 100644
index 0000000..fcb0dae
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.(0).cnf.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.(1).cnf.cdb b/ten_bit_adder/db/ten_bit_adder.(1).cnf.cdb
new file mode 100644
index 0000000..3bfc62a
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.(1).cnf.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.(1).cnf.hdb b/ten_bit_adder/db/ten_bit_adder.(1).cnf.hdb
new file mode 100644
index 0000000..0396635
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.(1).cnf.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.asm.qmsg b/ten_bit_adder/db/ten_bit_adder.asm.qmsg
new file mode 100644
index 0000000..85b71ee
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455834010331 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455834010332 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:20:10 2016 " "Processing started: Thu Feb 18 22:20:10 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455834010332 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455834010332 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455834010332 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455834011184 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455834011208 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455834011520 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:20:11 2016 " "Processing ended: Thu Feb 18 22:20:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455834011520 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455834011520 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455834011520 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455834011520 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.asm.rdb b/ten_bit_adder/db/ten_bit_adder.asm.rdb
new file mode 100644
index 0000000..623648c
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.asm.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.asm_labs.ddb b/ten_bit_adder/db/ten_bit_adder.asm_labs.ddb
new file mode 100644
index 0000000..6c8dc55
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.asm_labs.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.cbx.xml b/ten_bit_adder/db/ten_bit_adder.cbx.xml
new file mode 100644
index 0000000..7f9af1e
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ten_bit_adder">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.bpm b/ten_bit_adder/db/ten_bit_adder.cmp.bpm
new file mode 100644
index 0000000..51dd5b1
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.bpm
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.cdb b/ten_bit_adder/db/ten_bit_adder.cmp.cdb
new file mode 100644
index 0000000..f51083c
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.hdb b/ten_bit_adder/db/ten_bit_adder.cmp.hdb
new file mode 100644
index 0000000..9add29a
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.idb b/ten_bit_adder/db/ten_bit_adder.cmp.idb
new file mode 100644
index 0000000..cbba78e
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.idb
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.logdb b/ten_bit_adder/db/ten_bit_adder.cmp.logdb
new file mode 100644
index 0000000..d85d2ab
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.logdb
@@ -0,0 +1,74 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;32;0;0;32;32;0;11;0;0;21;0;11;21;0;0;0;11;0;0;0;0;0;32;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,32;32;32;32;32;0;32;32;0;0;32;21;32;32;11;32;21;11;32;32;32;21;32;32;32;32;32;0;32;32,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Cout,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,EN,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp.rdb b/ten_bit_adder/db/ten_bit_adder.cmp.rdb
new file mode 100644
index 0000000..c227a98
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.cmp_merge.kpt b/ten_bit_adder/db/ten_bit_adder.cmp_merge.kpt
new file mode 100644
index 0000000..6b84c1b
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.cmp_merge.kpt
diff --git a/ten_bit_adder/db/ten_bit_adder.db_info b/ten_bit_adder/db/ten_bit_adder.db_info
new file mode 100644
index 0000000..82d74e0
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 22:08:10 2016
diff --git a/ten_bit_adder/db/ten_bit_adder.eda.qmsg b/ten_bit_adder/db/ten_bit_adder.eda.qmsg
new file mode 100644
index 0000000..b714d2c
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455834017485 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455834017486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:20:17 2016 " "Processing started: Thu Feb 18 22:20:17 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455834017486 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455834017486 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455834017486 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834017953 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834017983 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018016 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018047 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018072 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018098 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018130 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_vhd.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ simulation " "Generated file ten_bit_adder_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455834018159 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "493 " "Peak virtual memory: 493 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455834018205 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:20:18 2016 " "Processing ended: Thu Feb 18 22:20:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455834018205 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455834018205 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455834018205 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455834018205 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.fit.qmsg b/ten_bit_adder/db/ten_bit_adder.fit.qmsg
new file mode 100644
index 0000000..bb1dfe2
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455834000922 ""}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "ten_bit_adder EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design ten_bit_adder" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455834001164 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455834001238 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455834001238 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455834001354 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455834001378 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455834001603 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455834001603 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455834001603 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 115 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455834001604 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 117 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455834001604 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 119 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455834001604 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 121 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455834001604 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 123 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455834001604 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455834001604 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455834001610 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "32 32 " "No exact pin location assignment(s) for 32 pins of 32 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cout " "Pin Cout not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cout } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 1520 976 1152 1536 "Cout" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 46 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[9\] " "Pin S\[9\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[9] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 36 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[8\] " "Pin S\[8\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[8] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 37 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[7\] " "Pin S\[7\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[7] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 38 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[6\] " "Pin S\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[6] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 39 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[5\] " "Pin S\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[5] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 40 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[4\] " "Pin S\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[4] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 41 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[3\] " "Pin S\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[3] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[2\] " "Pin S\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[2] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 43 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[1\] " "Pin S\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[1] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S\[0\] " "Pin S\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S[0] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 448 1072 1248 464 "S" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 45 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[9\] " "Pin Y\[9\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[9] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 26 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[9\] " "Pin X\[9\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[9] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[8\] " "Pin Y\[8\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[8] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 27 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[7\] " "Pin Y\[7\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[7] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 28 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[7\] " "Pin X\[7\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[7] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[6\] " "Pin Y\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[6] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 29 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[5\] " "Pin Y\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[5] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 30 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[5\] " "Pin X\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[5] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 20 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[4\] " "Pin Y\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[4] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 31 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[2\] " "Pin Y\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[2] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 33 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[0\] " "Pin Y\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[0] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 35 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[0\] " "Pin X\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[0] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[1\] " "Pin Y\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[1] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 34 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[1\] " "Pin X\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[1] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 24 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[2\] " "Pin X\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[2] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y\[3\] " "Pin Y\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y[3] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 464 320 488 480 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 32 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[3\] " "Pin X\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[3] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 22 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[4\] " "Pin X\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[4] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[6\] " "Pin X\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[6] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 19 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X\[8\] " "Pin X\[8\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X[8] } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 440 320 488 456 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 17 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "EN " "Pin EN not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { EN } } } { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 240 808 824 408 "EN" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455834002042 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455834002042 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_bit_adder.sdc " "Synopsys Design Constraints File file not found: 'ten_bit_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455834002398 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455834002399 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455834002400 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455834002400 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455834002400 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455834002401 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455834002401 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455834002402 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455834002403 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455834002403 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455834002404 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455834002404 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455834002404 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455834002404 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455834002404 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455834002404 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "32 unused 2.5V 21 11 0 " "Number of I/O pins in group: 32 (unused VREF, 2.5V VCCIO, 21 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455834002409 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455834002409 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455834002409 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 0 2 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455834002414 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455834002414 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455834002414 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455834002471 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455834004119 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455834004179 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455834004186 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455834004392 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455834004392 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455834004799 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X21_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} 11 0 11 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455834005372 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455834005372 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455834005426 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455834005427 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455834005427 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455834005427 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455834005440 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455834005554 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455834005760 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455834005851 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455834006049 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455834006633 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455834007484 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "911 " "Peak virtual memory: 911 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455834008161 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:20:08 2016 " "Processing ended: Thu Feb 18 22:20:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455834008161 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455834008161 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455834008161 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455834008161 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.hier_info b/ten_bit_adder/db/ten_bit_adder.hier_info
new file mode 100644
index 0000000..e734831
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.hier_info
@@ -0,0 +1,184 @@
+|ten_bit_adder
+Cout <= full_adder:inst17.Cout
+X[0] => full_adder:inst8.X
+X[1] => full_adder:inst9.X
+X[2] => full_adder:inst10.X
+X[3] => full_adder:inst11.X
+X[4] => full_adder:inst12.X
+X[5] => full_adder:inst13.X
+X[6] => full_adder:inst14.X
+X[7] => full_adder:inst15.X
+X[8] => full_adder:inst16.X
+X[9] => full_adder:inst17.X
+Y[0] => full_adder:inst8.Y
+Y[1] => full_adder:inst9.Y
+Y[2] => full_adder:inst10.Y
+Y[3] => full_adder:inst11.Y
+Y[4] => full_adder:inst12.Y
+Y[5] => full_adder:inst13.Y
+Y[6] => full_adder:inst14.Y
+Y[7] => full_adder:inst15.Y
+Y[8] => full_adder:inst16.Y
+Y[9] => full_adder:inst17.Y
+S[0] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+S[1] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+S[2] <= inst18.DB_MAX_OUTPUT_PORT_TYPE
+S[3] <= inst19.DB_MAX_OUTPUT_PORT_TYPE
+S[4] <= inst20.DB_MAX_OUTPUT_PORT_TYPE
+S[5] <= inst21.DB_MAX_OUTPUT_PORT_TYPE
+S[6] <= inst22.DB_MAX_OUTPUT_PORT_TYPE
+S[7] <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+S[8] <= inst24.DB_MAX_OUTPUT_PORT_TYPE
+S[9] <= inst25.DB_MAX_OUTPUT_PORT_TYPE
+EN => inst7.IN1
+EN => inst6.IN1
+EN => inst23.IN1
+EN => inst24.IN1
+EN => inst18.IN1
+EN => inst19.IN1
+EN => inst20.IN1
+EN => inst21.IN1
+EN => inst22.IN1
+EN => inst25.IN1
+
+
+|ten_bit_adder|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/ten_bit_adder/db/ten_bit_adder.hif b/ten_bit_adder/db/ten_bit_adder.hif
new file mode 100644
index 0000000..5ebc609
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.hif
diff --git a/ten_bit_adder/db/ten_bit_adder.ipinfo b/ten_bit_adder/db/ten_bit_adder.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.ipinfo
diff --git a/ten_bit_adder/db/ten_bit_adder.lpc.html b/ten_bit_adder/db/ten_bit_adder.lpc.html
new file mode 100644
index 0000000..c2f91e6
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.lpc.html
@@ -0,0 +1,178 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst10</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst11</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst12</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst13</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst15</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst16</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst17</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/ten_bit_adder/db/ten_bit_adder.lpc.rdb b/ten_bit_adder/db/ten_bit_adder.lpc.rdb
new file mode 100644
index 0000000..eeeec9c
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.lpc.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.lpc.txt b/ten_bit_adder/db/ten_bit_adder.lpc.txt
new file mode 100644
index 0000000..c862e87
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.lpc.txt
@@ -0,0 +1,16 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst8     ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9     ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst11    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst12    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst13    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst14    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst15    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst16    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst17    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/ten_bit_adder/db/ten_bit_adder.map.ammdb b/ten_bit_adder/db/ten_bit_adder.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.ammdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map.bpm b/ten_bit_adder/db/ten_bit_adder.map.bpm
new file mode 100644
index 0000000..5b92034
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.bpm
diff --git a/ten_bit_adder/db/ten_bit_adder.map.cdb b/ten_bit_adder/db/ten_bit_adder.map.cdb
new file mode 100644
index 0000000..21b02f4
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map.hdb b/ten_bit_adder/db/ten_bit_adder.map.hdb
new file mode 100644
index 0000000..0608a88
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map.kpt b/ten_bit_adder/db/ten_bit_adder.map.kpt
new file mode 100644
index 0000000..14a0b14
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.kpt
diff --git a/ten_bit_adder/db/ten_bit_adder.map.logdb b/ten_bit_adder/db/ten_bit_adder.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder/db/ten_bit_adder.map.qmsg b/ten_bit_adder/db/ten_bit_adder.map.qmsg
new file mode 100644
index 0000000..f0f0631
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.qmsg
@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455833997197 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455833997197 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:19:57 2016 " "Processing started: Thu Feb 18 22:19:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455833997197 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455833997197 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455833997198 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455833997530 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455833997596 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455833997596 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_bit_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_bit_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder " "Found entity 1: ten_bit_adder" {  } { { "ten_bit_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455833997598 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455833997598 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_no_bus " "Found entity 1: ten_bit_adder_no_bus" {  } { { "ten_bit_adder_no_bus.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder_no_bus.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455833997600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455833997600 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_bit_adder " "Elaborating entity \"ten_bit_adder\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455833997632 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"full_adder:inst17\"" {  } { { "ten_bit_adder.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf" { { 1424 680 776 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455833997635 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455833998253 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455833998511 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455833998511 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "55 " "Implemented 55 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "21 " "Implemented 21 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455833998576 ""} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Implemented 11 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455833998576 ""} { "Info" "ICUT_CUT_TM_LCELLS" "23 " "Implemented 23 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455833998576 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455833998576 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "557 " "Peak virtual memory: 557 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455833998599 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:19:58 2016 " "Processing ended: Thu Feb 18 22:19:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455833998599 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455833998599 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455833998599 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455833998599 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.map.rdb b/ten_bit_adder/db/ten_bit_adder.map.rdb
new file mode 100644
index 0000000..e3f5f21
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map_bb.cdb b/ten_bit_adder/db/ten_bit_adder.map_bb.cdb
new file mode 100644
index 0000000..315c6f5
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map_bb.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map_bb.hdb b/ten_bit_adder/db/ten_bit_adder.map_bb.hdb
new file mode 100644
index 0000000..b864502
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map_bb.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.map_bb.logdb b/ten_bit_adder/db/ten_bit_adder.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder/db/ten_bit_adder.pre_map.hdb b/ten_bit_adder/db/ten_bit_adder.pre_map.hdb
new file mode 100644
index 0000000..b05efcb
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.pre_map.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.pti_db_list.ddb b/ten_bit_adder/db/ten_bit_adder.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.pti_db_list.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.root_partition.map.reg_db.cdb b/ten_bit_adder/db/ten_bit_adder.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..d530f2a
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.root_partition.map.reg_db.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.routing.rdb b/ten_bit_adder/db/ten_bit_adder.routing.rdb
new file mode 100644
index 0000000..8d6e8cc
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.routing.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.rtlv.hdb b/ten_bit_adder/db/ten_bit_adder.rtlv.hdb
new file mode 100644
index 0000000..8e72e11
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.rtlv.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.rtlv_sg.cdb b/ten_bit_adder/db/ten_bit_adder.rtlv_sg.cdb
new file mode 100644
index 0000000..a74a487
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.rtlv_sg.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.rtlv_sg_swap.cdb b/ten_bit_adder/db/ten_bit_adder.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..1de9c7a
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.rtlv_sg_swap.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.sgdiff.cdb b/ten_bit_adder/db/ten_bit_adder.sgdiff.cdb
new file mode 100644
index 0000000..caaa261
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sgdiff.cdb
diff --git a/ten_bit_adder/db/ten_bit_adder.sgdiff.hdb b/ten_bit_adder/db/ten_bit_adder.sgdiff.hdb
new file mode 100644
index 0000000..5328492
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sgdiff.hdb
diff --git a/ten_bit_adder/db/ten_bit_adder.sld_design_entry.sci b/ten_bit_adder/db/ten_bit_adder.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sld_design_entry.sci
diff --git a/ten_bit_adder/db/ten_bit_adder.sld_design_entry_dsc.sci b/ten_bit_adder/db/ten_bit_adder.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sld_design_entry_dsc.sci
diff --git a/ten_bit_adder/db/ten_bit_adder.smart_action.txt b/ten_bit_adder/db/ten_bit_adder.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/ten_bit_adder/db/ten_bit_adder.sta.qmsg b/ten_bit_adder/db/ten_bit_adder.sta.qmsg
new file mode 100644
index 0000000..bacd695
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sta.qmsg
@@ -0,0 +1,48 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455834013673 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455834013674 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:20:13 2016 " "Processing started: Thu Feb 18 22:20:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455834013674 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455834013674 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_bit_adder -c ten_bit_adder " "Command: quartus_sta ten_bit_adder -c ten_bit_adder" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455834013674 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455834013768 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455834013916 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455834013988 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455834013989 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_bit_adder.sdc " "Synopsys Design Constraints File file not found: 'ten_bit_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455834014334 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455834014335 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455834014335 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455834014335 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455834014336 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455834014336 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455834014336 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455834014342 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455834014345 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014346 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014355 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014360 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014364 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014368 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014372 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455834014391 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455834014427 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455834014766 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455834014814 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455834014815 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455834014815 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455834014815 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014815 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014826 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014832 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014846 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014850 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834014857 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455834014880 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455834015093 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455834015094 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455834015094 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455834015094 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834015098 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834015103 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834015109 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834015113 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455834015118 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455834015661 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455834015662 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "532 " "Peak virtual memory: 532 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455834015738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:20:15 2016 " "Processing ended: Thu Feb 18 22:20:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455834015738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455834015738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455834015738 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455834015738 ""}
diff --git a/ten_bit_adder/db/ten_bit_adder.sta.rdb b/ten_bit_adder/db/ten_bit_adder.sta.rdb
new file mode 100644
index 0000000..4157a1d
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sta.rdb
diff --git a/ten_bit_adder/db/ten_bit_adder.sta_cmp.6_slow_1200mv_85c.tdb b/ten_bit_adder/db/ten_bit_adder.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..bfa8013
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..a413810
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
diff --git a/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
new file mode 100644
index 0000000..a546d32
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
diff --git a/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..e9b1d75
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
diff --git a/ten_bit_adder/db/ten_bit_adder.tis_db_list.ddb b/ten_bit_adder/db/ten_bit_adder.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.tis_db_list.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.tiscmp.fast_1200mv_0c.ddb b/ten_bit_adder/db/ten_bit_adder.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..ae25bf0
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.tiscmp.fast_1200mv_0c.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_0c.ddb b/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..eaaf0d7
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_0c.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_85c.ddb b/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..3901cdc
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.tiscmp.slow_1200mv_85c.ddb
diff --git a/ten_bit_adder/db/ten_bit_adder.tmw_info b/ten_bit_adder/db/ten_bit_adder.tmw_info
new file mode 100644
index 0000000..88b5083
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:23
+start_analysis_synthesis:s:00:00:04-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:09-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:04-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/ten_bit_adder/db/ten_bit_adder.vpr.ammdb b/ten_bit_adder/db/ten_bit_adder.vpr.ammdb
new file mode 100644
index 0000000..27c3a51
--- /dev/null
+++ b/ten_bit_adder/db/ten_bit_adder.vpr.ammdb
diff --git a/ten_bit_adder/incremental_db/README b/ten_bit_adder/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/ten_bit_adder/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.db_info b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.db_info
new file mode 100644
index 0000000..fcea881
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 18:57:48 2016
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.ammdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.ammdb
new file mode 100644
index 0000000..b55d774
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.ammdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.cdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.cdb
new file mode 100644
index 0000000..00f514a
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.cdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.dfp b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.dfp
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.hdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.hdb
new file mode 100644
index 0000000..ef42a6b
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.hdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.logdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.rcfdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..3666465
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.cmp.rcfdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.cdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.cdb
new file mode 100644
index 0000000..9eb3442
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.cdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.dpi b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.dpi
new file mode 100644
index 0000000..1d706d1
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.dpi
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.cdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..5d656dd
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.cdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hb_info b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hb_info
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..096f8bc
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.hdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.sig b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..91e140d
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+6d99a1516c2e2beefe1f386eab1dd580
\ No newline at end of file
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hdb b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hdb
new file mode 100644
index 0000000..18e1b52
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.hdb
diff --git a/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.kpt b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.kpt
new file mode 100644
index 0000000..a84d93c
--- /dev/null
+++ b/ten_bit_adder/incremental_db/compiled_partitions/ten_bit_adder.root_partition.map.kpt
diff --git a/ten_bit_adder/output_files/ten_bit_adder.asm.rpt b/ten_bit_adder/output_files/ten_bit_adder.asm.rpt
new file mode 100644
index 0000000..8eb3e16
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ten_bit_adder
+Thu Feb 18 22:20:11 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Thu Feb 18 22:20:11 2016 ;
+; Revision Name         ; ten_bit_adder                         ;
+; Top-level Entity Name ; ten_bit_adder                         ;
+; Family                ; Cyclone IV GX                         ;
+; Device                ; EP4CGX15BF14C6                        ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Assembler Generated Files                                                   ;
++-----------------------------------------------------------------------------+
+; File Name                                                                   ;
++-----------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.sof ;
++-----------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.sof ;
++----------------+--------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                              ;
++----------------+--------------------------------------------------------------------------------------+
+; Device         ; EP4CGX15BF14C6                                                                       ;
+; JTAG usercode  ; 0x000BFB8D                                                                           ;
+; Checksum       ; 0x000BFB8D                                                                           ;
++----------------+--------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:20:10 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 518 megabytes
+    Info: Processing ended: Thu Feb 18 22:20:11 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.done b/ten_bit_adder/output_files/ten_bit_adder.done
new file mode 100644
index 0000000..b6cd60a
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.done
@@ -0,0 +1 @@
+Thu Feb 18 22:20:18 2016
diff --git a/ten_bit_adder/output_files/ten_bit_adder.eda.rpt b/ten_bit_adder/output_files/ten_bit_adder.eda.rpt
new file mode 100644
index 0000000..89557c0
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for ten_bit_adder
+Thu Feb 18 22:20:18 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Thu Feb 18 22:20:18 2016 ;
+; Revision Name             ; ten_bit_adder                         ;
+; Top-level Entity Name     ; ten_bit_adder                         ;
+; Family                    ; Cyclone IV GX                         ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                ;
++-----------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                           ;
++-----------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder.vho                        ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_vhd.sdo                    ;
++-----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:20:17 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder
+Info (204019): Generated file ten_bit_adder_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 493 megabytes
+    Info: Processing ended: Thu Feb 18 22:20:18 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.fit.rpt b/ten_bit_adder/output_files/ten_bit_adder.fit.rpt
new file mode 100644
index 0000000..c1f558a
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.fit.rpt
@@ -0,0 +1,1168 @@
+Fitter report for ten_bit_adder
+Thu Feb 18 22:20:07 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Routing Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. I/O Rules Summary
+ 27. I/O Rules Details
+ 28. I/O Rules Matrix
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Thu Feb 18 22:20:07 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder                              ;
+; Top-level Entity Name              ; ten_bit_adder                              ;
+; Family                             ; Cyclone IV GX                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 23 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 23 / 14,400 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32 / 81 ( 40 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; auto                                  ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Generate GXB Reconfig MIF                                                  ; Off                                   ; Off                                   ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_40MHz                            ; FREQ_40MHz                            ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; Cout     ; Incomplete set of assignments ;
+; S[9]     ; Incomplete set of assignments ;
+; S[8]     ; Incomplete set of assignments ;
+; S[7]     ; Incomplete set of assignments ;
+; S[6]     ; Incomplete set of assignments ;
+; S[5]     ; Incomplete set of assignments ;
+; S[4]     ; Incomplete set of assignments ;
+; S[3]     ; Incomplete set of assignments ;
+; S[2]     ; Incomplete set of assignments ;
+; S[1]     ; Incomplete set of assignments ;
+; S[0]     ; Incomplete set of assignments ;
+; Y[9]     ; Incomplete set of assignments ;
+; X[9]     ; Incomplete set of assignments ;
+; Y[8]     ; Incomplete set of assignments ;
+; Y[7]     ; Incomplete set of assignments ;
+; X[7]     ; Incomplete set of assignments ;
+; Y[6]     ; Incomplete set of assignments ;
+; Y[5]     ; Incomplete set of assignments ;
+; X[5]     ; Incomplete set of assignments ;
+; Y[4]     ; Incomplete set of assignments ;
+; Y[2]     ; Incomplete set of assignments ;
+; Y[0]     ; Incomplete set of assignments ;
+; X[0]     ; Incomplete set of assignments ;
+; Y[1]     ; Incomplete set of assignments ;
+; X[1]     ; Incomplete set of assignments ;
+; X[2]     ; Incomplete set of assignments ;
+; Y[3]     ; Incomplete set of assignments ;
+; X[3]     ; Incomplete set of assignments ;
+; X[4]     ; Incomplete set of assignments ;
+; X[6]     ; Incomplete set of assignments ;
+; X[8]     ; Incomplete set of assignments ;
+; EN       ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 98 ) ; 0.00 % ( 0 / 98 )          ; 0.00 % ( 0 / 98 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 98 ) ; 0.00 % ( 0 / 98 )          ; 0.00 % ( 0 / 98 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 88 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 23 / 14,400 ( < 1 % ) ;
+;     -- Combinational with no register       ; 23                    ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 0                     ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 11                    ;
+;     -- 3 input functions                    ; 9                     ;
+;     -- <=2 input functions                  ; 3                     ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 23                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 0 / 14,733 ( 0 % )    ;
+;     -- Dedicated logic registers            ; 0 / 14,400 ( 0 % )    ;
+;     -- I/O registers                        ; 0 / 333 ( 0 % )       ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 2 / 900 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 32 / 81 ( 40 % )      ;
+;     -- Clock pins                           ; 2 / 6 ( 33 % )        ;
+;     -- Dedicated input pins                 ; 0 / 12 ( 0 % )        ;
+;                                             ;                       ;
+; Global signals                              ; 0                     ;
+; M9Ks                                        ; 0 / 60 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 552,960 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 552,960 ( 0 % )   ;
+; PLLs                                        ; 0 / 3 ( 0 % )         ;
+; Global clocks                               ; 0 / 20 ( 0 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; GXB Receiver channel PCSs                   ; 0 / 2 ( 0 % )         ;
+; GXB Receiver channel PMAs                   ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PCSs                ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PMAs                ; 0 / 2 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 3 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 1%          ;
+; Maximum fan-out                             ; 10                    ;
+; Highest non-global fan-out                  ; 10                    ;
+; Total fan-out                               ; 125                   ;
+; Average fan-out                             ; 1.29                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 23 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % )              ;
+;     -- Combinational with no register       ; 23                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 11                   ; 0                              ;
+;     -- 3 input functions                    ; 9                    ; 0                              ;
+;     -- <=2 input functions                  ; 3                    ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 23                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 0                    ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 14400 ( 0 % )    ; 0 / 14400 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 2 / 900 ( < 1 % )    ; 0 / 900 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 32                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0                    ; 0                              ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 120                  ; 5                              ;
+;     -- Registered Connections               ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 21                   ; 0                              ;
+;     -- Output Ports                         ; 11                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; EN   ; G10   ; 6        ; 33           ; 22           ; 7            ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[0] ; L7    ; 3        ; 14           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[1] ; F13   ; 6        ; 33           ; 16           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[2] ; F12   ; 6        ; 33           ; 16           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[3] ; L12   ; 5        ; 33           ; 12           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[4] ; N6    ; 3        ; 12           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[5] ; H12   ; 5        ; 33           ; 14           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[6] ; N13   ; 5        ; 33           ; 10           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[7] ; F9    ; 6        ; 33           ; 25           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[8] ; D10   ; 6        ; 33           ; 27           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X[9] ; N7    ; 4        ; 16           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[0] ; K10   ; 4        ; 31           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[1] ; N8    ; 4        ; 20           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[2] ; L4    ; 3        ; 8            ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[3] ; M6    ; 3        ; 12           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[4] ; N4    ; 3        ; 10           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[5] ; L5    ; 3        ; 14           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[6] ; K8    ; 4        ; 22           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[7] ; K13   ; 5        ; 33           ; 15           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[8] ; B8    ; 7        ; 22           ; 31           ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y[9] ; M7    ; 4        ; 16           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Cout ; D11   ; 6        ; 33           ; 28           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[0] ; N10   ; 4        ; 26           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[1] ; K9    ; 4        ; 22           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[2] ; N9    ; 4        ; 20           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[3] ; L9    ; 4        ; 24           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[4] ; M4    ; 3        ; 8            ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[5] ; K11   ; 5        ; 33           ; 11           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[6] ; A6    ; 8        ; 10           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[7] ; F10   ; 6        ; 33           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[8] ; C13   ; 7        ; 29           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S[9] ; E10   ; 6        ; 33           ; 27           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                            ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; Location ; Pin Name              ; Reserved As              ; User Signal Name ; Pin Type                  ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; L3       ; MSEL2                 ; -                        ; -                ; Dedicated Programming Pin ;
+; N3       ; MSEL1                 ; -                        ; -                ; Dedicated Programming Pin ;
+; K5       ; MSEL0                 ; -                        ; -                ; Dedicated Programming Pin ;
+; J5       ; CONF_DONE             ; -                        ; -                ; Dedicated Programming Pin ;
+; K6       ; nSTATUS               ; -                        ; -                ; Dedicated Programming Pin ;
+; N4       ; DIFFIO_B1p, CRC_ERROR ; Use as regular IO        ; Y[4]             ; Dual Purpose Pin          ;
+; N5       ; DIFFIO_B1n, NCEO      ; Use as programming pin   ; ~ALTERA_NCEO~    ; Dual Purpose Pin          ;
+; M6       ; DIFFIO_B2p, INIT_DONE ; Use as regular IO        ; Y[3]             ; Dual Purpose Pin          ;
+; G10      ; DIFFIO_R4n, DEV_OE    ; Use as regular IO        ; EN               ; Dual Purpose Pin          ;
+; D10      ; DIFFIO_R2n, DEV_CLRn  ; Use as regular IO        ; X[8]             ; Dual Purpose Pin          ;
+; A6       ; CLKUSR                ; Use as regular IO        ; S[6]             ; Dual Purpose Pin          ;
+; A5       ; DATA0                 ; As input tri-stated      ; ~ALTERA_DATA0~   ; Dual Purpose Pin          ;
+; B5       ; ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO~    ; Dual Purpose Pin          ;
+; C5       ; NCSO                  ; As input tri-stated      ; ~ALTERA_NCSO~    ; Dual Purpose Pin          ;
+; A4       ; DCLK                  ; As output driving ground ; ~ALTERA_DCLK~    ; Dual Purpose Pin          ;
+; D5       ; nCONFIG               ; -                        ; -                ; Dedicated Programming Pin ;
+; C4       ; nCE                   ; -                        ; -                ; Dedicated Programming Pin ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------+
+; I/O Bank Usage                                                               ;
++----------+-----------------+---------------+--------------+------------------+
+; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ;
++----------+-----------------+---------------+--------------+------------------+
+; QL0      ; 0 / 8 ( 0 % )   ; --            ; --           ; --               ;
+; 3        ; 8 / 8 ( 100 % ) ; 2.5V          ; --           ; --               ;
+; 3A       ; 0 / 2 ( 0 % )   ; --            ; --           ; 2.5V             ;
+; 4        ; 9 / 14 ( 64 % ) ; 2.5V          ; --           ; --               ;
+; 5        ; 5 / 12 ( 42 % ) ; 2.5V          ; --           ; --               ;
+; 6        ; 8 / 12 ( 67 % ) ; 2.5V          ; --           ; --               ;
+; 7        ; 2 / 14 ( 14 % ) ; 2.5V          ; --           ; --               ;
+; 8A       ; 0 / 2 ( 0 % )   ; --            ; --           ; 2.5V             ;
+; 8        ; 1 / 5 ( 20 % )  ; 2.5V          ; --           ; --               ;
+; 9        ; 4 / 4 ( 100 % ) ; 2.5V          ; --           ; --               ;
++----------+-----------------+---------------+--------------+------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                               ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                   ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ; 99         ; 9        ; #TDO                                             ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ; 98         ; 9        ; #TMS                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A3       ; 96         ; 9        ; #TDI                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A4       ; 93         ; 9        ; ~ALTERA_DCLK~                                    ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A5       ; 90         ; 9        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A6       ; 89         ; 8        ; S[6]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A7       ; 87         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 88         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 81         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A10      ; 82         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A11      ; 79         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A12      ; 80         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A13      ; 73         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 97         ; 9        ; #TCK                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; B4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B5       ; 91         ; 9        ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; B6       ; 86         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B8       ; 77         ; 7        ; Y[8]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B10      ; 76         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B11      ; 75         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B13      ; 74         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C1       ; 9          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C2       ; 8          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C3       ;            ; 9        ; VCCIO9                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C4       ; 95         ; 9        ; ^nCE                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C5       ; 92         ; 9        ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; C6       ; 85         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C7       ;            ; 8        ; VCCIO8                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C8       ; 78         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C10      ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C11      ; 69         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C12      ; 70         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C13      ; 71         ; 7        ; S[8]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; D1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D3       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ; 94         ; 9        ; ^nCONFIG                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; D6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D7       ;            ; 8A       ; VCC_CLKIN8A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 65         ; 6        ; X[8]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; D11      ; 68         ; 6        ; Cout                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; D12      ; 67         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D13      ; 72         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E1       ; 11         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E2       ; 10         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 83         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E7       ; 84         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E10      ; 66         ; 6        ; S[9]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; E11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E13      ; 63         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; F1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F9       ; 64         ; 6        ; X[7]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F10      ; 62         ; 6        ; S[7]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F11      ; 61         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F12      ; 58         ; 6        ; X[2]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F13      ; 57         ; 6        ; X[1]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G1       ; 13         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G2       ; 12         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G3       ;            ; --       ; VCCH_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G6       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ; 60         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G10      ; 59         ; 6        ; EN                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G13      ; 55         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H10      ; 52         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H12      ; 51         ; 5        ; X[5]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H13      ; 56         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J1       ; 15         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J2       ; 14         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J3       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J4       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J5       ; 19         ; 3        ; ^CONF_DONE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 29         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J7       ; 30         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J13      ; 53         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 18         ; 3        ; ^MSEL0                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 20         ; 3        ; ^nSTATUS                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ;            ; 3A       ; VCC_CLKIN3A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K8       ; 35         ; 4        ; Y[6]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K9       ; 36         ; 4        ; S[1]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K10      ; 43         ; 4        ; Y[0]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K11      ; 48         ; 5        ; S[5]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K12      ; 47         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K13      ; 54         ; 5        ; Y[7]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ;            ;          ; RREF                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 16         ; 3        ; ^MSEL2                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 21         ; 3        ; Y[2]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L5       ; 27         ; 3        ; Y[5]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L6       ;            ; 3        ; VCCIO3                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L7       ; 28         ; 3        ; X[0]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L8       ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L9       ; 37         ; 4        ; S[3]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L10      ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L11      ; 44         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L12      ; 50         ; 5        ; X[3]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L13      ; 49         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M2       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; M3       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M4       ; 22         ; 3        ; S[4]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 25         ; 3        ; Y[3]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M7       ; 31         ; 4        ; Y[9]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M9       ; 38         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M10      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ; 41         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ; 46         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N2       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N3       ; 17         ; 3        ; ^MSEL1                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ; 23         ; 3        ; Y[4]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N5       ; 24         ; 3        ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN       ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N6       ; 26         ; 3        ; X[4]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N7       ; 32         ; 4        ; X[9]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N8       ; 33         ; 4        ; Y[1]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N9       ; 34         ; 4        ; S[2]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N10      ; 39         ; 4        ; S[0]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N11      ; 40         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N12      ; 42         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N13      ; 45         ; 5        ; X[6]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name              ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+--------------+
+; |ten_bit_adder             ; 23 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; 23 (10)      ; 0 (0)             ; 0 (0)            ; |ten_bit_adder                   ; work         ;
+;    |full_adder:inst10|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst10 ; work         ;
+;    |full_adder:inst11|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst11 ; work         ;
+;    |full_adder:inst13|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst13 ; work         ;
+;    |full_adder:inst15|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst15 ; work         ;
+;    |full_adder:inst17|     ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst17 ; work         ;
+;    |full_adder:inst9|      ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder|full_adder:inst9  ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                  ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Cout ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Y[9] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; X[9] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; Y[8] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y[7] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X[7] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Y[6] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y[5] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X[5] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Y[4] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y[2] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y[0] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X[0] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y[1] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X[1] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; X[2] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; Y[3] ; Input    ; --            ; (6) 1313 ps   ; --                    ; --  ; --   ;
+; X[3] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X[4] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X[6] ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; X[8] ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; EN   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                 ;
++----------------------------------+-------------------+---------+
+; Source Pin / Fanout              ; Pad To Core Index ; Setting ;
++----------------------------------+-------------------+---------+
+; Y[9]                             ;                   ;         ;
+; X[9]                             ;                   ;         ;
+; Y[8]                             ;                   ;         ;
+;      - full_adder:inst17|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst17|inst2~0 ; 0                 ; 6       ;
+;      - inst24                    ; 0                 ; 6       ;
+; Y[7]                             ;                   ;         ;
+;      - full_adder:inst15|inst3~1 ; 0                 ; 6       ;
+;      - inst23                    ; 0                 ; 6       ;
+; X[7]                             ;                   ;         ;
+;      - full_adder:inst15|inst3~1 ; 0                 ; 6       ;
+;      - inst23                    ; 0                 ; 6       ;
+; Y[6]                             ;                   ;         ;
+;      - full_adder:inst15|inst3~0 ; 0                 ; 6       ;
+;      - inst22                    ; 0                 ; 6       ;
+; Y[5]                             ;                   ;         ;
+;      - full_adder:inst13|inst3~1 ; 0                 ; 6       ;
+;      - inst21                    ; 0                 ; 6       ;
+; X[5]                             ;                   ;         ;
+;      - full_adder:inst13|inst3~1 ; 0                 ; 6       ;
+;      - inst21                    ; 0                 ; 6       ;
+; Y[4]                             ;                   ;         ;
+;      - full_adder:inst13|inst3~0 ; 0                 ; 6       ;
+;      - inst20                    ; 0                 ; 6       ;
+; Y[2]                             ;                   ;         ;
+;      - full_adder:inst10|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst10|inst3~1 ; 0                 ; 6       ;
+;      - inst18                    ; 0                 ; 6       ;
+; Y[0]                             ;                   ;         ;
+;      - full_adder:inst9|inst3~0  ; 0                 ; 6       ;
+;      - full_adder:inst9|inst2~0  ; 0                 ; 6       ;
+;      - inst6                     ; 0                 ; 6       ;
+; X[0]                             ;                   ;         ;
+;      - full_adder:inst9|inst3~0  ; 0                 ; 6       ;
+;      - full_adder:inst9|inst2~0  ; 0                 ; 6       ;
+;      - inst6                     ; 0                 ; 6       ;
+; Y[1]                             ;                   ;         ;
+;      - full_adder:inst9|inst3~0  ; 0                 ; 6       ;
+;      - full_adder:inst9|inst2~0  ; 0                 ; 6       ;
+; X[1]                             ;                   ;         ;
+; X[2]                             ;                   ;         ;
+; Y[3]                             ;                   ;         ;
+;      - full_adder:inst11|inst3~0 ; 1                 ; 6       ;
+;      - full_adder:inst11|inst2   ; 1                 ; 6       ;
+; X[3]                             ;                   ;         ;
+;      - full_adder:inst11|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst11|inst2   ; 0                 ; 6       ;
+; X[4]                             ;                   ;         ;
+;      - full_adder:inst13|inst3~0 ; 0                 ; 6       ;
+;      - inst20                    ; 0                 ; 6       ;
+; X[6]                             ;                   ;         ;
+;      - full_adder:inst15|inst3~0 ; 1                 ; 6       ;
+;      - inst22                    ; 1                 ; 6       ;
+; X[8]                             ;                   ;         ;
+;      - full_adder:inst17|inst3~0 ; 1                 ; 6       ;
+;      - full_adder:inst17|inst2~0 ; 1                 ; 6       ;
+;      - inst24                    ; 1                 ; 6       ;
+; EN                               ;                   ;         ;
+;      - inst25                    ; 0                 ; 6       ;
+;      - inst24                    ; 0                 ; 6       ;
+;      - inst23                    ; 0                 ; 6       ;
+;      - inst22                    ; 0                 ; 6       ;
+;      - inst21                    ; 0                 ; 6       ;
+;      - inst20                    ; 0                 ; 6       ;
+;      - inst19                    ; 0                 ; 6       ;
+;      - inst18                    ; 0                 ; 6       ;
+;      - inst7                     ; 0                 ; 6       ;
+;      - inst6                     ; 0                 ; 6       ;
++----------------------------------+-------------------+---------+
+
+
++-------------------------------------+
+; Non-Global High Fan-Out Signals     ;
++---------------------------+---------+
+; Name                      ; Fan-Out ;
++---------------------------+---------+
+; EN~input                  ; 10      ;
+; X[8]~input                ; 3       ;
+; X[0]~input                ; 3       ;
+; Y[0]~input                ; 3       ;
+; Y[2]~input                ; 3       ;
+; Y[8]~input                ; 3       ;
+; full_adder:inst15|inst3~1 ; 3       ;
+; full_adder:inst9|inst3~0  ; 3       ;
+; X[6]~input                ; 2       ;
+; X[4]~input                ; 2       ;
+; X[3]~input                ; 2       ;
+; Y[3]~input                ; 2       ;
+; X[2]~input                ; 2       ;
+; X[1]~input                ; 2       ;
+; Y[1]~input                ; 2       ;
+; Y[4]~input                ; 2       ;
+; X[5]~input                ; 2       ;
+; Y[5]~input                ; 2       ;
+; Y[6]~input                ; 2       ;
+; X[7]~input                ; 2       ;
+; Y[7]~input                ; 2       ;
+; X[9]~input                ; 2       ;
+; Y[9]~input                ; 2       ;
+; full_adder:inst15|inst3~0 ; 2       ;
+; full_adder:inst13|inst3~1 ; 2       ;
+; full_adder:inst13|inst3~0 ; 2       ;
+; full_adder:inst11|inst3~0 ; 2       ;
+; full_adder:inst10|inst3~1 ; 2       ;
+; full_adder:inst10|inst3~0 ; 2       ;
+; inst6                     ; 1       ;
+; inst7                     ; 1       ;
+; full_adder:inst9|inst2~0  ; 1       ;
+; inst18                    ; 1       ;
+; inst19                    ; 1       ;
+; full_adder:inst11|inst2   ; 1       ;
+; inst20                    ; 1       ;
+; inst21                    ; 1       ;
+; inst22                    ; 1       ;
+; inst23                    ; 1       ;
+; inst24                    ; 1       ;
+; inst25                    ; 1       ;
+; full_adder:inst17|inst2~0 ; 1       ;
+; full_adder:inst17|inst3~1 ; 1       ;
+; full_adder:inst17|inst3~0 ; 1       ;
++---------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Routing Usage Summary                                     ;
++-----------------------------------+-----------------------+
+; Routing Resource Type             ; Usage                 ;
++-----------------------------------+-----------------------+
+; Block interconnects               ; 35 / 42,960 ( < 1 % ) ;
+; C16 interconnects                 ; 23 / 1,518 ( 2 % )    ;
+; C4 interconnects                  ; 37 / 26,928 ( < 1 % ) ;
+; Direct links                      ; 0 / 42,960 ( 0 % )    ;
+; GXB block output buffers          ; 0 / 1,200 ( 0 % )     ;
+; Global clocks                     ; 0 / 20 ( 0 % )        ;
+; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % )         ;
+; Interquad TXRX Clocks             ; 0 / 8 ( 0 % )         ;
+; Interquad TXRX PCSRX outputs      ; 0 / 4 ( 0 % )         ;
+; Interquad TXRX PCSTX outputs      ; 0 / 4 ( 0 % )         ;
+; Local interconnects               ; 11 / 14,400 ( < 1 % ) ;
+; R24 interconnects                 ; 18 / 1,710 ( 1 % )    ;
+; R4 interconnects                  ; 27 / 37,740 ( < 1 % ) ;
++-----------------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 11.50) ; Number of LABs  (Total = 2) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 1                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 0                           ;
+; 16                                          ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 11.50) ; Number of LABs  (Total = 2) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 1                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 6.00) ; Number of LABs  (Total = 2) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 1                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 0                           ;
+; 8                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 11.50) ; Number of LABs  (Total = 2) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 32        ; 0            ; 0            ; 32        ; 32        ; 0            ; 11           ; 0            ; 0            ; 21           ; 0            ; 11           ; 21           ; 0            ; 0            ; 0            ; 11           ; 0            ; 0            ; 0            ; 0            ; 0            ; 32        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 32           ; 32           ; 32           ; 32           ; 32           ; 0         ; 32           ; 32           ; 0         ; 0         ; 32           ; 21           ; 32           ; 32           ; 11           ; 32           ; 21           ; 11           ; 32           ; 32           ; 32           ; 21           ; 32           ; 32           ; 32           ; 32           ; 32           ; 0         ; 32           ; 32           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Cout               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[9]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[8]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[7]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[6]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[5]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[4]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[3]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[2]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[1]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S[0]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[9]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[9]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[8]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[7]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[7]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[6]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[5]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[5]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[4]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[2]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[0]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[0]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[1]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[1]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[2]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y[3]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[3]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[4]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[6]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X[8]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; EN                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                         ;
++------------------------------------------------------------------+----------------------------+
+; Option                                                           ; Setting                    ;
++------------------------------------------------------------------+----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                        ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                        ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                        ;
+; Enable INIT_DONE output                                          ; Off                        ;
+; Configuration scheme                                             ; Active Serial              ;
+; Error detection CRC                                              ; Off                        ;
+; Enable input tri-state on active configuration pins in user mode ; Off                        ;
+; Active Serial clock source                                       ; 40 MHz Internal Oscillator ;
+; Configuration Voltage Level                                      ; Auto                       ;
+; Force Configuration Voltage Level                                ; Off                        ;
+; nCEO                                                             ; As output driving ground   ;
+; Data[0]                                                          ; As input tri-stated        ;
+; Data[1]/ASDO                                                     ; As input tri-stated        ;
+; Data[7..2]                                                       ; Unreserved                 ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated        ;
+; DCLK                                                             ; As output driving ground   ;
+; Base pin-out file on sameframe device                            ; Off                        ;
++------------------------------------------------------------------+----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119004): Automatically selected device EP4CGX15BF14C6 for design ten_bit_adder
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CGX30BF14C6 is compatible
+    Info (176445): Device EP4CGX22BF14C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5
+    Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5
+    Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 32 pins of 32 total pins
+    Info (169086): Pin Cout not assigned to an exact location on the device
+    Info (169086): Pin S[9] not assigned to an exact location on the device
+    Info (169086): Pin S[8] not assigned to an exact location on the device
+    Info (169086): Pin S[7] not assigned to an exact location on the device
+    Info (169086): Pin S[6] not assigned to an exact location on the device
+    Info (169086): Pin S[5] not assigned to an exact location on the device
+    Info (169086): Pin S[4] not assigned to an exact location on the device
+    Info (169086): Pin S[3] not assigned to an exact location on the device
+    Info (169086): Pin S[2] not assigned to an exact location on the device
+    Info (169086): Pin S[1] not assigned to an exact location on the device
+    Info (169086): Pin S[0] not assigned to an exact location on the device
+    Info (169086): Pin Y[9] not assigned to an exact location on the device
+    Info (169086): Pin X[9] not assigned to an exact location on the device
+    Info (169086): Pin Y[8] not assigned to an exact location on the device
+    Info (169086): Pin Y[7] not assigned to an exact location on the device
+    Info (169086): Pin X[7] not assigned to an exact location on the device
+    Info (169086): Pin Y[6] not assigned to an exact location on the device
+    Info (169086): Pin Y[5] not assigned to an exact location on the device
+    Info (169086): Pin X[5] not assigned to an exact location on the device
+    Info (169086): Pin Y[4] not assigned to an exact location on the device
+    Info (169086): Pin Y[2] not assigned to an exact location on the device
+    Info (169086): Pin Y[0] not assigned to an exact location on the device
+    Info (169086): Pin X[0] not assigned to an exact location on the device
+    Info (169086): Pin Y[1] not assigned to an exact location on the device
+    Info (169086): Pin X[1] not assigned to an exact location on the device
+    Info (169086): Pin X[2] not assigned to an exact location on the device
+    Info (169086): Pin Y[3] not assigned to an exact location on the device
+    Info (169086): Pin X[3] not assigned to an exact location on the device
+    Info (169086): Pin X[4] not assigned to an exact location on the device
+    Info (169086): Pin X[6] not assigned to an exact location on the device
+    Info (169086): Pin X[8] not assigned to an exact location on the device
+    Info (169086): Pin EN not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_bit_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 32 (unused VREF, 2.5V VCCIO, 21 input, 11 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available
+        Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available
+        Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 911 megabytes
+    Info: Processing ended: Thu Feb 18 22:20:08 2016
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:07
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder/output_files/ten_bit_adder.fit.smsg.
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.fit.smsg b/ten_bit_adder/output_files/ten_bit_adder.fit.smsg
new file mode 100644
index 0000000..ed080d6
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/ten_bit_adder/output_files/ten_bit_adder.fit.summary b/ten_bit_adder/output_files/ten_bit_adder.fit.summary
new file mode 100644
index 0000000..0f5a501
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Thu Feb 18 22:20:07 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_bit_adder
+Top-level Entity Name : ten_bit_adder
+Family : Cyclone IV GX
+Device : EP4CGX15BF14C6
+Timing Models : Final
+Total logic elements : 23 / 14,400 ( < 1 % )
+    Total combinational functions : 23 / 14,400 ( < 1 % )
+    Dedicated logic registers : 0 / 14,400 ( 0 % )
+Total registers : 0
+Total pins : 32 / 81 ( 40 % )
+Total virtual pins : 0
+Total memory bits : 0 / 552,960 ( 0 % )
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0 / 2 ( 0 % )
+Total GXB Receiver Channel PMA : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PCS : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PMA : 0 / 2 ( 0 % )
+Total PLLs : 0 / 3 ( 0 % )
diff --git a/ten_bit_adder/output_files/ten_bit_adder.flow.rpt b/ten_bit_adder/output_files/ten_bit_adder.flow.rpt
new file mode 100644
index 0000000..d2ac6b2
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for ten_bit_adder
+Thu Feb 18 22:20:18 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Thu Feb 18 22:20:18 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder                              ;
+; Top-level Entity Name              ; ten_bit_adder                              ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 23 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 23 / 14,400 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32 / 81 ( 40 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/18/2016 22:19:57 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ten_bit_adder       ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145583399704476 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 546 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:07     ; 1.0                     ; 911 MB              ; 00:00:07                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 510 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 532 MB              ; 00:00:02                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 481 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:12     ; --                      ; --                  ; 00:00:12                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder
+quartus_fit --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder
+quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder
+quartus_sta ten_bit_adder -c ten_bit_adder
+quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder
+
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.jdi b/ten_bit_adder/output_files/ten_bit_adder.jdi
new file mode 100644
index 0000000..49ea161
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="cbfcb79786f742bd3c92"/>
+  </project>
+  <file_info>
+    <file device="EP4CGX15BF14C6" path="ten_bit_adder.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/ten_bit_adder/output_files/ten_bit_adder.map.rpt b/ten_bit_adder/output_files/ten_bit_adder.map.rpt
new file mode 100644
index 0000000..ba3e384
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.map.rpt
@@ -0,0 +1,256 @@
+Analysis & Synthesis report for ten_bit_adder
+Thu Feb 18 22:19:58 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Thu Feb 18 22:19:58 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder                              ;
+; Top-level Entity Name              ; ten_bit_adder                              ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 23                                         ;
+;     Total combinational functions  ; 23                                         ;
+;     Dedicated logic registers      ; 0                                          ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0                                          ;
+; Total GXB Receiver Channel PMA     ; 0                                          ;
+; Total GXB Transmitter Channel PCS  ; 0                                          ;
+; Total GXB Transmitter Channel PMA  ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Top-level entity name                                                      ; ten_bit_adder      ; ten_bit_adder      ;
+; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                             ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                   ; Library ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+; ../adder/full_adder.bdf          ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf            ;         ;
+; ten_bit_adder.bdf                ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+---------+
+
+
++---------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++--------------------------+------------------+
+; Resource                 ; Usage            ;
++--------------------------+------------------+
+; I/O pins                 ; 32               ;
+; DSP block 9-bit elements ; 0                ;
+; Maximum fan-out node     ; EN~input         ;
+; Maximum fan-out          ; 10               ;
+; Total fan-out            ; 120              ;
+; Average fan-out          ; 1.38             ;
++--------------------------+------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                  ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------+--------------+
+; |ten_bit_adder             ; 23 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; |ten_bit_adder                   ; work         ;
+;    |full_adder:inst10|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst10 ; work         ;
+;    |full_adder:inst11|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst11 ; work         ;
+;    |full_adder:inst13|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst13 ; work         ;
+;    |full_adder:inst15|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst15 ; work         ;
+;    |full_adder:inst17|     ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst17 ; work         ;
+;    |full_adder:inst9|      ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder|full_adder:inst9  ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+----------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:19:57 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder -c ten_bit_adder
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file ten_bit_adder.bdf
+    Info (12023): Found entity 1: ten_bit_adder
+Info (12021): Found 1 design units, including 1 entities, in source file ten_bit_adder_no_bus.bdf
+    Info (12023): Found entity 1: ten_bit_adder_no_bus
+Info (12127): Elaborating entity "ten_bit_adder" for the top level hierarchy
+Info (12128): Elaborating entity "full_adder" for hierarchy "full_adder:inst17"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 55 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 21 input pins
+    Info (21059): Implemented 11 output pins
+    Info (21061): Implemented 23 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 557 megabytes
+    Info: Processing ended: Thu Feb 18 22:19:58 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.map.summary b/ten_bit_adder/output_files/ten_bit_adder.map.summary
new file mode 100644
index 0000000..f4bb441
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.map.summary
@@ -0,0 +1,18 @@
+Analysis & Synthesis Status : Successful - Thu Feb 18 22:19:58 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_bit_adder
+Top-level Entity Name : ten_bit_adder
+Family : Cyclone IV GX
+Total logic elements : 23
+    Total combinational functions : 23
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 32
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0
+Total GXB Receiver Channel PMA : 0
+Total GXB Transmitter Channel PCS : 0
+Total GXB Transmitter Channel PMA : 0
+Total PLLs : 0
diff --git a/ten_bit_adder/output_files/ten_bit_adder.pin b/ten_bit_adder/output_files/ten_bit_adder.pin
new file mode 100644
index 0000000..1ca03ba
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.pin
@@ -0,0 +1,246 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ --					Bank 9:	2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --           	    either individually through a 10k Ohm resistor to GND or tie all pins
+ --           	    together and connect through a single 10k Ohm resistor to GND.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_GND*      : Unused GXB Receiver or dedicated reference clock pin. This pin
+ --                 must be connected to GXB_GND through a 10k Ohm resistor.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "ten_bit_adder"  ASSIGNED TO AN: EP4CGX15BF14C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+TDO                          : A1        : output :                   :         : 9         :                
+TMS                          : A2        : input  :                   :         : 9         :                
+TDI                          : A3        : input  :                   :         : 9         :                
+~ALTERA_DCLK~                : A4        : output : 2.5 V             :         : 9         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : A5        : input  : 2.5 V             :         : 9         : N              
+S[6]                         : A6        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+GND+                         : A10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+GND                          : B1        : gnd    :                   :         :           :                
+GND                          : B2        : gnd    :                   :         :           :                
+TCK                          : B3        : input  :                   :         : 9         :                
+GND                          : B4        : gnd    :                   :         :           :                
+~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : B5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+GND                          : B7        : gnd    :                   :         :           :                
+Y[8]                         : B8        : input  : 2.5 V             :         : 7         : N              
+GND                          : B9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7         :                
+GND                          : B12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+GXB_NC                       : C1        :        :                   :         : QL0       :                
+GXB_NC                       : C2        :        :                   :         : QL0       :                
+VCCIO9                       : C3        : power  :                   : 2.5V    : 9         :                
+nCE                          : C4        :        :                   :         : 9         :                
+~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 7         :                
+VCCIO7                       : C9        : power  :                   : 2.5V    : 7         :                
+VCCIO7                       : C10       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 7         :                
+S[8]                         : C13       : output : 2.5 V             :         : 7         : N              
+GND                          : D1        : gnd    :                   :         :           :                
+GND                          : D2        : gnd    :                   :         :           :                
+VCCD_PLL                     : D3        : power  :                   : 1.2V    :           :                
+VCCA                         : D4        : power  :                   : 2.5V    :           :                
+nCONFIG                      : D5        :        :                   :         : 9         :                
+GND                          : D6        : gnd    :                   :         :           :                
+VCC_CLKIN8A                  : D7        : power  :                   : 2.5V    : 8A        :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCA                         : D9        : power  :                   : 2.5V    :           :                
+X[8]                         : D10       : input  : 2.5 V             :         : 6         : N              
+Cout                         : D11       : output : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+GXB_GND*                     : E1        :        :                   :         : QL0       :                
+GXB_GND*                     : E2        :        :                   :         : QL0       :                
+GND                          : E3        : gnd    :                   :         :           :                
+VCCINT                       : E4        : power  :                   : 1.2V    :           :                
+GND                          : E5        : gnd    :                   :         :           :                
+GXB_GND*                     : E6        :        :                   :         : 8A        :                
+GXB_GND*                     : E7        :        :                   :         : 8A        :                
+VCCINT                       : E8        : power  :                   : 1.2V    :           :                
+GND                          : E9        : gnd    :                   :         :           :                
+S[9]                         : E10       : output : 2.5 V             :         : 6         : N              
+VCCIO6                       : E11       : power  :                   : 2.5V    : 6         :                
+GND                          : E12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 6         :                
+GND                          : F1        : gnd    :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+VCCL_GXB                     : F3        : power  :                   : 1.2V    :           :                
+GND                          : F4        : gnd    :                   :         :           :                
+VCCINT                       : F5        : power  :                   : 1.2V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+GND                          : F8        : gnd    :                   :         :           :                
+X[7]                         : F9        : input  : 2.5 V             :         : 6         : N              
+S[7]                         : F10       : output : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 6         :                
+X[2]                         : F12       : input  : 2.5 V             :         : 6         : N              
+X[1]                         : F13       : input  : 2.5 V             :         : 6         : N              
+GXB_NC                       : G1        :        :                   :         : QL0       :                
+GXB_NC                       : G2        :        :                   :         : QL0       :                
+VCCH_GXB                     : G3        : power  :                   : 2.5V    :           :                
+VCCINT                       : G4        : power  :                   : 1.2V    :           :                
+GND                          : G5        : gnd    :                   :         :           :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+GND                          : G7        : gnd    :                   :         :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 6         :                
+EN                           : G10       : input  : 2.5 V             :         : 6         : N              
+VCCIO6                       : G11       : power  :                   : 2.5V    : 6         :                
+GND                          : G12       : gnd    :                   :         :           :                
+GND+                         : G13       :        :                   :         : 5         :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+VCCL_GXB                     : H3        : power  :                   : 1.2V    :           :                
+GND                          : H4        : gnd    :                   :         :           :                
+VCCINT                       : H5        : power  :                   : 1.2V    :           :                
+GND                          : H6        : gnd    :                   :         :           :                
+VCCINT                       : H7        : power  :                   : 1.2V    :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+VCCA                         : H9        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 5         :                
+VCCIO5                       : H11       : power  :                   : 2.5V    : 5         :                
+X[5]                         : H12       : input  : 2.5 V             :         : 5         : N              
+GND+                         : H13       :        :                   :         : 5         :                
+GXB_GND*                     : J1        :        :                   :         : QL0       :                
+GXB_GND*                     : J2        :        :                   :         : QL0       :                
+VCCA_GXB                     : J3        : power  :                   : 2.5V    :           :                
+VCCD_PLL                     : J4        : power  :                   : 1.2V    :           :                
+CONF_DONE                    : J5        :        :                   :         : 3         :                
+GXB_GND*                     : J6        :        :                   :         : 3A        :                
+GXB_GND*                     : J7        :        :                   :         : 3A        :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCD_PLL                     : J10       : power  :                   : 1.2V    :           :                
+VCCIO5                       : J11       : power  :                   : 2.5V    : 5         :                
+GND                          : J12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 5         :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+GND                          : K3        : gnd    :                   :         :           :                
+VCCA                         : K4        : power  :                   : 2.5V    :           :                
+MSEL0                        : K5        :        :                   :         : 3         :                
+nSTATUS                      : K6        :        :                   :         : 3         :                
+VCC_CLKIN3A                  : K7        : power  :                   : 2.5V    : 3A        :                
+Y[6]                         : K8        : input  : 2.5 V             :         : 4         : N              
+S[1]                         : K9        : output : 2.5 V             :         : 4         : N              
+Y[0]                         : K10       : input  : 2.5 V             :         : 4         : N              
+S[5]                         : K11       : output : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 5         :                
+Y[7]                         : K13       : input  : 2.5 V             :         : 5         : N              
+RREF                         : L1        :        :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+MSEL2                        : L3        :        :                   :         : 3         :                
+Y[2]                         : L4        : input  : 2.5 V             :         : 3         : N              
+Y[5]                         : L5        : input  : 2.5 V             :         : 3         : N              
+VCCIO3                       : L6        : power  :                   : 2.5V    : 3         :                
+X[0]                         : L7        : input  : 2.5 V             :         : 3         : N              
+VCCIO4                       : L8        : power  :                   : 2.5V    : 4         :                
+S[3]                         : L9        : output : 2.5 V             :         : 4         : N              
+VCCIO4                       : L10       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L11       :        :                   :         : 4         :                
+X[3]                         : L12       : input  : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L13       :        :                   :         : 5         :                
+GND                          : M1        : gnd    :                   :         :           :                
+VCCA_GXB                     : M2        : power  :                   : 2.5V    :           :                
+NC                           : M3        :        :                   :         :           :                
+S[4]                         : M4        : output : 2.5 V             :         : 3         : N              
+GND                          : M5        : gnd    :                   :         :           :                
+Y[3]                         : M6        : input  : 2.5 V             :         : 3         : N              
+Y[9]                         : M7        : input  : 2.5 V             :         : 4         : N              
+GND                          : M8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 4         :                
+GND                          : M10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M11       :        :                   :         : 4         :                
+GND                          : M12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M13       :        :                   :         : 5         :                
+VCCL_GXB                     : N1        : power  :                   : 1.2V    :           :                
+NC                           : N2        :        :                   :         :           :                
+MSEL1                        : N3        :        :                   :         : 3         :                
+Y[4]                         : N4        : input  : 2.5 V             :         : 3         : N              
+~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : N5        : output : 2.5 V             :         : 3         : N              
+X[4]                         : N6        : input  : 2.5 V             :         : 3         : N              
+X[9]                         : N7        : input  : 2.5 V             :         : 4         : N              
+Y[1]                         : N8        : input  : 2.5 V             :         : 4         : N              
+S[2]                         : N9        : output : 2.5 V             :         : 4         : N              
+S[0]                         : N10       : output : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N12       :        :                   :         : 4         :                
+X[6]                         : N13       : input  : 2.5 V             :         : 5         : N              
diff --git a/ten_bit_adder/output_files/ten_bit_adder.sof b/ten_bit_adder/output_files/ten_bit_adder.sof
new file mode 100644
index 0000000..e891f98
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.sof
diff --git a/ten_bit_adder/output_files/ten_bit_adder.sta.rpt b/ten_bit_adder/output_files/ten_bit_adder.sta.rpt
new file mode 100644
index 0000000..9afeddc
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.sta.rpt
@@ -0,0 +1,1631 @@
+TimeQuest Timing Analyzer report for ten_bit_adder
+Thu Feb 18 22:20:15 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Propagation Delay
+ 34. Minimum Propagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 38. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 39. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 40. Clock Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths
+ 44. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; ten_bit_adder                                      ;
+; Device Family      ; Cyclone IV GX                                      ;
+; Device Name        ; EP4CGX15BF14C6                                     ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; EN         ; S[0]        ; 8.330  ;        ;        ; 8.707  ;
+; EN         ; S[1]        ; 8.376  ;        ;        ; 8.772  ;
+; EN         ; S[2]        ; 8.046  ;        ;        ; 8.418  ;
+; EN         ; S[3]        ; 8.524  ;        ;        ; 8.924  ;
+; EN         ; S[4]        ; 8.542  ;        ;        ; 8.959  ;
+; EN         ; S[5]        ; 8.247  ;        ;        ; 8.673  ;
+; EN         ; S[6]        ; 9.200  ;        ;        ; 9.649  ;
+; EN         ; S[7]        ; 8.619  ;        ;        ; 9.032  ;
+; EN         ; S[8]        ; 8.018  ;        ;        ; 8.364  ;
+; EN         ; S[9]        ; 8.157  ;        ;        ; 8.535  ;
+; X[0]       ; Cout        ; 13.242 ;        ;        ; 14.031 ;
+; X[0]       ; S[0]        ; 8.346  ; 8.263  ; 8.860  ; 8.727  ;
+; X[0]       ; S[1]        ; 8.521  ; 8.440  ; 9.029  ; 8.870  ;
+; X[0]       ; S[2]        ; 8.612  ; 8.517  ; 9.179  ; 9.032  ;
+; X[0]       ; S[3]        ; 9.549  ; 9.467  ; 10.120 ; 9.981  ;
+; X[0]       ; S[4]        ; 9.891  ; 9.811  ; 10.472 ; 10.423 ;
+; X[0]       ; S[5]        ; 10.110 ; 10.069 ; 10.778 ; 10.685 ;
+; X[0]       ; S[6]        ; 11.628 ; 11.607 ; 12.323 ; 12.267 ;
+; X[0]       ; S[7]        ; 12.380 ; 12.282 ; 13.114 ; 13.048 ;
+; X[0]       ; S[8]        ; 12.546 ; 12.469 ; 13.369 ; 13.240 ;
+; X[0]       ; S[9]        ; 13.037 ; 12.949 ; 13.813 ; 13.734 ;
+; X[1]       ; Cout        ; 10.881 ;        ;        ; 11.302 ;
+; X[1]       ; S[1]        ; 6.149  ; 6.027  ; 6.296  ; 6.165  ;
+; X[1]       ; S[2]        ; 6.251  ; 6.156  ; 6.450  ; 6.303  ;
+; X[1]       ; S[3]        ; 7.188  ; 7.106  ; 7.391  ; 7.252  ;
+; X[1]       ; S[4]        ; 7.530  ; 7.450  ; 7.743  ; 7.694  ;
+; X[1]       ; S[5]        ; 7.749  ; 7.708  ; 8.049  ; 7.956  ;
+; X[1]       ; S[6]        ; 9.267  ; 9.246  ; 9.594  ; 9.538  ;
+; X[1]       ; S[7]        ; 10.019 ; 9.921  ; 10.385 ; 10.319 ;
+; X[1]       ; S[8]        ; 10.185 ; 10.108 ; 10.640 ; 10.511 ;
+; X[1]       ; S[9]        ; 10.676 ; 10.588 ; 11.084 ; 11.005 ;
+; X[2]       ; Cout        ; 10.906 ;        ;        ; 11.330 ;
+; X[2]       ; S[2]        ; 6.036  ; 5.937  ; 6.174  ; 6.040  ;
+; X[2]       ; S[3]        ; 7.213  ; 7.131  ; 7.419  ; 7.280  ;
+; X[2]       ; S[4]        ; 7.555  ; 7.475  ; 7.771  ; 7.722  ;
+; X[2]       ; S[5]        ; 7.774  ; 7.733  ; 8.077  ; 7.984  ;
+; X[2]       ; S[6]        ; 9.292  ; 9.271  ; 9.622  ; 9.566  ;
+; X[2]       ; S[7]        ; 10.044 ; 9.946  ; 10.413 ; 10.347 ;
+; X[2]       ; S[8]        ; 10.210 ; 10.133 ; 10.668 ; 10.539 ;
+; X[2]       ; S[9]        ; 10.701 ; 10.613 ; 11.112 ; 11.033 ;
+; X[3]       ; Cout        ; 12.288 ;        ;        ; 12.987 ;
+; X[3]       ; S[3]        ; 8.597  ; 8.512  ; 9.069  ; 8.940  ;
+; X[3]       ; S[4]        ; 8.937  ; 8.857  ; 9.428  ; 9.379  ;
+; X[3]       ; S[5]        ; 9.156  ; 9.115  ; 9.734  ; 9.641  ;
+; X[3]       ; S[6]        ; 10.674 ; 10.653 ; 11.279 ; 11.223 ;
+; X[3]       ; S[7]        ; 11.426 ; 11.328 ; 12.070 ; 12.004 ;
+; X[3]       ; S[8]        ; 11.592 ; 11.515 ; 12.325 ; 12.196 ;
+; X[3]       ; S[9]        ; 12.083 ; 11.995 ; 12.769 ; 12.690 ;
+; X[4]       ; Cout        ; 11.878 ;        ;        ; 12.538 ;
+; X[4]       ; S[4]        ; 8.490  ; 8.437  ; 8.958  ; 8.870  ;
+; X[4]       ; S[5]        ; 8.746  ; 8.705  ; 9.285  ; 9.192  ;
+; X[4]       ; S[6]        ; 10.264 ; 10.243 ; 10.830 ; 10.774 ;
+; X[4]       ; S[7]        ; 11.016 ; 10.918 ; 11.621 ; 11.555 ;
+; X[4]       ; S[8]        ; 11.182 ; 11.105 ; 11.876 ; 11.747 ;
+; X[4]       ; S[9]        ; 11.673 ; 11.585 ; 12.320 ; 12.241 ;
+; X[5]       ; Cout        ; 11.259 ;        ;        ; 11.854 ;
+; X[5]       ; S[5]        ; 8.371  ; 8.326  ; 8.863  ; 8.783  ;
+; X[5]       ; S[6]        ; 9.645  ; 9.624  ; 10.146 ; 10.090 ;
+; X[5]       ; S[7]        ; 10.397 ; 10.299 ; 10.937 ; 10.871 ;
+; X[5]       ; S[8]        ; 10.563 ; 10.486 ; 11.192 ; 11.063 ;
+; X[5]       ; S[9]        ; 11.054 ; 10.966 ; 11.636 ; 11.557 ;
+; X[6]       ; Cout        ; 10.580 ;        ;        ; 11.148 ;
+; X[6]       ; S[6]        ; 9.093  ; 9.076  ; 9.587  ; 9.518  ;
+; X[6]       ; S[7]        ; 9.718  ; 9.620  ; 10.231 ; 10.165 ;
+; X[6]       ; S[8]        ; 9.884  ; 9.807  ; 10.486 ; 10.357 ;
+; X[6]       ; S[9]        ; 10.375 ; 10.287 ; 10.930 ; 10.851 ;
+; X[7]       ; Cout        ; 8.952  ;        ;        ; 9.422  ;
+; X[7]       ; S[7]        ; 8.088  ; 7.992  ; 8.540  ; 8.435  ;
+; X[7]       ; S[8]        ; 8.256  ; 8.179  ; 8.760  ; 8.631  ;
+; X[7]       ; S[9]        ; 8.747  ; 8.659  ; 9.204  ; 9.125  ;
+; X[8]       ; Cout        ; 8.538  ;        ;        ; 8.987  ;
+; X[8]       ; S[8]        ; 7.883  ; 7.775  ; 8.341  ; 8.264  ;
+; X[8]       ; S[9]        ; 8.579  ; 8.493  ; 9.068  ; 8.963  ;
+; X[9]       ; Cout        ; 5.998  ;        ;        ; 6.013  ;
+; X[9]       ; S[9]        ; 6.761  ; 6.656  ; 6.858  ; 6.756  ;
+; Y[0]       ; Cout        ; 13.236 ;        ;        ; 14.047 ;
+; Y[0]       ; S[0]        ; 8.360  ; 8.239  ; 8.859  ; 8.769  ;
+; Y[0]       ; S[1]        ; 8.500  ; 8.376  ; 8.998  ; 8.906  ;
+; Y[0]       ; S[2]        ; 8.606  ; 8.511  ; 9.195  ; 9.048  ;
+; Y[0]       ; S[3]        ; 9.543  ; 9.461  ; 10.136 ; 9.997  ;
+; Y[0]       ; S[4]        ; 9.885  ; 9.805  ; 10.488 ; 10.439 ;
+; Y[0]       ; S[5]        ; 10.104 ; 10.063 ; 10.794 ; 10.701 ;
+; Y[0]       ; S[6]        ; 11.622 ; 11.601 ; 12.339 ; 12.283 ;
+; Y[0]       ; S[7]        ; 12.374 ; 12.276 ; 13.130 ; 13.064 ;
+; Y[0]       ; S[8]        ; 12.540 ; 12.463 ; 13.385 ; 13.256 ;
+; Y[0]       ; S[9]        ; 13.031 ; 12.943 ; 13.829 ; 13.750 ;
+; Y[1]       ; Cout        ; 12.940 ;        ;        ; 13.716 ;
+; Y[1]       ; S[1]        ; 8.233  ; 8.135  ; 8.697  ; 8.596  ;
+; Y[1]       ; S[2]        ; 8.310  ; 8.215  ; 8.864  ; 8.717  ;
+; Y[1]       ; S[3]        ; 9.247  ; 9.165  ; 9.805  ; 9.666  ;
+; Y[1]       ; S[4]        ; 9.589  ; 9.509  ; 10.157 ; 10.108 ;
+; Y[1]       ; S[5]        ; 9.808  ; 9.767  ; 10.463 ; 10.370 ;
+; Y[1]       ; S[6]        ; 11.326 ; 11.305 ; 12.008 ; 11.952 ;
+; Y[1]       ; S[7]        ; 12.078 ; 11.980 ; 12.799 ; 12.733 ;
+; Y[1]       ; S[8]        ; 12.244 ; 12.167 ; 13.054 ; 12.925 ;
+; Y[1]       ; S[9]        ; 12.735 ; 12.647 ; 13.498 ; 13.419 ;
+; Y[2]       ; Cout        ; 13.046 ;        ;        ; 13.867 ;
+; Y[2]       ; S[2]        ; 8.079  ; 7.953  ; 8.571  ; 8.476  ;
+; Y[2]       ; S[3]        ; 9.353  ; 9.271  ; 9.956  ; 9.817  ;
+; Y[2]       ; S[4]        ; 9.695  ; 9.615  ; 10.308 ; 10.259 ;
+; Y[2]       ; S[5]        ; 9.914  ; 9.873  ; 10.614 ; 10.521 ;
+; Y[2]       ; S[6]        ; 11.432 ; 11.411 ; 12.159 ; 12.103 ;
+; Y[2]       ; S[7]        ; 12.184 ; 12.086 ; 12.950 ; 12.884 ;
+; Y[2]       ; S[8]        ; 12.350 ; 12.273 ; 13.205 ; 13.076 ;
+; Y[2]       ; S[9]        ; 12.841 ; 12.753 ; 13.649 ; 13.570 ;
+; Y[3]       ; Cout        ; 12.282 ;        ;        ; 13.006 ;
+; Y[3]       ; S[3]        ; 8.578  ; 8.459  ; 9.064  ; 8.977  ;
+; Y[3]       ; S[4]        ; 8.931  ; 8.851  ; 9.447  ; 9.398  ;
+; Y[3]       ; S[5]        ; 9.150  ; 9.109  ; 9.753  ; 9.660  ;
+; Y[3]       ; S[6]        ; 10.668 ; 10.647 ; 11.298 ; 11.242 ;
+; Y[3]       ; S[7]        ; 11.420 ; 11.322 ; 12.089 ; 12.023 ;
+; Y[3]       ; S[8]        ; 11.586 ; 11.509 ; 12.344 ; 12.215 ;
+; Y[3]       ; S[9]        ; 12.077 ; 11.989 ; 12.788 ; 12.709 ;
+; Y[4]       ; Cout        ; 12.015 ;        ;        ; 12.729 ;
+; Y[4]       ; S[4]        ; 8.625  ; 8.576  ; 9.158  ; 9.057  ;
+; Y[4]       ; S[5]        ; 8.883  ; 8.842  ; 9.476  ; 9.383  ;
+; Y[4]       ; S[6]        ; 10.401 ; 10.380 ; 11.021 ; 10.965 ;
+; Y[4]       ; S[7]        ; 11.153 ; 11.055 ; 11.812 ; 11.746 ;
+; Y[4]       ; S[8]        ; 11.319 ; 11.242 ; 12.067 ; 11.938 ;
+; Y[4]       ; S[9]        ; 11.810 ; 11.722 ; 12.511 ; 12.432 ;
+; Y[5]       ; Cout        ; 11.229 ;        ;        ; 11.852 ;
+; Y[5]       ; S[5]        ; 8.132  ; 8.060  ; 8.584  ; 8.543  ;
+; Y[5]       ; S[6]        ; 9.615  ; 9.594  ; 10.144 ; 10.088 ;
+; Y[5]       ; S[7]        ; 10.367 ; 10.269 ; 10.935 ; 10.869 ;
+; Y[5]       ; S[8]        ; 10.533 ; 10.456 ; 11.190 ; 11.061 ;
+; Y[5]       ; S[9]        ; 11.024 ; 10.936 ; 11.634 ; 11.555 ;
+; Y[6]       ; Cout        ; 10.487 ;        ;        ; 11.035 ;
+; Y[6]       ; S[6]        ; 9.057  ; 9.009  ; 9.487  ; 9.470  ;
+; Y[6]       ; S[7]        ; 9.625  ; 9.527  ; 10.118 ; 10.052 ;
+; Y[6]       ; S[8]        ; 9.791  ; 9.714  ; 10.373 ; 10.244 ;
+; Y[6]       ; S[9]        ; 10.282 ; 10.194 ; 10.817 ; 10.738 ;
+; Y[7]       ; Cout        ; 9.414  ;        ;        ; 9.931  ;
+; Y[7]       ; S[7]        ; 8.552  ; 8.495  ; 9.053  ; 8.971  ;
+; Y[7]       ; S[8]        ; 8.718  ; 8.641  ; 9.269  ; 9.140  ;
+; Y[7]       ; S[9]        ; 9.209  ; 9.121  ; 9.713  ; 9.634  ;
+; Y[8]       ; Cout        ; 8.434  ;        ;        ; 8.866  ;
+; Y[8]       ; S[8]        ; 7.744  ; 7.663  ; 8.201  ; 8.085  ;
+; Y[8]       ; S[9]        ; 8.516  ; 8.411  ; 8.901  ; 8.840  ;
+; Y[9]       ; Cout        ; 6.153  ;        ;        ; 6.185  ;
+; Y[9]       ; S[9]        ; 6.151  ; 6.111  ; 6.276  ; 6.159  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++--------------------------------------------------------------+
+; Minimum Propagation Delay                                    ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; EN         ; S[0]        ; 8.052  ;        ;        ; 8.413  ;
+; EN         ; S[1]        ; 8.079  ;        ;        ; 8.442  ;
+; EN         ; S[2]        ; 7.778  ;        ;        ; 8.134  ;
+; EN         ; S[3]        ; 8.224  ;        ;        ; 8.590  ;
+; EN         ; S[4]        ; 8.251  ;        ;        ; 8.651  ;
+; EN         ; S[5]        ; 7.970  ;        ;        ; 8.378  ;
+; EN         ; S[6]        ; 8.883  ;        ;        ; 9.313  ;
+; EN         ; S[7]        ; 8.276  ;        ;        ; 8.646  ;
+; EN         ; S[8]        ; 7.753  ;        ;        ; 8.083  ;
+; EN         ; S[9]        ; 7.883  ;        ;        ; 8.246  ;
+; X[0]       ; Cout        ; 12.293 ;        ;        ; 12.887 ;
+; X[0]       ; S[0]        ; 8.051  ; 7.955  ; 8.532  ; 8.406  ;
+; X[0]       ; S[1]        ; 8.181  ; 8.081  ; 8.660  ; 8.550  ;
+; X[0]       ; S[2]        ; 8.282  ; 8.180  ; 8.774  ; 8.644  ;
+; X[0]       ; S[3]        ; 8.945  ; 8.826  ; 9.430  ; 9.302  ;
+; X[0]       ; S[4]        ; 9.279  ; 9.199  ; 9.755  ; 9.704  ;
+; X[0]       ; S[5]        ; 9.480  ; 9.429  ; 10.016 ; 9.937  ;
+; X[0]       ; S[6]        ; 10.883 ; 10.853 ; 11.455 ; 11.399 ;
+; X[0]       ; S[7]        ; 11.567 ; 11.469 ; 12.178 ; 12.111 ;
+; X[0]       ; S[8]        ; 11.720 ; 11.634 ; 12.393 ; 12.279 ;
+; X[0]       ; S[9]        ; 12.154 ; 12.090 ; 12.813 ; 12.740 ;
+; X[1]       ; Cout        ; 10.060 ;        ;        ; 10.335 ;
+; X[1]       ; S[1]        ; 5.959  ; 5.836  ; 6.106  ; 5.974  ;
+; X[1]       ; S[2]        ; 6.049  ; 5.947  ; 6.222  ; 6.092  ;
+; X[1]       ; S[3]        ; 6.712  ; 6.593  ; 6.878  ; 6.750  ;
+; X[1]       ; S[4]        ; 7.046  ; 6.966  ; 7.203  ; 7.152  ;
+; X[1]       ; S[5]        ; 7.247  ; 7.196  ; 7.464  ; 7.385  ;
+; X[1]       ; S[6]        ; 8.650  ; 8.620  ; 8.903  ; 8.847  ;
+; X[1]       ; S[7]        ; 9.334  ; 9.236  ; 9.626  ; 9.559  ;
+; X[1]       ; S[8]        ; 9.487  ; 9.401  ; 9.841  ; 9.727  ;
+; X[1]       ; S[9]        ; 9.921  ; 9.857  ; 10.261 ; 10.188 ;
+; X[2]       ; Cout        ; 10.268 ;        ;        ; 10.519 ;
+; X[2]       ; S[2]        ; 5.838  ; 5.734  ; 5.969  ; 5.839  ;
+; X[2]       ; S[3]        ; 6.910  ; 6.817  ; 7.061  ; 6.957  ;
+; X[2]       ; S[4]        ; 7.254  ; 7.174  ; 7.387  ; 7.336  ;
+; X[2]       ; S[5]        ; 7.455  ; 7.404  ; 7.648  ; 7.569  ;
+; X[2]       ; S[6]        ; 8.858  ; 8.828  ; 9.087  ; 9.031  ;
+; X[2]       ; S[7]        ; 9.542  ; 9.444  ; 9.810  ; 9.743  ;
+; X[2]       ; S[8]        ; 9.695  ; 9.609  ; 10.025 ; 9.911  ;
+; X[2]       ; S[9]        ; 10.129 ; 10.065 ; 10.445 ; 10.372 ;
+; X[3]       ; Cout        ; 11.593 ;        ;        ; 12.161 ;
+; X[3]       ; S[3]        ; 8.246  ; 8.154  ; 8.699  ; 8.570  ;
+; X[3]       ; S[4]        ; 8.579  ; 8.499  ; 9.029  ; 8.978  ;
+; X[3]       ; S[5]        ; 8.780  ; 8.729  ; 9.290  ; 9.211  ;
+; X[3]       ; S[6]        ; 10.183 ; 10.153 ; 10.729 ; 10.673 ;
+; X[3]       ; S[7]        ; 10.867 ; 10.769 ; 11.452 ; 11.385 ;
+; X[3]       ; S[8]        ; 11.020 ; 10.934 ; 11.667 ; 11.553 ;
+; X[3]       ; S[9]        ; 11.454 ; 11.390 ; 12.087 ; 12.014 ;
+; X[4]       ; Cout        ; 11.196 ;        ;        ; 11.723 ;
+; X[4]       ; S[4]        ; 8.183  ; 8.123  ; 8.631  ; 8.545  ;
+; X[4]       ; S[5]        ; 8.383  ; 8.332  ; 8.852  ; 8.773  ;
+; X[4]       ; S[6]        ; 9.786  ; 9.756  ; 10.291 ; 10.235 ;
+; X[4]       ; S[7]        ; 10.470 ; 10.372 ; 11.014 ; 10.947 ;
+; X[4]       ; S[8]        ; 10.623 ; 10.537 ; 11.229 ; 11.115 ;
+; X[4]       ; S[9]        ; 11.057 ; 10.993 ; 11.649 ; 11.576 ;
+; X[5]       ; Cout        ; 10.706 ;        ;        ; 11.205 ;
+; X[5]       ; S[5]        ; 8.074  ; 8.021  ; 8.543  ; 8.464  ;
+; X[5]       ; S[6]        ; 9.296  ; 9.266  ; 9.773  ; 9.717  ;
+; X[5]       ; S[7]        ; 9.980  ; 9.882  ; 10.496 ; 10.429 ;
+; X[5]       ; S[8]        ; 10.133 ; 10.047 ; 10.711 ; 10.597 ;
+; X[5]       ; S[9]        ; 10.567 ; 10.503 ; 11.131 ; 11.058 ;
+; X[6]       ; Cout        ; 10.104 ;        ;        ; 10.585 ;
+; X[6]       ; S[6]        ; 8.771  ; 8.743  ; 9.226  ; 9.170  ;
+; X[6]       ; S[7]        ; 9.378  ; 9.280  ; 9.876  ; 9.809  ;
+; X[6]       ; S[8]        ; 9.531  ; 9.445  ; 10.091 ; 9.977  ;
+; X[6]       ; S[9]        ; 9.965  ; 9.901  ; 10.511 ; 10.438 ;
+; X[7]       ; Cout        ; 8.545  ;        ;        ; 8.930  ;
+; X[7]       ; S[7]        ; 7.817  ; 7.721  ; 8.255  ; 8.150  ;
+; X[7]       ; S[8]        ; 7.972  ; 7.886  ; 8.436  ; 8.322  ;
+; X[7]       ; S[9]        ; 8.406  ; 8.342  ; 8.856  ; 8.783  ;
+; X[8]       ; Cout        ; 8.196  ;        ;        ; 8.598  ;
+; X[8]       ; S[8]        ; 7.623  ; 7.515  ; 8.067  ; 7.988  ;
+; X[8]       ; S[9]        ; 8.244  ; 8.178  ; 8.687  ; 8.637  ;
+; X[9]       ; Cout        ; 5.811  ;        ;        ; 5.831  ;
+; X[9]       ; S[9]        ; 6.425  ; 6.375  ; 6.527  ; 6.458  ;
+; Y[0]       ; Cout        ; 12.309 ;        ;        ; 12.961 ;
+; Y[0]       ; S[0]        ; 8.076  ; 7.956  ; 8.562  ; 8.471  ;
+; Y[0]       ; S[1]        ; 8.205  ; 8.080  ; 8.691  ; 8.597  ;
+; Y[0]       ; S[2]        ; 8.298  ; 8.196  ; 8.848  ; 8.718  ;
+; Y[0]       ; S[3]        ; 8.961  ; 8.842  ; 9.504  ; 9.376  ;
+; Y[0]       ; S[4]        ; 9.295  ; 9.215  ; 9.829  ; 9.778  ;
+; Y[0]       ; S[5]        ; 9.496  ; 9.445  ; 10.090 ; 10.011 ;
+; Y[0]       ; S[6]        ; 10.899 ; 10.869 ; 11.529 ; 11.473 ;
+; Y[0]       ; S[7]        ; 11.583 ; 11.485 ; 12.252 ; 12.185 ;
+; Y[0]       ; S[8]        ; 11.736 ; 11.650 ; 12.467 ; 12.353 ;
+; Y[0]       ; S[9]        ; 12.170 ; 12.106 ; 12.887 ; 12.814 ;
+; Y[1]       ; Cout        ; 11.990 ;        ;        ; 12.580 ;
+; Y[1]       ; S[1]        ; 7.888  ; 7.786  ; 8.351  ; 8.243  ;
+; Y[1]       ; S[2]        ; 7.979  ; 7.877  ; 8.467  ; 8.337  ;
+; Y[1]       ; S[3]        ; 8.642  ; 8.523  ; 9.123  ; 8.995  ;
+; Y[1]       ; S[4]        ; 8.976  ; 8.896  ; 9.448  ; 9.397  ;
+; Y[1]       ; S[5]        ; 9.177  ; 9.126  ; 9.709  ; 9.630  ;
+; Y[1]       ; S[6]        ; 10.580 ; 10.550 ; 11.148 ; 11.092 ;
+; Y[1]       ; S[7]        ; 11.264 ; 11.166 ; 11.871 ; 11.804 ;
+; Y[1]       ; S[8]        ; 11.417 ; 11.331 ; 12.086 ; 11.972 ;
+; Y[1]       ; S[9]        ; 11.851 ; 11.787 ; 12.506 ; 12.433 ;
+; Y[2]       ; Cout        ; 12.001 ;        ;        ; 12.635 ;
+; Y[2]       ; S[2]        ; 7.804  ; 7.680  ; 8.284  ; 8.189  ;
+; Y[2]       ; S[3]        ; 8.653  ; 8.534  ; 9.178  ; 9.050  ;
+; Y[2]       ; S[4]        ; 8.987  ; 8.907  ; 9.503  ; 9.452  ;
+; Y[2]       ; S[5]        ; 9.188  ; 9.137  ; 9.764  ; 9.685  ;
+; Y[2]       ; S[6]        ; 10.591 ; 10.561 ; 11.203 ; 11.147 ;
+; Y[2]       ; S[7]        ; 11.275 ; 11.177 ; 11.926 ; 11.859 ;
+; Y[2]       ; S[8]        ; 11.428 ; 11.342 ; 12.141 ; 12.027 ;
+; Y[2]       ; S[9]        ; 11.862 ; 11.798 ; 12.561 ; 12.488 ;
+; Y[3]       ; Cout        ; 11.631 ;        ;        ; 12.252 ;
+; Y[3]       ; S[3]        ; 8.283  ; 8.162  ; 8.757  ; 8.667  ;
+; Y[3]       ; S[4]        ; 8.617  ; 8.537  ; 9.120  ; 9.069  ;
+; Y[3]       ; S[5]        ; 8.818  ; 8.767  ; 9.381  ; 9.302  ;
+; Y[3]       ; S[6]        ; 10.221 ; 10.191 ; 10.820 ; 10.764 ;
+; Y[3]       ; S[7]        ; 10.905 ; 10.807 ; 11.543 ; 11.476 ;
+; Y[3]       ; S[8]        ; 11.058 ; 10.972 ; 11.758 ; 11.644 ;
+; Y[3]       ; S[9]        ; 11.492 ; 11.428 ; 12.178 ; 12.105 ;
+; Y[4]       ; Cout        ; 11.329 ;        ;        ; 11.905 ;
+; Y[4]       ; S[4]        ; 8.317  ; 8.259  ; 8.812  ; 8.726  ;
+; Y[4]       ; S[5]        ; 8.516  ; 8.465  ; 9.034  ; 8.955  ;
+; Y[4]       ; S[6]        ; 9.919  ; 9.889  ; 10.473 ; 10.417 ;
+; Y[4]       ; S[7]        ; 10.603 ; 10.505 ; 11.196 ; 11.129 ;
+; Y[4]       ; S[8]        ; 10.756 ; 10.670 ; 11.411 ; 11.297 ;
+; Y[4]       ; S[9]        ; 11.190 ; 11.126 ; 11.831 ; 11.758 ;
+; Y[5]       ; Cout        ; 10.671 ;        ;        ; 11.201 ;
+; Y[5]       ; S[5]        ; 7.855  ; 7.782  ; 8.296  ; 8.252  ;
+; Y[5]       ; S[6]        ; 9.261  ; 9.231  ; 9.769  ; 9.713  ;
+; Y[5]       ; S[7]        ; 9.945  ; 9.847  ; 10.492 ; 10.425 ;
+; Y[5]       ; S[8]        ; 10.098 ; 10.012 ; 10.707 ; 10.593 ;
+; Y[5]       ; S[9]        ; 10.532 ; 10.468 ; 11.127 ; 11.054 ;
+; Y[6]       ; Cout        ; 10.011 ;        ;        ; 10.475 ;
+; Y[6]       ; S[6]        ; 8.741  ; 8.691  ; 9.161  ; 9.140  ;
+; Y[6]       ; S[7]        ; 9.285  ; 9.187  ; 9.766  ; 9.699  ;
+; Y[6]       ; S[8]        ; 9.438  ; 9.352  ; 9.981  ; 9.867  ;
+; Y[6]       ; S[9]        ; 9.872  ; 9.808  ; 10.401 ; 10.328 ;
+; Y[7]       ; Cout        ; 8.941  ;        ;        ; 9.365  ;
+; Y[7]       ; S[7]        ; 8.214  ; 8.158  ; 8.720  ; 8.603  ;
+; Y[7]       ; S[8]        ; 8.368  ; 8.282  ; 8.871  ; 8.757  ;
+; Y[7]       ; S[9]        ; 8.802  ; 8.738  ; 9.291  ; 9.218  ;
+; Y[8]       ; Cout        ; 8.041  ;        ;        ; 8.397  ;
+; Y[8]       ; S[8]        ; 7.472  ; 7.384  ; 7.909  ; 7.795  ;
+; Y[8]       ; S[9]        ; 8.106  ; 8.056  ; 8.551  ; 8.460  ;
+; Y[9]       ; Cout        ; 5.911  ;        ;        ; 5.911  ;
+; Y[9]       ; S[9]        ; 5.958  ; 5.913  ; 6.085  ; 5.968  ;
++------------+-------------+--------+--------+--------+--------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; EN         ; S[0]        ; 7.431  ;        ;        ; 7.645  ;
+; EN         ; S[1]        ; 7.434  ;        ;        ; 7.709  ;
+; EN         ; S[2]        ; 7.169  ;        ;        ; 7.385  ;
+; EN         ; S[3]        ; 7.600  ;        ;        ; 7.837  ;
+; EN         ; S[4]        ; 7.600  ;        ;        ; 7.875  ;
+; EN         ; S[5]        ; 7.350  ;        ;        ; 7.603  ;
+; EN         ; S[6]        ; 8.204  ;        ;        ; 8.493  ;
+; EN         ; S[7]        ; 7.688  ;        ;        ; 7.939  ;
+; EN         ; S[8]        ; 7.136  ;        ;        ; 7.344  ;
+; EN         ; S[9]        ; 7.263  ;        ;        ; 7.487  ;
+; X[0]       ; Cout        ; 11.899 ;        ;        ; 12.361 ;
+; X[0]       ; S[0]        ; 7.435  ; 7.301  ; 7.829  ; 7.650  ;
+; X[0]       ; S[1]        ; 7.562  ; 7.468  ; 7.951  ; 7.789  ;
+; X[0]       ; S[2]        ; 7.672  ; 7.531  ; 8.099  ; 7.918  ;
+; X[0]       ; S[3]        ; 8.527  ; 8.390  ; 8.948  ; 8.764  ;
+; X[0]       ; S[4]        ; 8.814  ; 8.708  ; 9.241  ; 9.164  ;
+; X[0]       ; S[5]        ; 9.031  ; 8.927  ; 9.519  ; 9.375  ;
+; X[0]       ; S[6]        ; 10.400 ; 10.330 ; 10.899 ; 10.803 ;
+; X[0]       ; S[7]        ; 11.123 ; 10.970 ; 11.619 ; 11.495 ;
+; X[0]       ; S[8]        ; 11.266 ; 11.142 ; 11.826 ; 11.662 ;
+; X[0]       ; S[9]        ; 11.699 ; 11.569 ; 12.223 ; 12.101 ;
+; X[1]       ; Cout        ; 9.870  ;        ;        ; 10.091 ;
+; X[1]       ; S[1]        ; 5.520  ; 5.389  ; 5.676  ; 5.537  ;
+; X[1]       ; S[2]        ; 5.643  ; 5.502  ; 5.829  ; 5.648  ;
+; X[1]       ; S[3]        ; 6.498  ; 6.361  ; 6.678  ; 6.494  ;
+; X[1]       ; S[4]        ; 6.785  ; 6.679  ; 6.971  ; 6.894  ;
+; X[1]       ; S[5]        ; 7.002  ; 6.898  ; 7.249  ; 7.105  ;
+; X[1]       ; S[6]        ; 8.371  ; 8.301  ; 8.629  ; 8.533  ;
+; X[1]       ; S[7]        ; 9.094  ; 8.941  ; 9.349  ; 9.225  ;
+; X[1]       ; S[8]        ; 9.237  ; 9.113  ; 9.556  ; 9.392  ;
+; X[1]       ; S[9]        ; 9.670  ; 9.540  ; 9.953  ; 9.831  ;
+; X[2]       ; Cout        ; 9.874  ;        ;        ; 10.119 ;
+; X[2]       ; S[2]        ; 5.435  ; 5.290  ; 5.588  ; 5.417  ;
+; X[2]       ; S[3]        ; 6.502  ; 6.365  ; 6.706  ; 6.522  ;
+; X[2]       ; S[4]        ; 6.789  ; 6.683  ; 6.999  ; 6.922  ;
+; X[2]       ; S[5]        ; 7.006  ; 6.902  ; 7.277  ; 7.133  ;
+; X[2]       ; S[6]        ; 8.375  ; 8.305  ; 8.657  ; 8.561  ;
+; X[2]       ; S[7]        ; 9.098  ; 8.945  ; 9.377  ; 9.253  ;
+; X[2]       ; S[8]        ; 9.241  ; 9.117  ; 9.584  ; 9.420  ;
+; X[2]       ; S[9]        ; 9.674  ; 9.544  ; 9.981  ; 9.859  ;
+; X[3]       ; Cout        ; 11.030 ;        ;        ; 11.455 ;
+; X[3]       ; S[3]        ; 7.659  ; 7.518  ; 8.037  ; 7.860  ;
+; X[3]       ; S[4]        ; 7.945  ; 7.839  ; 8.335  ; 8.258  ;
+; X[3]       ; S[5]        ; 8.162  ; 8.058  ; 8.613  ; 8.469  ;
+; X[3]       ; S[6]        ; 9.531  ; 9.461  ; 9.993  ; 9.897  ;
+; X[3]       ; S[7]        ; 10.254 ; 10.101 ; 10.713 ; 10.589 ;
+; X[3]       ; S[8]        ; 10.397 ; 10.273 ; 10.920 ; 10.756 ;
+; X[3]       ; S[9]        ; 10.830 ; 10.700 ; 11.317 ; 11.195 ;
+; X[4]       ; Cout        ; 10.651 ;        ;        ; 11.047 ;
+; X[4]       ; S[4]        ; 7.533  ; 7.448  ; 7.906  ; 7.795  ;
+; X[4]       ; S[5]        ; 7.783  ; 7.679  ; 8.205  ; 8.061  ;
+; X[4]       ; S[6]        ; 9.152  ; 9.082  ; 9.585  ; 9.489  ;
+; X[4]       ; S[7]        ; 9.875  ; 9.722  ; 10.305 ; 10.181 ;
+; X[4]       ; S[8]        ; 10.018 ; 9.894  ; 10.512 ; 10.348 ;
+; X[4]       ; S[9]        ; 10.451 ; 10.321 ; 10.909 ; 10.787 ;
+; X[5]       ; Cout        ; 10.102 ;        ;        ; 10.444 ;
+; X[5]       ; S[5]        ; 7.454  ; 7.346  ; 7.836  ; 7.702  ;
+; X[5]       ; S[6]        ; 8.603  ; 8.533  ; 8.982  ; 8.886  ;
+; X[5]       ; S[7]        ; 9.326  ; 9.173  ; 9.702  ; 9.578  ;
+; X[5]       ; S[8]        ; 9.469  ; 9.345  ; 9.909  ; 9.745  ;
+; X[5]       ; S[9]        ; 9.902  ; 9.772  ; 10.306 ; 10.184 ;
+; X[6]       ; Cout        ; 9.484  ;        ;        ; 9.823  ;
+; X[6]       ; S[6]        ; 8.099  ; 8.033  ; 8.486  ; 8.380  ;
+; X[6]       ; S[7]        ; 8.708  ; 8.555  ; 9.081  ; 8.957  ;
+; X[6]       ; S[8]        ; 8.851  ; 8.727  ; 9.288  ; 9.124  ;
+; X[6]       ; S[9]        ; 9.284  ; 9.154  ; 9.685  ; 9.563  ;
+; X[7]       ; Cout        ; 7.979  ;        ;        ; 8.274  ;
+; X[7]       ; S[7]        ; 7.199  ; 7.048  ; 7.563  ; 7.404  ;
+; X[7]       ; S[8]        ; 7.346  ; 7.222  ; 7.739  ; 7.575  ;
+; X[7]       ; S[9]        ; 7.779  ; 7.649  ; 8.136  ; 8.014  ;
+; X[8]       ; Cout        ; 7.610  ;        ;        ; 7.891  ;
+; X[8]       ; S[8]        ; 7.013  ; 6.864  ; 7.373  ; 7.253  ;
+; X[8]       ; S[9]        ; 7.630  ; 7.502  ; 8.019  ; 7.862  ;
+; X[9]       ; Cout        ; 5.412  ;        ;        ; 5.397  ;
+; X[9]       ; S[9]        ; 6.085  ; 5.929  ; 6.199  ; 6.057  ;
+; Y[0]       ; Cout        ; 11.899 ;        ;        ; 12.393 ;
+; Y[0]       ; S[0]        ; 7.451  ; 7.283  ; 7.846  ; 7.707  ;
+; Y[0]       ; S[1]        ; 7.545  ; 7.412  ; 7.941  ; 7.837  ;
+; Y[0]       ; S[2]        ; 7.672  ; 7.531  ; 8.131  ; 7.950  ;
+; Y[0]       ; S[3]        ; 8.527  ; 8.390  ; 8.980  ; 8.796  ;
+; Y[0]       ; S[4]        ; 8.814  ; 8.708  ; 9.273  ; 9.196  ;
+; Y[0]       ; S[5]        ; 9.031  ; 8.927  ; 9.551  ; 9.407  ;
+; Y[0]       ; S[6]        ; 10.400 ; 10.330 ; 10.931 ; 10.835 ;
+; Y[0]       ; S[7]        ; 11.123 ; 10.970 ; 11.651 ; 11.527 ;
+; Y[0]       ; S[8]        ; 11.266 ; 11.142 ; 11.858 ; 11.694 ;
+; Y[0]       ; S[9]        ; 11.699 ; 11.569 ; 12.255 ; 12.133 ;
+; Y[1]       ; Cout        ; 11.608 ;        ;        ; 12.087 ;
+; Y[1]       ; S[1]        ; 7.284  ; 7.175  ; 7.661  ; 7.548  ;
+; Y[1]       ; S[2]        ; 7.381  ; 7.240  ; 7.825  ; 7.644  ;
+; Y[1]       ; S[3]        ; 8.236  ; 8.099  ; 8.674  ; 8.490  ;
+; Y[1]       ; S[4]        ; 8.523  ; 8.417  ; 8.967  ; 8.890  ;
+; Y[1]       ; S[5]        ; 8.740  ; 8.636  ; 9.245  ; 9.101  ;
+; Y[1]       ; S[6]        ; 10.109 ; 10.039 ; 10.625 ; 10.529 ;
+; Y[1]       ; S[7]        ; 10.832 ; 10.679 ; 11.345 ; 11.221 ;
+; Y[1]       ; S[8]        ; 10.975 ; 10.851 ; 11.552 ; 11.388 ;
+; Y[1]       ; S[9]        ; 11.408 ; 11.278 ; 11.949 ; 11.827 ;
+; Y[2]       ; Cout        ; 11.715 ;        ;        ; 12.232 ;
+; Y[2]       ; S[2]        ; 7.188  ; 7.022  ; 7.585  ; 7.448  ;
+; Y[2]       ; S[3]        ; 8.343  ; 8.206  ; 8.819  ; 8.635  ;
+; Y[2]       ; S[4]        ; 8.630  ; 8.524  ; 9.112  ; 9.035  ;
+; Y[2]       ; S[5]        ; 8.847  ; 8.743  ; 9.390  ; 9.246  ;
+; Y[2]       ; S[6]        ; 10.216 ; 10.146 ; 10.770 ; 10.674 ;
+; Y[2]       ; S[7]        ; 10.939 ; 10.786 ; 11.490 ; 11.366 ;
+; Y[2]       ; S[8]        ; 11.082 ; 10.958 ; 11.697 ; 11.533 ;
+; Y[2]       ; S[9]        ; 11.515 ; 11.385 ; 12.094 ; 11.972 ;
+; Y[3]       ; Cout        ; 11.026 ;        ;        ; 11.468 ;
+; Y[3]       ; S[3]        ; 7.643  ; 7.473  ; 8.030  ; 7.889  ;
+; Y[3]       ; S[4]        ; 7.941  ; 7.835  ; 8.348  ; 8.271  ;
+; Y[3]       ; S[5]        ; 8.158  ; 8.054  ; 8.626  ; 8.482  ;
+; Y[3]       ; S[6]        ; 9.527  ; 9.457  ; 10.006 ; 9.910  ;
+; Y[3]       ; S[7]        ; 10.250 ; 10.097 ; 10.726 ; 10.602 ;
+; Y[3]       ; S[8]        ; 10.393 ; 10.269 ; 10.933 ; 10.769 ;
+; Y[3]       ; S[9]        ; 10.826 ; 10.696 ; 11.330 ; 11.208 ;
+; Y[4]       ; Cout        ; 10.783 ;        ;        ; 11.220 ;
+; Y[4]       ; S[4]        ; 7.665  ; 7.584  ; 8.086  ; 7.965  ;
+; Y[4]       ; S[5]        ; 7.915  ; 7.811  ; 8.378  ; 8.234  ;
+; Y[4]       ; S[6]        ; 9.284  ; 9.214  ; 9.758  ; 9.662  ;
+; Y[4]       ; S[7]        ; 10.007 ; 9.854  ; 10.478 ; 10.354 ;
+; Y[4]       ; S[8]        ; 10.150 ; 10.026 ; 10.685 ; 10.521 ;
+; Y[4]       ; S[9]        ; 10.583 ; 10.453 ; 11.082 ; 10.960 ;
+; Y[5]       ; Cout        ; 10.070 ;        ;        ; 10.438 ;
+; Y[5]       ; S[5]        ; 7.235  ; 7.106  ; 7.584  ; 7.484  ;
+; Y[5]       ; S[6]        ; 8.571  ; 8.501  ; 8.976  ; 8.880  ;
+; Y[5]       ; S[7]        ; 9.294  ; 9.141  ; 9.696  ; 9.572  ;
+; Y[5]       ; S[8]        ; 9.437  ; 9.313  ; 9.903  ; 9.739  ;
+; Y[5]       ; S[9]        ; 9.870  ; 9.740  ; 10.300 ; 10.178 ;
+; Y[6]       ; Cout        ; 9.392  ;        ;        ; 9.709  ;
+; Y[6]       ; S[6]        ; 8.056  ; 7.965  ; 8.394  ; 8.332  ;
+; Y[6]       ; S[7]        ; 8.616  ; 8.463  ; 8.967  ; 8.843  ;
+; Y[6]       ; S[8]        ; 8.759  ; 8.635  ; 9.174  ; 9.010  ;
+; Y[6]       ; S[9]        ; 9.192  ; 9.062  ; 9.571  ; 9.449  ;
+; Y[7]       ; Cout        ; 8.407  ;        ;        ; 8.722  ;
+; Y[7]       ; S[7]        ; 7.625  ; 7.513  ; 8.015  ; 7.876  ;
+; Y[7]       ; S[8]        ; 7.774  ; 7.650  ; 8.187  ; 8.023  ;
+; Y[7]       ; S[9]        ; 8.207  ; 8.077  ; 8.584  ; 8.462  ;
+; Y[8]       ; Cout        ; 7.505  ;        ;        ; 7.770  ;
+; Y[8]       ; S[8]        ; 6.878  ; 6.750  ; 7.234  ; 7.080  ;
+; Y[8]       ; S[9]        ; 7.563  ; 7.406  ; 7.857  ; 7.752  ;
+; Y[9]       ; Cout        ; 5.542  ;        ;        ; 5.552  ;
+; Y[9]       ; S[9]        ; 5.543  ; 5.442  ; 5.689  ; 5.524  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++--------------------------------------------------------------+
+; Minimum Propagation Delay                                    ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; EN         ; S[0]        ; 7.178  ;        ;        ; 7.387  ;
+; EN         ; S[1]        ; 7.163  ;        ;        ; 7.420  ;
+; EN         ; S[2]        ; 6.927  ;        ;        ; 7.137  ;
+; EN         ; S[3]        ; 7.327  ;        ;        ; 7.546  ;
+; EN         ; S[4]        ; 7.337  ;        ;        ; 7.604  ;
+; EN         ; S[5]        ; 7.102  ;        ;        ; 7.347  ;
+; EN         ; S[6]        ; 7.916  ;        ;        ; 8.197  ;
+; EN         ; S[7]        ; 7.378  ;        ;        ; 7.599  ;
+; EN         ; S[8]        ; 6.897  ;        ;        ; 7.098  ;
+; EN         ; S[9]        ; 7.018  ;        ;        ; 7.236  ;
+; X[0]       ; Cout        ; 11.041 ;        ;        ; 11.356 ;
+; X[0]       ; S[0]        ; 7.169  ; 7.031  ; 7.539  ; 7.370  ;
+; X[0]       ; S[1]        ; 7.255  ; 7.152  ; 7.623  ; 7.508  ;
+; X[0]       ; S[2]        ; 7.379  ; 7.241  ; 7.746  ; 7.579  ;
+; X[0]       ; S[3]        ; 7.986  ; 7.821  ; 8.342  ; 8.171  ;
+; X[0]       ; S[4]        ; 8.268  ; 8.163  ; 8.613  ; 8.535  ;
+; X[0]       ; S[5]        ; 8.470  ; 8.366  ; 8.858  ; 8.725  ;
+; X[0]       ; S[6]        ; 9.728  ; 9.661  ; 10.136 ; 10.041 ;
+; X[0]       ; S[7]        ; 10.390 ; 10.239 ; 10.797 ; 10.674 ;
+; X[0]       ; S[8]        ; 10.519 ; 10.396 ; 10.970 ; 10.818 ;
+; X[0]       ; S[9]        ; 10.918 ; 10.785 ; 11.359 ; 11.220 ;
+; X[1]       ; Cout        ; 9.119  ;        ;        ; 9.237  ;
+; X[1]       ; S[1]        ; 5.345  ; 5.217  ; 5.501  ; 5.367  ;
+; X[1]       ; S[2]        ; 5.457  ; 5.319  ; 5.627  ; 5.460  ;
+; X[1]       ; S[3]        ; 6.064  ; 5.899  ; 6.223  ; 6.052  ;
+; X[1]       ; S[4]        ; 6.346  ; 6.241  ; 6.494  ; 6.416  ;
+; X[1]       ; S[5]        ; 6.548  ; 6.444  ; 6.739  ; 6.606  ;
+; X[1]       ; S[6]        ; 7.806  ; 7.739  ; 8.017  ; 7.922  ;
+; X[1]       ; S[7]        ; 8.468  ; 8.317  ; 8.678  ; 8.555  ;
+; X[1]       ; S[8]        ; 8.597  ; 8.474  ; 8.851  ; 8.699  ;
+; X[1]       ; S[9]        ; 8.996  ; 8.863  ; 9.240  ; 9.101  ;
+; X[2]       ; Cout        ; 9.291  ;        ;        ; 9.399  ;
+; X[2]       ; S[2]        ; 5.253  ; 5.114  ; 5.402  ; 5.235  ;
+; X[2]       ; S[3]        ; 6.227  ; 6.090  ; 6.385  ; 6.233  ;
+; X[2]       ; S[4]        ; 6.518  ; 6.413  ; 6.656  ; 6.578  ;
+; X[2]       ; S[5]        ; 6.720  ; 6.616  ; 6.901  ; 6.768  ;
+; X[2]       ; S[6]        ; 7.978  ; 7.911  ; 8.179  ; 8.084  ;
+; X[2]       ; S[7]        ; 8.640  ; 8.489  ; 8.840  ; 8.717  ;
+; X[2]       ; S[8]        ; 8.769  ; 8.646  ; 9.013  ; 8.861  ;
+; X[2]       ; S[9]        ; 9.168  ; 9.035  ; 9.402  ; 9.263  ;
+; X[3]       ; Cout        ; 10.393 ;        ;        ; 10.723 ;
+; X[3]       ; S[3]        ; 7.340  ; 7.203  ; 7.706  ; 7.534  ;
+; X[3]       ; S[4]        ; 7.620  ; 7.515  ; 7.980  ; 7.902  ;
+; X[3]       ; S[5]        ; 7.822  ; 7.718  ; 8.225  ; 8.092  ;
+; X[3]       ; S[6]        ; 9.080  ; 9.013  ; 9.503  ; 9.408  ;
+; X[3]       ; S[7]        ; 9.742  ; 9.591  ; 10.164 ; 10.041 ;
+; X[3]       ; S[8]        ; 9.871  ; 9.748  ; 10.337 ; 10.185 ;
+; X[3]       ; S[9]        ; 10.270 ; 10.137 ; 10.726 ; 10.587 ;
+; X[4]       ; Cout        ; 10.030 ;        ;        ; 10.325 ;
+; X[4]       ; S[4]        ; 7.258  ; 7.177  ; 7.617  ; 7.508  ;
+; X[4]       ; S[5]        ; 7.459  ; 7.355  ; 7.827  ; 7.694  ;
+; X[4]       ; S[6]        ; 8.717  ; 8.650  ; 9.105  ; 9.010  ;
+; X[4]       ; S[7]        ; 9.379  ; 9.228  ; 9.766  ; 9.643  ;
+; X[4]       ; S[8]        ; 9.508  ; 9.385  ; 9.939  ; 9.787  ;
+; X[4]       ; S[9]        ; 9.907  ; 9.774  ; 10.328 ; 10.189 ;
+; X[5]       ; Cout        ; 9.597  ;        ;        ; 9.871  ;
+; X[5]       ; S[5]        ; 7.188  ; 7.083  ; 7.556  ; 7.423  ;
+; X[5]       ; S[6]        ; 8.284  ; 8.217  ; 8.651  ; 8.556  ;
+; X[5]       ; S[7]        ; 8.946  ; 8.795  ; 9.312  ; 9.189  ;
+; X[5]       ; S[8]        ; 9.075  ; 8.952  ; 9.485  ; 9.333  ;
+; X[5]       ; S[9]        ; 9.474  ; 9.341  ; 9.874  ; 9.735  ;
+; X[6]       ; Cout        ; 9.052  ;        ;        ; 9.328  ;
+; X[6]       ; S[6]        ; 7.806  ; 7.740  ; 8.167  ; 8.072  ;
+; X[6]       ; S[7]        ; 8.401  ; 8.250  ; 8.769  ; 8.646  ;
+; X[6]       ; S[8]        ; 8.530  ; 8.407  ; 8.942  ; 8.790  ;
+; X[6]       ; S[9]        ; 8.929  ; 8.796  ; 9.331  ; 9.192  ;
+; X[7]       ; Cout        ; 7.611  ;        ;        ; 7.842  ;
+; X[7]       ; S[7]        ; 6.957  ; 6.808  ; 7.311  ; 7.156  ;
+; X[7]       ; S[8]        ; 7.089  ; 6.966  ; 7.456  ; 7.304  ;
+; X[7]       ; S[9]        ; 7.488  ; 7.355  ; 7.845  ; 7.706  ;
+; X[8]       ; Cout        ; 7.299  ;        ;        ; 7.548  ;
+; X[8]       ; S[8]        ; 6.779  ; 6.631  ; 7.131  ; 7.010  ;
+; X[8]       ; S[9]        ; 7.345  ; 7.210  ; 7.697  ; 7.587  ;
+; X[9]       ; Cout        ; 5.243  ;        ;        ; 5.233  ;
+; X[9]       ; S[9]        ; 5.797  ; 5.679  ; 5.915  ; 5.778  ;
+; Y[0]       ; Cout        ; 11.058 ;        ;        ; 11.438 ;
+; Y[0]       ; S[0]        ; 7.196  ; 7.031  ; 7.582  ; 7.444  ;
+; Y[0]       ; S[1]        ; 7.280  ; 7.150  ; 7.667  ; 7.565  ;
+; Y[0]       ; S[2]        ; 7.396  ; 7.258  ; 7.828  ; 7.661  ;
+; Y[0]       ; S[3]        ; 8.003  ; 7.838  ; 8.424  ; 8.253  ;
+; Y[0]       ; S[4]        ; 8.285  ; 8.180  ; 8.695  ; 8.617  ;
+; Y[0]       ; S[5]        ; 8.487  ; 8.383  ; 8.940  ; 8.807  ;
+; Y[0]       ; S[6]        ; 9.745  ; 9.678  ; 10.218 ; 10.123 ;
+; Y[0]       ; S[7]        ; 10.407 ; 10.256 ; 10.879 ; 10.756 ;
+; Y[0]       ; S[8]        ; 10.536 ; 10.413 ; 11.052 ; 10.900 ;
+; Y[0]       ; S[9]        ; 10.935 ; 10.802 ; 11.441 ; 11.302 ;
+; Y[1]       ; Cout        ; 10.749 ;        ;        ; 11.086 ;
+; Y[1]       ; S[1]        ; 6.973  ; 6.869  ; 7.349  ; 7.237  ;
+; Y[1]       ; S[2]        ; 7.087  ; 6.949  ; 7.476  ; 7.309  ;
+; Y[1]       ; S[3]        ; 7.694  ; 7.529  ; 8.072  ; 7.901  ;
+; Y[1]       ; S[4]        ; 7.976  ; 7.871  ; 8.343  ; 8.265  ;
+; Y[1]       ; S[5]        ; 8.178  ; 8.074  ; 8.588  ; 8.455  ;
+; Y[1]       ; S[6]        ; 9.436  ; 9.369  ; 9.866  ; 9.771  ;
+; Y[1]       ; S[7]        ; 10.098 ; 9.947  ; 10.527 ; 10.404 ;
+; Y[1]       ; S[8]        ; 10.227 ; 10.104 ; 10.700 ; 10.548 ;
+; Y[1]       ; S[9]        ; 10.626 ; 10.493 ; 11.089 ; 10.950 ;
+; Y[2]       ; Cout        ; 10.772 ;        ;        ; 11.151 ;
+; Y[2]       ; S[2]        ; 6.943  ; 6.780  ; 7.331  ; 7.195  ;
+; Y[2]       ; S[3]        ; 7.717  ; 7.552  ; 8.137  ; 7.966  ;
+; Y[2]       ; S[4]        ; 7.999  ; 7.894  ; 8.408  ; 8.330  ;
+; Y[2]       ; S[5]        ; 8.201  ; 8.097  ; 8.653  ; 8.520  ;
+; Y[2]       ; S[6]        ; 9.459  ; 9.392  ; 9.931  ; 9.836  ;
+; Y[2]       ; S[7]        ; 10.121 ; 9.970  ; 10.592 ; 10.469 ;
+; Y[2]       ; S[8]        ; 10.250 ; 10.127 ; 10.765 ; 10.613 ;
+; Y[2]       ; S[9]        ; 10.649 ; 10.516 ; 11.154 ; 11.015 ;
+; Y[3]       ; Cout        ; 10.433 ;        ;        ; 10.801 ;
+; Y[3]       ; S[3]        ; 7.378  ; 7.211  ; 7.756  ; 7.617  ;
+; Y[3]       ; S[4]        ; 7.660  ; 7.555  ; 8.058  ; 7.980  ;
+; Y[3]       ; S[5]        ; 7.862  ; 7.758  ; 8.303  ; 8.170  ;
+; Y[3]       ; S[6]        ; 9.120  ; 9.053  ; 9.581  ; 9.486  ;
+; Y[3]       ; S[7]        ; 9.782  ; 9.631  ; 10.242 ; 10.119 ;
+; Y[3]       ; S[8]        ; 9.911  ; 9.788  ; 10.415 ; 10.263 ;
+; Y[3]       ; S[9]        ; 10.310 ; 10.177 ; 10.804 ; 10.665 ;
+; Y[4]       ; Cout        ; 10.160 ;        ;        ; 10.491 ;
+; Y[4]       ; S[4]        ; 7.389  ; 7.309  ; 7.782  ; 7.673  ;
+; Y[4]       ; S[5]        ; 7.589  ; 7.485  ; 7.993  ; 7.860  ;
+; Y[4]       ; S[6]        ; 8.847  ; 8.780  ; 9.271  ; 9.176  ;
+; Y[4]       ; S[7]        ; 9.509  ; 9.358  ; 9.932  ; 9.809  ;
+; Y[4]       ; S[8]        ; 9.638  ; 9.515  ; 10.105 ; 9.953  ;
+; Y[4]       ; S[9]        ; 10.037 ; 9.904  ; 10.494 ; 10.355 ;
+; Y[5]       ; Cout        ; 9.564  ;        ;        ; 9.862  ;
+; Y[5]       ; S[5]        ; 6.991  ; 6.862  ; 7.333  ; 7.231  ;
+; Y[5]       ; S[6]        ; 8.251  ; 8.184  ; 8.642  ; 8.547  ;
+; Y[5]       ; S[7]        ; 8.913  ; 8.762  ; 9.303  ; 9.180  ;
+; Y[5]       ; S[8]        ; 9.042  ; 8.919  ; 9.476  ; 9.324  ;
+; Y[5]       ; S[9]        ; 9.441  ; 9.308  ; 9.865  ; 9.726  ;
+; Y[6]       ; Cout        ; 8.963  ;        ;        ; 9.218  ;
+; Y[6]       ; S[6]        ; 7.772  ; 7.681  ; 8.103  ; 8.039  ;
+; Y[6]       ; S[7]        ; 8.312  ; 8.161  ; 8.659  ; 8.536  ;
+; Y[6]       ; S[8]        ; 8.441  ; 8.318  ; 8.832  ; 8.680  ;
+; Y[6]       ; S[9]        ; 8.840  ; 8.707  ; 9.221  ; 9.082  ;
+; Y[7]       ; Cout        ; 7.977  ;        ;        ; 8.225  ;
+; Y[7]       ; S[7]        ; 7.325  ; 7.211  ; 7.719  ; 7.556  ;
+; Y[7]       ; S[8]        ; 7.455  ; 7.332  ; 7.839  ; 7.687  ;
+; Y[7]       ; S[9]        ; 7.854  ; 7.721  ; 8.228  ; 8.089  ;
+; Y[8]       ; Cout        ; 7.151  ;        ;        ; 7.356  ;
+; Y[8]       ; S[8]        ; 6.634  ; 6.510  ; 6.977  ; 6.825  ;
+; Y[8]       ; S[9]        ; 7.214  ; 7.102  ; 7.562  ; 7.406  ;
+; Y[9]       ; Cout        ; 5.325  ;        ;        ; 5.308  ;
+; Y[9]       ; S[9]        ; 5.369  ; 5.263  ; 5.518  ; 5.352  ;
++------------+-------------+--------+--------+--------+--------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; EN         ; S[0]        ; 4.814 ;       ;       ; 5.506 ;
+; EN         ; S[1]        ; 4.837 ;       ;       ; 5.523 ;
+; EN         ; S[2]        ; 4.653 ;       ;       ; 5.322 ;
+; EN         ; S[3]        ; 4.921 ;       ;       ; 5.628 ;
+; EN         ; S[4]        ; 4.950 ;       ;       ; 5.654 ;
+; EN         ; S[5]        ; 4.840 ;       ;       ; 5.484 ;
+; EN         ; S[6]        ; 5.313 ;       ;       ; 6.078 ;
+; EN         ; S[7]        ; 5.044 ;       ;       ; 5.702 ;
+; EN         ; S[8]        ; 4.648 ;       ;       ; 5.304 ;
+; EN         ; S[9]        ; 4.775 ;       ;       ; 5.401 ;
+; X[0]       ; Cout        ; 7.522 ;       ;       ; 8.520 ;
+; X[0]       ; S[0]        ; 4.801 ; 4.883 ; 5.449 ; 5.501 ;
+; X[0]       ; S[1]        ; 4.891 ; 4.960 ; 5.537 ; 5.555 ;
+; X[0]       ; S[2]        ; 4.938 ; 4.992 ; 5.626 ; 5.651 ;
+; X[0]       ; S[3]        ; 5.448 ; 5.535 ; 6.150 ; 6.198 ;
+; X[0]       ; S[4]        ; 5.653 ; 5.728 ; 6.359 ; 6.453 ;
+; X[0]       ; S[5]        ; 5.816 ; 5.846 ; 6.589 ; 6.590 ;
+; X[0]       ; S[6]        ; 6.596 ; 6.745 ; 7.397 ; 7.523 ;
+; X[0]       ; S[7]        ; 7.071 ; 7.085 ; 7.962 ; 7.994 ;
+; X[0]       ; S[8]        ; 7.091 ; 7.148 ; 8.050 ; 8.078 ;
+; X[0]       ; S[9]        ; 7.422 ; 7.411 ; 8.346 ; 8.339 ;
+; X[1]       ; Cout        ; 6.230 ;       ;       ; 6.885 ;
+; X[1]       ; S[1]        ; 3.593 ; 3.643 ; 3.893 ; 3.936 ;
+; X[1]       ; S[2]        ; 3.646 ; 3.700 ; 3.991 ; 4.016 ;
+; X[1]       ; S[3]        ; 4.156 ; 4.243 ; 4.515 ; 4.563 ;
+; X[1]       ; S[4]        ; 4.361 ; 4.436 ; 4.724 ; 4.818 ;
+; X[1]       ; S[5]        ; 4.524 ; 4.554 ; 4.954 ; 4.955 ;
+; X[1]       ; S[6]        ; 5.304 ; 5.453 ; 5.762 ; 5.888 ;
+; X[1]       ; S[7]        ; 5.779 ; 5.793 ; 6.327 ; 6.359 ;
+; X[1]       ; S[8]        ; 5.799 ; 5.856 ; 6.415 ; 6.443 ;
+; X[1]       ; S[9]        ; 6.130 ; 6.119 ; 6.711 ; 6.704 ;
+; X[2]       ; Cout        ; 6.250 ;       ;       ; 6.887 ;
+; X[2]       ; S[2]        ; 3.530 ; 3.583 ; 3.826 ; 3.856 ;
+; X[2]       ; S[3]        ; 4.176 ; 4.263 ; 4.517 ; 4.565 ;
+; X[2]       ; S[4]        ; 4.381 ; 4.456 ; 4.726 ; 4.820 ;
+; X[2]       ; S[5]        ; 4.544 ; 4.574 ; 4.956 ; 4.957 ;
+; X[2]       ; S[6]        ; 5.324 ; 5.473 ; 5.764 ; 5.890 ;
+; X[2]       ; S[7]        ; 5.799 ; 5.813 ; 6.329 ; 6.361 ;
+; X[2]       ; S[8]        ; 5.819 ; 5.876 ; 6.417 ; 6.445 ;
+; X[2]       ; S[9]        ; 6.150 ; 6.139 ; 6.713 ; 6.706 ;
+; X[3]       ; Cout        ; 7.035 ;       ;       ; 7.953 ;
+; X[3]       ; S[3]        ; 4.963 ; 5.049 ; 5.580 ; 5.634 ;
+; X[3]       ; S[4]        ; 5.166 ; 5.241 ; 5.792 ; 5.886 ;
+; X[3]       ; S[5]        ; 5.329 ; 5.359 ; 6.022 ; 6.023 ;
+; X[3]       ; S[6]        ; 6.109 ; 6.258 ; 6.830 ; 6.956 ;
+; X[3]       ; S[7]        ; 6.584 ; 6.598 ; 7.395 ; 7.427 ;
+; X[3]       ; S[8]        ; 6.604 ; 6.661 ; 7.483 ; 7.511 ;
+; X[3]       ; S[9]        ; 6.935 ; 6.924 ; 7.779 ; 7.772 ;
+; X[4]       ; Cout        ; 6.801 ;       ;       ; 7.696 ;
+; X[4]       ; S[4]        ; 4.909 ; 4.999 ; 5.531 ; 5.598 ;
+; X[4]       ; S[5]        ; 5.095 ; 5.125 ; 5.765 ; 5.766 ;
+; X[4]       ; S[6]        ; 5.875 ; 6.024 ; 6.573 ; 6.699 ;
+; X[4]       ; S[7]        ; 6.350 ; 6.364 ; 7.138 ; 7.170 ;
+; X[4]       ; S[8]        ; 6.370 ; 6.427 ; 7.226 ; 7.254 ;
+; X[4]       ; S[9]        ; 6.701 ; 6.690 ; 7.522 ; 7.515 ;
+; X[5]       ; Cout        ; 6.466 ;       ;       ; 7.316 ;
+; X[5]       ; S[5]        ; 4.894 ; 4.923 ; 5.533 ; 5.539 ;
+; X[5]       ; S[6]        ; 5.540 ; 5.689 ; 6.193 ; 6.319 ;
+; X[5]       ; S[7]        ; 6.015 ; 6.029 ; 6.758 ; 6.790 ;
+; X[5]       ; S[8]        ; 6.035 ; 6.092 ; 6.846 ; 6.874 ;
+; X[5]       ; S[9]        ; 6.366 ; 6.355 ; 7.142 ; 7.135 ;
+; X[6]       ; Cout        ; 6.109 ;       ;       ; 6.917 ;
+; X[6]       ; S[6]        ; 5.255 ; 5.405 ; 5.878 ; 5.999 ;
+; X[6]       ; S[7]        ; 5.658 ; 5.672 ; 6.359 ; 6.391 ;
+; X[6]       ; S[8]        ; 5.678 ; 5.735 ; 6.447 ; 6.475 ;
+; X[6]       ; S[9]        ; 6.009 ; 5.998 ; 6.743 ; 6.736 ;
+; X[7]       ; Cout        ; 5.196 ;       ;       ; 5.877 ;
+; X[7]       ; S[7]        ; 4.742 ; 4.759 ; 5.338 ; 5.348 ;
+; X[7]       ; S[8]        ; 4.765 ; 4.822 ; 5.407 ; 5.435 ;
+; X[7]       ; S[9]        ; 5.096 ; 5.085 ; 5.703 ; 5.696 ;
+; X[8]       ; Cout        ; 4.980 ;       ;       ; 5.637 ;
+; X[8]       ; S[8]        ; 4.577 ; 4.618 ; 5.172 ; 5.232 ;
+; X[8]       ; S[9]        ; 5.018 ; 5.007 ; 5.632 ; 5.621 ;
+; X[9]       ; Cout        ; 3.591 ;       ;       ; 3.878 ;
+; X[9]       ; S[9]        ; 4.022 ; 4.011 ; 4.298 ; 4.287 ;
+; Y[0]       ; Cout        ; 7.544 ;       ;       ; 8.553 ;
+; Y[0]       ; S[0]        ; 4.834 ; 4.896 ; 5.465 ; 5.546 ;
+; Y[0]       ; S[1]        ; 4.903 ; 4.950 ; 5.535 ; 5.600 ;
+; Y[0]       ; S[2]        ; 4.960 ; 5.014 ; 5.659 ; 5.684 ;
+; Y[0]       ; S[3]        ; 5.470 ; 5.557 ; 6.183 ; 6.231 ;
+; Y[0]       ; S[4]        ; 5.675 ; 5.750 ; 6.392 ; 6.486 ;
+; Y[0]       ; S[5]        ; 5.838 ; 5.868 ; 6.622 ; 6.623 ;
+; Y[0]       ; S[6]        ; 6.618 ; 6.767 ; 7.430 ; 7.556 ;
+; Y[0]       ; S[7]        ; 7.093 ; 7.107 ; 7.995 ; 8.027 ;
+; Y[0]       ; S[8]        ; 7.113 ; 7.170 ; 8.083 ; 8.111 ;
+; Y[0]       ; S[9]        ; 7.444 ; 7.433 ; 8.379 ; 8.372 ;
+; Y[1]       ; Cout        ; 7.359 ;       ;       ; 8.330 ;
+; Y[1]       ; S[1]        ; 4.733 ; 4.793 ; 5.339 ; 5.390 ;
+; Y[1]       ; S[2]        ; 4.775 ; 4.829 ; 5.436 ; 5.461 ;
+; Y[1]       ; S[3]        ; 5.285 ; 5.372 ; 5.960 ; 6.008 ;
+; Y[1]       ; S[4]        ; 5.490 ; 5.565 ; 6.169 ; 6.263 ;
+; Y[1]       ; S[5]        ; 5.653 ; 5.683 ; 6.399 ; 6.400 ;
+; Y[1]       ; S[6]        ; 6.433 ; 6.582 ; 7.207 ; 7.333 ;
+; Y[1]       ; S[7]        ; 6.908 ; 6.922 ; 7.772 ; 7.804 ;
+; Y[1]       ; S[8]        ; 6.928 ; 6.985 ; 7.860 ; 7.888 ;
+; Y[1]       ; S[9]        ; 7.259 ; 7.248 ; 8.156 ; 8.149 ;
+; Y[2]       ; Cout        ; 7.465 ;       ;       ; 8.472 ;
+; Y[2]       ; S[2]        ; 4.692 ; 4.730 ; 5.320 ; 5.377 ;
+; Y[2]       ; S[3]        ; 5.391 ; 5.478 ; 6.102 ; 6.150 ;
+; Y[2]       ; S[4]        ; 5.596 ; 5.671 ; 6.311 ; 6.405 ;
+; Y[2]       ; S[5]        ; 5.759 ; 5.789 ; 6.541 ; 6.542 ;
+; Y[2]       ; S[6]        ; 6.539 ; 6.688 ; 7.349 ; 7.475 ;
+; Y[2]       ; S[7]        ; 7.014 ; 7.028 ; 7.914 ; 7.946 ;
+; Y[2]       ; S[8]        ; 7.034 ; 7.091 ; 8.002 ; 8.030 ;
+; Y[2]       ; S[9]        ; 7.365 ; 7.354 ; 8.298 ; 8.291 ;
+; Y[3]       ; Cout        ; 7.022 ;       ;       ; 7.956 ;
+; Y[3]       ; S[3]        ; 4.942 ; 5.011 ; 5.561 ; 5.648 ;
+; Y[3]       ; S[4]        ; 5.153 ; 5.228 ; 5.795 ; 5.889 ;
+; Y[3]       ; S[5]        ; 5.316 ; 5.346 ; 6.025 ; 6.026 ;
+; Y[3]       ; S[6]        ; 6.096 ; 6.245 ; 6.833 ; 6.959 ;
+; Y[3]       ; S[7]        ; 6.571 ; 6.585 ; 7.398 ; 7.430 ;
+; Y[3]       ; S[8]        ; 6.591 ; 6.648 ; 7.486 ; 7.514 ;
+; Y[3]       ; S[9]        ; 6.922 ; 6.911 ; 7.782 ; 7.775 ;
+; Y[4]       ; Cout        ; 6.895 ;       ;       ; 7.825 ;
+; Y[4]       ; S[4]        ; 5.002 ; 5.093 ; 5.663 ; 5.725 ;
+; Y[4]       ; S[5]        ; 5.189 ; 5.219 ; 5.894 ; 5.895 ;
+; Y[4]       ; S[6]        ; 5.969 ; 6.118 ; 6.702 ; 6.828 ;
+; Y[4]       ; S[7]        ; 6.444 ; 6.458 ; 7.267 ; 7.299 ;
+; Y[4]       ; S[8]        ; 6.464 ; 6.521 ; 7.355 ; 7.383 ;
+; Y[4]       ; S[9]        ; 6.795 ; 6.784 ; 7.651 ; 7.644 ;
+; Y[5]       ; Cout        ; 6.448 ;       ;       ; 7.304 ;
+; Y[5]       ; S[5]        ; 4.763 ; 4.777 ; 5.359 ; 5.392 ;
+; Y[5]       ; S[6]        ; 5.522 ; 5.671 ; 6.181 ; 6.307 ;
+; Y[5]       ; S[7]        ; 5.997 ; 6.011 ; 6.746 ; 6.778 ;
+; Y[5]       ; S[8]        ; 6.017 ; 6.074 ; 6.834 ; 6.862 ;
+; Y[5]       ; S[9]        ; 6.348 ; 6.337 ; 7.130 ; 7.123 ;
+; Y[6]       ; Cout        ; 6.036 ;       ;       ; 6.842 ;
+; Y[6]       ; S[6]        ; 5.209 ; 5.343 ; 5.798 ; 5.951 ;
+; Y[6]       ; S[7]        ; 5.585 ; 5.599 ; 6.284 ; 6.316 ;
+; Y[6]       ; S[8]        ; 5.605 ; 5.662 ; 6.372 ; 6.400 ;
+; Y[6]       ; S[9]        ; 5.936 ; 5.925 ; 6.668 ; 6.661 ;
+; Y[7]       ; Cout        ; 5.464 ;       ;       ; 6.178 ;
+; Y[7]       ; S[7]        ; 5.011 ; 5.045 ; 5.647 ; 5.662 ;
+; Y[7]       ; S[8]        ; 5.033 ; 5.090 ; 5.708 ; 5.736 ;
+; Y[7]       ; S[9]        ; 5.364 ; 5.353 ; 6.004 ; 5.997 ;
+; Y[8]       ; Cout        ; 4.914 ;       ;       ; 5.547 ;
+; Y[8]       ; S[8]        ; 4.490 ; 4.546 ; 5.080 ; 5.113 ;
+; Y[8]       ; S[9]        ; 4.974 ; 4.963 ; 5.519 ; 5.529 ;
+; Y[9]       ; Cout        ; 3.675 ;       ;       ; 3.965 ;
+; Y[9]       ; S[9]        ; 3.672 ; 3.702 ; 3.964 ; 3.946 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; EN         ; S[0]        ; 4.648 ;       ;       ; 5.327 ;
+; EN         ; S[1]        ; 4.661 ;       ;       ; 5.320 ;
+; EN         ; S[2]        ; 4.493 ;       ;       ; 5.149 ;
+; EN         ; S[3]        ; 4.743 ;       ;       ; 5.423 ;
+; EN         ; S[4]        ; 4.776 ;       ;       ; 5.467 ;
+; EN         ; S[5]        ; 4.674 ;       ;       ; 5.307 ;
+; EN         ; S[6]        ; 5.124 ;       ;       ; 5.872 ;
+; EN         ; S[7]        ; 4.843 ;       ;       ; 5.472 ;
+; EN         ; S[8]        ; 4.488 ;       ;       ; 5.133 ;
+; EN         ; S[9]        ; 4.612 ;       ;       ; 5.226 ;
+; X[0]       ; Cout        ; 6.992 ;       ;       ; 7.865 ;
+; X[0]       ; S[0]        ; 4.629 ; 4.700 ; 5.251 ; 5.305 ;
+; X[0]       ; S[1]        ; 4.693 ; 4.748 ; 5.313 ; 5.367 ;
+; X[0]       ; S[2]        ; 4.748 ; 4.794 ; 5.384 ; 5.414 ;
+; X[0]       ; S[3]        ; 5.101 ; 5.171 ; 5.744 ; 5.807 ;
+; X[0]       ; S[4]        ; 5.304 ; 5.375 ; 5.947 ; 6.037 ;
+; X[0]       ; S[5]        ; 5.460 ; 5.483 ; 6.150 ; 6.157 ;
+; X[0]       ; S[6]        ; 6.177 ; 6.313 ; 6.896 ; 7.016 ;
+; X[0]       ; S[7]        ; 6.615 ; 6.626 ; 7.422 ; 7.453 ;
+; X[0]       ; S[8]        ; 6.629 ; 6.679 ; 7.485 ; 7.519 ;
+; X[0]       ; S[9]        ; 6.909 ; 6.931 ; 7.757 ; 7.779 ;
+; X[1]       ; Cout        ; 5.770 ;       ;       ; 6.336 ;
+; X[1]       ; S[1]        ; 3.476 ; 3.524 ; 3.780 ; 3.821 ;
+; X[1]       ; S[2]        ; 3.526 ; 3.572 ; 3.855 ; 3.885 ;
+; X[1]       ; S[3]        ; 3.879 ; 3.949 ; 4.215 ; 4.278 ;
+; X[1]       ; S[4]        ; 4.082 ; 4.153 ; 4.418 ; 4.508 ;
+; X[1]       ; S[5]        ; 4.238 ; 4.261 ; 4.621 ; 4.628 ;
+; X[1]       ; S[6]        ; 4.955 ; 5.091 ; 5.367 ; 5.487 ;
+; X[1]       ; S[7]        ; 5.393 ; 5.404 ; 5.893 ; 5.924 ;
+; X[1]       ; S[8]        ; 5.407 ; 5.457 ; 5.956 ; 5.990 ;
+; X[1]       ; S[9]        ; 5.687 ; 5.709 ; 6.228 ; 6.250 ;
+; X[2]       ; Cout        ; 5.893 ;       ;       ; 6.425 ;
+; X[2]       ; S[2]        ; 3.413 ; 3.457 ; 3.704 ; 3.732 ;
+; X[2]       ; S[3]        ; 3.997 ; 4.074 ; 4.309 ; 4.381 ;
+; X[2]       ; S[4]        ; 4.205 ; 4.276 ; 4.507 ; 4.597 ;
+; X[2]       ; S[5]        ; 4.361 ; 4.384 ; 4.710 ; 4.717 ;
+; X[2]       ; S[6]        ; 5.078 ; 5.214 ; 5.456 ; 5.576 ;
+; X[2]       ; S[7]        ; 5.516 ; 5.527 ; 5.982 ; 6.013 ;
+; X[2]       ; S[8]        ; 5.530 ; 5.580 ; 6.045 ; 6.079 ;
+; X[2]       ; S[9]        ; 5.810 ; 5.832 ; 6.317 ; 6.339 ;
+; X[3]       ; Cout        ; 6.645 ;       ;       ; 7.475 ;
+; X[3]       ; S[3]        ; 4.756 ; 4.833 ; 5.356 ; 5.415 ;
+; X[3]       ; S[4]        ; 4.957 ; 5.028 ; 5.557 ; 5.647 ;
+; X[3]       ; S[5]        ; 5.113 ; 5.136 ; 5.760 ; 5.767 ;
+; X[3]       ; S[6]        ; 5.830 ; 5.966 ; 6.506 ; 6.626 ;
+; X[3]       ; S[7]        ; 6.268 ; 6.279 ; 7.032 ; 7.063 ;
+; X[3]       ; S[8]        ; 6.282 ; 6.332 ; 7.095 ; 7.129 ;
+; X[3]       ; S[9]        ; 6.562 ; 6.584 ; 7.367 ; 7.389 ;
+; X[4]       ; Cout        ; 6.418 ;       ;       ; 7.225 ;
+; X[4]       ; S[4]        ; 4.731 ; 4.811 ; 5.335 ; 5.399 ;
+; X[4]       ; S[5]        ; 4.886 ; 4.909 ; 5.510 ; 5.517 ;
+; X[4]       ; S[6]        ; 5.603 ; 5.739 ; 6.256 ; 6.376 ;
+; X[4]       ; S[7]        ; 6.041 ; 6.052 ; 6.782 ; 6.813 ;
+; X[4]       ; S[8]        ; 6.055 ; 6.105 ; 6.845 ; 6.879 ;
+; X[4]       ; S[9]        ; 6.335 ; 6.357 ; 7.117 ; 7.139 ;
+; X[5]       ; Cout        ; 6.151 ;       ;       ; 6.939 ;
+; X[5]       ; S[5]        ; 4.721 ; 4.742 ; 5.340 ; 5.345 ;
+; X[5]       ; S[6]        ; 5.336 ; 5.472 ; 5.970 ; 6.090 ;
+; X[5]       ; S[7]        ; 5.774 ; 5.785 ; 6.496 ; 6.527 ;
+; X[5]       ; S[8]        ; 5.788 ; 5.838 ; 6.559 ; 6.593 ;
+; X[5]       ; S[9]        ; 6.068 ; 6.090 ; 6.831 ; 6.853 ;
+; X[6]       ; Cout        ; 5.838 ;       ;       ; 6.590 ;
+; X[6]       ; S[6]        ; 5.065 ; 5.203 ; 5.660 ; 5.782 ;
+; X[6]       ; S[7]        ; 5.461 ; 5.472 ; 6.147 ; 6.178 ;
+; X[6]       ; S[8]        ; 5.475 ; 5.525 ; 6.210 ; 6.244 ;
+; X[6]       ; S[9]        ; 5.755 ; 5.777 ; 6.482 ; 6.504 ;
+; X[7]       ; Cout        ; 4.960 ;       ;       ; 5.590 ;
+; X[7]       ; S[7]        ; 4.580 ; 4.596 ; 5.167 ; 5.176 ;
+; X[7]       ; S[8]        ; 4.597 ; 4.647 ; 5.210 ; 5.244 ;
+; X[7]       ; S[9]        ; 4.877 ; 4.899 ; 5.482 ; 5.504 ;
+; X[8]       ; Cout        ; 4.782 ;       ;       ; 5.409 ;
+; X[8]       ; S[8]        ; 4.421 ; 4.460 ; 5.006 ; 5.064 ;
+; X[8]       ; S[9]        ; 4.806 ; 4.828 ; 5.391 ; 5.413 ;
+; X[9]       ; Cout        ; 3.480 ;       ;       ; 3.768 ;
+; X[9]       ; S[9]        ; 3.812 ; 3.834 ; 4.092 ; 4.113 ;
+; Y[0]       ; Cout        ; 7.026 ;       ;       ; 7.932 ;
+; Y[0]       ; S[0]        ; 4.666 ; 4.725 ; 5.287 ; 5.365 ;
+; Y[0]       ; S[1]        ; 4.730 ; 4.773 ; 5.351 ; 5.414 ;
+; Y[0]       ; S[2]        ; 4.782 ; 4.828 ; 5.451 ; 5.481 ;
+; Y[0]       ; S[3]        ; 5.135 ; 5.205 ; 5.811 ; 5.874 ;
+; Y[0]       ; S[4]        ; 5.338 ; 5.409 ; 6.014 ; 6.104 ;
+; Y[0]       ; S[5]        ; 5.494 ; 5.517 ; 6.217 ; 6.224 ;
+; Y[0]       ; S[6]        ; 6.211 ; 6.347 ; 6.963 ; 7.083 ;
+; Y[0]       ; S[7]        ; 6.649 ; 6.660 ; 7.489 ; 7.520 ;
+; Y[0]       ; S[8]        ; 6.663 ; 6.713 ; 7.552 ; 7.586 ;
+; Y[0]       ; S[9]        ; 6.943 ; 6.965 ; 7.824 ; 7.846 ;
+; Y[1]       ; Cout        ; 6.827 ;       ;       ; 7.684 ;
+; Y[1]       ; S[1]        ; 4.532 ; 4.585 ; 5.129 ; 5.181 ;
+; Y[1]       ; S[2]        ; 4.583 ; 4.629 ; 5.203 ; 5.233 ;
+; Y[1]       ; S[3]        ; 4.936 ; 5.006 ; 5.563 ; 5.626 ;
+; Y[1]       ; S[4]        ; 5.139 ; 5.210 ; 5.766 ; 5.856 ;
+; Y[1]       ; S[5]        ; 5.295 ; 5.318 ; 5.969 ; 5.976 ;
+; Y[1]       ; S[6]        ; 6.012 ; 6.148 ; 6.715 ; 6.835 ;
+; Y[1]       ; S[7]        ; 6.450 ; 6.461 ; 7.241 ; 7.272 ;
+; Y[1]       ; S[8]        ; 6.464 ; 6.514 ; 7.304 ; 7.338 ;
+; Y[1]       ; S[9]        ; 6.744 ; 6.766 ; 7.576 ; 7.598 ;
+; Y[2]       ; Cout        ; 6.878 ;       ;       ; 7.763 ;
+; Y[2]       ; S[2]        ; 4.530 ; 4.565 ; 5.148 ; 5.202 ;
+; Y[2]       ; S[3]        ; 4.987 ; 5.057 ; 5.642 ; 5.705 ;
+; Y[2]       ; S[4]        ; 5.190 ; 5.261 ; 5.845 ; 5.935 ;
+; Y[2]       ; S[5]        ; 5.346 ; 5.369 ; 6.048 ; 6.055 ;
+; Y[2]       ; S[6]        ; 6.063 ; 6.199 ; 6.794 ; 6.914 ;
+; Y[2]       ; S[7]        ; 6.501 ; 6.512 ; 7.320 ; 7.351 ;
+; Y[2]       ; S[8]        ; 6.515 ; 6.565 ; 7.383 ; 7.417 ;
+; Y[2]       ; S[9]        ; 6.795 ; 6.817 ; 7.655 ; 7.677 ;
+; Y[3]       ; Cout        ; 6.659 ;       ;       ; 7.520 ;
+; Y[3]       ; S[3]        ; 4.769 ; 4.834 ; 5.377 ; 5.462 ;
+; Y[3]       ; S[4]        ; 4.971 ; 5.042 ; 5.602 ; 5.692 ;
+; Y[3]       ; S[5]        ; 5.127 ; 5.150 ; 5.805 ; 5.812 ;
+; Y[3]       ; S[6]        ; 5.844 ; 5.980 ; 6.551 ; 6.671 ;
+; Y[3]       ; S[7]        ; 6.282 ; 6.293 ; 7.077 ; 7.108 ;
+; Y[3]       ; S[8]        ; 6.296 ; 6.346 ; 7.140 ; 7.174 ;
+; Y[3]       ; S[9]        ; 6.576 ; 6.598 ; 7.412 ; 7.434 ;
+; Y[4]       ; Cout        ; 6.509 ;       ;       ; 7.346 ;
+; Y[4]       ; S[4]        ; 4.822 ; 4.904 ; 5.454 ; 5.520 ;
+; Y[4]       ; S[5]        ; 4.977 ; 5.000 ; 5.631 ; 5.638 ;
+; Y[4]       ; S[6]        ; 5.694 ; 5.830 ; 6.377 ; 6.497 ;
+; Y[4]       ; S[7]        ; 6.132 ; 6.143 ; 6.903 ; 6.934 ;
+; Y[4]       ; S[8]        ; 6.146 ; 6.196 ; 6.966 ; 7.000 ;
+; Y[4]       ; S[9]        ; 6.426 ; 6.448 ; 7.238 ; 7.260 ;
+; Y[5]       ; Cout        ; 6.134 ;       ;       ; 6.928 ;
+; Y[5]       ; S[5]        ; 4.601 ; 4.613 ; 5.189 ; 5.220 ;
+; Y[5]       ; S[6]        ; 5.319 ; 5.455 ; 5.959 ; 6.079 ;
+; Y[5]       ; S[7]        ; 5.757 ; 5.768 ; 6.485 ; 6.516 ;
+; Y[5]       ; S[8]        ; 5.771 ; 5.821 ; 6.548 ; 6.582 ;
+; Y[5]       ; S[9]        ; 6.051 ; 6.073 ; 6.820 ; 6.842 ;
+; Y[6]       ; Cout        ; 5.765 ;       ;       ; 6.517 ;
+; Y[6]       ; S[6]        ; 5.024 ; 5.151 ; 5.604 ; 5.750 ;
+; Y[6]       ; S[7]        ; 5.388 ; 5.399 ; 6.074 ; 6.105 ;
+; Y[6]       ; S[8]        ; 5.402 ; 5.452 ; 6.137 ; 6.171 ;
+; Y[6]       ; S[9]        ; 5.682 ; 5.704 ; 6.409 ; 6.431 ;
+; Y[7]       ; Cout        ; 5.192 ;       ;       ; 5.846 ;
+; Y[7]       ; S[7]        ; 4.812 ; 4.844 ; 5.447 ; 5.446 ;
+; Y[7]       ; S[8]        ; 4.829 ; 4.879 ; 5.466 ; 5.500 ;
+; Y[7]       ; S[9]        ; 5.109 ; 5.131 ; 5.738 ; 5.760 ;
+; Y[8]       ; Cout        ; 4.689 ;       ;       ; 5.276 ;
+; Y[8]       ; S[8]        ; 4.330 ; 4.378 ; 4.904 ; 4.936 ;
+; Y[8]       ; S[9]        ; 4.721 ; 4.743 ; 5.303 ; 5.308 ;
+; Y[9]       ; Cout        ; 3.532 ;       ;       ; 3.803 ;
+; Y[9]       ; S[9]        ; 3.557 ; 3.580 ; 3.853 ; 3.832 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; EN         ; S[0]        ; 8.330  ;        ;        ; 8.707  ;
+; EN         ; S[1]        ; 8.376  ;        ;        ; 8.772  ;
+; EN         ; S[2]        ; 8.046  ;        ;        ; 8.418  ;
+; EN         ; S[3]        ; 8.524  ;        ;        ; 8.924  ;
+; EN         ; S[4]        ; 8.542  ;        ;        ; 8.959  ;
+; EN         ; S[5]        ; 8.247  ;        ;        ; 8.673  ;
+; EN         ; S[6]        ; 9.200  ;        ;        ; 9.649  ;
+; EN         ; S[7]        ; 8.619  ;        ;        ; 9.032  ;
+; EN         ; S[8]        ; 8.018  ;        ;        ; 8.364  ;
+; EN         ; S[9]        ; 8.157  ;        ;        ; 8.535  ;
+; X[0]       ; Cout        ; 13.242 ;        ;        ; 14.031 ;
+; X[0]       ; S[0]        ; 8.346  ; 8.263  ; 8.860  ; 8.727  ;
+; X[0]       ; S[1]        ; 8.521  ; 8.440  ; 9.029  ; 8.870  ;
+; X[0]       ; S[2]        ; 8.612  ; 8.517  ; 9.179  ; 9.032  ;
+; X[0]       ; S[3]        ; 9.549  ; 9.467  ; 10.120 ; 9.981  ;
+; X[0]       ; S[4]        ; 9.891  ; 9.811  ; 10.472 ; 10.423 ;
+; X[0]       ; S[5]        ; 10.110 ; 10.069 ; 10.778 ; 10.685 ;
+; X[0]       ; S[6]        ; 11.628 ; 11.607 ; 12.323 ; 12.267 ;
+; X[0]       ; S[7]        ; 12.380 ; 12.282 ; 13.114 ; 13.048 ;
+; X[0]       ; S[8]        ; 12.546 ; 12.469 ; 13.369 ; 13.240 ;
+; X[0]       ; S[9]        ; 13.037 ; 12.949 ; 13.813 ; 13.734 ;
+; X[1]       ; Cout        ; 10.881 ;        ;        ; 11.302 ;
+; X[1]       ; S[1]        ; 6.149  ; 6.027  ; 6.296  ; 6.165  ;
+; X[1]       ; S[2]        ; 6.251  ; 6.156  ; 6.450  ; 6.303  ;
+; X[1]       ; S[3]        ; 7.188  ; 7.106  ; 7.391  ; 7.252  ;
+; X[1]       ; S[4]        ; 7.530  ; 7.450  ; 7.743  ; 7.694  ;
+; X[1]       ; S[5]        ; 7.749  ; 7.708  ; 8.049  ; 7.956  ;
+; X[1]       ; S[6]        ; 9.267  ; 9.246  ; 9.594  ; 9.538  ;
+; X[1]       ; S[7]        ; 10.019 ; 9.921  ; 10.385 ; 10.319 ;
+; X[1]       ; S[8]        ; 10.185 ; 10.108 ; 10.640 ; 10.511 ;
+; X[1]       ; S[9]        ; 10.676 ; 10.588 ; 11.084 ; 11.005 ;
+; X[2]       ; Cout        ; 10.906 ;        ;        ; 11.330 ;
+; X[2]       ; S[2]        ; 6.036  ; 5.937  ; 6.174  ; 6.040  ;
+; X[2]       ; S[3]        ; 7.213  ; 7.131  ; 7.419  ; 7.280  ;
+; X[2]       ; S[4]        ; 7.555  ; 7.475  ; 7.771  ; 7.722  ;
+; X[2]       ; S[5]        ; 7.774  ; 7.733  ; 8.077  ; 7.984  ;
+; X[2]       ; S[6]        ; 9.292  ; 9.271  ; 9.622  ; 9.566  ;
+; X[2]       ; S[7]        ; 10.044 ; 9.946  ; 10.413 ; 10.347 ;
+; X[2]       ; S[8]        ; 10.210 ; 10.133 ; 10.668 ; 10.539 ;
+; X[2]       ; S[9]        ; 10.701 ; 10.613 ; 11.112 ; 11.033 ;
+; X[3]       ; Cout        ; 12.288 ;        ;        ; 12.987 ;
+; X[3]       ; S[3]        ; 8.597  ; 8.512  ; 9.069  ; 8.940  ;
+; X[3]       ; S[4]        ; 8.937  ; 8.857  ; 9.428  ; 9.379  ;
+; X[3]       ; S[5]        ; 9.156  ; 9.115  ; 9.734  ; 9.641  ;
+; X[3]       ; S[6]        ; 10.674 ; 10.653 ; 11.279 ; 11.223 ;
+; X[3]       ; S[7]        ; 11.426 ; 11.328 ; 12.070 ; 12.004 ;
+; X[3]       ; S[8]        ; 11.592 ; 11.515 ; 12.325 ; 12.196 ;
+; X[3]       ; S[9]        ; 12.083 ; 11.995 ; 12.769 ; 12.690 ;
+; X[4]       ; Cout        ; 11.878 ;        ;        ; 12.538 ;
+; X[4]       ; S[4]        ; 8.490  ; 8.437  ; 8.958  ; 8.870  ;
+; X[4]       ; S[5]        ; 8.746  ; 8.705  ; 9.285  ; 9.192  ;
+; X[4]       ; S[6]        ; 10.264 ; 10.243 ; 10.830 ; 10.774 ;
+; X[4]       ; S[7]        ; 11.016 ; 10.918 ; 11.621 ; 11.555 ;
+; X[4]       ; S[8]        ; 11.182 ; 11.105 ; 11.876 ; 11.747 ;
+; X[4]       ; S[9]        ; 11.673 ; 11.585 ; 12.320 ; 12.241 ;
+; X[5]       ; Cout        ; 11.259 ;        ;        ; 11.854 ;
+; X[5]       ; S[5]        ; 8.371  ; 8.326  ; 8.863  ; 8.783  ;
+; X[5]       ; S[6]        ; 9.645  ; 9.624  ; 10.146 ; 10.090 ;
+; X[5]       ; S[7]        ; 10.397 ; 10.299 ; 10.937 ; 10.871 ;
+; X[5]       ; S[8]        ; 10.563 ; 10.486 ; 11.192 ; 11.063 ;
+; X[5]       ; S[9]        ; 11.054 ; 10.966 ; 11.636 ; 11.557 ;
+; X[6]       ; Cout        ; 10.580 ;        ;        ; 11.148 ;
+; X[6]       ; S[6]        ; 9.093  ; 9.076  ; 9.587  ; 9.518  ;
+; X[6]       ; S[7]        ; 9.718  ; 9.620  ; 10.231 ; 10.165 ;
+; X[6]       ; S[8]        ; 9.884  ; 9.807  ; 10.486 ; 10.357 ;
+; X[6]       ; S[9]        ; 10.375 ; 10.287 ; 10.930 ; 10.851 ;
+; X[7]       ; Cout        ; 8.952  ;        ;        ; 9.422  ;
+; X[7]       ; S[7]        ; 8.088  ; 7.992  ; 8.540  ; 8.435  ;
+; X[7]       ; S[8]        ; 8.256  ; 8.179  ; 8.760  ; 8.631  ;
+; X[7]       ; S[9]        ; 8.747  ; 8.659  ; 9.204  ; 9.125  ;
+; X[8]       ; Cout        ; 8.538  ;        ;        ; 8.987  ;
+; X[8]       ; S[8]        ; 7.883  ; 7.775  ; 8.341  ; 8.264  ;
+; X[8]       ; S[9]        ; 8.579  ; 8.493  ; 9.068  ; 8.963  ;
+; X[9]       ; Cout        ; 5.998  ;        ;        ; 6.013  ;
+; X[9]       ; S[9]        ; 6.761  ; 6.656  ; 6.858  ; 6.756  ;
+; Y[0]       ; Cout        ; 13.236 ;        ;        ; 14.047 ;
+; Y[0]       ; S[0]        ; 8.360  ; 8.239  ; 8.859  ; 8.769  ;
+; Y[0]       ; S[1]        ; 8.500  ; 8.376  ; 8.998  ; 8.906  ;
+; Y[0]       ; S[2]        ; 8.606  ; 8.511  ; 9.195  ; 9.048  ;
+; Y[0]       ; S[3]        ; 9.543  ; 9.461  ; 10.136 ; 9.997  ;
+; Y[0]       ; S[4]        ; 9.885  ; 9.805  ; 10.488 ; 10.439 ;
+; Y[0]       ; S[5]        ; 10.104 ; 10.063 ; 10.794 ; 10.701 ;
+; Y[0]       ; S[6]        ; 11.622 ; 11.601 ; 12.339 ; 12.283 ;
+; Y[0]       ; S[7]        ; 12.374 ; 12.276 ; 13.130 ; 13.064 ;
+; Y[0]       ; S[8]        ; 12.540 ; 12.463 ; 13.385 ; 13.256 ;
+; Y[0]       ; S[9]        ; 13.031 ; 12.943 ; 13.829 ; 13.750 ;
+; Y[1]       ; Cout        ; 12.940 ;        ;        ; 13.716 ;
+; Y[1]       ; S[1]        ; 8.233  ; 8.135  ; 8.697  ; 8.596  ;
+; Y[1]       ; S[2]        ; 8.310  ; 8.215  ; 8.864  ; 8.717  ;
+; Y[1]       ; S[3]        ; 9.247  ; 9.165  ; 9.805  ; 9.666  ;
+; Y[1]       ; S[4]        ; 9.589  ; 9.509  ; 10.157 ; 10.108 ;
+; Y[1]       ; S[5]        ; 9.808  ; 9.767  ; 10.463 ; 10.370 ;
+; Y[1]       ; S[6]        ; 11.326 ; 11.305 ; 12.008 ; 11.952 ;
+; Y[1]       ; S[7]        ; 12.078 ; 11.980 ; 12.799 ; 12.733 ;
+; Y[1]       ; S[8]        ; 12.244 ; 12.167 ; 13.054 ; 12.925 ;
+; Y[1]       ; S[9]        ; 12.735 ; 12.647 ; 13.498 ; 13.419 ;
+; Y[2]       ; Cout        ; 13.046 ;        ;        ; 13.867 ;
+; Y[2]       ; S[2]        ; 8.079  ; 7.953  ; 8.571  ; 8.476  ;
+; Y[2]       ; S[3]        ; 9.353  ; 9.271  ; 9.956  ; 9.817  ;
+; Y[2]       ; S[4]        ; 9.695  ; 9.615  ; 10.308 ; 10.259 ;
+; Y[2]       ; S[5]        ; 9.914  ; 9.873  ; 10.614 ; 10.521 ;
+; Y[2]       ; S[6]        ; 11.432 ; 11.411 ; 12.159 ; 12.103 ;
+; Y[2]       ; S[7]        ; 12.184 ; 12.086 ; 12.950 ; 12.884 ;
+; Y[2]       ; S[8]        ; 12.350 ; 12.273 ; 13.205 ; 13.076 ;
+; Y[2]       ; S[9]        ; 12.841 ; 12.753 ; 13.649 ; 13.570 ;
+; Y[3]       ; Cout        ; 12.282 ;        ;        ; 13.006 ;
+; Y[3]       ; S[3]        ; 8.578  ; 8.459  ; 9.064  ; 8.977  ;
+; Y[3]       ; S[4]        ; 8.931  ; 8.851  ; 9.447  ; 9.398  ;
+; Y[3]       ; S[5]        ; 9.150  ; 9.109  ; 9.753  ; 9.660  ;
+; Y[3]       ; S[6]        ; 10.668 ; 10.647 ; 11.298 ; 11.242 ;
+; Y[3]       ; S[7]        ; 11.420 ; 11.322 ; 12.089 ; 12.023 ;
+; Y[3]       ; S[8]        ; 11.586 ; 11.509 ; 12.344 ; 12.215 ;
+; Y[3]       ; S[9]        ; 12.077 ; 11.989 ; 12.788 ; 12.709 ;
+; Y[4]       ; Cout        ; 12.015 ;        ;        ; 12.729 ;
+; Y[4]       ; S[4]        ; 8.625  ; 8.576  ; 9.158  ; 9.057  ;
+; Y[4]       ; S[5]        ; 8.883  ; 8.842  ; 9.476  ; 9.383  ;
+; Y[4]       ; S[6]        ; 10.401 ; 10.380 ; 11.021 ; 10.965 ;
+; Y[4]       ; S[7]        ; 11.153 ; 11.055 ; 11.812 ; 11.746 ;
+; Y[4]       ; S[8]        ; 11.319 ; 11.242 ; 12.067 ; 11.938 ;
+; Y[4]       ; S[9]        ; 11.810 ; 11.722 ; 12.511 ; 12.432 ;
+; Y[5]       ; Cout        ; 11.229 ;        ;        ; 11.852 ;
+; Y[5]       ; S[5]        ; 8.132  ; 8.060  ; 8.584  ; 8.543  ;
+; Y[5]       ; S[6]        ; 9.615  ; 9.594  ; 10.144 ; 10.088 ;
+; Y[5]       ; S[7]        ; 10.367 ; 10.269 ; 10.935 ; 10.869 ;
+; Y[5]       ; S[8]        ; 10.533 ; 10.456 ; 11.190 ; 11.061 ;
+; Y[5]       ; S[9]        ; 11.024 ; 10.936 ; 11.634 ; 11.555 ;
+; Y[6]       ; Cout        ; 10.487 ;        ;        ; 11.035 ;
+; Y[6]       ; S[6]        ; 9.057  ; 9.009  ; 9.487  ; 9.470  ;
+; Y[6]       ; S[7]        ; 9.625  ; 9.527  ; 10.118 ; 10.052 ;
+; Y[6]       ; S[8]        ; 9.791  ; 9.714  ; 10.373 ; 10.244 ;
+; Y[6]       ; S[9]        ; 10.282 ; 10.194 ; 10.817 ; 10.738 ;
+; Y[7]       ; Cout        ; 9.414  ;        ;        ; 9.931  ;
+; Y[7]       ; S[7]        ; 8.552  ; 8.495  ; 9.053  ; 8.971  ;
+; Y[7]       ; S[8]        ; 8.718  ; 8.641  ; 9.269  ; 9.140  ;
+; Y[7]       ; S[9]        ; 9.209  ; 9.121  ; 9.713  ; 9.634  ;
+; Y[8]       ; Cout        ; 8.434  ;        ;        ; 8.866  ;
+; Y[8]       ; S[8]        ; 7.744  ; 7.663  ; 8.201  ; 8.085  ;
+; Y[8]       ; S[9]        ; 8.516  ; 8.411  ; 8.901  ; 8.840  ;
+; Y[9]       ; Cout        ; 6.153  ;        ;        ; 6.185  ;
+; Y[9]       ; S[9]        ; 6.151  ; 6.111  ; 6.276  ; 6.159  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; EN         ; S[0]        ; 4.648 ;       ;       ; 5.327 ;
+; EN         ; S[1]        ; 4.661 ;       ;       ; 5.320 ;
+; EN         ; S[2]        ; 4.493 ;       ;       ; 5.149 ;
+; EN         ; S[3]        ; 4.743 ;       ;       ; 5.423 ;
+; EN         ; S[4]        ; 4.776 ;       ;       ; 5.467 ;
+; EN         ; S[5]        ; 4.674 ;       ;       ; 5.307 ;
+; EN         ; S[6]        ; 5.124 ;       ;       ; 5.872 ;
+; EN         ; S[7]        ; 4.843 ;       ;       ; 5.472 ;
+; EN         ; S[8]        ; 4.488 ;       ;       ; 5.133 ;
+; EN         ; S[9]        ; 4.612 ;       ;       ; 5.226 ;
+; X[0]       ; Cout        ; 6.992 ;       ;       ; 7.865 ;
+; X[0]       ; S[0]        ; 4.629 ; 4.700 ; 5.251 ; 5.305 ;
+; X[0]       ; S[1]        ; 4.693 ; 4.748 ; 5.313 ; 5.367 ;
+; X[0]       ; S[2]        ; 4.748 ; 4.794 ; 5.384 ; 5.414 ;
+; X[0]       ; S[3]        ; 5.101 ; 5.171 ; 5.744 ; 5.807 ;
+; X[0]       ; S[4]        ; 5.304 ; 5.375 ; 5.947 ; 6.037 ;
+; X[0]       ; S[5]        ; 5.460 ; 5.483 ; 6.150 ; 6.157 ;
+; X[0]       ; S[6]        ; 6.177 ; 6.313 ; 6.896 ; 7.016 ;
+; X[0]       ; S[7]        ; 6.615 ; 6.626 ; 7.422 ; 7.453 ;
+; X[0]       ; S[8]        ; 6.629 ; 6.679 ; 7.485 ; 7.519 ;
+; X[0]       ; S[9]        ; 6.909 ; 6.931 ; 7.757 ; 7.779 ;
+; X[1]       ; Cout        ; 5.770 ;       ;       ; 6.336 ;
+; X[1]       ; S[1]        ; 3.476 ; 3.524 ; 3.780 ; 3.821 ;
+; X[1]       ; S[2]        ; 3.526 ; 3.572 ; 3.855 ; 3.885 ;
+; X[1]       ; S[3]        ; 3.879 ; 3.949 ; 4.215 ; 4.278 ;
+; X[1]       ; S[4]        ; 4.082 ; 4.153 ; 4.418 ; 4.508 ;
+; X[1]       ; S[5]        ; 4.238 ; 4.261 ; 4.621 ; 4.628 ;
+; X[1]       ; S[6]        ; 4.955 ; 5.091 ; 5.367 ; 5.487 ;
+; X[1]       ; S[7]        ; 5.393 ; 5.404 ; 5.893 ; 5.924 ;
+; X[1]       ; S[8]        ; 5.407 ; 5.457 ; 5.956 ; 5.990 ;
+; X[1]       ; S[9]        ; 5.687 ; 5.709 ; 6.228 ; 6.250 ;
+; X[2]       ; Cout        ; 5.893 ;       ;       ; 6.425 ;
+; X[2]       ; S[2]        ; 3.413 ; 3.457 ; 3.704 ; 3.732 ;
+; X[2]       ; S[3]        ; 3.997 ; 4.074 ; 4.309 ; 4.381 ;
+; X[2]       ; S[4]        ; 4.205 ; 4.276 ; 4.507 ; 4.597 ;
+; X[2]       ; S[5]        ; 4.361 ; 4.384 ; 4.710 ; 4.717 ;
+; X[2]       ; S[6]        ; 5.078 ; 5.214 ; 5.456 ; 5.576 ;
+; X[2]       ; S[7]        ; 5.516 ; 5.527 ; 5.982 ; 6.013 ;
+; X[2]       ; S[8]        ; 5.530 ; 5.580 ; 6.045 ; 6.079 ;
+; X[2]       ; S[9]        ; 5.810 ; 5.832 ; 6.317 ; 6.339 ;
+; X[3]       ; Cout        ; 6.645 ;       ;       ; 7.475 ;
+; X[3]       ; S[3]        ; 4.756 ; 4.833 ; 5.356 ; 5.415 ;
+; X[3]       ; S[4]        ; 4.957 ; 5.028 ; 5.557 ; 5.647 ;
+; X[3]       ; S[5]        ; 5.113 ; 5.136 ; 5.760 ; 5.767 ;
+; X[3]       ; S[6]        ; 5.830 ; 5.966 ; 6.506 ; 6.626 ;
+; X[3]       ; S[7]        ; 6.268 ; 6.279 ; 7.032 ; 7.063 ;
+; X[3]       ; S[8]        ; 6.282 ; 6.332 ; 7.095 ; 7.129 ;
+; X[3]       ; S[9]        ; 6.562 ; 6.584 ; 7.367 ; 7.389 ;
+; X[4]       ; Cout        ; 6.418 ;       ;       ; 7.225 ;
+; X[4]       ; S[4]        ; 4.731 ; 4.811 ; 5.335 ; 5.399 ;
+; X[4]       ; S[5]        ; 4.886 ; 4.909 ; 5.510 ; 5.517 ;
+; X[4]       ; S[6]        ; 5.603 ; 5.739 ; 6.256 ; 6.376 ;
+; X[4]       ; S[7]        ; 6.041 ; 6.052 ; 6.782 ; 6.813 ;
+; X[4]       ; S[8]        ; 6.055 ; 6.105 ; 6.845 ; 6.879 ;
+; X[4]       ; S[9]        ; 6.335 ; 6.357 ; 7.117 ; 7.139 ;
+; X[5]       ; Cout        ; 6.151 ;       ;       ; 6.939 ;
+; X[5]       ; S[5]        ; 4.721 ; 4.742 ; 5.340 ; 5.345 ;
+; X[5]       ; S[6]        ; 5.336 ; 5.472 ; 5.970 ; 6.090 ;
+; X[5]       ; S[7]        ; 5.774 ; 5.785 ; 6.496 ; 6.527 ;
+; X[5]       ; S[8]        ; 5.788 ; 5.838 ; 6.559 ; 6.593 ;
+; X[5]       ; S[9]        ; 6.068 ; 6.090 ; 6.831 ; 6.853 ;
+; X[6]       ; Cout        ; 5.838 ;       ;       ; 6.590 ;
+; X[6]       ; S[6]        ; 5.065 ; 5.203 ; 5.660 ; 5.782 ;
+; X[6]       ; S[7]        ; 5.461 ; 5.472 ; 6.147 ; 6.178 ;
+; X[6]       ; S[8]        ; 5.475 ; 5.525 ; 6.210 ; 6.244 ;
+; X[6]       ; S[9]        ; 5.755 ; 5.777 ; 6.482 ; 6.504 ;
+; X[7]       ; Cout        ; 4.960 ;       ;       ; 5.590 ;
+; X[7]       ; S[7]        ; 4.580 ; 4.596 ; 5.167 ; 5.176 ;
+; X[7]       ; S[8]        ; 4.597 ; 4.647 ; 5.210 ; 5.244 ;
+; X[7]       ; S[9]        ; 4.877 ; 4.899 ; 5.482 ; 5.504 ;
+; X[8]       ; Cout        ; 4.782 ;       ;       ; 5.409 ;
+; X[8]       ; S[8]        ; 4.421 ; 4.460 ; 5.006 ; 5.064 ;
+; X[8]       ; S[9]        ; 4.806 ; 4.828 ; 5.391 ; 5.413 ;
+; X[9]       ; Cout        ; 3.480 ;       ;       ; 3.768 ;
+; X[9]       ; S[9]        ; 3.812 ; 3.834 ; 4.092 ; 4.113 ;
+; Y[0]       ; Cout        ; 7.026 ;       ;       ; 7.932 ;
+; Y[0]       ; S[0]        ; 4.666 ; 4.725 ; 5.287 ; 5.365 ;
+; Y[0]       ; S[1]        ; 4.730 ; 4.773 ; 5.351 ; 5.414 ;
+; Y[0]       ; S[2]        ; 4.782 ; 4.828 ; 5.451 ; 5.481 ;
+; Y[0]       ; S[3]        ; 5.135 ; 5.205 ; 5.811 ; 5.874 ;
+; Y[0]       ; S[4]        ; 5.338 ; 5.409 ; 6.014 ; 6.104 ;
+; Y[0]       ; S[5]        ; 5.494 ; 5.517 ; 6.217 ; 6.224 ;
+; Y[0]       ; S[6]        ; 6.211 ; 6.347 ; 6.963 ; 7.083 ;
+; Y[0]       ; S[7]        ; 6.649 ; 6.660 ; 7.489 ; 7.520 ;
+; Y[0]       ; S[8]        ; 6.663 ; 6.713 ; 7.552 ; 7.586 ;
+; Y[0]       ; S[9]        ; 6.943 ; 6.965 ; 7.824 ; 7.846 ;
+; Y[1]       ; Cout        ; 6.827 ;       ;       ; 7.684 ;
+; Y[1]       ; S[1]        ; 4.532 ; 4.585 ; 5.129 ; 5.181 ;
+; Y[1]       ; S[2]        ; 4.583 ; 4.629 ; 5.203 ; 5.233 ;
+; Y[1]       ; S[3]        ; 4.936 ; 5.006 ; 5.563 ; 5.626 ;
+; Y[1]       ; S[4]        ; 5.139 ; 5.210 ; 5.766 ; 5.856 ;
+; Y[1]       ; S[5]        ; 5.295 ; 5.318 ; 5.969 ; 5.976 ;
+; Y[1]       ; S[6]        ; 6.012 ; 6.148 ; 6.715 ; 6.835 ;
+; Y[1]       ; S[7]        ; 6.450 ; 6.461 ; 7.241 ; 7.272 ;
+; Y[1]       ; S[8]        ; 6.464 ; 6.514 ; 7.304 ; 7.338 ;
+; Y[1]       ; S[9]        ; 6.744 ; 6.766 ; 7.576 ; 7.598 ;
+; Y[2]       ; Cout        ; 6.878 ;       ;       ; 7.763 ;
+; Y[2]       ; S[2]        ; 4.530 ; 4.565 ; 5.148 ; 5.202 ;
+; Y[2]       ; S[3]        ; 4.987 ; 5.057 ; 5.642 ; 5.705 ;
+; Y[2]       ; S[4]        ; 5.190 ; 5.261 ; 5.845 ; 5.935 ;
+; Y[2]       ; S[5]        ; 5.346 ; 5.369 ; 6.048 ; 6.055 ;
+; Y[2]       ; S[6]        ; 6.063 ; 6.199 ; 6.794 ; 6.914 ;
+; Y[2]       ; S[7]        ; 6.501 ; 6.512 ; 7.320 ; 7.351 ;
+; Y[2]       ; S[8]        ; 6.515 ; 6.565 ; 7.383 ; 7.417 ;
+; Y[2]       ; S[9]        ; 6.795 ; 6.817 ; 7.655 ; 7.677 ;
+; Y[3]       ; Cout        ; 6.659 ;       ;       ; 7.520 ;
+; Y[3]       ; S[3]        ; 4.769 ; 4.834 ; 5.377 ; 5.462 ;
+; Y[3]       ; S[4]        ; 4.971 ; 5.042 ; 5.602 ; 5.692 ;
+; Y[3]       ; S[5]        ; 5.127 ; 5.150 ; 5.805 ; 5.812 ;
+; Y[3]       ; S[6]        ; 5.844 ; 5.980 ; 6.551 ; 6.671 ;
+; Y[3]       ; S[7]        ; 6.282 ; 6.293 ; 7.077 ; 7.108 ;
+; Y[3]       ; S[8]        ; 6.296 ; 6.346 ; 7.140 ; 7.174 ;
+; Y[3]       ; S[9]        ; 6.576 ; 6.598 ; 7.412 ; 7.434 ;
+; Y[4]       ; Cout        ; 6.509 ;       ;       ; 7.346 ;
+; Y[4]       ; S[4]        ; 4.822 ; 4.904 ; 5.454 ; 5.520 ;
+; Y[4]       ; S[5]        ; 4.977 ; 5.000 ; 5.631 ; 5.638 ;
+; Y[4]       ; S[6]        ; 5.694 ; 5.830 ; 6.377 ; 6.497 ;
+; Y[4]       ; S[7]        ; 6.132 ; 6.143 ; 6.903 ; 6.934 ;
+; Y[4]       ; S[8]        ; 6.146 ; 6.196 ; 6.966 ; 7.000 ;
+; Y[4]       ; S[9]        ; 6.426 ; 6.448 ; 7.238 ; 7.260 ;
+; Y[5]       ; Cout        ; 6.134 ;       ;       ; 6.928 ;
+; Y[5]       ; S[5]        ; 4.601 ; 4.613 ; 5.189 ; 5.220 ;
+; Y[5]       ; S[6]        ; 5.319 ; 5.455 ; 5.959 ; 6.079 ;
+; Y[5]       ; S[7]        ; 5.757 ; 5.768 ; 6.485 ; 6.516 ;
+; Y[5]       ; S[8]        ; 5.771 ; 5.821 ; 6.548 ; 6.582 ;
+; Y[5]       ; S[9]        ; 6.051 ; 6.073 ; 6.820 ; 6.842 ;
+; Y[6]       ; Cout        ; 5.765 ;       ;       ; 6.517 ;
+; Y[6]       ; S[6]        ; 5.024 ; 5.151 ; 5.604 ; 5.750 ;
+; Y[6]       ; S[7]        ; 5.388 ; 5.399 ; 6.074 ; 6.105 ;
+; Y[6]       ; S[8]        ; 5.402 ; 5.452 ; 6.137 ; 6.171 ;
+; Y[6]       ; S[9]        ; 5.682 ; 5.704 ; 6.409 ; 6.431 ;
+; Y[7]       ; Cout        ; 5.192 ;       ;       ; 5.846 ;
+; Y[7]       ; S[7]        ; 4.812 ; 4.844 ; 5.447 ; 5.446 ;
+; Y[7]       ; S[8]        ; 4.829 ; 4.879 ; 5.466 ; 5.500 ;
+; Y[7]       ; S[9]        ; 5.109 ; 5.131 ; 5.738 ; 5.760 ;
+; Y[8]       ; Cout        ; 4.689 ;       ;       ; 5.276 ;
+; Y[8]       ; S[8]        ; 4.330 ; 4.378 ; 4.904 ; 4.936 ;
+; Y[8]       ; S[9]        ; 4.721 ; 4.743 ; 5.303 ; 5.308 ;
+; Y[9]       ; Cout        ; 3.532 ;       ;       ; 3.803 ;
+; Y[9]       ; S[9]        ; 3.557 ; 3.580 ; 3.853 ; 3.832 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Cout          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[9]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[8]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[7]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[6]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[5]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[4]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[3]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[2]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[1]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S[0]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------------+
+; Input Transition Times                                            ;
++----------------+--------------+-----------------+-----------------+
+; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------------+--------------+-----------------+-----------------+
+; Y[9]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[9]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[8]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[7]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[7]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[6]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[5]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[5]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[4]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[2]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[0]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[0]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[1]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[1]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[2]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y[3]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[3]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[4]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[6]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X[8]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; EN             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; S[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; S[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; S[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; S[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; S[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; S[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.94e-09 V                   ; 2.39 V              ; -0.0344 V           ; 0.156 V                              ; 0.089 V                              ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.94e-09 V                  ; 2.39 V             ; -0.0344 V          ; 0.156 V                             ; 0.089 V                             ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; S[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; S[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; S[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; S[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; S[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; S[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00439 V          ; 0.088 V                              ; 0.007 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00439 V         ; 0.088 V                             ; 0.007 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; S[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; S[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; S[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; S[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; S[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; S[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0542 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0542 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 21    ; 21   ;
+; Unconstrained Input Port Paths  ; 140   ; 140  ;
+; Unconstrained Output Ports      ; 11    ; 11   ;
+; Unconstrained Output Port Paths ; 140   ; 140  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:20:13 2016
+Info: Command: quartus_sta ten_bit_adder -c ten_bit_adder
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_bit_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 532 megabytes
+    Info: Processing ended: Thu Feb 18 22:20:15 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/ten_bit_adder/output_files/ten_bit_adder.sta.summary b/ten_bit_adder/output_files/ten_bit_adder.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/ten_bit_adder/output_files/ten_bit_adder.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder.sft b/ten_bit_adder/simulation/modelsim/ten_bit_adder.sft
new file mode 100644
index 0000000..5c405dc
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {ten_bit_adder_6_1200mv_85c_slow.vho ten_bit_adder_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {ten_bit_adder_6_1200mv_0c_slow.vho ten_bit_adder_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {ten_bit_adder_min_1200mv_0c_fast.vho ten_bit_adder_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder.vho b/ten_bit_adder/simulation/modelsim/ten_bit_adder.vho
new file mode 100644
index 0000000..7aea7bb
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder.vho
@@ -0,0 +1,923 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:20:18"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder IS
+    PORT (
+	Cout : OUT std_logic;
+	X : IN std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(9 DOWNTO 0);
+	S : OUT std_logic_vector(9 DOWNTO 0);
+	EN : IN std_logic
+	);
+END ten_bit_adder;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[9]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[8]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[7]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[6]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[5]	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[4]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[3]	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[2]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[1]	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[0]	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[9]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[9]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[8]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[7]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[7]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[6]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[5]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[5]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[6]	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[8]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- EN	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_S : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_EN : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S[9]~output_o\ : std_logic;
+SIGNAL \S[8]~output_o\ : std_logic;
+SIGNAL \S[7]~output_o\ : std_logic;
+SIGNAL \S[6]~output_o\ : std_logic;
+SIGNAL \S[5]~output_o\ : std_logic;
+SIGNAL \S[4]~output_o\ : std_logic;
+SIGNAL \S[3]~output_o\ : std_logic;
+SIGNAL \S[2]~output_o\ : std_logic;
+SIGNAL \S[1]~output_o\ : std_logic;
+SIGNAL \S[0]~output_o\ : std_logic;
+SIGNAL \Y[8]~input_o\ : std_logic;
+SIGNAL \Y[7]~input_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \inst10|inst3~1_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \Y[5]~input_o\ : std_logic;
+SIGNAL \X[5]~input_o\ : std_logic;
+SIGNAL \inst13|inst3~1_combout\ : std_logic;
+SIGNAL \X[6]~input_o\ : std_logic;
+SIGNAL \Y[6]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \X[7]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~1_combout\ : std_logic;
+SIGNAL \X[8]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \Y[9]~input_o\ : std_logic;
+SIGNAL \X[9]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~1_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+SIGNAL \EN~input_o\ : std_logic;
+SIGNAL \inst25~combout\ : std_logic;
+SIGNAL \inst24~combout\ : std_logic;
+SIGNAL \inst23~combout\ : std_logic;
+SIGNAL \inst22~combout\ : std_logic;
+SIGNAL \inst21~combout\ : std_logic;
+SIGNAL \inst20~combout\ : std_logic;
+SIGNAL \inst11|inst2~combout\ : std_logic;
+SIGNAL \inst19~combout\ : std_logic;
+SIGNAL \inst18~combout\ : std_logic;
+SIGNAL \inst9|inst2~0_combout\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X <= X;
+ww_Y <= Y;
+S <= ww_S;
+ww_EN <= EN;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X33_Y28_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~1_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y27_N2
+\S[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst25~combout\,
+	devoe => ww_devoe,
+	o => \S[9]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\S[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst24~combout\,
+	devoe => ww_devoe,
+	o => \S[8]~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N2
+\S[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~combout\,
+	devoe => ww_devoe,
+	o => \S[7]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\S[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst22~combout\,
+	devoe => ww_devoe,
+	o => \S[6]~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~combout\,
+	devoe => ww_devoe,
+	o => \S[5]~output_o\);
+
+-- Location: IOOBUF_X8_Y0_N2
+\S[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~combout\,
+	devoe => ww_devoe,
+	o => \S[4]~output_o\);
+
+-- Location: IOOBUF_X24_Y0_N9
+\S[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst19~combout\,
+	devoe => ww_devoe,
+	o => \S[3]~output_o\);
+
+-- Location: IOOBUF_X20_Y0_N2
+\S[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst18~combout\,
+	devoe => ww_devoe,
+	o => \S[2]~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N2
+\S[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~combout\,
+	devoe => ww_devoe,
+	o => \S[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N9
+\S[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~combout\,
+	devoe => ww_devoe,
+	o => \S[0]~output_o\);
+
+-- Location: IOIBUF_X22_Y31_N1
+\Y[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(8),
+	o => \Y[8]~input_o\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\Y[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(7),
+	o => \Y[7]~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\X[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\Y[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\X[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: IOIBUF_X14_Y0_N1
+\X[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N24
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\Y[1]~input_o\ & ((\X[1]~input_o\) # ((\X[0]~input_o\ & \Y[0]~input_o\)))) # (!\Y[1]~input_o\ & (\X[0]~input_o\ & (\Y[0]~input_o\ & \X[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N4
+\inst10|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~1_combout\ = (\X[2]~input_o\ & ((\Y[2]~input_o\) # (\inst9|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~1_combout\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\Y[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N2
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\Y[2]~input_o\ & \inst9|inst3~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N14
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\X[3]~input_o\ & ((\inst10|inst3~1_combout\) # ((\Y[3]~input_o\) # (\inst10|inst3~0_combout\)))) # (!\X[3]~input_o\ & (\Y[3]~input_o\ & ((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N16
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X[4]~input_o\ & ((\Y[4]~input_o\) # (\inst11|inst3~0_combout\))) # (!\X[4]~input_o\ & (\Y[4]~input_o\ & \inst11|inst3~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: IOIBUF_X14_Y0_N8
+\Y[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(5),
+	o => \Y[5]~input_o\);
+
+-- Location: IOIBUF_X33_Y14_N8
+\X[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(5),
+	o => \X[5]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N26
+\inst13|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~1_combout\ = (\inst13|inst3~0_combout\ & ((\Y[5]~input_o\) # (\X[5]~input_o\))) # (!\inst13|inst3~0_combout\ & (\Y[5]~input_o\ & \X[5]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \X[5]~input_o\,
+	combout => \inst13|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y10_N8
+\X[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(6),
+	o => \X[6]~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N8
+\Y[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(6),
+	o => \Y[6]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N28
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\inst13|inst3~1_combout\ & ((\X[6]~input_o\) # (\Y[6]~input_o\))) # (!\inst13|inst3~1_combout\ & (\X[6]~input_o\ & \Y[6]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datac => \X[6]~input_o\,
+	datad => \Y[6]~input_o\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y25_N1
+\X[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(7),
+	o => \X[7]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N0
+\inst15|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~1_combout\ = (\Y[7]~input_o\ & ((\inst15|inst3~0_combout\) # (\X[7]~input_o\))) # (!\Y[7]~input_o\ & (\inst15|inst3~0_combout\ & \X[7]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst15|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\X[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(8),
+	o => \X[8]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N26
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\Y[8]~input_o\ & ((\inst15|inst3~1_combout\) # (\X[8]~input_o\))) # (!\Y[8]~input_o\ & (\inst15|inst3~1_combout\ & \X[8]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(9),
+	o => \Y[9]~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\X[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(9),
+	o => \X[9]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N28
+\inst17|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~1_combout\ = (\inst17|inst3~0_combout\ & ((\Y[9]~input_o\) # (\X[9]~input_o\))) # (!\inst17|inst3~0_combout\ & (\Y[9]~input_o\ & \X[9]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst3~0_combout\,
+	datab => \Y[9]~input_o\,
+	datac => \X[9]~input_o\,
+	combout => \inst17|inst3~1_combout\);
+
+-- Location: LCCOMB_X20_Y28_N6
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X[9]~input_o\ $ (((\Y[8]~input_o\ & ((\X[8]~input_o\) # (\inst15|inst3~1_combout\))) # (!\Y[8]~input_o\ & (\X[8]~input_o\ & \inst15|inst3~1_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011001101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \X[9]~input_o\,
+	datac => \X[8]~input_o\,
+	datad => \inst15|inst3~1_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+-- Location: IOIBUF_X33_Y22_N8
+\EN~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_EN,
+	o => \EN~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N16
+inst25 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst25~combout\ = (\EN~input_o\ & (\inst17|inst2~0_combout\ $ (\Y[9]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst2~0_combout\,
+	datab => \Y[9]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst25~combout\);
+
+-- Location: LCCOMB_X20_Y28_N2
+inst24 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst24~combout\ = (\EN~input_o\ & (\Y[8]~input_o\ $ (\inst15|inst3~1_combout\ $ (\X[8]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst24~combout\);
+
+-- Location: LCCOMB_X20_Y28_N12
+inst23 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst23~combout\ = (\EN~input_o\ & (\Y[7]~input_o\ $ (\inst15|inst3~0_combout\ $ (\X[7]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000001000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \EN~input_o\,
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst23~combout\);
+
+-- Location: LCCOMB_X19_Y9_N22
+inst22 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst22~combout\ = (\EN~input_o\ & (\inst13|inst3~1_combout\ $ (\X[6]~input_o\ $ (\Y[6]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datab => \X[6]~input_o\,
+	datac => \Y[6]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst22~combout\);
+
+-- Location: LCCOMB_X19_Y9_N0
+inst21 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst21~combout\ = (\EN~input_o\ & (\X[5]~input_o\ $ (\inst13|inst3~0_combout\ $ (\Y[5]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[5]~input_o\,
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst21~combout\);
+
+-- Location: LCCOMB_X19_Y9_N18
+inst20 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst20~combout\ = (\EN~input_o\ & (\X[4]~input_o\ $ (\Y[4]~input_o\ $ (\inst11|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	datad => \EN~input_o\,
+	combout => \inst20~combout\);
+
+-- Location: LCCOMB_X19_Y9_N12
+\inst11|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~combout\ = \X[3]~input_o\ $ (\Y[3]~input_o\ $ (((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst2~combout\);
+
+-- Location: LCCOMB_X19_Y9_N30
+inst19 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst19~combout\ = (\EN~input_o\ & \inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst11|inst2~combout\,
+	combout => \inst19~combout\);
+
+-- Location: LCCOMB_X19_Y9_N8
+inst18 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst18~combout\ = (\EN~input_o\ & (\X[2]~input_o\ $ (\inst9|inst3~0_combout\ $ (\Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst18~combout\);
+
+-- Location: LCCOMB_X19_Y9_N10
+\inst9|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~0_combout\ = \Y[1]~input_o\ $ (\X[1]~input_o\ $ (((\X[0]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst2~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N20
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\EN~input_o\ & \inst9|inst2~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst9|inst2~0_combout\,
+	combout => \inst7~combout\);
+
+-- Location: LCCOMB_X19_Y9_N6
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\EN~input_o\ & (\X[0]~input_o\ $ (\Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst6~combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S(9) <= \S[9]~output_o\;
+
+ww_S(8) <= \S[8]~output_o\;
+
+ww_S(7) <= \S[7]~output_o\;
+
+ww_S(6) <= \S[6]~output_o\;
+
+ww_S(5) <= \S[5]~output_o\;
+
+ww_S(4) <= \S[4]~output_o\;
+
+ww_S(3) <= \S[3]~output_o\;
+
+ww_S(2) <= \S[2]~output_o\;
+
+ww_S(1) <= \S[1]~output_o\;
+
+ww_S(0) <= \S[0]~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_slow.vho b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..498c06b
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_slow.vho
@@ -0,0 +1,923 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:20:17"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder IS
+    PORT (
+	Cout : OUT std_logic;
+	X : IN std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(9 DOWNTO 0);
+	S : OUT std_logic_vector(9 DOWNTO 0);
+	EN : IN std_logic
+	);
+END ten_bit_adder;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[9]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[8]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[7]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[6]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[5]	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[4]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[3]	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[2]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[1]	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[0]	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[9]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[9]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[8]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[7]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[7]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[6]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[5]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[5]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[6]	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[8]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- EN	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_S : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_EN : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S[9]~output_o\ : std_logic;
+SIGNAL \S[8]~output_o\ : std_logic;
+SIGNAL \S[7]~output_o\ : std_logic;
+SIGNAL \S[6]~output_o\ : std_logic;
+SIGNAL \S[5]~output_o\ : std_logic;
+SIGNAL \S[4]~output_o\ : std_logic;
+SIGNAL \S[3]~output_o\ : std_logic;
+SIGNAL \S[2]~output_o\ : std_logic;
+SIGNAL \S[1]~output_o\ : std_logic;
+SIGNAL \S[0]~output_o\ : std_logic;
+SIGNAL \Y[8]~input_o\ : std_logic;
+SIGNAL \Y[7]~input_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \inst10|inst3~1_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \Y[5]~input_o\ : std_logic;
+SIGNAL \X[5]~input_o\ : std_logic;
+SIGNAL \inst13|inst3~1_combout\ : std_logic;
+SIGNAL \X[6]~input_o\ : std_logic;
+SIGNAL \Y[6]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \X[7]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~1_combout\ : std_logic;
+SIGNAL \X[8]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \Y[9]~input_o\ : std_logic;
+SIGNAL \X[9]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~1_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+SIGNAL \EN~input_o\ : std_logic;
+SIGNAL \inst25~combout\ : std_logic;
+SIGNAL \inst24~combout\ : std_logic;
+SIGNAL \inst23~combout\ : std_logic;
+SIGNAL \inst22~combout\ : std_logic;
+SIGNAL \inst21~combout\ : std_logic;
+SIGNAL \inst20~combout\ : std_logic;
+SIGNAL \inst11|inst2~combout\ : std_logic;
+SIGNAL \inst19~combout\ : std_logic;
+SIGNAL \inst18~combout\ : std_logic;
+SIGNAL \inst9|inst2~0_combout\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X <= X;
+ww_Y <= Y;
+S <= ww_S;
+ww_EN <= EN;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X33_Y28_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~1_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y27_N2
+\S[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst25~combout\,
+	devoe => ww_devoe,
+	o => \S[9]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\S[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst24~combout\,
+	devoe => ww_devoe,
+	o => \S[8]~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N2
+\S[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~combout\,
+	devoe => ww_devoe,
+	o => \S[7]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\S[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst22~combout\,
+	devoe => ww_devoe,
+	o => \S[6]~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~combout\,
+	devoe => ww_devoe,
+	o => \S[5]~output_o\);
+
+-- Location: IOOBUF_X8_Y0_N2
+\S[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~combout\,
+	devoe => ww_devoe,
+	o => \S[4]~output_o\);
+
+-- Location: IOOBUF_X24_Y0_N9
+\S[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst19~combout\,
+	devoe => ww_devoe,
+	o => \S[3]~output_o\);
+
+-- Location: IOOBUF_X20_Y0_N2
+\S[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst18~combout\,
+	devoe => ww_devoe,
+	o => \S[2]~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N2
+\S[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~combout\,
+	devoe => ww_devoe,
+	o => \S[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N9
+\S[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~combout\,
+	devoe => ww_devoe,
+	o => \S[0]~output_o\);
+
+-- Location: IOIBUF_X22_Y31_N1
+\Y[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(8),
+	o => \Y[8]~input_o\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\Y[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(7),
+	o => \Y[7]~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\X[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\Y[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\X[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: IOIBUF_X14_Y0_N1
+\X[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N24
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\Y[1]~input_o\ & ((\X[1]~input_o\) # ((\X[0]~input_o\ & \Y[0]~input_o\)))) # (!\Y[1]~input_o\ & (\X[0]~input_o\ & (\Y[0]~input_o\ & \X[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N4
+\inst10|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~1_combout\ = (\X[2]~input_o\ & ((\Y[2]~input_o\) # (\inst9|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~1_combout\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\Y[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N2
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\Y[2]~input_o\ & \inst9|inst3~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N14
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\X[3]~input_o\ & ((\inst10|inst3~1_combout\) # ((\Y[3]~input_o\) # (\inst10|inst3~0_combout\)))) # (!\X[3]~input_o\ & (\Y[3]~input_o\ & ((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N16
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X[4]~input_o\ & ((\Y[4]~input_o\) # (\inst11|inst3~0_combout\))) # (!\X[4]~input_o\ & (\Y[4]~input_o\ & \inst11|inst3~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: IOIBUF_X14_Y0_N8
+\Y[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(5),
+	o => \Y[5]~input_o\);
+
+-- Location: IOIBUF_X33_Y14_N8
+\X[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(5),
+	o => \X[5]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N26
+\inst13|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~1_combout\ = (\inst13|inst3~0_combout\ & ((\Y[5]~input_o\) # (\X[5]~input_o\))) # (!\inst13|inst3~0_combout\ & (\Y[5]~input_o\ & \X[5]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \X[5]~input_o\,
+	combout => \inst13|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y10_N8
+\X[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(6),
+	o => \X[6]~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N8
+\Y[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(6),
+	o => \Y[6]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N28
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\inst13|inst3~1_combout\ & ((\X[6]~input_o\) # (\Y[6]~input_o\))) # (!\inst13|inst3~1_combout\ & (\X[6]~input_o\ & \Y[6]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datac => \X[6]~input_o\,
+	datad => \Y[6]~input_o\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y25_N1
+\X[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(7),
+	o => \X[7]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N0
+\inst15|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~1_combout\ = (\Y[7]~input_o\ & ((\inst15|inst3~0_combout\) # (\X[7]~input_o\))) # (!\Y[7]~input_o\ & (\inst15|inst3~0_combout\ & \X[7]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst15|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\X[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(8),
+	o => \X[8]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N26
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\Y[8]~input_o\ & ((\inst15|inst3~1_combout\) # (\X[8]~input_o\))) # (!\Y[8]~input_o\ & (\inst15|inst3~1_combout\ & \X[8]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(9),
+	o => \Y[9]~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\X[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(9),
+	o => \X[9]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N28
+\inst17|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~1_combout\ = (\inst17|inst3~0_combout\ & ((\Y[9]~input_o\) # (\X[9]~input_o\))) # (!\inst17|inst3~0_combout\ & (\Y[9]~input_o\ & \X[9]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst3~0_combout\,
+	datab => \Y[9]~input_o\,
+	datac => \X[9]~input_o\,
+	combout => \inst17|inst3~1_combout\);
+
+-- Location: LCCOMB_X20_Y28_N6
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X[9]~input_o\ $ (((\Y[8]~input_o\ & ((\X[8]~input_o\) # (\inst15|inst3~1_combout\))) # (!\Y[8]~input_o\ & (\X[8]~input_o\ & \inst15|inst3~1_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011001101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \X[9]~input_o\,
+	datac => \X[8]~input_o\,
+	datad => \inst15|inst3~1_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+-- Location: IOIBUF_X33_Y22_N8
+\EN~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_EN,
+	o => \EN~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N16
+inst25 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst25~combout\ = (\EN~input_o\ & (\inst17|inst2~0_combout\ $ (\Y[9]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst2~0_combout\,
+	datab => \Y[9]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst25~combout\);
+
+-- Location: LCCOMB_X20_Y28_N2
+inst24 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst24~combout\ = (\EN~input_o\ & (\Y[8]~input_o\ $ (\inst15|inst3~1_combout\ $ (\X[8]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst24~combout\);
+
+-- Location: LCCOMB_X20_Y28_N12
+inst23 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst23~combout\ = (\EN~input_o\ & (\Y[7]~input_o\ $ (\inst15|inst3~0_combout\ $ (\X[7]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000001000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \EN~input_o\,
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst23~combout\);
+
+-- Location: LCCOMB_X19_Y9_N22
+inst22 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst22~combout\ = (\EN~input_o\ & (\inst13|inst3~1_combout\ $ (\X[6]~input_o\ $ (\Y[6]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datab => \X[6]~input_o\,
+	datac => \Y[6]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst22~combout\);
+
+-- Location: LCCOMB_X19_Y9_N0
+inst21 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst21~combout\ = (\EN~input_o\ & (\X[5]~input_o\ $ (\inst13|inst3~0_combout\ $ (\Y[5]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[5]~input_o\,
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst21~combout\);
+
+-- Location: LCCOMB_X19_Y9_N18
+inst20 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst20~combout\ = (\EN~input_o\ & (\X[4]~input_o\ $ (\Y[4]~input_o\ $ (\inst11|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	datad => \EN~input_o\,
+	combout => \inst20~combout\);
+
+-- Location: LCCOMB_X19_Y9_N12
+\inst11|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~combout\ = \X[3]~input_o\ $ (\Y[3]~input_o\ $ (((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst2~combout\);
+
+-- Location: LCCOMB_X19_Y9_N30
+inst19 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst19~combout\ = (\EN~input_o\ & \inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst11|inst2~combout\,
+	combout => \inst19~combout\);
+
+-- Location: LCCOMB_X19_Y9_N8
+inst18 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst18~combout\ = (\EN~input_o\ & (\X[2]~input_o\ $ (\inst9|inst3~0_combout\ $ (\Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst18~combout\);
+
+-- Location: LCCOMB_X19_Y9_N10
+\inst9|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~0_combout\ = \Y[1]~input_o\ $ (\X[1]~input_o\ $ (((\X[0]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst2~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N20
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\EN~input_o\ & \inst9|inst2~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst9|inst2~0_combout\,
+	combout => \inst7~combout\);
+
+-- Location: LCCOMB_X19_Y9_N6
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\EN~input_o\ & (\X[0]~input_o\ $ (\Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst6~combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S(9) <= \S[9]~output_o\;
+
+ww_S(8) <= \S[8]~output_o\;
+
+ww_S(7) <= \S[7]~output_o\;
+
+ww_S(6) <= \S[6]~output_o\;
+
+ww_S(5) <= \S[5]~output_o\;
+
+ww_S(4) <= \S[4]~output_o\;
+
+ww_S(3) <= \S[3]~output_o\;
+
+ww_S(2) <= \S[2]~output_o\;
+
+ww_S(1) <= \S[1]~output_o\;
+
+ww_S(0) <= \S[0]~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_vhd_slow.sdo b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..6a0f6df
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,676 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder")
+  (DATE "02/18/2016 22:20:18")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (934:934:934) (890:890:890))
+        (IOPATH i o (2419:2419:2419) (2331:2331:2331))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (956:956:956) (924:924:924))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (907:907:907) (878:878:878))
+        (IOPATH i o (2354:2354:2354) (2247:2247:2247))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1171:1171:1171) (1121:1121:1121))
+        (IOPATH i o (2419:2419:2419) (2331:2331:2331))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2067:2067:2067) (2060:2060:2060))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (988:988:988) (960:960:960))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1452:1452:1452) (1430:1430:1430))
+        (IOPATH i o (2221:2221:2221) (2150:2150:2150))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1169:1169:1169) (1126:1126:1126))
+        (IOPATH i o (2314:2314:2314) (2207:2207:2207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (915:915:915) (869:869:869))
+        (IOPATH i o (2324:2324:2324) (2217:2217:2217))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1103:1103:1103) (1061:1061:1061))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1166:1166:1166) (1118:1118:1118))
+        (IOPATH i o (2334:2334:2334) (2227:2227:2227))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (478:478:478) (634:634:634))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (679:679:679))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (508:508:508) (664:664:664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (689:689:689))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (495:495:495) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2886:2886:2886) (3108:3108:3108))
+        (PORT datab (3172:3172:3172) (3388:3388:3388))
+        (PORT datac (3247:3247:3247) (3504:3504:3504))
+        (PORT datad (1302:1302:1302) (1308:1308:1308))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1429:1429:1429) (1413:1413:1413))
+        (PORT datab (3271:3271:3271) (3530:3530:3530))
+        (PORT datad (175:175:175) (200:200:200))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (3242:3242:3242) (3502:3502:3502))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3043:3043:3043) (3257:3257:3257))
+        (PORT datab (197:197:197) (224:224:224))
+        (PORT datac (3173:3173:3173) (3422:3422:3422))
+        (PORT datad (165:165:165) (187:187:187))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3292:3292:3292))
+        (PORT datab (3211:3211:3211) (3454:3454:3454))
+        (PORT datac (169:169:169) (192:192:192))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (495:495:495) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (197:197:197) (222:222:222))
+        (PORT datac (3101:3101:3101) (3312:3312:3312))
+        (PORT datad (3237:3237:3237) (3444:3444:3444))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (689:689:689))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (228:228:228))
+        (PORT datac (2986:2986:2986) (3196:3196:3196))
+        (PORT datad (3042:3042:3042) (3248:3248:3248))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (669:669:669))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3206:3206:3206) (3423:3423:3423))
+        (PORT datac (1155:1155:1155) (1186:1186:1186))
+        (PORT datad (2977:2977:2977) (3190:3190:3190))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (669:669:669))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2867:2867:2867) (3052:3052:3052))
+        (PORT datab (207:207:207) (235:235:235))
+        (PORT datac (3022:3022:3022) (3245:3245:3245))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (193:193:193) (217:217:217))
+        (PORT datab (1393:1393:1393) (1363:1363:1363))
+        (PORT datac (1351:1351:1351) (1316:1316:1316))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2867:2867:2867) (3052:3052:3052))
+        (PORT datab (1374:1374:1374) (1340:1340:1340))
+        (PORT datac (3019:3019:3019) (3243:3243:3243))
+        (PORT datad (171:171:171) (196:196:196))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\EN\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (194:194:194) (219:219:219))
+        (PORT datab (1395:1395:1395) (1365:1365:1365))
+        (PORT datad (3254:3254:3254) (3468:3468:3468))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2867:2867:2867) (3052:3052:3052))
+        (PORT datab (201:201:201) (229:229:229))
+        (PORT datac (3019:3019:3019) (3243:3243:3243))
+        (PORT datad (3251:3251:3251) (3465:3465:3465))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3286:3286:3286) (3505:3505:3505))
+        (PORT datab (3204:3204:3204) (3421:3421:3421))
+        (PORT datac (1157:1157:1157) (1188:1188:1188))
+        (PORT datad (2975:2975:2975) (3188:3188:3188))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (229:229:229))
+        (PORT datab (3013:3013:3013) (3224:3224:3224))
+        (PORT datac (3072:3072:3072) (3272:3272:3272))
+        (PORT datad (3302:3302:3302) (3539:3539:3539))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3270:3270:3270) (3483:3483:3483))
+        (PORT datab (198:198:198) (224:224:224))
+        (PORT datac (3102:3102:3102) (3313:3313:3313))
+        (PORT datad (3309:3309:3309) (3548:3548:3548))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3292:3292:3292))
+        (PORT datab (3211:3211:3211) (3454:3454:3454))
+        (PORT datac (169:169:169) (193:193:193))
+        (PORT datad (3303:3303:3303) (3541:3541:3541))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3044:3044:3044) (3257:3257:3257))
+        (PORT datab (197:197:197) (223:223:223))
+        (PORT datac (3173:3173:3173) (3422:3422:3422))
+        (PORT datad (164:164:164) (187:187:187))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3337:3337:3337) (3574:3574:3574))
+        (PORT datad (160:160:160) (179:179:179))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1429:1429:1429) (1413:1413:1413))
+        (PORT datab (205:205:205) (233:233:233))
+        (PORT datac (3243:3243:3243) (3502:3502:3502))
+        (PORT datad (3306:3306:3306) (3545:3545:3545))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2886:2886:2886) (3107:3107:3107))
+        (PORT datab (3174:3174:3174) (3390:3390:3390))
+        (PORT datac (3245:3245:3245) (3503:3503:3503))
+        (PORT datad (1304:1304:1304) (1309:1309:1309))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3340:3340:3340) (3578:3578:3578))
+        (PORT datad (159:159:159) (178:178:178))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3174:3174:3174) (3390:3390:3390))
+        (PORT datac (3245:3245:3245) (3502:3502:3502))
+        (PORT datad (3307:3307:3307) (3546:3546:3546))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_slow.vho b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..498c06b
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_slow.vho
@@ -0,0 +1,923 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:20:17"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder IS
+    PORT (
+	Cout : OUT std_logic;
+	X : IN std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(9 DOWNTO 0);
+	S : OUT std_logic_vector(9 DOWNTO 0);
+	EN : IN std_logic
+	);
+END ten_bit_adder;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[9]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[8]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[7]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[6]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[5]	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[4]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[3]	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[2]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[1]	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[0]	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[9]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[9]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[8]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[7]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[7]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[6]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[5]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[5]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[6]	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[8]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- EN	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_S : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_EN : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S[9]~output_o\ : std_logic;
+SIGNAL \S[8]~output_o\ : std_logic;
+SIGNAL \S[7]~output_o\ : std_logic;
+SIGNAL \S[6]~output_o\ : std_logic;
+SIGNAL \S[5]~output_o\ : std_logic;
+SIGNAL \S[4]~output_o\ : std_logic;
+SIGNAL \S[3]~output_o\ : std_logic;
+SIGNAL \S[2]~output_o\ : std_logic;
+SIGNAL \S[1]~output_o\ : std_logic;
+SIGNAL \S[0]~output_o\ : std_logic;
+SIGNAL \Y[8]~input_o\ : std_logic;
+SIGNAL \Y[7]~input_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \inst10|inst3~1_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \Y[5]~input_o\ : std_logic;
+SIGNAL \X[5]~input_o\ : std_logic;
+SIGNAL \inst13|inst3~1_combout\ : std_logic;
+SIGNAL \X[6]~input_o\ : std_logic;
+SIGNAL \Y[6]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \X[7]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~1_combout\ : std_logic;
+SIGNAL \X[8]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \Y[9]~input_o\ : std_logic;
+SIGNAL \X[9]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~1_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+SIGNAL \EN~input_o\ : std_logic;
+SIGNAL \inst25~combout\ : std_logic;
+SIGNAL \inst24~combout\ : std_logic;
+SIGNAL \inst23~combout\ : std_logic;
+SIGNAL \inst22~combout\ : std_logic;
+SIGNAL \inst21~combout\ : std_logic;
+SIGNAL \inst20~combout\ : std_logic;
+SIGNAL \inst11|inst2~combout\ : std_logic;
+SIGNAL \inst19~combout\ : std_logic;
+SIGNAL \inst18~combout\ : std_logic;
+SIGNAL \inst9|inst2~0_combout\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X <= X;
+ww_Y <= Y;
+S <= ww_S;
+ww_EN <= EN;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X33_Y28_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~1_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y27_N2
+\S[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst25~combout\,
+	devoe => ww_devoe,
+	o => \S[9]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\S[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst24~combout\,
+	devoe => ww_devoe,
+	o => \S[8]~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N2
+\S[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~combout\,
+	devoe => ww_devoe,
+	o => \S[7]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\S[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst22~combout\,
+	devoe => ww_devoe,
+	o => \S[6]~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~combout\,
+	devoe => ww_devoe,
+	o => \S[5]~output_o\);
+
+-- Location: IOOBUF_X8_Y0_N2
+\S[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~combout\,
+	devoe => ww_devoe,
+	o => \S[4]~output_o\);
+
+-- Location: IOOBUF_X24_Y0_N9
+\S[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst19~combout\,
+	devoe => ww_devoe,
+	o => \S[3]~output_o\);
+
+-- Location: IOOBUF_X20_Y0_N2
+\S[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst18~combout\,
+	devoe => ww_devoe,
+	o => \S[2]~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N2
+\S[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~combout\,
+	devoe => ww_devoe,
+	o => \S[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N9
+\S[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~combout\,
+	devoe => ww_devoe,
+	o => \S[0]~output_o\);
+
+-- Location: IOIBUF_X22_Y31_N1
+\Y[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(8),
+	o => \Y[8]~input_o\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\Y[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(7),
+	o => \Y[7]~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\X[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\Y[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\X[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: IOIBUF_X14_Y0_N1
+\X[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N24
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\Y[1]~input_o\ & ((\X[1]~input_o\) # ((\X[0]~input_o\ & \Y[0]~input_o\)))) # (!\Y[1]~input_o\ & (\X[0]~input_o\ & (\Y[0]~input_o\ & \X[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N4
+\inst10|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~1_combout\ = (\X[2]~input_o\ & ((\Y[2]~input_o\) # (\inst9|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~1_combout\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\Y[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N2
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\Y[2]~input_o\ & \inst9|inst3~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N14
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\X[3]~input_o\ & ((\inst10|inst3~1_combout\) # ((\Y[3]~input_o\) # (\inst10|inst3~0_combout\)))) # (!\X[3]~input_o\ & (\Y[3]~input_o\ & ((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N16
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X[4]~input_o\ & ((\Y[4]~input_o\) # (\inst11|inst3~0_combout\))) # (!\X[4]~input_o\ & (\Y[4]~input_o\ & \inst11|inst3~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: IOIBUF_X14_Y0_N8
+\Y[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(5),
+	o => \Y[5]~input_o\);
+
+-- Location: IOIBUF_X33_Y14_N8
+\X[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(5),
+	o => \X[5]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N26
+\inst13|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~1_combout\ = (\inst13|inst3~0_combout\ & ((\Y[5]~input_o\) # (\X[5]~input_o\))) # (!\inst13|inst3~0_combout\ & (\Y[5]~input_o\ & \X[5]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \X[5]~input_o\,
+	combout => \inst13|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y10_N8
+\X[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(6),
+	o => \X[6]~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N8
+\Y[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(6),
+	o => \Y[6]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N28
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\inst13|inst3~1_combout\ & ((\X[6]~input_o\) # (\Y[6]~input_o\))) # (!\inst13|inst3~1_combout\ & (\X[6]~input_o\ & \Y[6]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datac => \X[6]~input_o\,
+	datad => \Y[6]~input_o\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y25_N1
+\X[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(7),
+	o => \X[7]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N0
+\inst15|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~1_combout\ = (\Y[7]~input_o\ & ((\inst15|inst3~0_combout\) # (\X[7]~input_o\))) # (!\Y[7]~input_o\ & (\inst15|inst3~0_combout\ & \X[7]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst15|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\X[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(8),
+	o => \X[8]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N26
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\Y[8]~input_o\ & ((\inst15|inst3~1_combout\) # (\X[8]~input_o\))) # (!\Y[8]~input_o\ & (\inst15|inst3~1_combout\ & \X[8]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(9),
+	o => \Y[9]~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\X[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(9),
+	o => \X[9]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N28
+\inst17|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~1_combout\ = (\inst17|inst3~0_combout\ & ((\Y[9]~input_o\) # (\X[9]~input_o\))) # (!\inst17|inst3~0_combout\ & (\Y[9]~input_o\ & \X[9]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst3~0_combout\,
+	datab => \Y[9]~input_o\,
+	datac => \X[9]~input_o\,
+	combout => \inst17|inst3~1_combout\);
+
+-- Location: LCCOMB_X20_Y28_N6
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X[9]~input_o\ $ (((\Y[8]~input_o\ & ((\X[8]~input_o\) # (\inst15|inst3~1_combout\))) # (!\Y[8]~input_o\ & (\X[8]~input_o\ & \inst15|inst3~1_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011001101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \X[9]~input_o\,
+	datac => \X[8]~input_o\,
+	datad => \inst15|inst3~1_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+-- Location: IOIBUF_X33_Y22_N8
+\EN~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_EN,
+	o => \EN~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N16
+inst25 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst25~combout\ = (\EN~input_o\ & (\inst17|inst2~0_combout\ $ (\Y[9]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst2~0_combout\,
+	datab => \Y[9]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst25~combout\);
+
+-- Location: LCCOMB_X20_Y28_N2
+inst24 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst24~combout\ = (\EN~input_o\ & (\Y[8]~input_o\ $ (\inst15|inst3~1_combout\ $ (\X[8]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst24~combout\);
+
+-- Location: LCCOMB_X20_Y28_N12
+inst23 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst23~combout\ = (\EN~input_o\ & (\Y[7]~input_o\ $ (\inst15|inst3~0_combout\ $ (\X[7]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000001000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \EN~input_o\,
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst23~combout\);
+
+-- Location: LCCOMB_X19_Y9_N22
+inst22 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst22~combout\ = (\EN~input_o\ & (\inst13|inst3~1_combout\ $ (\X[6]~input_o\ $ (\Y[6]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datab => \X[6]~input_o\,
+	datac => \Y[6]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst22~combout\);
+
+-- Location: LCCOMB_X19_Y9_N0
+inst21 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst21~combout\ = (\EN~input_o\ & (\X[5]~input_o\ $ (\inst13|inst3~0_combout\ $ (\Y[5]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[5]~input_o\,
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst21~combout\);
+
+-- Location: LCCOMB_X19_Y9_N18
+inst20 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst20~combout\ = (\EN~input_o\ & (\X[4]~input_o\ $ (\Y[4]~input_o\ $ (\inst11|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	datad => \EN~input_o\,
+	combout => \inst20~combout\);
+
+-- Location: LCCOMB_X19_Y9_N12
+\inst11|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~combout\ = \X[3]~input_o\ $ (\Y[3]~input_o\ $ (((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst2~combout\);
+
+-- Location: LCCOMB_X19_Y9_N30
+inst19 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst19~combout\ = (\EN~input_o\ & \inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst11|inst2~combout\,
+	combout => \inst19~combout\);
+
+-- Location: LCCOMB_X19_Y9_N8
+inst18 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst18~combout\ = (\EN~input_o\ & (\X[2]~input_o\ $ (\inst9|inst3~0_combout\ $ (\Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst18~combout\);
+
+-- Location: LCCOMB_X19_Y9_N10
+\inst9|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~0_combout\ = \Y[1]~input_o\ $ (\X[1]~input_o\ $ (((\X[0]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst2~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N20
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\EN~input_o\ & \inst9|inst2~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst9|inst2~0_combout\,
+	combout => \inst7~combout\);
+
+-- Location: LCCOMB_X19_Y9_N6
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\EN~input_o\ & (\X[0]~input_o\ $ (\Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst6~combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S(9) <= \S[9]~output_o\;
+
+ww_S(8) <= \S[8]~output_o\;
+
+ww_S(7) <= \S[7]~output_o\;
+
+ww_S(6) <= \S[6]~output_o\;
+
+ww_S(5) <= \S[5]~output_o\;
+
+ww_S(4) <= \S[4]~output_o\;
+
+ww_S(3) <= \S[3]~output_o\;
+
+ww_S(2) <= \S[2]~output_o\;
+
+ww_S(1) <= \S[1]~output_o\;
+
+ww_S(0) <= \S[0]~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_vhd_slow.sdo b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..4ef4927
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,676 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder")
+  (DATE "02/18/2016 22:20:18")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1008:1008:1008) (991:991:991))
+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1033:1033:1033) (1038:1038:1038))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (983:983:983) (987:987:987))
+        (IOPATH i o (2659:2659:2659) (2557:2557:2557))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1262:1262:1262) (1247:1247:1247))
+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2241:2241:2241) (2301:2301:2301))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1070:1070:1070) (1079:1079:1079))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1572:1572:1572) (1600:1600:1600))
+        (IOPATH i o (2544:2544:2544) (2446:2446:2446))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1264:1264:1264) (1255:1255:1255))
+        (IOPATH i o (2619:2619:2619) (2517:2517:2517))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (987:987:987) (973:973:973))
+        (IOPATH i o (2629:2629:2629) (2527:2527:2527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1198:1198:1198) (1180:1180:1180))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1261:1261:1261) (1252:1252:1252))
+        (IOPATH i o (2639:2639:2639) (2537:2537:2537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (497:497:497) (671:671:671))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (545:545:545) (718:718:718))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (555:555:555) (728:728:728))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3335:3335:3335) (3624:3624:3624))
+        (PORT datab (3633:3633:3633) (3944:3944:3944))
+        (PORT datac (3715:3715:3715) (4060:4060:4060))
+        (PORT datad (1455:1455:1455) (1430:1430:1430))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1601:1601:1601) (1544:1544:1544))
+        (PORT datab (3744:3744:3744) (4086:4086:4086))
+        (PORT datad (190:190:190) (223:223:223))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (3714:3714:3714) (4052:4052:4052))
+        (PORT datad (191:191:191) (223:223:223))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3499:3499:3499) (3781:3781:3781))
+        (PORT datab (214:214:214) (251:251:251))
+        (PORT datac (3639:3639:3639) (3972:3972:3972))
+        (PORT datad (180:180:180) (209:209:209))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3554:3554:3554) (3826:3826:3826))
+        (PORT datab (3678:3678:3678) (4005:4005:4005))
+        (PORT datac (184:184:184) (215:215:215))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (214:214:214) (248:248:248))
+        (PORT datac (3559:3559:3559) (3855:3855:3855))
+        (PORT datad (3704:3704:3704) (3992:3992:3992))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (555:555:555) (728:728:728))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (217:217:217) (255:255:255))
+        (PORT datac (3430:3430:3430) (3716:3716:3716))
+        (PORT datad (3498:3498:3498) (3782:3782:3782))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3667:3667:3667) (3975:3975:3975))
+        (PORT datac (1249:1249:1249) (1324:1324:1324))
+        (PORT datad (3427:3427:3427) (3708:3708:3708))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3303:3303:3303) (3563:3563:3563))
+        (PORT datab (223:223:223) (262:262:262))
+        (PORT datac (3467:3467:3467) (3772:3772:3772))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (209:209:209) (243:243:243))
+        (PORT datab (1559:1559:1559) (1480:1480:1480))
+        (PORT datac (1505:1505:1505) (1435:1435:1435))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3303:3303:3303) (3563:3563:3563))
+        (PORT datab (1533:1533:1533) (1460:1460:1460))
+        (PORT datac (3465:3465:3465) (3770:3770:3770))
+        (PORT datad (187:187:187) (220:220:220))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\EN\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (245:245:245))
+        (PORT datab (1560:1560:1560) (1481:1481:1481))
+        (PORT datad (3724:3724:3724) (4015:4015:4015))
+        (IOPATH dataa combout (325:325:325) (328:328:328))
+        (IOPATH datab combout (336:336:336) (332:332:332))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3302:3302:3302) (3563:3563:3563))
+        (PORT datab (218:218:218) (256:256:256))
+        (PORT datac (3465:3465:3465) (3770:3770:3770))
+        (PORT datad (3721:3721:3721) (4012:4012:4012))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3756:3756:3756) (4056:4056:4056))
+        (PORT datab (3666:3666:3666) (3973:3973:3973))
+        (PORT datac (1250:1250:1250) (1326:1326:1326))
+        (PORT datad (3426:3426:3426) (3706:3706:3706))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (256:256:256))
+        (PORT datab (3459:3459:3459) (3748:3748:3748))
+        (PORT datac (3534:3534:3534) (3810:3810:3810))
+        (PORT datad (3770:3770:3770) (4104:4104:4104))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3738:3738:3738) (4035:4035:4035))
+        (PORT datab (215:215:215) (250:250:250))
+        (PORT datac (3559:3559:3559) (3857:3857:3857))
+        (PORT datad (3777:3777:3777) (4112:4112:4112))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3554:3554:3554) (3826:3826:3826))
+        (PORT datab (3678:3678:3678) (4005:4005:4005))
+        (PORT datac (185:185:185) (215:215:215))
+        (PORT datad (3771:3771:3771) (4105:4105:4105))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3499:3499:3499) (3781:3781:3781))
+        (PORT datab (214:214:214) (250:250:250))
+        (PORT datac (3639:3639:3639) (3972:3972:3972))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3810:3810:3810) (4143:4143:4143))
+        (PORT datad (176:176:176) (200:200:200))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1602:1602:1602) (1545:1545:1545))
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (3715:3715:3715) (4053:4053:4053))
+        (PORT datad (3775:3775:3775) (4110:4110:4110))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3335:3335:3335) (3623:3623:3623))
+        (PORT datab (3635:3635:3635) (3946:3946:3946))
+        (PORT datac (3713:3713:3713) (4058:4058:4058))
+        (PORT datad (1457:1457:1457) (1432:1432:1432))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3813:3813:3813) (4147:4147:4147))
+        (PORT datad (175:175:175) (199:199:199))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3635:3635:3635) (3946:3946:3946))
+        (PORT datac (3712:3712:3712) (4057:4057:4057))
+        (PORT datad (3775:3775:3775) (4110:4110:4110))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_fast.vho b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..7aea7bb
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_fast.vho
@@ -0,0 +1,923 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:20:18"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder IS
+    PORT (
+	Cout : OUT std_logic;
+	X : IN std_logic_vector(9 DOWNTO 0);
+	Y : IN std_logic_vector(9 DOWNTO 0);
+	S : OUT std_logic_vector(9 DOWNTO 0);
+	EN : IN std_logic
+	);
+END ten_bit_adder;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[9]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[8]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[7]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[6]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[5]	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[4]	=>  Location: PIN_M4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[3]	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[2]	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[1]	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S[0]	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[9]	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[9]	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[8]	=>  Location: PIN_B8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[7]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[7]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[6]	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[5]	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[5]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[4]	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[2]	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[0]	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[0]	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[1]	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[1]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[2]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y[3]	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[3]	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[4]	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[6]	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X[8]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- EN	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_Y : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_S : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_EN : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S[9]~output_o\ : std_logic;
+SIGNAL \S[8]~output_o\ : std_logic;
+SIGNAL \S[7]~output_o\ : std_logic;
+SIGNAL \S[6]~output_o\ : std_logic;
+SIGNAL \S[5]~output_o\ : std_logic;
+SIGNAL \S[4]~output_o\ : std_logic;
+SIGNAL \S[3]~output_o\ : std_logic;
+SIGNAL \S[2]~output_o\ : std_logic;
+SIGNAL \S[1]~output_o\ : std_logic;
+SIGNAL \S[0]~output_o\ : std_logic;
+SIGNAL \Y[8]~input_o\ : std_logic;
+SIGNAL \Y[7]~input_o\ : std_logic;
+SIGNAL \X[4]~input_o\ : std_logic;
+SIGNAL \Y[4]~input_o\ : std_logic;
+SIGNAL \X[3]~input_o\ : std_logic;
+SIGNAL \X[2]~input_o\ : std_logic;
+SIGNAL \Y[2]~input_o\ : std_logic;
+SIGNAL \Y[1]~input_o\ : std_logic;
+SIGNAL \X[0]~input_o\ : std_logic;
+SIGNAL \Y[0]~input_o\ : std_logic;
+SIGNAL \X[1]~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \inst10|inst3~1_combout\ : std_logic;
+SIGNAL \Y[3]~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \Y[5]~input_o\ : std_logic;
+SIGNAL \X[5]~input_o\ : std_logic;
+SIGNAL \inst13|inst3~1_combout\ : std_logic;
+SIGNAL \X[6]~input_o\ : std_logic;
+SIGNAL \Y[6]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \X[7]~input_o\ : std_logic;
+SIGNAL \inst15|inst3~1_combout\ : std_logic;
+SIGNAL \X[8]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \Y[9]~input_o\ : std_logic;
+SIGNAL \X[9]~input_o\ : std_logic;
+SIGNAL \inst17|inst3~1_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+SIGNAL \EN~input_o\ : std_logic;
+SIGNAL \inst25~combout\ : std_logic;
+SIGNAL \inst24~combout\ : std_logic;
+SIGNAL \inst23~combout\ : std_logic;
+SIGNAL \inst22~combout\ : std_logic;
+SIGNAL \inst21~combout\ : std_logic;
+SIGNAL \inst20~combout\ : std_logic;
+SIGNAL \inst11|inst2~combout\ : std_logic;
+SIGNAL \inst19~combout\ : std_logic;
+SIGNAL \inst18~combout\ : std_logic;
+SIGNAL \inst9|inst2~0_combout\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X <= X;
+ww_Y <= Y;
+S <= ww_S;
+ww_EN <= EN;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X33_Y28_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~1_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y27_N2
+\S[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst25~combout\,
+	devoe => ww_devoe,
+	o => \S[9]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\S[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst24~combout\,
+	devoe => ww_devoe,
+	o => \S[8]~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N2
+\S[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~combout\,
+	devoe => ww_devoe,
+	o => \S[7]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\S[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst22~combout\,
+	devoe => ww_devoe,
+	o => \S[6]~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst21~combout\,
+	devoe => ww_devoe,
+	o => \S[5]~output_o\);
+
+-- Location: IOOBUF_X8_Y0_N2
+\S[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst20~combout\,
+	devoe => ww_devoe,
+	o => \S[4]~output_o\);
+
+-- Location: IOOBUF_X24_Y0_N9
+\S[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst19~combout\,
+	devoe => ww_devoe,
+	o => \S[3]~output_o\);
+
+-- Location: IOOBUF_X20_Y0_N2
+\S[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst18~combout\,
+	devoe => ww_devoe,
+	o => \S[2]~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N2
+\S[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~combout\,
+	devoe => ww_devoe,
+	o => \S[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N9
+\S[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~combout\,
+	devoe => ww_devoe,
+	o => \S[0]~output_o\);
+
+-- Location: IOIBUF_X22_Y31_N1
+\Y[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(8),
+	o => \Y[8]~input_o\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\Y[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(7),
+	o => \Y[7]~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\X[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(4),
+	o => \X[4]~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\Y[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(4),
+	o => \Y[4]~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\X[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(3),
+	o => \X[3]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(2),
+	o => \X[2]~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\Y[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(2),
+	o => \Y[2]~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(1),
+	o => \Y[1]~input_o\);
+
+-- Location: IOIBUF_X14_Y0_N1
+\X[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(0),
+	o => \X[0]~input_o\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(0),
+	o => \Y[0]~input_o\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(1),
+	o => \X[1]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N24
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\Y[1]~input_o\ & ((\X[1]~input_o\) # ((\X[0]~input_o\ & \Y[0]~input_o\)))) # (!\Y[1]~input_o\ & (\X[0]~input_o\ & (\Y[0]~input_o\ & \X[1]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N4
+\inst10|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~1_combout\ = (\X[2]~input_o\ & ((\Y[2]~input_o\) # (\inst9|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~1_combout\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\Y[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(3),
+	o => \Y[3]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N2
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\Y[2]~input_o\ & \inst9|inst3~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \Y[2]~input_o\,
+	datad => \inst9|inst3~0_combout\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N14
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\X[3]~input_o\ & ((\inst10|inst3~1_combout\) # ((\Y[3]~input_o\) # (\inst10|inst3~0_combout\)))) # (!\X[3]~input_o\ & (\Y[3]~input_o\ & ((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N16
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X[4]~input_o\ & ((\Y[4]~input_o\) # (\inst11|inst3~0_combout\))) # (!\X[4]~input_o\ & (\Y[4]~input_o\ & \inst11|inst3~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: IOIBUF_X14_Y0_N8
+\Y[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(5),
+	o => \Y[5]~input_o\);
+
+-- Location: IOIBUF_X33_Y14_N8
+\X[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(5),
+	o => \X[5]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N26
+\inst13|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~1_combout\ = (\inst13|inst3~0_combout\ & ((\Y[5]~input_o\) # (\X[5]~input_o\))) # (!\inst13|inst3~0_combout\ & (\Y[5]~input_o\ & \X[5]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \X[5]~input_o\,
+	combout => \inst13|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y10_N8
+\X[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(6),
+	o => \X[6]~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N8
+\Y[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(6),
+	o => \Y[6]~input_o\);
+
+-- Location: LCCOMB_X19_Y9_N28
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\inst13|inst3~1_combout\ & ((\X[6]~input_o\) # (\Y[6]~input_o\))) # (!\inst13|inst3~1_combout\ & (\X[6]~input_o\ & \Y[6]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101010100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datac => \X[6]~input_o\,
+	datad => \Y[6]~input_o\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y25_N1
+\X[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(7),
+	o => \X[7]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N0
+\inst15|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~1_combout\ = (\Y[7]~input_o\ & ((\inst15|inst3~0_combout\) # (\X[7]~input_o\))) # (!\Y[7]~input_o\ & (\inst15|inst3~0_combout\ & \X[7]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst15|inst3~1_combout\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\X[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(8),
+	o => \X[8]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N26
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\Y[8]~input_o\ & ((\inst15|inst3~1_combout\) # (\X[8]~input_o\))) # (!\Y[8]~input_o\ & (\inst15|inst3~1_combout\ & \X[8]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y(9),
+	o => \Y[9]~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\X[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X(9),
+	o => \X[9]~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N28
+\inst17|inst3~1\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~1_combout\ = (\inst17|inst3~0_combout\ & ((\Y[9]~input_o\) # (\X[9]~input_o\))) # (!\inst17|inst3~0_combout\ & (\Y[9]~input_o\ & \X[9]~input_o\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst3~0_combout\,
+	datab => \Y[9]~input_o\,
+	datac => \X[9]~input_o\,
+	combout => \inst17|inst3~1_combout\);
+
+-- Location: LCCOMB_X20_Y28_N6
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X[9]~input_o\ $ (((\Y[8]~input_o\ & ((\X[8]~input_o\) # (\inst15|inst3~1_combout\))) # (!\Y[8]~input_o\ & (\X[8]~input_o\ & \inst15|inst3~1_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011011001101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \X[9]~input_o\,
+	datac => \X[8]~input_o\,
+	datad => \inst15|inst3~1_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+-- Location: IOIBUF_X33_Y22_N8
+\EN~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_EN,
+	o => \EN~input_o\);
+
+-- Location: LCCOMB_X20_Y28_N16
+inst25 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst25~combout\ = (\EN~input_o\ & (\inst17|inst2~0_combout\ $ (\Y[9]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst17|inst2~0_combout\,
+	datab => \Y[9]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst25~combout\);
+
+-- Location: LCCOMB_X20_Y28_N2
+inst24 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst24~combout\ = (\EN~input_o\ & (\Y[8]~input_o\ $ (\inst15|inst3~1_combout\ $ (\X[8]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[8]~input_o\,
+	datab => \inst15|inst3~1_combout\,
+	datac => \X[8]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst24~combout\);
+
+-- Location: LCCOMB_X20_Y28_N12
+inst23 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst23~combout\ = (\EN~input_o\ & (\Y[7]~input_o\ $ (\inst15|inst3~0_combout\ $ (\X[7]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000001000101000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \EN~input_o\,
+	datab => \Y[7]~input_o\,
+	datac => \inst15|inst3~0_combout\,
+	datad => \X[7]~input_o\,
+	combout => \inst23~combout\);
+
+-- Location: LCCOMB_X19_Y9_N22
+inst22 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst22~combout\ = (\EN~input_o\ & (\inst13|inst3~1_combout\ $ (\X[6]~input_o\ $ (\Y[6]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst13|inst3~1_combout\,
+	datab => \X[6]~input_o\,
+	datac => \Y[6]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst22~combout\);
+
+-- Location: LCCOMB_X19_Y9_N0
+inst21 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst21~combout\ = (\EN~input_o\ & (\X[5]~input_o\ $ (\inst13|inst3~0_combout\ $ (\Y[5]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[5]~input_o\,
+	datab => \inst13|inst3~0_combout\,
+	datac => \Y[5]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst21~combout\);
+
+-- Location: LCCOMB_X19_Y9_N18
+inst20 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst20~combout\ = (\EN~input_o\ & (\X[4]~input_o\ $ (\Y[4]~input_o\ $ (\inst11|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[4]~input_o\,
+	datab => \Y[4]~input_o\,
+	datac => \inst11|inst3~0_combout\,
+	datad => \EN~input_o\,
+	combout => \inst20~combout\);
+
+-- Location: LCCOMB_X19_Y9_N12
+\inst11|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~combout\ = \X[3]~input_o\ $ (\Y[3]~input_o\ $ (((\inst10|inst3~1_combout\) # (\inst10|inst3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010110010110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[3]~input_o\,
+	datab => \inst10|inst3~1_combout\,
+	datac => \Y[3]~input_o\,
+	datad => \inst10|inst3~0_combout\,
+	combout => \inst11|inst2~combout\);
+
+-- Location: LCCOMB_X19_Y9_N30
+inst19 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst19~combout\ = (\EN~input_o\ & \inst11|inst2~combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst11|inst2~combout\,
+	combout => \inst19~combout\);
+
+-- Location: LCCOMB_X19_Y9_N8
+inst18 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst18~combout\ = (\EN~input_o\ & (\X[2]~input_o\ $ (\inst9|inst3~0_combout\ $ (\Y[2]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X[2]~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \Y[2]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst18~combout\);
+
+-- Location: LCCOMB_X19_Y9_N10
+\inst9|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~0_combout\ = \Y[1]~input_o\ $ (\X[1]~input_o\ $ (((\X[0]~input_o\ & \Y[0]~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y[1]~input_o\,
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \X[1]~input_o\,
+	combout => \inst9|inst2~0_combout\);
+
+-- Location: LCCOMB_X19_Y9_N20
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\EN~input_o\ & \inst9|inst2~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \EN~input_o\,
+	datad => \inst9|inst2~0_combout\,
+	combout => \inst7~combout\);
+
+-- Location: LCCOMB_X19_Y9_N6
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\EN~input_o\ & (\X[0]~input_o\ $ (\Y[0]~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \X[0]~input_o\,
+	datac => \Y[0]~input_o\,
+	datad => \EN~input_o\,
+	combout => \inst6~combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S(9) <= \S[9]~output_o\;
+
+ww_S(8) <= \S[8]~output_o\;
+
+ww_S(7) <= \S[7]~output_o\;
+
+ww_S(6) <= \S[6]~output_o\;
+
+ww_S(5) <= \S[5]~output_o\;
+
+ww_S(4) <= \S[4]~output_o\;
+
+ww_S(3) <= \S[3]~output_o\;
+
+ww_S(2) <= \S[2]~output_o\;
+
+ww_S(1) <= \S[1]~output_o\;
+
+ww_S(0) <= \S[0]~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..43549a6
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,676 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder")
+  (DATE "02/18/2016 22:20:18")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (544:544:544) (598:598:598))
+        (IOPATH i o (1723:1723:1723) (1675:1675:1675))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (553:553:553) (617:617:617))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (532:532:532) (589:589:589))
+        (IOPATH i o (1630:1630:1630) (1619:1619:1619))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (696:696:696) (763:763:763))
+        (IOPATH i o (1723:1723:1723) (1675:1675:1675))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1248:1248:1248) (1414:1414:1414))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (580:580:580) (647:647:647))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (874:874:874) (981:981:981))
+        (IOPATH i o (1555:1555:1555) (1528:1528:1528))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (695:695:695) (767:767:767))
+        (IOPATH i o (1590:1590:1590) (1579:1579:1579))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (529:529:529) (583:583:583))
+        (IOPATH i o (1600:1600:1600) (1589:1589:1589))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (654:654:654) (720:720:720))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (679:679:679) (757:757:757))
+        (IOPATH i o (1610:1610:1610) (1599:1599:1599))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (242:242:242) (617:617:617))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (283:283:283) (658:658:658))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (272:272:272) (647:647:647))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (293:293:293) (668:668:668))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (253:253:253) (628:628:628))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1929:1929:1929) (2149:2149:2149))
+        (PORT datab (2091:2091:2091) (2339:2339:2339))
+        (PORT datac (2165:2165:2165) (2432:2432:2432))
+        (PORT datad (902:902:902) (823:823:823))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (882:882:882))
+        (PORT datab (2196:2196:2196) (2465:2465:2465))
+        (PORT datad (102:102:102) (125:125:125))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2181:2181:2181) (2444:2444:2444))
+        (PORT datad (102:102:102) (125:125:125))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2029:2029:2029) (2254:2254:2254))
+        (PORT datab (112:112:112) (139:139:139))
+        (PORT datac (2115:2115:2115) (2369:2369:2369))
+        (PORT datad (95:95:95) (115:115:115))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2053:2053:2053) (2279:2279:2279))
+        (PORT datab (2135:2135:2135) (2395:2395:2395))
+        (PORT datac (97:97:97) (118:118:118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (253:253:253) (628:628:628))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (111:111:111) (138:138:138))
+        (PORT datac (2057:2057:2057) (2289:2289:2289))
+        (PORT datad (2146:2146:2146) (2380:2380:2380))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (293:293:293) (668:668:668))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (114:114:114) (142:142:142))
+        (PORT datac (1989:1989:1989) (2206:2206:2206))
+        (PORT datad (2019:2019:2019) (2242:2242:2242))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (273:273:273) (648:648:648))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2121:2121:2121) (2361:2361:2361))
+        (PORT datac (695:695:695) (811:811:811))
+        (PORT datad (1983:1983:1983) (2200:2200:2200))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (273:273:273) (648:648:648))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1921:1921:1921) (2115:2115:2115))
+        (PORT datab (119:119:119) (148:148:148))
+        (PORT datac (2014:2014:2014) (2245:2245:2245))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (108:108:108) (134:134:134))
+        (PORT datab (966:966:966) (858:858:858))
+        (PORT datac (942:942:942) (845:845:845))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1921:1921:1921) (2115:2115:2115))
+        (PORT datab (957:957:957) (856:856:856))
+        (PORT datac (2012:2012:2012) (2243:2243:2243))
+        (PORT datad (98:98:98) (121:121:121))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\EN\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (110:110:110) (136:136:136))
+        (PORT datab (967:967:967) (859:859:859))
+        (PORT datad (2158:2158:2158) (2398:2398:2398))
+        (IOPATH dataa combout (166:166:166) (159:159:159))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1921:1921:1921) (2115:2115:2115))
+        (PORT datab (113:113:113) (142:142:142))
+        (PORT datac (2012:2012:2012) (2243:2243:2243))
+        (PORT datad (2155:2155:2155) (2395:2395:2395))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2174:2174:2174) (2422:2422:2422))
+        (PORT datab (2119:2119:2119) (2359:2359:2359))
+        (PORT datac (697:697:697) (813:813:813))
+        (PORT datad (1982:1982:1982) (2199:2199:2199))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (115:115:115) (143:143:143))
+        (PORT datab (2003:2003:2003) (2225:2225:2225))
+        (PORT datac (2034:2034:2034) (2259:2259:2259))
+        (PORT datad (2189:2189:2189) (2445:2445:2445))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2163:2163:2163) (2406:2406:2406))
+        (PORT datab (113:113:113) (140:140:140))
+        (PORT datac (2058:2058:2058) (2290:2290:2290))
+        (PORT datad (2196:2196:2196) (2451:2451:2451))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2053:2053:2053) (2279:2279:2279))
+        (PORT datab (2135:2135:2135) (2395:2395:2395))
+        (PORT datac (97:97:97) (118:118:118))
+        (PORT datad (2190:2190:2190) (2444:2444:2444))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2030:2030:2030) (2254:2254:2254))
+        (PORT datab (112:112:112) (139:139:139))
+        (PORT datac (2115:2115:2115) (2369:2369:2369))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2206:2206:2206) (2468:2468:2468))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (983:983:983) (883:883:883))
+        (PORT datab (118:118:118) (146:146:146))
+        (PORT datac (2181:2181:2181) (2445:2445:2445))
+        (PORT datad (2193:2193:2193) (2449:2449:2449))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1928:1928:1928) (2149:2149:2149))
+        (PORT datab (2093:2093:2093) (2341:2341:2341))
+        (PORT datac (2163:2163:2163) (2430:2430:2430))
+        (PORT datad (904:904:904) (825:825:825))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2208:2208:2208) (2471:2471:2471))
+        (PORT datad (91:91:91) (109:109:109))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2094:2094:2094) (2342:2342:2342))
+        (PORT datac (2163:2163:2163) (2430:2430:2430))
+        (PORT datad (2194:2194:2194) (2449:2449:2449))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_modelsim.xrf b/ten_bit_adder/simulation/modelsim/ten_bit_adder_modelsim.xrf
new file mode 100644
index 0000000..b027809
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_modelsim.xrf
@@ -0,0 +1,53 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder_no_bus.bsf
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bsf
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder/ten_bit_adder_no_bus.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder/db/ten_bit_adder.cbx.xml
+design_name = ten_bit_adder
+instance = comp, \Cout~output\, Cout~output, ten_bit_adder, 1
+instance = comp, \S[9]~output\, S[9]~output, ten_bit_adder, 1
+instance = comp, \S[8]~output\, S[8]~output, ten_bit_adder, 1
+instance = comp, \S[7]~output\, S[7]~output, ten_bit_adder, 1
+instance = comp, \S[6]~output\, S[6]~output, ten_bit_adder, 1
+instance = comp, \S[5]~output\, S[5]~output, ten_bit_adder, 1
+instance = comp, \S[4]~output\, S[4]~output, ten_bit_adder, 1
+instance = comp, \S[3]~output\, S[3]~output, ten_bit_adder, 1
+instance = comp, \S[2]~output\, S[2]~output, ten_bit_adder, 1
+instance = comp, \S[1]~output\, S[1]~output, ten_bit_adder, 1
+instance = comp, \S[0]~output\, S[0]~output, ten_bit_adder, 1
+instance = comp, \Y[8]~input\, Y[8]~input, ten_bit_adder, 1
+instance = comp, \Y[7]~input\, Y[7]~input, ten_bit_adder, 1
+instance = comp, \X[4]~input\, X[4]~input, ten_bit_adder, 1
+instance = comp, \Y[4]~input\, Y[4]~input, ten_bit_adder, 1
+instance = comp, \X[3]~input\, X[3]~input, ten_bit_adder, 1
+instance = comp, \X[2]~input\, X[2]~input, ten_bit_adder, 1
+instance = comp, \Y[2]~input\, Y[2]~input, ten_bit_adder, 1
+instance = comp, \Y[1]~input\, Y[1]~input, ten_bit_adder, 1
+instance = comp, \X[0]~input\, X[0]~input, ten_bit_adder, 1
+instance = comp, \Y[0]~input\, Y[0]~input, ten_bit_adder, 1
+instance = comp, \X[1]~input\, X[1]~input, ten_bit_adder, 1
+instance = comp, \inst9|inst3~0\, inst9|inst3~0, ten_bit_adder, 1
+instance = comp, \inst10|inst3~1\, inst10|inst3~1, ten_bit_adder, 1
+instance = comp, \Y[3]~input\, Y[3]~input, ten_bit_adder, 1
+instance = comp, \inst10|inst3~0\, inst10|inst3~0, ten_bit_adder, 1
+instance = comp, \inst11|inst3~0\, inst11|inst3~0, ten_bit_adder, 1
+instance = comp, \inst13|inst3~0\, inst13|inst3~0, ten_bit_adder, 1
+instance = comp, \Y[5]~input\, Y[5]~input, ten_bit_adder, 1
+instance = comp, \X[5]~input\, X[5]~input, ten_bit_adder, 1
+instance = comp, \inst13|inst3~1\, inst13|inst3~1, ten_bit_adder, 1
+instance = comp, \X[6]~input\, X[6]~input, ten_bit_adder, 1
+instance = comp, \Y[6]~input\, Y[6]~input, ten_bit_adder, 1
+instance = comp, \inst15|inst3~0\, inst15|inst3~0, ten_bit_adder, 1
+instance = comp, \X[7]~input\, X[7]~input, ten_bit_adder, 1
+instance = comp, \inst15|inst3~1\, inst15|inst3~1, ten_bit_adder, 1
+instance = comp, \X[8]~input\, X[8]~input, ten_bit_adder, 1
+instance = comp, \inst17|inst3~0\, inst17|inst3~0, ten_bit_adder, 1
+instance = comp, \Y[9]~input\, Y[9]~input, ten_bit_adder, 1
+instance = comp, \X[9]~input\, X[9]~input, ten_bit_adder, 1
+instance = comp, \inst17|inst3~1\, inst17|inst3~1, ten_bit_adder, 1
+instance = comp, \inst17|inst2~0\, inst17|inst2~0, ten_bit_adder, 1
+instance = comp, \EN~input\, EN~input, ten_bit_adder, 1
+instance = comp, \inst11|inst2\, inst11|inst2, ten_bit_adder, 1
+instance = comp, \inst9|inst2~0\, inst9|inst2~0, ten_bit_adder, 1
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_vhd.sdo b/ten_bit_adder/simulation/modelsim/ten_bit_adder_vhd.sdo
new file mode 100644
index 0000000..4ef4927
--- /dev/null
+++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_vhd.sdo
@@ -0,0 +1,676 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder")
+  (DATE "02/18/2016 22:20:18")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1008:1008:1008) (991:991:991))
+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1033:1033:1033) (1038:1038:1038))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (983:983:983) (987:987:987))
+        (IOPATH i o (2659:2659:2659) (2557:2557:2557))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1262:1262:1262) (1247:1247:1247))
+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2241:2241:2241) (2301:2301:2301))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1070:1070:1070) (1079:1079:1079))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1572:1572:1572) (1600:1600:1600))
+        (IOPATH i o (2544:2544:2544) (2446:2446:2446))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S\[3\]\~output\\)
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+    (DELAY
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+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
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+    (DELAY
+      (ABSOLUTE
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+        (IOPATH i o (2639:2639:2639) (2537:2537:2537))
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+    (DELAY
+      (ABSOLUTE
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+    (DELAY
+      (ABSOLUTE
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+    (DELAY
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+    (INSTANCE \\Y\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
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+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[3\]\~input\\)
+    (DELAY
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+    (INSTANCE \\X\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
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+    (DELAY
+      (ABSOLUTE
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+    (DELAY
+      (ABSOLUTE
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+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
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+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
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+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3335:3335:3335) (3624:3624:3624))
+        (PORT datab (3633:3633:3633) (3944:3944:3944))
+        (PORT datac (3715:3715:3715) (4060:4060:4060))
+        (PORT datad (1455:1455:1455) (1430:1430:1430))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1601:1601:1601) (1544:1544:1544))
+        (PORT datab (3744:3744:3744) (4086:4086:4086))
+        (PORT datad (190:190:190) (223:223:223))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (3714:3714:3714) (4052:4052:4052))
+        (PORT datad (191:191:191) (223:223:223))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3499:3499:3499) (3781:3781:3781))
+        (PORT datab (214:214:214) (251:251:251))
+        (PORT datac (3639:3639:3639) (3972:3972:3972))
+        (PORT datad (180:180:180) (209:209:209))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3554:3554:3554) (3826:3826:3826))
+        (PORT datab (3678:3678:3678) (4005:4005:4005))
+        (PORT datac (184:184:184) (215:215:215))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (214:214:214) (248:248:248))
+        (PORT datac (3559:3559:3559) (3855:3855:3855))
+        (PORT datad (3704:3704:3704) (3992:3992:3992))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (555:555:555) (728:728:728))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (217:217:217) (255:255:255))
+        (PORT datac (3430:3430:3430) (3716:3716:3716))
+        (PORT datad (3498:3498:3498) (3782:3782:3782))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3667:3667:3667) (3975:3975:3975))
+        (PORT datac (1249:1249:1249) (1324:1324:1324))
+        (PORT datad (3427:3427:3427) (3708:3708:3708))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3303:3303:3303) (3563:3563:3563))
+        (PORT datab (223:223:223) (262:262:262))
+        (PORT datac (3467:3467:3467) (3772:3772:3772))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (209:209:209) (243:243:243))
+        (PORT datab (1559:1559:1559) (1480:1480:1480))
+        (PORT datac (1505:1505:1505) (1435:1435:1435))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3303:3303:3303) (3563:3563:3563))
+        (PORT datab (1533:1533:1533) (1460:1460:1460))
+        (PORT datac (3465:3465:3465) (3770:3770:3770))
+        (PORT datad (187:187:187) (220:220:220))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\EN\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst25)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (245:245:245))
+        (PORT datab (1560:1560:1560) (1481:1481:1481))
+        (PORT datad (3724:3724:3724) (4015:4015:4015))
+        (IOPATH dataa combout (325:325:325) (328:328:328))
+        (IOPATH datab combout (336:336:336) (332:332:332))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst24)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3302:3302:3302) (3563:3563:3563))
+        (PORT datab (218:218:218) (256:256:256))
+        (PORT datac (3465:3465:3465) (3770:3770:3770))
+        (PORT datad (3721:3721:3721) (4012:4012:4012))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst23)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3756:3756:3756) (4056:4056:4056))
+        (PORT datab (3666:3666:3666) (3973:3973:3973))
+        (PORT datac (1250:1250:1250) (1326:1326:1326))
+        (PORT datad (3426:3426:3426) (3706:3706:3706))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst22)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (218:218:218) (256:256:256))
+        (PORT datab (3459:3459:3459) (3748:3748:3748))
+        (PORT datac (3534:3534:3534) (3810:3810:3810))
+        (PORT datad (3770:3770:3770) (4104:4104:4104))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst21)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3738:3738:3738) (4035:4035:4035))
+        (PORT datab (215:215:215) (250:250:250))
+        (PORT datac (3559:3559:3559) (3857:3857:3857))
+        (PORT datad (3777:3777:3777) (4112:4112:4112))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3554:3554:3554) (3826:3826:3826))
+        (PORT datab (3678:3678:3678) (4005:4005:4005))
+        (PORT datac (185:185:185) (215:215:215))
+        (PORT datad (3771:3771:3771) (4105:4105:4105))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3499:3499:3499) (3781:3781:3781))
+        (PORT datab (214:214:214) (250:250:250))
+        (PORT datac (3639:3639:3639) (3972:3972:3972))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3810:3810:3810) (4143:4143:4143))
+        (PORT datad (176:176:176) (200:200:200))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1602:1602:1602) (1545:1545:1545))
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (3715:3715:3715) (4053:4053:4053))
+        (PORT datad (3775:3775:3775) (4110:4110:4110))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3335:3335:3335) (3623:3623:3623))
+        (PORT datab (3635:3635:3635) (3946:3946:3946))
+        (PORT datac (3713:3713:3713) (4058:4058:4058))
+        (PORT datad (1457:1457:1457) (1432:1432:1432))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3813:3813:3813) (4147:4147:4147))
+        (PORT datad (175:175:175) (199:199:199))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3635:3635:3635) (3946:3946:3946))
+        (PORT datac (3712:3712:3712) (4057:4057:4057))
+        (PORT datad (3775:3775:3775) (4110:4110:4110))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder/ten_bit_adder.bdf b/ten_bit_adder/ten_bit_adder.bdf
new file mode 100644
index 0000000..cfbf632
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder.bdf
@@ -0,0 +1,1364 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
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+	(pt 816 1024)
+)
+(connector
+	(pt 816 1024)
+	(pt 816 1136)
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+(connector
+	(pt 816 1136)
+	(pt 816 1248)
+)
+(connector
+	(pt 816 1248)
+	(pt 816 1360)
+)
+(connector
+	(text "EN" (rect 800 411 812 426)(font "Arial" )(vertical))
+	(pt 816 408)
+	(pt 816 464)
+)
+(connector
+	(pt 816 464)
+	(pt 816 576)
+)
+(connector
+	(pt 816 576)
+	(pt 816 688)
+)
+(junction (pt 816 576))
+(junction (pt 816 688))
+(junction (pt 816 800))
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diff --git a/ten_bit_adder/ten_bit_adder.bsf b/ten_bit_adder/ten_bit_adder.bsf
new file mode 100644
index 0000000..3d8ebbb
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 144 112)
+	(text "ten_bit_adder" (rect 5 0 82 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "EN" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "EN" (rect 21 27 36 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "X[9..0]" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "X[9..0]" (rect 21 43 57 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Y[9..0]" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "Y[9..0]" (rect 21 59 58 73)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 128 32)
+		(output)
+		(text "S[9..0]" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "S[9..0]" (rect 71 27 107 41)(font "Arial" (font_size 8)))
+		(line (pt 128 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 128 48)
+		(output)
+		(text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "Cout" (rect 82 43 107 57)(font "Arial" (font_size 8)))
+		(line (pt 128 48)(pt 112 48))
+	)
+	(drawing
+		(rectangle (rect 16 16 112 80))
+	)
+)
diff --git a/ten_bit_adder/ten_bit_adder.qpf b/ten_bit_adder/ten_bit_adder.qpf
new file mode 100644
index 0000000..c6149fc
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 18:54:51  February 18, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "18:54:51  February 18, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ten_bit_adder"
diff --git a/ten_bit_adder/ten_bit_adder.qsf b/ten_bit_adder/ten_bit_adder.qsf
new file mode 100644
index 0000000..c9a3a5d
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder.qsf
@@ -0,0 +1,56 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 18:54:51  February 18, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ten_bit_adder_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name DEVICE auto
+set_global_assignment -name TOP_LEVEL_ENTITY ten_bit_adder
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:54:51  FEBRUARY 18, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BSF_FILE ten_bit_adder_no_bus.bsf
+set_global_assignment -name BSF_FILE ../adder/full_adder.bsf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name BDF_FILE ten_bit_adder.bdf
+set_global_assignment -name BDF_FILE ten_bit_adder_no_bus.bdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/ten_bit_adder/ten_bit_adder.qws b/ten_bit_adder/ten_bit_adder.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder.qws
diff --git a/ten_bit_adder/ten_bit_adder_no_bus.bdf b/ten_bit_adder/ten_bit_adder_no_bus.bdf
new file mode 100644
index 0000000..821e6bb
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder_no_bus.bdf
@@ -0,0 +1,1872 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
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+(pin
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+	(rect 112 448 280 464)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y0" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
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+	(pt 552 1024)
+)
+(connector
+	(pt 680 1136)
+	(pt 552 1136)
+)
+(connector
+	(pt 680 1360)
+	(pt 552 1360)
+)
+(connector
+	(pt 680 1472)
+	(pt 552 1472)
+)
+(connector
+	(pt 488 472)
+	(pt 440 472)
+)
+(connector
+	(pt 488 584)
+	(pt 440 584)
+)
+(connector
+	(pt 488 696)
+	(pt 440 696)
+)
+(connector
+	(pt 488 808)
+	(pt 440 808)
+)
+(connector
+	(pt 488 920)
+	(pt 440 920)
+)
+(connector
+	(pt 488 1032)
+	(pt 440 1032)
+)
+(connector
+	(pt 488 1144)
+	(pt 440 1144)
+)
+(connector
+	(pt 488 1368)
+	(pt 440 1368)
+)
+(connector
+	(pt 488 1480)
+	(pt 440 1480)
+)
+(connector
+	(pt 680 1248)
+	(pt 552 1248)
+)
+(connector
+	(pt 440 1256)
+	(pt 488 1256)
+)
+(connector
+	(text "EN" (rect 426 417 438 432)(font "Arial" )(vertical))
+	(pt 440 416)
+	(pt 440 472)
+)
+(connector
+	(pt 440 472)
+	(pt 440 584)
+)
+(connector
+	(pt 440 584)
+	(pt 440 696)
+)
+(connector
+	(pt 440 696)
+	(pt 440 808)
+)
+(connector
+	(pt 440 808)
+	(pt 440 920)
+)
+(connector
+	(pt 440 920)
+	(pt 440 1032)
+)
+(connector
+	(pt 440 1032)
+	(pt 440 1144)
+)
+(connector
+	(pt 440 1144)
+	(pt 440 1256)
+)
+(connector
+	(pt 440 1256)
+	(pt 440 1368)
+)
+(connector
+	(pt 440 1368)
+	(pt 440 1480)
+)
+(connector
+	(text "Y0" (rect 449 440 463 452)(font "Arial" ))
+	(pt 416 456)
+	(pt 488 456)
+)
+(connector
+	(text "Y1" (rect 446 552 460 564)(font "Arial" ))
+	(pt 416 568)
+	(pt 488 568)
+)
+(connector
+	(text "Y2" (rect 447 664 461 676)(font "Arial" ))
+	(pt 416 680)
+	(pt 488 680)
+)
+(connector
+	(text "Y3" (rect 444 776 458 788)(font "Arial" ))
+	(pt 416 792)
+	(pt 488 792)
+)
+(connector
+	(text "Y4" (rect 447 888 461 900)(font "Arial" ))
+	(pt 416 904)
+	(pt 488 904)
+)
+(connector
+	(text "Y5" (rect 444 1000 458 1012)(font "Arial" ))
+	(pt 416 1016)
+	(pt 488 1016)
+)
+(connector
+	(text "Y6" (rect 443 1112 457 1124)(font "Arial" ))
+	(pt 416 1128)
+	(pt 488 1128)
+)
+(connector
+	(text "Y7" (rect 444 1224 458 1236)(font "Arial" ))
+	(pt 416 1240)
+	(pt 488 1240)
+)
+(connector
+	(text "Y8" (rect 446 1336 460 1348)(font "Arial" ))
+	(pt 416 1352)
+	(pt 488 1352)
+)
+(connector
+	(text "Y9" (rect 446 1448 460 1460)(font "Arial" ))
+	(pt 416 1464)
+	(pt 488 1464)
+)
+(junction (pt 440 920))
+(junction (pt 440 1032))
+(junction (pt 440 1144))
+(junction (pt 440 1368))
+(junction (pt 440 472))
+(junction (pt 440 584))
+(junction (pt 440 696))
+(junction (pt 440 808))
+(junction (pt 440 1256))
diff --git a/ten_bit_adder/ten_bit_adder_no_bus.bsf b/ten_bit_adder/ten_bit_adder_no_bus.bsf
new file mode 100644
index 0000000..26b68ad
--- /dev/null
+++ b/ten_bit_adder/ten_bit_adder_no_bus.bsf
@@ -0,0 +1,253 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 112 400)
+	(text "ten_bit_adder_no_bus" (rect 5 0 132 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 368 25 380)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "EN Y" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+		(text "EN Y" (rect 21 27 49 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "X0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X0" (rect 21 43 36 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "X1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X1" (rect 21 59 36 73)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "X2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X2" (rect 21 75 36 89)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "X3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X3" (rect 21 91 36 105)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "X4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X4" (rect 21 107 36 121)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "X5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X5" (rect 21 123 36 137)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "X6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X6" (rect 21 139 36 153)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "X7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X7" (rect 21 155 36 169)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 16 160))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "X8" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X8" (rect 21 171 36 185)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 16 176))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "X9" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X9" (rect 21 187 36 201)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 16 192))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y0" (rect 21 203 37 217)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "Y1" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y1" (rect 21 219 37 233)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224))
+	)
+	(port
+		(pt 0 240)
+		(input)
+		(text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y2" (rect 21 235 37 249)(font "Arial" (font_size 8)))
+		(line (pt 0 240)(pt 16 240))
+	)
+	(port
+		(pt 0 256)
+		(input)
+		(text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y3" (rect 21 251 37 265)(font "Arial" (font_size 8)))
+		(line (pt 0 256)(pt 16 256))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y4" (rect 21 267 37 281)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 16 272))
+	)
+	(port
+		(pt 0 288)
+		(input)
+		(text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y5" (rect 21 283 37 297)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 16 288))
+	)
+	(port
+		(pt 0 304)
+		(input)
+		(text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y6" (rect 21 299 37 313)(font "Arial" (font_size 8)))
+		(line (pt 0 304)(pt 16 304))
+	)
+	(port
+		(pt 0 320)
+		(input)
+		(text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y7" (rect 21 315 37 329)(font "Arial" (font_size 8)))
+		(line (pt 0 320)(pt 16 320))
+	)
+	(port
+		(pt 0 336)
+		(input)
+		(text "Y8" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y8" (rect 21 331 37 345)(font "Arial" (font_size 8)))
+		(line (pt 0 336)(pt 16 336))
+	)
+	(port
+		(pt 0 352)
+		(input)
+		(text "Y9" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y9" (rect 21 347 37 361)(font "Arial" (font_size 8)))
+		(line (pt 0 352)(pt 16 352))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "S0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S0" (rect 60 27 75 41)(font "Arial" (font_size 8)))
+		(line (pt 96 32)(pt 80 32))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "S1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S1" (rect 60 43 75 57)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 80 48))
+	)
+	(port
+		(pt 96 64)
+		(output)
+		(text "S2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S2" (rect 60 59 75 73)(font "Arial" (font_size 8)))
+		(line (pt 96 64)(pt 80 64))
+	)
+	(port
+		(pt 96 80)
+		(output)
+		(text "S3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S3" (rect 60 75 75 89)(font "Arial" (font_size 8)))
+		(line (pt 96 80)(pt 80 80))
+	)
+	(port
+		(pt 96 96)
+		(output)
+		(text "S4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S4" (rect 60 91 75 105)(font "Arial" (font_size 8)))
+		(line (pt 96 96)(pt 80 96))
+	)
+	(port
+		(pt 96 112)
+		(output)
+		(text "S5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S5" (rect 60 107 75 121)(font "Arial" (font_size 8)))
+		(line (pt 96 112)(pt 80 112))
+	)
+	(port
+		(pt 96 128)
+		(output)
+		(text "S6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S6" (rect 60 123 75 137)(font "Arial" (font_size 8)))
+		(line (pt 96 128)(pt 80 128))
+	)
+	(port
+		(pt 96 144)
+		(output)
+		(text "S7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S7" (rect 60 139 75 153)(font "Arial" (font_size 8)))
+		(line (pt 96 144)(pt 80 144))
+	)
+	(port
+		(pt 96 160)
+		(output)
+		(text "S8" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S8" (rect 60 155 75 169)(font "Arial" (font_size 8)))
+		(line (pt 96 160)(pt 80 160))
+	)
+	(port
+		(pt 96 176)
+		(output)
+		(text "S9" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S9" (rect 60 171 75 185)(font "Arial" (font_size 8)))
+		(line (pt 96 176)(pt 80 176))
+	)
+	(port
+		(pt 96 192)
+		(output)
+		(text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "Cout" (rect 50 187 75 201)(font "Arial" (font_size 8)))
+		(line (pt 96 192)(pt 80 192))
+	)
+	(drawing
+		(rectangle (rect 16 16 80 368))
+	)
+)
diff --git a/ten_bit_adder_NO_BUS/Waveform.vwf b/ten_bit_adder_NO_BUS/Waveform.vwf
new file mode 100644
index 0000000..bb7e9a8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/Waveform.vwf
@@ -0,0 +1,936 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("Cout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("ENY")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("S0")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S1")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S2")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S3")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S4")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S5")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S6")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S7")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S8")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("S9")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("X0")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X1")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X2")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X3")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X4")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X5")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X6")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X7")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X8")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("X9")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y0")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y1")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y2")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y3")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y4")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y5")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y6")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y7")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y8")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("Y9")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("Cout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("ENY")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S0")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S1")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S2")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S3")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S4")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S5")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S6")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S7")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S8")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("S9")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X0")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X1")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X2")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X3")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X4")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X5")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X6")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X7")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X8")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("X9")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y0")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y1")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y2")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y3")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y4")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y5")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y6")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y7")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y8")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("Y9")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Cout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ENY";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S0";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S1";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S2";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S3";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S4";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S5";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S6";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S7";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S8";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "S9";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 11;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X0";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 12;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X1";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 13;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X2";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 14;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X3";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 15;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X4";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 16;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X5";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 17;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X6";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 18;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X7";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 19;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X8";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 20;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "X9";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 21;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y0";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 22;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y1";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 23;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y2";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 24;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y3";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 25;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y4";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 26;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y5";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 27;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y6";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 28;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y7";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 29;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y8";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 30;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "Y9";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 31;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
diff --git a/ten_bit_adder_NO_BUS/db/.cmp.kpt b/ten_bit_adder_NO_BUS/db/.cmp.kpt
new file mode 100644
index 0000000..2ad8576
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/.cmp.kpt
diff --git a/ten_bit_adder_NO_BUS/db/logic_util_heursitic.dat b/ten_bit_adder_NO_BUS/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..ce9ad3e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/logic_util_heursitic.dat
diff --git a/ten_bit_adder_NO_BUS/db/prev_cmp_ten_bit_adder_NO_BUS.qmsg b/ten_bit_adder_NO_BUS/db/prev_cmp_ten_bit_adder_NO_BUS.qmsg
new file mode 100644
index 0000000..2114e54
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/prev_cmp_ten_bit_adder_NO_BUS.qmsg
@@ -0,0 +1,11 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455836171675 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455836171676 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:56:11 2016 " "Processing started: Thu Feb 18 22:56:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455836171676 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455836171676 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455836171676 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455836171951 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455836171993 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455836171993 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455836171995 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455836171995 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_bit_adder_NO_BUS " "Elaborating entity \"ten_bit_adder_NO_BUS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455836172018 ""}
+{ "Error" "EGDFX_ILLEGAL_WIRE_OR_BUS_NAME" "pin EN Y " "Illegal wire or bus name \"EN Y\" of type pin " {  } { { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 248 320 488 264 "EN Y" "" } } } }  } 0 275021 "Illegal wire or bus name \"%2!s!\" of type %1!s! " 0 0 "Quartus II" 0 -1 1455836172020 ""}
+{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" {  } {  } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Quartus II" 0 -1 1455836172021 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "540 " "Peak virtual memory: 540 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836172094 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:12 2016 " "Processing ended: Thu Feb 18 22:56:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836172094 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836172094 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836172094 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455836172094 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 4 s 1  " "Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455836172691 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.cdb
new file mode 100644
index 0000000..caba431
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.hdb
new file mode 100644
index 0000000..1eccc08
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(0).cnf.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.cdb
new file mode 100644
index 0000000..3bfc62a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.hdb
new file mode 100644
index 0000000..a7c2865
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.(1).cnf.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.qmsg b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.qmsg
new file mode 100644
index 0000000..d6cfe2a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455836205678 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455836205679 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:56:45 2016 " "Processing started: Thu Feb 18 22:56:45 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455836205679 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455836205679 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455836205679 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455836206388 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455836206409 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836206693 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:46 2016 " "Processing ended: Thu Feb 18 22:56:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836206693 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836206693 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836206693 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455836206693 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.rdb
new file mode 100644
index 0000000..8f5d5b4
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm_labs.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm_labs.ddb
new file mode 100644
index 0000000..0255201
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.asm_labs.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cbx.xml b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cbx.xml
new file mode 100644
index 0000000..8253b40
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ten_bit_adder_NO_BUS">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.bpm b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.bpm
new file mode 100644
index 0000000..b6f2bfc
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.bpm
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.cdb
new file mode 100644
index 0000000..355b055
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.hdb
new file mode 100644
index 0000000..87015a0
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.idb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.idb
new file mode 100644
index 0000000..dac0c66
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.idb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.logdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.logdb
new file mode 100644
index 0000000..73f5c4d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.logdb
@@ -0,0 +1,74 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;32;0;0;32;32;0;11;0;0;21;0;11;21;0;0;0;11;0;0;0;0;0;32;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,32;32;32;32;32;0;32;32;0;0;32;21;32;32;11;32;21;11;32;32;32;21;32;32;32;32;32;0;32;32,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Cout,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,S9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ENY,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Y1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X4,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X5,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X6,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X7,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X8,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,X9,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.rdb
new file mode 100644
index 0000000..ccfaab4
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp_merge.kpt b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp_merge.kpt
new file mode 100644
index 0000000..48a1330
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cmp_merge.kpt
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.db_info b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.db_info
new file mode 100644
index 0000000..53f1e6e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 14:39:14 2016
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.eda.qmsg b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.eda.qmsg
new file mode 100644
index 0000000..eb81c29
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455836212217 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455836212217 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:56:52 2016 " "Processing started: Thu Feb 18 22:56:52 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455836212217 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455836212217 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455836212217 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212630 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212659 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212685 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS.vho C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212711 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212741 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212769 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212792 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_bit_adder_NO_BUS_vhd.sdo C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ simulation " "Generated file ten_bit_adder_NO_BUS_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455836212816 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "483 " "Peak virtual memory: 483 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836212865 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:52 2016 " "Processing ended: Thu Feb 18 22:56:52 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836212865 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836212865 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836212865 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455836212865 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.fit.qmsg b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.fit.qmsg
new file mode 100644
index 0000000..4aa1c02
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455836198501 ""}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "ten_bit_adder_NO_BUS EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design ten_bit_adder_NO_BUS" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455836198637 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455836198692 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455836198692 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455836198779 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455836198790 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455836198964 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455836198964 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455836198964 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 119 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455836198966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 121 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455836198966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 123 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455836198966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 125 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455836198966 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 127 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455836198966 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455836198966 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455836198967 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "32 32 " "No exact pin location assignment(s) for 32 pins of 32 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cout " "Pin Cout not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cout } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1520 1184 1360 1536 "Cout" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S0 " "Pin S0 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S0 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 440 1016 1192 456 "S0" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 35 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S1 " "Pin S1 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S1 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 552 1016 1192 568 "S1" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 36 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S2 " "Pin S2 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S2 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 664 1016 1192 680 "S2" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 37 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S3 " "Pin S3 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S3 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 776 1016 1192 792 "S3" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 38 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S4 " "Pin S4 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S4 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 888 1016 1192 904 "S4" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 39 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S5 " "Pin S5 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S5 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1000 1016 1192 1016 "S5" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 40 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S6 " "Pin S6 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S6 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1112 1016 1192 1128 "S6" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 41 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S7 " "Pin S7 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S7 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1224 1016 1192 1240 "S7" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S8 " "Pin S8 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S8 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1336 1016 1192 1352 "S8" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 43 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "S9 " "Pin S9 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { S9 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1448 1016 1192 1464 "S9" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { S9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y9 " "Pin Y9 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y9 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 592 320 488 608 "Y9" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "ENY " "Pin ENY not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ENY } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 248 320 488 264 "ENY" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ENY } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y8 " "Pin Y8 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y8 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 576 320 488 592 "Y8" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y7 " "Pin Y7 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y7 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 560 320 488 576 "Y7" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 20 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y6 " "Pin Y6 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y6 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 544 320 488 560 "Y6" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 22 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y5 " "Pin Y5 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y5 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 528 320 488 544 "Y5" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 24 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y4 " "Pin Y4 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y4 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 512 320 488 528 "Y4" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 26 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y3 " "Pin Y3 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y3 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 496 320 488 512 "Y3" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 28 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y2 " "Pin Y2 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y2 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 480 320 488 496 "Y2" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 30 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y0 " "Pin Y0 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y0 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 448 320 488 464 "Y0" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 34 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X0 " "Pin X0 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X0 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 280 320 488 296 "X0" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 33 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y1 " "Pin Y1 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y1 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 464 320 488 480 "Y1" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 32 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X1 " "Pin X1 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X1 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 296 320 488 312 "X1" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 31 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X2 " "Pin X2 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X2 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 312 320 488 328 "X2" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 29 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X3 " "Pin X3 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X3 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 328 320 488 344 "X3" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 27 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X4 " "Pin X4 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X4 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 344 320 488 360 "X4" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X5 " "Pin X5 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X5 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 360 320 488 376 "X5" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X5 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X6 " "Pin X6 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X6 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 376 320 488 392 "X6" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X7 " "Pin X7 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X7 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 392 320 488 408 "X7" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X7 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 19 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X8 " "Pin X8 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X8 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 408 320 488 424 "X8" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X8 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 17 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X9 " "Pin X9 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X9 } } } { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 424 320 488 440 "X9" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X9 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455836199303 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455836199303 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_bit_adder_NO_BUS.sdc " "Synopsys Design Constraints File file not found: 'ten_bit_adder_NO_BUS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455836199545 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455836199545 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1455836199546 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455836199546 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455836199546 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455836199546 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455836199546 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455836199548 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455836199548 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455836199549 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455836199549 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455836199549 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455836199550 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455836199550 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455836199550 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455836199550 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "32 unused 2.5V 21 11 0 " "Number of I/O pins in group: 32 (unused VREF, 2.5V VCCIO, 21 input, 11 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455836199552 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455836199552 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455836199552 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 0 2 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455836199552 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455836199552 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455836199552 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455836199588 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455836200564 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455836200622 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455836200629 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455836200829 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455836200829 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455836201840 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X22_Y0 X33_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9"} 22 0 12 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455836202311 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455836202311 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455836202361 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455836202362 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455836202362 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455836202362 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455836202372 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455836202470 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455836202654 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455836202738 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455836202916 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455836203307 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455836203683 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "911 " "Peak virtual memory: 911 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836204008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:44 2016 " "Processing ended: Thu Feb 18 22:56:44 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836204008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836204008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836204008 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455836204008 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hier_info b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hier_info
new file mode 100644
index 0000000..21add7d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hier_info
@@ -0,0 +1,184 @@
+|ten_bit_adder_NO_BUS
+Cout <= full_adder:inst17.Cout
+X9 => full_adder:inst17.X
+Y9 => inst25.IN0
+ENY => inst25.IN1
+ENY => inst24.IN1
+ENY => inst23.IN1
+ENY => inst22.IN1
+ENY => inst21.IN1
+ENY => inst20.IN1
+ENY => inst19.IN1
+ENY => inst18.IN1
+ENY => inst7.IN1
+ENY => inst6.IN1
+X8 => full_adder:inst16.X
+Y8 => inst24.IN0
+X7 => full_adder:inst15.X
+Y7 => inst23.IN0
+X6 => full_adder:inst14.X
+Y6 => inst22.IN0
+X5 => full_adder:inst13.X
+Y5 => inst21.IN0
+X4 => full_adder:inst12.X
+Y4 => inst20.IN0
+X3 => full_adder:inst11.X
+Y3 => inst19.IN0
+X2 => full_adder:inst10.X
+Y2 => inst18.IN0
+X1 => full_adder:inst9.X
+Y1 => inst7.IN0
+X0 => full_adder:inst8.X
+Y0 => inst6.IN0
+S0 <= full_adder:inst8.SUM
+S1 <= full_adder:inst9.SUM
+S2 <= full_adder:inst10.SUM
+S3 <= full_adder:inst11.SUM
+S4 <= full_adder:inst12.SUM
+S5 <= full_adder:inst13.SUM
+S6 <= full_adder:inst14.SUM
+S7 <= full_adder:inst15.SUM
+S8 <= full_adder:inst16.SUM
+S9 <= full_adder:inst17.SUM
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst17
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst16
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst15
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst14
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst13
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst12
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst11
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst10
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst9
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ten_bit_adder_NO_BUS|full_adder:inst8
+SUM <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+X => inst.IN0
+X => inst6.IN0
+X => inst4.IN1
+Y => inst.IN1
+Y => inst5.IN1
+Y => inst6.IN1
+Cin => inst2.IN1
+Cin => inst5.IN0
+Cin => inst4.IN0
+Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hif b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hif
new file mode 100644
index 0000000..86d9298
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.hif
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.ipinfo b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.ipinfo
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.html b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.html
new file mode 100644
index 0000000..c2f91e6
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.html
@@ -0,0 +1,178 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst8</TD>
+<TD >3</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >2</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst9</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst10</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst11</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst12</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst13</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst14</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst15</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst16</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst17</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.rdb
new file mode 100644
index 0000000..eeeec9c
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.txt b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.txt
new file mode 100644
index 0000000..c862e87
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.lpc.txt
@@ -0,0 +1,16 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst8     ; 3     ; 1              ; 0            ; 1              ; 2      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst9     ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst11    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst12    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst13    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst14    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst15    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst16    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst17    ; 3     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.ammdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.ammdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.bpm b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.bpm
new file mode 100644
index 0000000..78b1dff
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.bpm
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.cdb
new file mode 100644
index 0000000..2ba2ae6
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.hdb
new file mode 100644
index 0000000..0620083
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.kpt b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.kpt
new file mode 100644
index 0000000..559b449
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.kpt
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.logdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.qmsg b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.qmsg
new file mode 100644
index 0000000..27b247f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455836195301 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455836195301 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:56:35 2016 " "Processing started: Thu Feb 18 22:56:35 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455836195301 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455836195301 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455836195301 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455836195578 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/asus/documents/github/adder/full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" {  } { { "../adder/full_adder.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455836195618 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455836195618 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_bit_adder_no_bus.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_bit_adder_no_bus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_bit_adder_NO_BUS " "Found entity 1: ten_bit_adder_NO_BUS" {  } { { "ten_bit_adder_NO_BUS.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455836195620 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455836195620 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_bit_adder_NO_BUS " "Elaborating entity \"ten_bit_adder_NO_BUS\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455836195643 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "full_adder full_adder:inst17 " "Elaborating entity \"full_adder\" for hierarchy \"full_adder:inst17\"" {  } { { "ten_bit_adder_NO_BUS.bdf" "inst17" { Schematic "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf" { { 1424 888 984 1520 "inst17" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1455836195654 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455836196192 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455836196438 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455836196438 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "53 " "Implemented 53 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "21 " "Implemented 21 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455836196485 ""} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Implemented 11 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455836196485 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455836196485 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455836196485 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "561 " "Peak virtual memory: 561 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836196505 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:36 2016 " "Processing ended: Thu Feb 18 22:56:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836196505 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836196505 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836196505 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455836196505 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.rdb
new file mode 100644
index 0000000..51ff137
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.cdb
new file mode 100644
index 0000000..70b00b4
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.hdb
new file mode 100644
index 0000000..8667d8c
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.logdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pre_map.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pre_map.hdb
new file mode 100644
index 0000000..924e3f1
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pre_map.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pti_db_list.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.pti_db_list.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.root_partition.map.reg_db.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..b40dcd7
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.root_partition.map.reg_db.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.routing.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.routing.rdb
new file mode 100644
index 0000000..2565ace
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.routing.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv.hdb
new file mode 100644
index 0000000..c8e8c58
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg.cdb
new file mode 100644
index 0000000..f8efddf
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg_swap.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..1718dc7
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.rtlv_sg_swap.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.cdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.cdb
new file mode 100644
index 0000000..7237b9f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.cdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.hdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.hdb
new file mode 100644
index 0000000..9347938
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sgdiff.hdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry.sci b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry.sci
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry_dsc.sci b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sld_design_entry_dsc.sci
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.smart_action.txt b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.qmsg b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.qmsg
new file mode 100644
index 0000000..2969fca
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.qmsg
@@ -0,0 +1,48 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455836208450 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455836208451 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 18 22:56:48 2016 " "Processing started: Thu Feb 18 22:56:48 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455836208451 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455836208451 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS " "Command: quartus_sta ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455836208451 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455836208520 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455836208645 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455836208708 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455836208708 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_bit_adder_NO_BUS.sdc " "Synopsys Design Constraints File file not found: 'ten_bit_adder_NO_BUS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455836208999 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455836208999 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455836209001 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455836209001 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455836209002 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455836209002 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455836209003 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455836209007 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455836209010 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209011 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209018 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209022 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209025 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209028 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209030 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455836209043 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455836209069 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455836209698 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455836209734 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455836209734 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455836209734 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455836209734 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209734 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209741 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209745 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209749 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209752 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209756 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455836209772 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455836209963 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455836209963 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455836209964 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455836209964 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209968 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209972 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209976 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209982 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455836209987 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455836210492 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455836210493 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "528 " "Peak virtual memory: 528 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455836210560 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 18 22:56:50 2016 " "Processing ended: Thu Feb 18 22:56:50 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455836210560 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455836210560 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455836210560 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455836210560 ""}
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.rdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.rdb
new file mode 100644
index 0000000..564d339
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta.rdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta_cmp.6_slow_1200mv_85c.tdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..b415911
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..53dad4c
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
new file mode 100644
index 0000000..a546d32
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..e9b1d75
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tis_db_list.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tis_db_list.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.fast_1200mv_0c.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..a33ec1f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.fast_1200mv_0c.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_0c.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..358bef8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_0c.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_85c.ddb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..96b85b5
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.tiscmp.slow_1200mv_85c.ddb
diff --git a/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.vpr.ammdb b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.vpr.ammdb
new file mode 100644
index 0000000..018b6a1
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.vpr.ammdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/README b/ten_bit_adder_NO_BUS/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.db_info b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.db_info
new file mode 100644
index 0000000..3fe4223
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Thu Feb 18 22:56:35 2016
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.ammdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.ammdb
new file mode 100644
index 0000000..e941746
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.ammdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.cdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.cdb
new file mode 100644
index 0000000..5409dae
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.cdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.dfp b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.dfp
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.hdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.hdb
new file mode 100644
index 0000000..9128f8e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.hdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.logdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.rcfdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..c5e2c0d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.cmp.rcfdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.cdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.cdb
new file mode 100644
index 0000000..19e594b
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.cdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.dpi b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.dpi
new file mode 100644
index 0000000..100fe07
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.dpi
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.cdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..b00f911
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.cdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hb_info b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hb_info
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..27a5ee1
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.hdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.sig b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..91e140d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+6d99a1516c2e2beefe1f386eab1dd580
\ No newline at end of file
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hdb b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hdb
new file mode 100644
index 0000000..ff17e67
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.hdb
diff --git a/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.kpt b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.kpt
new file mode 100644
index 0000000..f2cf438
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/incremental_db/compiled_partitions/ten_bit_adder_NO_BUS.root_partition.map.kpt
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.asm.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.asm.rpt
new file mode 100644
index 0000000..bd78428
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:46 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Thu Feb 18 22:56:46 2016 ;
+; Revision Name         ; ten_bit_adder_NO_BUS                  ;
+; Top-level Entity Name ; ten_bit_adder_NO_BUS                  ;
+; Family                ; Cyclone IV GX                         ;
+; Device                ; EP4CGX15BF14C6                        ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                 ;
++-------------------------------------------------------------------------------------------+
+; File Name                                                                                 ;
++-------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof ;
++-------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof ;
++----------------+----------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                            ;
++----------------+----------------------------------------------------------------------------------------------------+
+; Device         ; EP4CGX15BF14C6                                                                                     ;
+; JTAG usercode  ; 0x000BFCC1                                                                                         ;
+; Checksum       ; 0x000BFCC1                                                                                         ;
++----------------+----------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:56:45 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 522 megabytes
+    Info: Processing ended: Thu Feb 18 22:56:46 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.done b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.done
new file mode 100644
index 0000000..39819d1
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.done
@@ -0,0 +1 @@
+Thu Feb 18 22:56:53 2016
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.eda.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.eda.rpt
new file mode 100644
index 0000000..6fb49ef
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:52 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Thu Feb 18 22:56:52 2016 ;
+; Revision Name             ; ten_bit_adder_NO_BUS                  ;
+; Top-level Entity Name     ; ten_bit_adder_NO_BUS                  ;
+; Family                    ; Cyclone IV GX                         ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                              ;
++-------------------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                                         ;
++-------------------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.vho                        ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_vhd.sdo                    ;
++-------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:56:52 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+Info (204019): Generated file ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_bit_adder_NO_BUS_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 483 megabytes
+    Info: Processing ended: Thu Feb 18 22:56:52 2016
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt
new file mode 100644
index 0000000..5baa30d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt
@@ -0,0 +1,1153 @@
+Fitter report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:43 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Non-Global High Fan-Out Signals
+ 21. Routing Usage Summary
+ 22. LAB Logic Elements
+ 23. LAB Signals Sourced
+ 24. LAB Signals Sourced Out
+ 25. LAB Distinct Inputs
+ 26. I/O Rules Summary
+ 27. I/O Rules Details
+ 28. I/O Rules Matrix
+ 29. Fitter Device Options
+ 30. Operating Settings and Conditions
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Thu Feb 18 22:56:43 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder_NO_BUS                       ;
+; Top-level Entity Name              ; ten_bit_adder_NO_BUS                       ;
+; Family                             ; Cyclone IV GX                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 21 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 21 / 14,400 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32 / 81 ( 40 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; auto                                  ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Generate GXB Reconfig MIF                                                  ; Off                                   ; Off                                   ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_40MHz                            ; FREQ_40MHz                            ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; Cout     ; Incomplete set of assignments ;
+; S0       ; Incomplete set of assignments ;
+; S1       ; Incomplete set of assignments ;
+; S2       ; Incomplete set of assignments ;
+; S3       ; Incomplete set of assignments ;
+; S4       ; Incomplete set of assignments ;
+; S5       ; Incomplete set of assignments ;
+; S6       ; Incomplete set of assignments ;
+; S7       ; Incomplete set of assignments ;
+; S8       ; Incomplete set of assignments ;
+; S9       ; Incomplete set of assignments ;
+; Y9       ; Incomplete set of assignments ;
+; ENY      ; Incomplete set of assignments ;
+; Y8       ; Incomplete set of assignments ;
+; Y7       ; Incomplete set of assignments ;
+; Y6       ; Incomplete set of assignments ;
+; Y5       ; Incomplete set of assignments ;
+; Y4       ; Incomplete set of assignments ;
+; Y3       ; Incomplete set of assignments ;
+; Y2       ; Incomplete set of assignments ;
+; Y0       ; Incomplete set of assignments ;
+; X0       ; Incomplete set of assignments ;
+; Y1       ; Incomplete set of assignments ;
+; X1       ; Incomplete set of assignments ;
+; X2       ; Incomplete set of assignments ;
+; X3       ; Incomplete set of assignments ;
+; X4       ; Incomplete set of assignments ;
+; X5       ; Incomplete set of assignments ;
+; X6       ; Incomplete set of assignments ;
+; X7       ; Incomplete set of assignments ;
+; X8       ; Incomplete set of assignments ;
+; X9       ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 )          ; 0.00 % ( 0 / 96 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 )          ; 0.00 % ( 0 / 96 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 86 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 21 / 14,400 ( < 1 % ) ;
+;     -- Combinational with no register       ; 21                    ;
+;     -- Register only                        ; 0                     ;
+;     -- Combinational with a register        ; 0                     ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 18                    ;
+;     -- 3 input functions                    ; 1                     ;
+;     -- <=2 input functions                  ; 2                     ;
+;     -- Register only                        ; 0                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 21                    ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 0 / 14,733 ( 0 % )    ;
+;     -- Dedicated logic registers            ; 0 / 14,400 ( 0 % )    ;
+;     -- I/O registers                        ; 0 / 333 ( 0 % )       ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 2 / 900 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 32 / 81 ( 40 % )      ;
+;     -- Clock pins                           ; 2 / 6 ( 33 % )        ;
+;     -- Dedicated input pins                 ; 0 / 12 ( 0 % )        ;
+;                                             ;                       ;
+; Global signals                              ; 0                     ;
+; M9Ks                                        ; 0 / 60 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 552,960 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 552,960 ( 0 % )   ;
+; PLLs                                        ; 0 / 3 ( 0 % )         ;
+; Global clocks                               ; 0 / 20 ( 0 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; GXB Receiver channel PCSs                   ; 0 / 2 ( 0 % )         ;
+; GXB Receiver channel PMAs                   ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PCSs                ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PMAs                ; 0 / 2 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 3 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 1%          ;
+; Maximum fan-out                             ; 19                    ;
+; Highest non-global fan-out                  ; 19                    ;
+; Total fan-out                               ; 127                   ;
+; Average fan-out                             ; 1.34                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 21 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % )              ;
+;     -- Combinational with no register       ; 21                   ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;     -- Combinational with a register        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 18                   ; 0                              ;
+;     -- 3 input functions                    ; 1                    ; 0                              ;
+;     -- <=2 input functions                  ; 2                    ; 0                              ;
+;     -- Register only                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 21                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 0                    ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 14400 ( 0 % )    ; 0 / 14400 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 2 / 900 ( < 1 % )    ; 0 / 900 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 32                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0                    ; 0                              ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 122                  ; 5                              ;
+;     -- Registered Connections               ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 21                   ; 0                              ;
+;     -- Output Ports                         ; 11                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; ENY  ; N7    ; 4        ; 16           ; 0            ; 0            ; 19                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X0   ; L13   ; 5        ; 33           ; 12           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X1   ; K13   ; 5        ; 33           ; 15           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X2   ; F13   ; 6        ; 33           ; 16           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X3   ; F12   ; 6        ; 33           ; 16           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X4   ; K12   ; 5        ; 33           ; 11           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X5   ; L9    ; 4        ; 24           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X6   ; K9    ; 4        ; 22           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X7   ; M6    ; 3        ; 12           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X8   ; N4    ; 3        ; 10           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; X9   ; L4    ; 3        ; 8            ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y0   ; A13   ; 7        ; 26           ; 31           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y1   ; K10   ; 4        ; 31           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y2   ; L12   ; 5        ; 33           ; 12           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y3   ; N10   ; 4        ; 26           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y4   ; N12   ; 4        ; 29           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y5   ; M13   ; 5        ; 33           ; 10           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y6   ; M9    ; 4        ; 24           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y7   ; N8    ; 4        ; 20           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y8   ; N6    ; 3        ; 12           ; 0            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; Y9   ; M7    ; 4        ; 16           ; 0            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Cout ; N9    ; 4        ; 20           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S0   ; J13   ; 5        ; 33           ; 15           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S1   ; H10   ; 5        ; 33           ; 14           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S2   ; N11   ; 4        ; 26           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S3   ; F11   ; 6        ; 33           ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S4   ; K11   ; 5        ; 33           ; 11           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S5   ; M11   ; 4        ; 29           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S6   ; N13   ; 5        ; 33           ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S7   ; L5    ; 3        ; 14           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S8   ; K8    ; 4        ; 22           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; S9   ; L7    ; 3        ; 14           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                            ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; Location ; Pin Name              ; Reserved As              ; User Signal Name ; Pin Type                  ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+; L3       ; MSEL2                 ; -                        ; -                ; Dedicated Programming Pin ;
+; N3       ; MSEL1                 ; -                        ; -                ; Dedicated Programming Pin ;
+; K5       ; MSEL0                 ; -                        ; -                ; Dedicated Programming Pin ;
+; J5       ; CONF_DONE             ; -                        ; -                ; Dedicated Programming Pin ;
+; K6       ; nSTATUS               ; -                        ; -                ; Dedicated Programming Pin ;
+; N4       ; DIFFIO_B1p, CRC_ERROR ; Use as regular IO        ; X8               ; Dual Purpose Pin          ;
+; N5       ; DIFFIO_B1n, NCEO      ; Use as programming pin   ; ~ALTERA_NCEO~    ; Dual Purpose Pin          ;
+; M6       ; DIFFIO_B2p, INIT_DONE ; Use as regular IO        ; X7               ; Dual Purpose Pin          ;
+; A5       ; DATA0                 ; As input tri-stated      ; ~ALTERA_DATA0~   ; Dual Purpose Pin          ;
+; B5       ; ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO~    ; Dual Purpose Pin          ;
+; C5       ; NCSO                  ; As input tri-stated      ; ~ALTERA_NCSO~    ; Dual Purpose Pin          ;
+; A4       ; DCLK                  ; As output driving ground ; ~ALTERA_DCLK~    ; Dual Purpose Pin          ;
+; D5       ; nCONFIG               ; -                        ; -                ; Dedicated Programming Pin ;
+; C4       ; nCE                   ; -                        ; -                ; Dedicated Programming Pin ;
++----------+-----------------------+--------------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------+
+; I/O Bank Usage                                                                ;
++----------+------------------+---------------+--------------+------------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ;
++----------+------------------+---------------+--------------+------------------+
+; QL0      ; 0 / 8 ( 0 % )    ; --            ; --           ; --               ;
+; 3        ; 7 / 8 ( 88 % )   ; 2.5V          ; --           ; --               ;
+; 3A       ; 0 / 2 ( 0 % )    ; --            ; --           ; 2.5V             ;
+; 4        ; 13 / 14 ( 93 % ) ; 2.5V          ; --           ; --               ;
+; 5        ; 9 / 12 ( 75 % )  ; 2.5V          ; --           ; --               ;
+; 6        ; 3 / 12 ( 25 % )  ; 2.5V          ; --           ; --               ;
+; 7        ; 1 / 14 ( 7 % )   ; 2.5V          ; --           ; --               ;
+; 8A       ; 0 / 2 ( 0 % )    ; --            ; --           ; 2.5V             ;
+; 8        ; 0 / 5 ( 0 % )    ; 2.5V          ; --           ; --               ;
+; 9        ; 4 / 4 ( 100 % )  ; 2.5V          ; --           ; --               ;
++----------+------------------+---------------+--------------+------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                               ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                   ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ; 99         ; 9        ; #TDO                                             ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ; 98         ; 9        ; #TMS                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A3       ; 96         ; 9        ; #TDI                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A4       ; 93         ; 9        ; ~ALTERA_DCLK~                                    ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A5       ; 90         ; 9        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A6       ; 89         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 87         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 88         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 81         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A10      ; 82         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A11      ; 79         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A12      ; 80         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A13      ; 73         ; 7        ; Y0                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 97         ; 9        ; #TCK                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; B4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B5       ; 91         ; 9        ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; B6       ; 86         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B8       ; 77         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B10      ; 76         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B11      ; 75         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B13      ; 74         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C1       ; 9          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C2       ; 8          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C3       ;            ; 9        ; VCCIO9                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C4       ; 95         ; 9        ; ^nCE                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C5       ; 92         ; 9        ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; C6       ; 85         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C7       ;            ; 8        ; VCCIO8                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C8       ; 78         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C10      ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C11      ; 69         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C12      ; 70         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C13      ; 71         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D3       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ; 94         ; 9        ; ^nCONFIG                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; D6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D7       ;            ; 8A       ; VCC_CLKIN8A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 65         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D11      ; 68         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D12      ; 67         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D13      ; 72         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E1       ; 11         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E2       ; 10         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 83         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E7       ; 84         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E10      ; 66         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E13      ; 63         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; F1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F9       ; 64         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F10      ; 62         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F11      ; 61         ; 6        ; S3                                               ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F12      ; 58         ; 6        ; X3                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F13      ; 57         ; 6        ; X2                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G1       ; 13         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G2       ; 12         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G3       ;            ; --       ; VCCH_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G6       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ; 60         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G10      ; 59         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G13      ; 55         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H10      ; 52         ; 5        ; S1                                               ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; H11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H12      ; 51         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H13      ; 56         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J1       ; 15         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J2       ; 14         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J3       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J4       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J5       ; 19         ; 3        ; ^CONF_DONE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 29         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J7       ; 30         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J13      ; 53         ; 5        ; S0                                               ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 18         ; 3        ; ^MSEL0                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 20         ; 3        ; ^nSTATUS                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ;            ; 3A       ; VCC_CLKIN3A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K8       ; 35         ; 4        ; S8                                               ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K9       ; 36         ; 4        ; X6                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K10      ; 43         ; 4        ; Y1                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; K11      ; 48         ; 5        ; S4                                               ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K12      ; 47         ; 5        ; X4                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K13      ; 54         ; 5        ; X1                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ;            ;          ; RREF                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 16         ; 3        ; ^MSEL2                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 21         ; 3        ; X9                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L5       ; 27         ; 3        ; S7                                               ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L6       ;            ; 3        ; VCCIO3                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L7       ; 28         ; 3        ; S9                                               ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L8       ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L9       ; 37         ; 4        ; X5                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; L10      ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L11      ; 44         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L12      ; 50         ; 5        ; Y2                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L13      ; 49         ; 5        ; X0                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M2       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; M3       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M4       ; 22         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 25         ; 3        ; X7                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M7       ; 31         ; 4        ; Y9                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M9       ; 38         ; 4        ; Y6                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M10      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ; 41         ; 4        ; S5                                               ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ; 46         ; 5        ; Y5                                               ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N1       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N2       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N3       ; 17         ; 3        ; ^MSEL1                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ; 23         ; 3        ; X8                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N5       ; 24         ; 3        ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN       ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N6       ; 26         ; 3        ; Y8                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N7       ; 32         ; 4        ; ENY                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N8       ; 33         ; 4        ; Y7                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N9       ; 34         ; 4        ; Cout                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N10      ; 39         ; 4        ; Y3                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N11      ; 40         ; 4        ; S2                                               ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N12      ; 42         ; 4        ; Y4                                               ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N13      ; 45         ; 5        ; S6                                               ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                     ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+
+; |ten_bit_adder_NO_BUS      ; 21 (2)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; 21 (2)       ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS                   ; work         ;
+;    |full_adder:inst10|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst10 ; work         ;
+;    |full_adder:inst11|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst11 ; work         ;
+;    |full_adder:inst12|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst12 ; work         ;
+;    |full_adder:inst13|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst13 ; work         ;
+;    |full_adder:inst14|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst14 ; work         ;
+;    |full_adder:inst15|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst15 ; work         ;
+;    |full_adder:inst16|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst16 ; work         ;
+;    |full_adder:inst17|     ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst17 ; work         ;
+;    |full_adder:inst8|      ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst8  ; work         ;
+;    |full_adder:inst9|      ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |ten_bit_adder_NO_BUS|full_adder:inst9  ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                  ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Cout ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S0   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S1   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S2   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S3   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S4   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S5   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S6   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S7   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S8   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; S9   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Y9   ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; ENY  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; Y8   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y7   ; Input    ; --            ; (6) 1313 ps   ; --                    ; --  ; --   ;
+; Y6   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y5   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Y4   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y3   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; Y2   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; Y0   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X0   ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; Y1   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X1   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X2   ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; X3   ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; X4   ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; X5   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X6   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X7   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X8   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; X9   ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                 ;
++----------------------------------+-------------------+---------+
+; Source Pin / Fanout              ; Pad To Core Index ; Setting ;
++----------------------------------+-------------------+---------+
+; Y9                               ;                   ;         ;
+; ENY                              ;                   ;         ;
+; Y8                               ;                   ;         ;
+;      - full_adder:inst16|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst16|inst2~0 ; 0                 ; 6       ;
+; Y7                               ;                   ;         ;
+;      - full_adder:inst15|inst3~0 ; 1                 ; 6       ;
+;      - full_adder:inst15|inst2~0 ; 1                 ; 6       ;
+; Y6                               ;                   ;         ;
+;      - full_adder:inst14|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst14|inst2~0 ; 0                 ; 6       ;
+; Y5                               ;                   ;         ;
+;      - full_adder:inst13|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst13|inst2~0 ; 0                 ; 6       ;
+; Y4                               ;                   ;         ;
+;      - full_adder:inst12|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst12|inst2~0 ; 0                 ; 6       ;
+; Y3                               ;                   ;         ;
+;      - full_adder:inst11|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst11|inst2~0 ; 0                 ; 6       ;
+; Y2                               ;                   ;         ;
+;      - full_adder:inst10|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst10|inst2~0 ; 0                 ; 6       ;
+; Y0                               ;                   ;         ;
+;      - inst6                     ; 0                 ; 6       ;
+;      - full_adder:inst8|inst     ; 0                 ; 6       ;
+; X0                               ;                   ;         ;
+;      - full_adder:inst9|inst3~0  ; 1                 ; 6       ;
+;      - full_adder:inst8|inst     ; 1                 ; 6       ;
+;      - full_adder:inst9|inst2    ; 1                 ; 6       ;
+; Y1                               ;                   ;         ;
+;      - inst7                     ; 0                 ; 6       ;
+; X1                               ;                   ;         ;
+;      - full_adder:inst9|inst3~0  ; 0                 ; 6       ;
+;      - full_adder:inst9|inst2    ; 0                 ; 6       ;
+; X2                               ;                   ;         ;
+; X3                               ;                   ;         ;
+; X4                               ;                   ;         ;
+;      - full_adder:inst12|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst12|inst2~0 ; 0                 ; 6       ;
+; X5                               ;                   ;         ;
+;      - full_adder:inst13|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst13|inst2~0 ; 0                 ; 6       ;
+; X6                               ;                   ;         ;
+;      - full_adder:inst14|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst14|inst2~0 ; 0                 ; 6       ;
+; X7                               ;                   ;         ;
+;      - full_adder:inst15|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst15|inst2~0 ; 0                 ; 6       ;
+; X8                               ;                   ;         ;
+;      - full_adder:inst16|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst16|inst2~0 ; 0                 ; 6       ;
+; X9                               ;                   ;         ;
+;      - full_adder:inst17|inst3~0 ; 0                 ; 6       ;
+;      - full_adder:inst17|inst2~0 ; 0                 ; 6       ;
++----------------------------------+-------------------+---------+
+
+
++-------------------------------------+
+; Non-Global High Fan-Out Signals     ;
++---------------------------+---------+
+; Name                      ; Fan-Out ;
++---------------------------+---------+
+; ENY~input                 ; 19      ;
+; X0~input                  ; 3       ;
+; X9~input                  ; 2       ;
+; X8~input                  ; 2       ;
+; X7~input                  ; 2       ;
+; X6~input                  ; 2       ;
+; X5~input                  ; 2       ;
+; X4~input                  ; 2       ;
+; X3~input                  ; 2       ;
+; X2~input                  ; 2       ;
+; X1~input                  ; 2       ;
+; Y0~input                  ; 2       ;
+; Y2~input                  ; 2       ;
+; Y3~input                  ; 2       ;
+; Y4~input                  ; 2       ;
+; Y5~input                  ; 2       ;
+; Y6~input                  ; 2       ;
+; Y7~input                  ; 2       ;
+; Y8~input                  ; 2       ;
+; Y9~input                  ; 2       ;
+; full_adder:inst16|inst3~0 ; 2       ;
+; full_adder:inst15|inst3~0 ; 2       ;
+; full_adder:inst14|inst3~0 ; 2       ;
+; full_adder:inst13|inst3~0 ; 2       ;
+; full_adder:inst12|inst3~0 ; 2       ;
+; full_adder:inst11|inst3~0 ; 2       ;
+; full_adder:inst10|inst3~0 ; 2       ;
+; full_adder:inst9|inst3~0  ; 2       ;
+; inst7                     ; 2       ;
+; inst6                     ; 2       ;
+; Y1~input                  ; 1       ;
+; full_adder:inst17|inst2~0 ; 1       ;
+; full_adder:inst16|inst2~0 ; 1       ;
+; full_adder:inst15|inst2~0 ; 1       ;
+; full_adder:inst14|inst2~0 ; 1       ;
+; full_adder:inst13|inst2~0 ; 1       ;
+; full_adder:inst12|inst2~0 ; 1       ;
+; full_adder:inst11|inst2~0 ; 1       ;
+; full_adder:inst10|inst2~0 ; 1       ;
+; full_adder:inst9|inst2    ; 1       ;
+; full_adder:inst8|inst     ; 1       ;
+; full_adder:inst17|inst3~0 ; 1       ;
++---------------------------+---------+
+
+
++-----------------------------------------------------------+
+; Routing Usage Summary                                     ;
++-----------------------------------+-----------------------+
+; Routing Resource Type             ; Usage                 ;
++-----------------------------------+-----------------------+
+; Block interconnects               ; 34 / 42,960 ( < 1 % ) ;
+; C16 interconnects                 ; 11 / 1,518 ( < 1 % )  ;
+; C4 interconnects                  ; 44 / 26,928 ( < 1 % ) ;
+; Direct links                      ; 0 / 42,960 ( 0 % )    ;
+; GXB block output buffers          ; 0 / 1,200 ( 0 % )     ;
+; Global clocks                     ; 0 / 20 ( 0 % )        ;
+; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % )         ;
+; Interquad TXRX Clocks             ; 0 / 8 ( 0 % )         ;
+; Interquad TXRX PCSRX outputs      ; 0 / 4 ( 0 % )         ;
+; Interquad TXRX PCSTX outputs      ; 0 / 4 ( 0 % )         ;
+; Local interconnects               ; 9 / 14,400 ( < 1 % )  ;
+; R24 interconnects                 ; 8 / 1,710 ( < 1 % )   ;
+; R4 interconnects                  ; 31 / 37,740 ( < 1 % ) ;
++-----------------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 10.50) ; Number of LABs  (Total = 2) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 1                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 0                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 0                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 0                           ;
+; 15                                          ; 1                           ;
+; 16                                          ; 0                           ;
++---------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 10.50) ; Number of LABs  (Total = 2) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 1                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 6.00) ; Number of LABs  (Total = 2) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 1                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 0                           ;
+; 8                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 11.50) ; Number of LABs  (Total = 2) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 32        ; 0            ; 0            ; 32        ; 32        ; 0            ; 11           ; 0            ; 0            ; 21           ; 0            ; 11           ; 21           ; 0            ; 0            ; 0            ; 11           ; 0            ; 0            ; 0            ; 0            ; 0            ; 32        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 32           ; 32           ; 32           ; 32           ; 32           ; 0         ; 32           ; 32           ; 0         ; 0         ; 32           ; 21           ; 32           ; 32           ; 11           ; 32           ; 21           ; 11           ; 32           ; 32           ; 32           ; 21           ; 32           ; 32           ; 32           ; 32           ; 32           ; 0         ; 32           ; 32           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Cout               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S0                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S1                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S2                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S3                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S4                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S5                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S6                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S7                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S8                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; S9                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y9                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ENY                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y8                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y7                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y6                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y5                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y4                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y3                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y2                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y0                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X0                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Y1                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X1                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X2                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X3                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X4                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X5                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X6                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X7                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X8                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; X9                 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                         ;
++------------------------------------------------------------------+----------------------------+
+; Option                                                           ; Setting                    ;
++------------------------------------------------------------------+----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                        ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                        ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                        ;
+; Enable INIT_DONE output                                          ; Off                        ;
+; Configuration scheme                                             ; Active Serial              ;
+; Error detection CRC                                              ; Off                        ;
+; Enable input tri-state on active configuration pins in user mode ; Off                        ;
+; Active Serial clock source                                       ; 40 MHz Internal Oscillator ;
+; Configuration Voltage Level                                      ; Auto                       ;
+; Force Configuration Voltage Level                                ; Off                        ;
+; nCEO                                                             ; As output driving ground   ;
+; Data[0]                                                          ; As input tri-stated        ;
+; Data[1]/ASDO                                                     ; As input tri-stated        ;
+; Data[7..2]                                                       ; Unreserved                 ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated        ;
+; DCLK                                                             ; As output driving ground   ;
+; Base pin-out file on sameframe device                            ; Off                        ;
++------------------------------------------------------------------+----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119004): Automatically selected device EP4CGX15BF14C6 for design ten_bit_adder_NO_BUS
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CGX30BF14C6 is compatible
+    Info (176445): Device EP4CGX22BF14C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5
+    Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5
+    Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 32 pins of 32 total pins
+    Info (169086): Pin Cout not assigned to an exact location on the device
+    Info (169086): Pin S0 not assigned to an exact location on the device
+    Info (169086): Pin S1 not assigned to an exact location on the device
+    Info (169086): Pin S2 not assigned to an exact location on the device
+    Info (169086): Pin S3 not assigned to an exact location on the device
+    Info (169086): Pin S4 not assigned to an exact location on the device
+    Info (169086): Pin S5 not assigned to an exact location on the device
+    Info (169086): Pin S6 not assigned to an exact location on the device
+    Info (169086): Pin S7 not assigned to an exact location on the device
+    Info (169086): Pin S8 not assigned to an exact location on the device
+    Info (169086): Pin S9 not assigned to an exact location on the device
+    Info (169086): Pin Y9 not assigned to an exact location on the device
+    Info (169086): Pin ENY not assigned to an exact location on the device
+    Info (169086): Pin Y8 not assigned to an exact location on the device
+    Info (169086): Pin Y7 not assigned to an exact location on the device
+    Info (169086): Pin Y6 not assigned to an exact location on the device
+    Info (169086): Pin Y5 not assigned to an exact location on the device
+    Info (169086): Pin Y4 not assigned to an exact location on the device
+    Info (169086): Pin Y3 not assigned to an exact location on the device
+    Info (169086): Pin Y2 not assigned to an exact location on the device
+    Info (169086): Pin Y0 not assigned to an exact location on the device
+    Info (169086): Pin X0 not assigned to an exact location on the device
+    Info (169086): Pin Y1 not assigned to an exact location on the device
+    Info (169086): Pin X1 not assigned to an exact location on the device
+    Info (169086): Pin X2 not assigned to an exact location on the device
+    Info (169086): Pin X3 not assigned to an exact location on the device
+    Info (169086): Pin X4 not assigned to an exact location on the device
+    Info (169086): Pin X5 not assigned to an exact location on the device
+    Info (169086): Pin X6 not assigned to an exact location on the device
+    Info (169086): Pin X7 not assigned to an exact location on the device
+    Info (169086): Pin X8 not assigned to an exact location on the device
+    Info (169086): Pin X9 not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_bit_adder_NO_BUS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 32 (unused VREF, 2.5V VCCIO, 21 input, 11 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available
+        Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available
+        Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 911 megabytes
+    Info: Processing ended: Thu Feb 18 22:56:44 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg.
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg
new file mode 100644
index 0000000..ed080d6
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.summary b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.summary
new file mode 100644
index 0000000..7dd3558
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Thu Feb 18 22:56:43 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_bit_adder_NO_BUS
+Top-level Entity Name : ten_bit_adder_NO_BUS
+Family : Cyclone IV GX
+Device : EP4CGX15BF14C6
+Timing Models : Final
+Total logic elements : 21 / 14,400 ( < 1 % )
+    Total combinational functions : 21 / 14,400 ( < 1 % )
+    Dedicated logic registers : 0 / 14,400 ( 0 % )
+Total registers : 0
+Total pins : 32 / 81 ( 40 % )
+Total virtual pins : 0
+Total memory bits : 0 / 552,960 ( 0 % )
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0 / 2 ( 0 % )
+Total GXB Receiver Channel PMA : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PCS : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PMA : 0 / 2 ( 0 % )
+Total PLLs : 0 / 3 ( 0 % )
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.flow.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.flow.rpt
new file mode 100644
index 0000000..8bcd52e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:52 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Thu Feb 18 22:56:52 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder_NO_BUS                       ;
+; Top-level Entity Name              ; ten_bit_adder_NO_BUS                       ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 21 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 21 / 14,400 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 0 / 14,400 ( 0 % )                         ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32 / 81 ( 40 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------+
+; Flow Settings                            ;
++-------------------+----------------------+
+; Option            ; Setting              ;
++-------------------+----------------------+
+; Start date & time ; 02/18/2016 22:56:35  ;
+; Main task         ; Compilation          ;
+; Revision Name     ; ten_bit_adder_NO_BUS ;
++-------------------+----------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145583619508540 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 550 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:06     ; 1.0                     ; 911 MB              ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 514 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 528 MB              ; 00:00:02                           ;
+; EDA Netlist Writer        ; 00:00:00     ; 1.0                     ; 471 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:10     ; --                      ; --                  ; 00:00:11                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+quartus_fit --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+quartus_asm --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+quartus_sta ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.jdi b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.jdi
new file mode 100644
index 0000000..6f83b3d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="3a5948ae1abf24368f68"/>
+  </project>
+  <file_info>
+    <file device="EP4CGX15BF14C6" path="ten_bit_adder_NO_BUS.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.rpt
new file mode 100644
index 0000000..39504ff
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.rpt
@@ -0,0 +1,258 @@
+Analysis & Synthesis report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:36 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Thu Feb 18 22:56:36 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_bit_adder_NO_BUS                       ;
+; Top-level Entity Name              ; ten_bit_adder_NO_BUS                       ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 21                                         ;
+;     Total combinational functions  ; 21                                         ;
+;     Dedicated logic registers      ; 0                                          ;
+; Total registers                    ; 0                                          ;
+; Total pins                         ; 32                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0                                          ;
+; Total GXB Receiver Channel PMA     ; 0                                          ;
+; Total GXB Transmitter Channel PCS  ; 0                                          ;
+; Total GXB Transmitter Channel PMA  ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                            ;
++----------------------------------------------------------------------------+----------------------+----------------------+
+; Option                                                                     ; Setting              ; Default Value        ;
++----------------------------------------------------------------------------+----------------------+----------------------+
+; Top-level entity name                                                      ; ten_bit_adder_NO_BUS ; ten_bit_adder_NO_BUS ;
+; Family name                                                                ; Cyclone IV GX        ; Cyclone IV GX        ;
+; Use smart compilation                                                      ; Off                  ; Off                  ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                   ; On                   ;
+; Enable compact report table                                                ; Off                  ; Off                  ;
+; Restructure Multiplexers                                                   ; Auto                 ; Auto                 ;
+; Create Debugging Nodes for IP Cores                                        ; Off                  ; Off                  ;
+; Preserve fewer node names                                                  ; On                   ; On                   ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                  ; Off                  ;
+; Verilog Version                                                            ; Verilog_2001         ; Verilog_2001         ;
+; VHDL Version                                                               ; VHDL_1993            ; VHDL_1993            ;
+; State Machine Processing                                                   ; Auto                 ; Auto                 ;
+; Safe State Machine                                                         ; Off                  ; Off                  ;
+; Extract Verilog State Machines                                             ; On                   ; On                   ;
+; Extract VHDL State Machines                                                ; On                   ; On                   ;
+; Ignore Verilog initial constructs                                          ; Off                  ; Off                  ;
+; Iteration limit for constant Verilog loops                                 ; 5000                 ; 5000                 ;
+; Iteration limit for non-constant Verilog loops                             ; 250                  ; 250                  ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                   ; On                   ;
+; Infer RAMs from Raw Logic                                                  ; On                   ; On                   ;
+; Parallel Synthesis                                                         ; On                   ; On                   ;
+; DSP Block Balancing                                                        ; Auto                 ; Auto                 ;
+; NOT Gate Push-Back                                                         ; On                   ; On                   ;
+; Power-Up Don't Care                                                        ; On                   ; On                   ;
+; Remove Redundant Logic Cells                                               ; Off                  ; Off                  ;
+; Remove Duplicate Registers                                                 ; On                   ; On                   ;
+; Ignore CARRY Buffers                                                       ; Off                  ; Off                  ;
+; Ignore CASCADE Buffers                                                     ; Off                  ; Off                  ;
+; Ignore GLOBAL Buffers                                                      ; Off                  ; Off                  ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                  ; Off                  ;
+; Ignore LCELL Buffers                                                       ; Off                  ; Off                  ;
+; Ignore SOFT Buffers                                                        ; On                   ; On                   ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                  ; Off                  ;
+; Optimization Technique                                                     ; Balanced             ; Balanced             ;
+; Carry Chain Length                                                         ; 70                   ; 70                   ;
+; Auto Carry Chains                                                          ; On                   ; On                   ;
+; Auto Open-Drain Pins                                                       ; On                   ; On                   ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                  ; Off                  ;
+; Auto ROM Replacement                                                       ; On                   ; On                   ;
+; Auto RAM Replacement                                                       ; On                   ; On                   ;
+; Auto DSP Block Replacement                                                 ; On                   ; On                   ;
+; Auto Shift Register Replacement                                            ; Auto                 ; Auto                 ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto                 ; Auto                 ;
+; Auto Clock Enable Replacement                                              ; On                   ; On                   ;
+; Strict RAM Replacement                                                     ; Off                  ; Off                  ;
+; Allow Synchronous Control Signals                                          ; On                   ; On                   ;
+; Force Use of Synchronous Clear Signals                                     ; Off                  ; Off                  ;
+; Auto RAM Block Balancing                                                   ; On                   ; On                   ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                  ; Off                  ;
+; Auto Resource Sharing                                                      ; Off                  ; Off                  ;
+; Allow Any RAM Size For Recognition                                         ; Off                  ; Off                  ;
+; Allow Any ROM Size For Recognition                                         ; Off                  ; Off                  ;
+; Allow Any Shift Register Size For Recognition                              ; Off                  ; Off                  ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                   ; On                   ;
+; Ignore translate_off and synthesis_off directives                          ; Off                  ; Off                  ;
+; Timing-Driven Synthesis                                                    ; On                   ; On                   ;
+; Report Parameter Settings                                                  ; On                   ; On                   ;
+; Report Source Assignments                                                  ; On                   ; On                   ;
+; Report Connectivity Checks                                                 ; On                   ; On                   ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                  ; Off                  ;
+; Synchronization Register Chain Length                                      ; 2                    ; 2                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation   ; Normal compilation   ;
+; HDL message level                                                          ; Level2               ; Level2               ;
+; Suppress Register Optimization Related Messages                            ; Off                  ; Off                  ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000                 ; 5000                 ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                 ; 5000                 ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                  ; 100                  ;
+; Clock MUX Protection                                                       ; On                   ; On                   ;
+; Auto Gated Clock Conversion                                                ; Off                  ; Off                  ;
+; Block Design Naming                                                        ; Auto                 ; Auto                 ;
+; SDC constraint protection                                                  ; Off                  ; Off                  ;
+; Synthesis Effort                                                           ; Auto                 ; Auto                 ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                   ; On                   ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                  ; Off                  ;
+; Analysis & Synthesis Message Level                                         ; Medium               ; Medium               ;
+; Disable Register Merging Across Hierarchies                                ; Auto                 ; Auto                 ;
+; Resource Aware Inference For Block RAM                                     ; On                   ; On                   ;
+; Synthesis Seed                                                             ; 1                    ; 1                    ;
++----------------------------------------------------------------------------+----------------------+----------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                           ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                 ; Library ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+; ../adder/full_adder.bdf          ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf                          ;         ;
+; ten_bit_adder_NO_BUS.bdf         ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++--------------------------+------------------+
+; Resource                 ; Usage            ;
++--------------------------+------------------+
+; I/O pins                 ; 32               ;
+; DSP block 9-bit elements ; 0                ;
+; Maximum fan-out node     ; ENY~input        ;
+; Maximum fan-out          ; 19               ;
+; Total fan-out            ; 122              ;
+; Average fan-out          ; 1.44             ;
++--------------------------+------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                     ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------+--------------+
+; |ten_bit_adder_NO_BUS      ; 21 (2)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 32   ; 0            ; |ten_bit_adder_NO_BUS                   ; work         ;
+;    |full_adder:inst10|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst10 ; work         ;
+;    |full_adder:inst11|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst11 ; work         ;
+;    |full_adder:inst12|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst12 ; work         ;
+;    |full_adder:inst13|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst13 ; work         ;
+;    |full_adder:inst14|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst14 ; work         ;
+;    |full_adder:inst15|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst15 ; work         ;
+;    |full_adder:inst16|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst16 ; work         ;
+;    |full_adder:inst17|     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst17 ; work         ;
+;    |full_adder:inst8|      ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst8  ; work         ;
+;    |full_adder:inst9|      ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |ten_bit_adder_NO_BUS|full_adder:inst9  ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-----------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:56:35 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file /users/asus/documents/github/adder/full_adder.bdf
+    Info (12023): Found entity 1: full_adder
+Info (12021): Found 1 design units, including 1 entities, in source file ten_bit_adder_no_bus.bdf
+    Info (12023): Found entity 1: ten_bit_adder_NO_BUS
+Info (12127): Elaborating entity "ten_bit_adder_NO_BUS" for the top level hierarchy
+Info (12128): Elaborating entity "full_adder" for hierarchy "full_adder:inst17"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 53 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 21 input pins
+    Info (21059): Implemented 11 output pins
+    Info (21061): Implemented 21 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 561 megabytes
+    Info: Processing ended: Thu Feb 18 22:56:36 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.summary b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.summary
new file mode 100644
index 0000000..e9fc8de
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.map.summary
@@ -0,0 +1,18 @@
+Analysis & Synthesis Status : Successful - Thu Feb 18 22:56:36 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_bit_adder_NO_BUS
+Top-level Entity Name : ten_bit_adder_NO_BUS
+Family : Cyclone IV GX
+Total logic elements : 21
+    Total combinational functions : 21
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 32
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0
+Total GXB Receiver Channel PMA : 0
+Total GXB Transmitter Channel PCS : 0
+Total GXB Transmitter Channel PMA : 0
+Total PLLs : 0
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.pin b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.pin
new file mode 100644
index 0000000..1052414
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.pin
@@ -0,0 +1,246 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ --					Bank 9:	2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --           	    either individually through a 10k Ohm resistor to GND or tie all pins
+ --           	    together and connect through a single 10k Ohm resistor to GND.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_GND*      : Unused GXB Receiver or dedicated reference clock pin. This pin
+ --                 must be connected to GXB_GND through a 10k Ohm resistor.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "ten_bit_adder_NO_BUS"  ASSIGNED TO AN: EP4CGX15BF14C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+TDO                          : A1        : output :                   :         : 9         :                
+TMS                          : A2        : input  :                   :         : 9         :                
+TDI                          : A3        : input  :                   :         : 9         :                
+~ALTERA_DCLK~                : A4        : output : 2.5 V             :         : 9         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : A5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+GND+                         : A10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+Y0                           : A13       : input  : 2.5 V             :         : 7         : N              
+GND                          : B1        : gnd    :                   :         :           :                
+GND                          : B2        : gnd    :                   :         :           :                
+TCK                          : B3        : input  :                   :         : 9         :                
+GND                          : B4        : gnd    :                   :         :           :                
+~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : B5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+GND                          : B7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 7         :                
+GND                          : B9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7         :                
+GND                          : B12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+GXB_NC                       : C1        :        :                   :         : QL0       :                
+GXB_NC                       : C2        :        :                   :         : QL0       :                
+VCCIO9                       : C3        : power  :                   : 2.5V    : 9         :                
+nCE                          : C4        :        :                   :         : 9         :                
+~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 7         :                
+VCCIO7                       : C9        : power  :                   : 2.5V    : 7         :                
+VCCIO7                       : C10       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : D1        : gnd    :                   :         :           :                
+GND                          : D2        : gnd    :                   :         :           :                
+VCCD_PLL                     : D3        : power  :                   : 1.2V    :           :                
+VCCA                         : D4        : power  :                   : 2.5V    :           :                
+nCONFIG                      : D5        :        :                   :         : 9         :                
+GND                          : D6        : gnd    :                   :         :           :                
+VCC_CLKIN8A                  : D7        : power  :                   : 2.5V    : 8A        :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCA                         : D9        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+GXB_GND*                     : E1        :        :                   :         : QL0       :                
+GXB_GND*                     : E2        :        :                   :         : QL0       :                
+GND                          : E3        : gnd    :                   :         :           :                
+VCCINT                       : E4        : power  :                   : 1.2V    :           :                
+GND                          : E5        : gnd    :                   :         :           :                
+GXB_GND*                     : E6        :        :                   :         : 8A        :                
+GXB_GND*                     : E7        :        :                   :         : 8A        :                
+VCCINT                       : E8        : power  :                   : 1.2V    :           :                
+GND                          : E9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 6         :                
+VCCIO6                       : E11       : power  :                   : 2.5V    : 6         :                
+GND                          : E12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 6         :                
+GND                          : F1        : gnd    :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+VCCL_GXB                     : F3        : power  :                   : 1.2V    :           :                
+GND                          : F4        : gnd    :                   :         :           :                
+VCCINT                       : F5        : power  :                   : 1.2V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+GND                          : F8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 6         :                
+S3                           : F11       : output : 2.5 V             :         : 6         : N              
+X3                           : F12       : input  : 2.5 V             :         : 6         : N              
+X2                           : F13       : input  : 2.5 V             :         : 6         : N              
+GXB_NC                       : G1        :        :                   :         : QL0       :                
+GXB_NC                       : G2        :        :                   :         : QL0       :                
+VCCH_GXB                     : G3        : power  :                   : 2.5V    :           :                
+VCCINT                       : G4        : power  :                   : 1.2V    :           :                
+GND                          : G5        : gnd    :                   :         :           :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+GND                          : G7        : gnd    :                   :         :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 6         :                
+VCCIO6                       : G11       : power  :                   : 2.5V    : 6         :                
+GND                          : G12       : gnd    :                   :         :           :                
+GND+                         : G13       :        :                   :         : 5         :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+VCCL_GXB                     : H3        : power  :                   : 1.2V    :           :                
+GND                          : H4        : gnd    :                   :         :           :                
+VCCINT                       : H5        : power  :                   : 1.2V    :           :                
+GND                          : H6        : gnd    :                   :         :           :                
+VCCINT                       : H7        : power  :                   : 1.2V    :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+VCCA                         : H9        : power  :                   : 2.5V    :           :                
+S1                           : H10       : output : 2.5 V             :         : 5         : N              
+VCCIO5                       : H11       : power  :                   : 2.5V    : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 5         :                
+GND+                         : H13       :        :                   :         : 5         :                
+GXB_GND*                     : J1        :        :                   :         : QL0       :                
+GXB_GND*                     : J2        :        :                   :         : QL0       :                
+VCCA_GXB                     : J3        : power  :                   : 2.5V    :           :                
+VCCD_PLL                     : J4        : power  :                   : 1.2V    :           :                
+CONF_DONE                    : J5        :        :                   :         : 3         :                
+GXB_GND*                     : J6        :        :                   :         : 3A        :                
+GXB_GND*                     : J7        :        :                   :         : 3A        :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCD_PLL                     : J10       : power  :                   : 1.2V    :           :                
+VCCIO5                       : J11       : power  :                   : 2.5V    : 5         :                
+GND                          : J12       : gnd    :                   :         :           :                
+S0                           : J13       : output : 2.5 V             :         : 5         : N              
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+GND                          : K3        : gnd    :                   :         :           :                
+VCCA                         : K4        : power  :                   : 2.5V    :           :                
+MSEL0                        : K5        :        :                   :         : 3         :                
+nSTATUS                      : K6        :        :                   :         : 3         :                
+VCC_CLKIN3A                  : K7        : power  :                   : 2.5V    : 3A        :                
+S8                           : K8        : output : 2.5 V             :         : 4         : N              
+X6                           : K9        : input  : 2.5 V             :         : 4         : N              
+Y1                           : K10       : input  : 2.5 V             :         : 4         : N              
+S4                           : K11       : output : 2.5 V             :         : 5         : N              
+X4                           : K12       : input  : 2.5 V             :         : 5         : N              
+X1                           : K13       : input  : 2.5 V             :         : 5         : N              
+RREF                         : L1        :        :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+MSEL2                        : L3        :        :                   :         : 3         :                
+X9                           : L4        : input  : 2.5 V             :         : 3         : N              
+S7                           : L5        : output : 2.5 V             :         : 3         : N              
+VCCIO3                       : L6        : power  :                   : 2.5V    : 3         :                
+S9                           : L7        : output : 2.5 V             :         : 3         : N              
+VCCIO4                       : L8        : power  :                   : 2.5V    : 4         :                
+X5                           : L9        : input  : 2.5 V             :         : 4         : N              
+VCCIO4                       : L10       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L11       :        :                   :         : 4         :                
+Y2                           : L12       : input  : 2.5 V             :         : 5         : N              
+X0                           : L13       : input  : 2.5 V             :         : 5         : N              
+GND                          : M1        : gnd    :                   :         :           :                
+VCCA_GXB                     : M2        : power  :                   : 2.5V    :           :                
+NC                           : M3        :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 3         :                
+GND                          : M5        : gnd    :                   :         :           :                
+X7                           : M6        : input  : 2.5 V             :         : 3         : N              
+Y9                           : M7        : input  : 2.5 V             :         : 4         : N              
+GND                          : M8        : gnd    :                   :         :           :                
+Y6                           : M9        : input  : 2.5 V             :         : 4         : N              
+GND                          : M10       : gnd    :                   :         :           :                
+S5                           : M11       : output : 2.5 V             :         : 4         : N              
+GND                          : M12       : gnd    :                   :         :           :                
+Y5                           : M13       : input  : 2.5 V             :         : 5         : N              
+VCCL_GXB                     : N1        : power  :                   : 1.2V    :           :                
+NC                           : N2        :        :                   :         :           :                
+MSEL1                        : N3        :        :                   :         : 3         :                
+X8                           : N4        : input  : 2.5 V             :         : 3         : N              
+~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : N5        : output : 2.5 V             :         : 3         : N              
+Y8                           : N6        : input  : 2.5 V             :         : 3         : N              
+ENY                          : N7        : input  : 2.5 V             :         : 4         : N              
+Y7                           : N8        : input  : 2.5 V             :         : 4         : N              
+Cout                         : N9        : output : 2.5 V             :         : 4         : N              
+Y3                           : N10       : input  : 2.5 V             :         : 4         : N              
+S2                           : N11       : output : 2.5 V             :         : 4         : N              
+Y4                           : N12       : input  : 2.5 V             :         : 4         : N              
+S6                           : N13       : output : 2.5 V             :         : 5         : N              
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof
new file mode 100644
index 0000000..5bbcefa
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sof
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.rpt
new file mode 100644
index 0000000..c89ed1b
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.rpt
@@ -0,0 +1,1639 @@
+TimeQuest Timing Analyzer report for ten_bit_adder_NO_BUS
+Thu Feb 18 22:56:50 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Propagation Delay
+ 13. Minimum Propagation Delay
+ 14. Slow 1200mV 85C Model Metastability Report
+ 15. Slow 1200mV 0C Model Fmax Summary
+ 16. Slow 1200mV 0C Model Setup Summary
+ 17. Slow 1200mV 0C Model Hold Summary
+ 18. Slow 1200mV 0C Model Recovery Summary
+ 19. Slow 1200mV 0C Model Removal Summary
+ 20. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 21. Propagation Delay
+ 22. Minimum Propagation Delay
+ 23. Slow 1200mV 0C Model Metastability Report
+ 24. Fast 1200mV 0C Model Setup Summary
+ 25. Fast 1200mV 0C Model Hold Summary
+ 26. Fast 1200mV 0C Model Recovery Summary
+ 27. Fast 1200mV 0C Model Removal Summary
+ 28. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 29. Propagation Delay
+ 30. Minimum Propagation Delay
+ 31. Fast 1200mV 0C Model Metastability Report
+ 32. Multicorner Timing Analysis Summary
+ 33. Propagation Delay
+ 34. Minimum Propagation Delay
+ 35. Board Trace Model Assignments
+ 36. Input Transition Times
+ 37. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 38. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 39. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 40. Clock Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths
+ 44. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; ten_bit_adder_NO_BUS                               ;
+; Device Family      ; Cyclone IV GX                                      ;
+; Device Name        ; EP4CGX15BF14C6                                     ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; ENY        ; Cout        ; 10.944 ;        ;        ; 11.182 ;
+; ENY        ; S0          ; 6.434  ; 6.385  ; 6.552  ; 6.462  ;
+; ENY        ; S1          ; 6.742  ; 6.661  ; 6.899  ; 6.793  ;
+; ENY        ; S2          ; 7.083  ; 6.997  ; 7.276  ; 7.176  ;
+; ENY        ; S3          ; 8.653  ; 8.639  ; 8.891  ; 8.863  ;
+; ENY        ; S4          ; 8.304  ; 8.235  ; 8.578  ; 8.495  ;
+; ENY        ; S5          ; 8.829  ; 8.747  ; 9.167  ; 9.028  ;
+; ENY        ; S6          ; 8.958  ; 8.841  ; 9.320  ; 9.194  ;
+; ENY        ; S7          ; 9.811  ; 9.686  ; 10.190 ; 10.056 ;
+; ENY        ; S8          ; 11.429 ; 11.338 ; 11.816 ; 11.716 ;
+; ENY        ; S9          ; 11.292 ; 11.223 ; 11.686 ; 11.608 ;
+; X0         ; Cout        ; 12.785 ;        ;        ; 13.371 ;
+; X0         ; S0          ; 8.593  ; 8.507  ; 9.044  ; 8.991  ;
+; X0         ; S1          ; 8.587  ; 8.506  ; 9.079  ; 8.980  ;
+; X0         ; S2          ; 8.924  ; 8.838  ; 9.465  ; 9.365  ;
+; X0         ; S3          ; 10.494 ; 10.480 ; 11.080 ; 11.052 ;
+; X0         ; S4          ; 10.145 ; 10.076 ; 10.767 ; 10.684 ;
+; X0         ; S5          ; 10.670 ; 10.588 ; 11.356 ; 11.217 ;
+; X0         ; S6          ; 10.799 ; 10.682 ; 11.509 ; 11.383 ;
+; X0         ; S7          ; 11.652 ; 11.527 ; 12.379 ; 12.245 ;
+; X0         ; S8          ; 13.270 ; 13.179 ; 14.005 ; 13.905 ;
+; X0         ; S9          ; 13.133 ; 13.064 ; 13.875 ; 13.797 ;
+; X1         ; Cout        ; 12.518 ;        ;        ; 13.065 ;
+; X1         ; S1          ; 8.303  ; 8.183  ; 8.778  ; 8.649  ;
+; X1         ; S2          ; 8.657  ; 8.571  ; 9.159  ; 9.059  ;
+; X1         ; S3          ; 10.227 ; 10.213 ; 10.774 ; 10.746 ;
+; X1         ; S4          ; 9.878  ; 9.809  ; 10.461 ; 10.378 ;
+; X1         ; S5          ; 10.403 ; 10.321 ; 11.050 ; 10.911 ;
+; X1         ; S6          ; 10.532 ; 10.415 ; 11.203 ; 11.077 ;
+; X1         ; S7          ; 11.385 ; 11.260 ; 12.073 ; 11.939 ;
+; X1         ; S8          ; 13.003 ; 12.912 ; 13.699 ; 13.599 ;
+; X1         ; S9          ; 12.866 ; 12.797 ; 13.569 ; 13.491 ;
+; X2         ; Cout        ; 9.971  ;        ;        ; 10.145 ;
+; X2         ; S2          ; 6.084  ; 5.970  ; 6.232  ; 6.109  ;
+; X2         ; S3          ; 7.680  ; 7.666  ; 7.854  ; 7.826  ;
+; X2         ; S4          ; 7.331  ; 7.262  ; 7.541  ; 7.458  ;
+; X2         ; S5          ; 7.856  ; 7.774  ; 8.130  ; 7.991  ;
+; X2         ; S6          ; 7.985  ; 7.868  ; 8.283  ; 8.157  ;
+; X2         ; S7          ; 8.838  ; 8.713  ; 9.153  ; 9.019  ;
+; X2         ; S8          ; 10.456 ; 10.365 ; 10.779 ; 10.679 ;
+; X2         ; S9          ; 10.319 ; 10.250 ; 10.649 ; 10.571 ;
+; X3         ; Cout        ; 9.487  ;        ;        ; 9.659  ;
+; X3         ; S3          ; 7.182  ; 7.138  ; 7.324  ; 7.312  ;
+; X3         ; S4          ; 6.847  ; 6.778  ; 7.055  ; 6.972  ;
+; X3         ; S5          ; 7.372  ; 7.290  ; 7.644  ; 7.505  ;
+; X3         ; S6          ; 7.501  ; 7.384  ; 7.797  ; 7.671  ;
+; X3         ; S7          ; 8.354  ; 8.229  ; 8.667  ; 8.533  ;
+; X3         ; S8          ; 9.972  ; 9.881  ; 10.293 ; 10.193 ;
+; X3         ; S9          ; 9.835  ; 9.766  ; 10.163 ; 10.085 ;
+; X4         ; Cout        ; 10.527 ;        ;        ; 10.918 ;
+; X4         ; S4          ; 7.866  ; 7.769  ; 8.314  ; 8.208  ;
+; X4         ; S5          ; 8.412  ; 8.330  ; 8.903  ; 8.764  ;
+; X4         ; S6          ; 8.541  ; 8.424  ; 9.056  ; 8.930  ;
+; X4         ; S7          ; 9.394  ; 9.269  ; 9.926  ; 9.792  ;
+; X4         ; S8          ; 11.012 ; 10.921 ; 11.552 ; 11.452 ;
+; X4         ; S9          ; 10.875 ; 10.806 ; 11.422 ; 11.344 ;
+; X5         ; Cout        ; 10.115 ;        ;        ; 10.488 ;
+; X5         ; S5          ; 8.000  ; 7.915  ; 8.461  ; 8.332  ;
+; X5         ; S6          ; 8.129  ; 8.012  ; 8.626  ; 8.500  ;
+; X5         ; S7          ; 8.982  ; 8.857  ; 9.496  ; 9.362  ;
+; X5         ; S8          ; 10.600 ; 10.509 ; 11.122 ; 11.022 ;
+; X5         ; S9          ; 10.463 ; 10.394 ; 10.992 ; 10.914 ;
+; X6         ; Cout        ; 9.844  ;        ;        ; 10.186 ;
+; X6         ; S6          ; 7.857  ; 7.738  ; 8.283  ; 8.196  ;
+; X6         ; S7          ; 8.711  ; 8.586  ; 9.194  ; 9.060  ;
+; X6         ; S8          ; 10.329 ; 10.238 ; 10.820 ; 10.720 ;
+; X6         ; S9          ; 10.192 ; 10.123 ; 10.690 ; 10.612 ;
+; X7         ; Cout        ; 8.257  ;        ;        ; 8.571  ;
+; X7         ; S7          ; 7.151  ; 7.050  ; 7.569  ; 7.465  ;
+; X7         ; S8          ; 8.742  ; 8.651  ; 9.205  ; 9.105  ;
+; X7         ; S9          ; 8.605  ; 8.536  ; 9.075  ; 8.997  ;
+; X8         ; Cout        ; 7.986  ;        ;        ; 8.302  ;
+; X8         ; S8          ; 8.497  ; 8.430  ; 8.924  ; 8.854  ;
+; X8         ; S9          ; 8.334  ; 8.265  ; 8.806  ; 8.728  ;
+; X9         ; Cout        ; 7.751  ;        ;        ; 8.004  ;
+; X9         ; S9          ; 8.097  ; 8.026  ; 8.467  ; 8.428  ;
+; Y0         ; Cout        ; 12.977 ;        ;        ; 13.606 ;
+; Y0         ; S0          ; 8.360  ; 8.276  ; 8.869  ; 8.776  ;
+; Y0         ; S1          ; 8.775  ; 8.694  ; 9.323  ; 9.217  ;
+; Y0         ; S2          ; 9.116  ; 9.030  ; 9.700  ; 9.600  ;
+; Y0         ; S3          ; 10.686 ; 10.672 ; 11.315 ; 11.287 ;
+; Y0         ; S4          ; 10.337 ; 10.268 ; 11.002 ; 10.919 ;
+; Y0         ; S5          ; 10.862 ; 10.780 ; 11.591 ; 11.452 ;
+; Y0         ; S6          ; 10.991 ; 10.874 ; 11.744 ; 11.618 ;
+; Y0         ; S7          ; 11.844 ; 11.719 ; 12.614 ; 12.480 ;
+; Y0         ; S8          ; 13.462 ; 13.371 ; 14.240 ; 14.140 ;
+; Y0         ; S9          ; 13.325 ; 13.256 ; 14.110 ; 14.032 ;
+; Y1         ; Cout        ; 12.770 ;        ;        ; 13.318 ;
+; Y1         ; S1          ; 8.559  ; 8.437  ; 8.996  ; 8.906  ;
+; Y1         ; S2          ; 8.909  ; 8.823  ; 9.412  ; 9.312  ;
+; Y1         ; S3          ; 10.479 ; 10.465 ; 11.027 ; 10.999 ;
+; Y1         ; S4          ; 10.130 ; 10.061 ; 10.714 ; 10.631 ;
+; Y1         ; S5          ; 10.655 ; 10.573 ; 11.303 ; 11.164 ;
+; Y1         ; S6          ; 10.784 ; 10.667 ; 11.456 ; 11.330 ;
+; Y1         ; S7          ; 11.637 ; 11.512 ; 12.326 ; 12.192 ;
+; Y1         ; S8          ; 13.255 ; 13.164 ; 13.952 ; 13.852 ;
+; Y1         ; S9          ; 13.118 ; 13.049 ; 13.822 ; 13.744 ;
+; Y2         ; Cout        ; 12.146 ;        ;        ; 12.658 ;
+; Y2         ; S2          ; 8.273  ; 8.196  ; 8.736  ; 8.595  ;
+; Y2         ; S3          ; 9.855  ; 9.841  ; 10.367 ; 10.339 ;
+; Y2         ; S4          ; 9.506  ; 9.437  ; 10.054 ; 9.971  ;
+; Y2         ; S5          ; 10.031 ; 9.949  ; 10.643 ; 10.504 ;
+; Y2         ; S6          ; 10.160 ; 10.043 ; 10.796 ; 10.670 ;
+; Y2         ; S7          ; 11.013 ; 10.888 ; 11.666 ; 11.532 ;
+; Y2         ; S8          ; 12.631 ; 12.540 ; 13.292 ; 13.192 ;
+; Y2         ; S9          ; 12.494 ; 12.425 ; 13.162 ; 13.084 ;
+; Y3         ; Cout        ; 10.994 ;        ;        ; 11.449 ;
+; Y3         ; S3          ; 8.693  ; 8.651  ; 9.157  ; 9.106  ;
+; Y3         ; S4          ; 8.354  ; 8.285  ; 8.845  ; 8.762  ;
+; Y3         ; S5          ; 8.879  ; 8.797  ; 9.434  ; 9.295  ;
+; Y3         ; S6          ; 9.008  ; 8.891  ; 9.587  ; 9.461  ;
+; Y3         ; S7          ; 9.861  ; 9.736  ; 10.457 ; 10.323 ;
+; Y3         ; S8          ; 11.479 ; 11.388 ; 12.083 ; 11.983 ;
+; Y3         ; S9          ; 11.342 ; 11.273 ; 11.953 ; 11.875 ;
+; Y4         ; Cout        ; 11.026 ;        ;        ; 11.478 ;
+; Y4         ; S4          ; 8.375  ; 8.315  ; 8.858  ; 8.734  ;
+; Y4         ; S5          ; 8.911  ; 8.829  ; 9.463  ; 9.324  ;
+; Y4         ; S6          ; 9.040  ; 8.923  ; 9.616  ; 9.490  ;
+; Y4         ; S7          ; 9.893  ; 9.768  ; 10.486 ; 10.352 ;
+; Y4         ; S8          ; 11.511 ; 11.420 ; 12.112 ; 12.012 ;
+; Y4         ; S9          ; 11.374 ; 11.305 ; 11.982 ; 11.904 ;
+; Y5         ; Cout        ; 9.982  ;        ;        ; 10.305 ;
+; Y5         ; S5          ; 7.853  ; 7.736  ; 8.293  ; 8.167  ;
+; Y5         ; S6          ; 7.996  ; 7.879  ; 8.443  ; 8.317  ;
+; Y5         ; S7          ; 8.849  ; 8.724  ; 9.313  ; 9.179  ;
+; Y5         ; S8          ; 10.467 ; 10.376 ; 10.939 ; 10.839 ;
+; Y5         ; S9          ; 10.330 ; 10.261 ; 10.809 ; 10.731 ;
+; Y6         ; Cout        ; 9.872  ;        ;        ; 10.219 ;
+; Y6         ; S6          ; 7.902  ; 7.824  ; 8.365  ; 8.262  ;
+; Y6         ; S7          ; 8.739  ; 8.614  ; 9.227  ; 9.093  ;
+; Y6         ; S8          ; 10.357 ; 10.266 ; 10.853 ; 10.753 ;
+; Y6         ; S9          ; 10.220 ; 10.151 ; 10.723 ; 10.645 ;
+; Y7         ; Cout        ; 8.206  ;        ;        ; 8.503  ;
+; Y7         ; S7          ; 7.078  ; 6.951  ; 7.477  ; 7.382  ;
+; Y7         ; S8          ; 8.691  ; 8.600  ; 9.137  ; 9.037  ;
+; Y7         ; S9          ; 8.554  ; 8.485  ; 9.007  ; 8.929  ;
+; Y8         ; Cout        ; 7.843  ;        ;        ; 8.140  ;
+; Y8         ; S8          ; 8.319  ; 8.226  ; 8.725  ; 8.664  ;
+; Y8         ; S9          ; 8.191  ; 8.122  ; 8.644  ; 8.566  ;
+; Y9         ; Cout        ; 5.214  ;        ;        ; 5.277  ;
+; Y9         ; S9          ; 5.574  ; 5.544  ; 5.771  ; 5.723  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++--------------------------------------------------------------+
+; Minimum Propagation Delay                                    ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; ENY        ; Cout        ; 5.058  ;        ;        ; 5.111  ;
+; ENY        ; S0          ; 6.217  ; 6.155  ; 6.331  ; 6.242  ;
+; ENY        ; S1          ; 6.391  ; 6.269  ; 6.505  ; 6.414  ;
+; ENY        ; S2          ; 5.784  ; 5.668  ; 5.866  ; 5.781  ;
+; ENY        ; S3          ; 6.859  ; 6.836  ; 6.972  ; 6.923  ;
+; ENY        ; S4          ; 5.897  ; 5.799  ; 5.979  ; 5.912  ;
+; ENY        ; S5          ; 5.872  ; 5.758  ; 5.954  ; 5.869  ;
+; ENY        ; S6          ; 5.800  ; 5.724  ; 5.936  ; 5.812  ;
+; ENY        ; S7          ; 4.566  ; 4.466  ; 4.745  ; 4.635  ;
+; ENY        ; S8          ; 5.849  ; 5.783  ; 6.028  ; 5.952  ;
+; ENY        ; S9          ; 5.421  ; 5.392  ; 5.633  ; 5.543  ;
+; X0         ; Cout        ; 12.119 ;        ;        ; 12.589 ;
+; X0         ; S0          ; 8.299  ; 8.216  ; 8.739  ; 8.684  ;
+; X0         ; S1          ; 8.240  ; 8.160  ; 8.735  ; 8.607  ;
+; X0         ; S2          ; 8.526  ; 8.435  ; 9.046  ; 8.945  ;
+; X0         ; S3          ; 9.993  ; 9.972  ; 10.535 ; 10.486 ;
+; X0         ; S4          ; 9.609  ; 9.536  ; 10.175 ; 10.092 ;
+; X0         ; S5          ; 10.073 ; 9.981  ; 10.664 ; 10.544 ;
+; X0         ; S6          ; 10.203 ; 10.087 ; 10.799 ; 10.674 ;
+; X0         ; S7          ; 11.027 ; 10.904 ; 11.638 ; 11.506 ;
+; X0         ; S8          ; 12.614 ; 12.525 ; 13.232 ; 13.134 ;
+; X0         ; S9          ; 12.483 ; 12.414 ; 13.108 ; 13.030 ;
+; X1         ; Cout        ; 11.901 ;        ;        ; 12.333 ;
+; X1         ; S1          ; 8.017  ; 7.897  ; 8.477  ; 8.348  ;
+; X1         ; S2          ; 8.308  ; 8.217  ; 8.790  ; 8.689  ;
+; X1         ; S3          ; 9.775  ; 9.754  ; 10.279 ; 10.230 ;
+; X1         ; S4          ; 9.391  ; 9.318  ; 9.919  ; 9.836  ;
+; X1         ; S5          ; 9.855  ; 9.763  ; 10.408 ; 10.288 ;
+; X1         ; S6          ; 9.985  ; 9.869  ; 10.543 ; 10.418 ;
+; X1         ; S7          ; 10.809 ; 10.686 ; 11.382 ; 11.250 ;
+; X1         ; S8          ; 12.396 ; 12.307 ; 12.976 ; 12.878 ;
+; X1         ; S9          ; 12.265 ; 12.196 ; 12.852 ; 12.774 ;
+; X2         ; Cout        ; 9.496  ;        ;        ; 9.594  ;
+; X2         ; S2          ; 5.899  ; 5.785  ; 6.049  ; 5.926  ;
+; X2         ; S3          ; 7.370  ; 7.349  ; 7.540  ; 7.491  ;
+; X2         ; S4          ; 6.986  ; 6.913  ; 7.180  ; 7.097  ;
+; X2         ; S5          ; 7.450  ; 7.358  ; 7.669  ; 7.549  ;
+; X2         ; S6          ; 7.580  ; 7.464  ; 7.804  ; 7.679  ;
+; X2         ; S7          ; 8.404  ; 8.281  ; 8.643  ; 8.511  ;
+; X2         ; S8          ; 9.991  ; 9.902  ; 10.237 ; 10.139 ;
+; X2         ; S9          ; 9.860  ; 9.791  ; 10.113 ; 10.035 ;
+; X3         ; Cout        ; 9.076  ;        ;        ; 9.186  ;
+; X3         ; S3          ; 6.948  ; 6.902  ; 7.092  ; 7.077  ;
+; X3         ; S4          ; 6.566  ; 6.493  ; 6.772  ; 6.689  ;
+; X3         ; S5          ; 7.030  ; 6.938  ; 7.261  ; 7.141  ;
+; X3         ; S6          ; 7.160  ; 7.044  ; 7.396  ; 7.271  ;
+; X3         ; S7          ; 7.984  ; 7.861  ; 8.235  ; 8.103  ;
+; X3         ; S8          ; 9.571  ; 9.482  ; 9.829  ; 9.731  ;
+; X3         ; S9          ; 9.440  ; 9.371  ; 9.705  ; 9.627  ;
+; X4         ; Cout        ; 10.112 ;        ;        ; 10.448 ;
+; X4         ; S4          ; 7.603  ; 7.507  ; 8.036  ; 7.931  ;
+; X4         ; S5          ; 8.066  ; 7.974  ; 8.523  ; 8.403  ;
+; X4         ; S6          ; 8.196  ; 8.080  ; 8.658  ; 8.533  ;
+; X4         ; S7          ; 9.020  ; 8.897  ; 9.497  ; 9.365  ;
+; X4         ; S8          ; 10.607 ; 10.518 ; 11.091 ; 10.993 ;
+; X4         ; S9          ; 10.476 ; 10.407 ; 10.967 ; 10.889 ;
+; X5         ; Cout        ; 9.712  ;        ;        ; 10.036 ;
+; X5         ; S5          ; 7.662  ; 7.568  ; 8.108  ; 7.988  ;
+; X5         ; S6          ; 7.796  ; 7.680  ; 8.246  ; 8.121  ;
+; X5         ; S7          ; 8.620  ; 8.497  ; 9.085  ; 8.953  ;
+; X5         ; S8          ; 10.207 ; 10.118 ; 10.679 ; 10.581 ;
+; X5         ; S9          ; 10.076 ; 10.007 ; 10.555 ; 10.477 ;
+; X6         ; Cout        ; 9.499  ;        ;        ; 9.828  ;
+; X6         ; S6          ; 7.582  ; 7.464  ; 7.999  ; 7.912  ;
+; X6         ; S7          ; 8.407  ; 8.284  ; 8.877  ; 8.745  ;
+; X6         ; S8          ; 9.994  ; 9.905  ; 10.471 ; 10.373 ;
+; X6         ; S9          ; 9.863  ; 9.794  ; 10.347 ; 10.269 ;
+; X7         ; Cout        ; 7.940  ;        ;        ; 8.217  ;
+; X7         ; S7          ; 6.848  ; 6.746  ; 7.266  ; 7.158  ;
+; X7         ; S8          ; 8.435  ; 8.346  ; 8.860  ; 8.762  ;
+; X7         ; S9          ; 8.304  ; 8.235  ; 8.736  ; 8.658  ;
+; X8         ; Cout        ; 7.680  ;        ;        ; 7.959  ;
+; X8         ; S8          ; 8.175  ; 8.107  ; 8.602  ; 8.528  ;
+; X8         ; S9          ; 8.044  ; 7.975  ; 8.478  ; 8.400  ;
+; X9         ; Cout        ; 7.489  ;        ;        ; 7.735  ;
+; X9         ; S9          ; 7.851  ; 7.780  ; 8.214  ; 8.174  ;
+; Y0         ; Cout        ; 12.300 ;        ;        ; 12.821 ;
+; Y0         ; S0          ; 8.074  ; 7.990  ; 8.570  ; 8.477  ;
+; Y0         ; S1          ; 8.417  ; 8.337  ; 8.971  ; 8.830  ;
+; Y0         ; S2          ; 8.707  ; 8.616  ; 9.278  ; 9.177  ;
+; Y0         ; S3          ; 10.174 ; 10.153 ; 10.767 ; 10.718 ;
+; Y0         ; S4          ; 9.790  ; 9.717  ; 10.407 ; 10.324 ;
+; Y0         ; S5          ; 10.254 ; 10.162 ; 10.896 ; 10.776 ;
+; Y0         ; S6          ; 10.384 ; 10.268 ; 11.031 ; 10.906 ;
+; Y0         ; S7          ; 11.208 ; 11.085 ; 11.870 ; 11.738 ;
+; Y0         ; S8          ; 12.795 ; 12.706 ; 13.464 ; 13.366 ;
+; Y0         ; S9          ; 12.664 ; 12.595 ; 13.340 ; 13.262 ;
+; Y1         ; Cout        ; 12.136 ;        ;        ; 12.572 ;
+; Y1         ; S1          ; 8.256  ; 8.134  ; 8.682  ; 8.591  ;
+; Y1         ; S2          ; 8.543  ; 8.452  ; 9.029  ; 8.928  ;
+; Y1         ; S3          ; 10.010 ; 9.989  ; 10.518 ; 10.469 ;
+; Y1         ; S4          ; 9.626  ; 9.553  ; 10.158 ; 10.075 ;
+; Y1         ; S5          ; 10.090 ; 9.998  ; 10.647 ; 10.527 ;
+; Y1         ; S6          ; 10.220 ; 10.104 ; 10.782 ; 10.657 ;
+; Y1         ; S7          ; 11.044 ; 10.921 ; 11.621 ; 11.489 ;
+; Y1         ; S8          ; 12.631 ; 12.542 ; 13.215 ; 13.117 ;
+; Y1         ; S9          ; 12.500 ; 12.431 ; 13.091 ; 13.013 ;
+; Y2         ; Cout        ; 11.558 ;        ;        ; 11.937 ;
+; Y2         ; S2          ; 7.948  ; 7.855  ; 8.394  ; 8.294  ;
+; Y2         ; S3          ; 9.432  ; 9.411  ; 9.883  ; 9.834  ;
+; Y2         ; S4          ; 9.048  ; 8.975  ; 9.523  ; 9.440  ;
+; Y2         ; S5          ; 9.512  ; 9.420  ; 10.012 ; 9.892  ;
+; Y2         ; S6          ; 9.642  ; 9.526  ; 10.147 ; 10.022 ;
+; Y2         ; S7          ; 10.466 ; 10.343 ; 10.986 ; 10.854 ;
+; Y2         ; S8          ; 12.053 ; 11.964 ; 12.580 ; 12.482 ;
+; Y2         ; S9          ; 11.922 ; 11.853 ; 12.456 ; 12.378 ;
+; Y3         ; Cout        ; 10.518 ;        ;        ; 10.897 ;
+; Y3         ; S3          ; 8.393  ; 8.349  ; 8.846  ; 8.793  ;
+; Y3         ; S4          ; 8.008  ; 7.935  ; 8.483  ; 8.400  ;
+; Y3         ; S5          ; 8.472  ; 8.380  ; 8.972  ; 8.852  ;
+; Y3         ; S6          ; 8.602  ; 8.486  ; 9.107  ; 8.982  ;
+; Y3         ; S7          ; 9.426  ; 9.303  ; 9.946  ; 9.814  ;
+; Y3         ; S8          ; 11.013 ; 10.924 ; 11.540 ; 11.442 ;
+; Y3         ; S9          ; 10.882 ; 10.813 ; 11.416 ; 11.338 ;
+; Y4         ; Cout        ; 10.564 ;        ;        ; 10.921 ;
+; Y4         ; S4          ; 8.037  ; 7.962  ; 8.506  ; 8.424  ;
+; Y4         ; S5          ; 8.518  ; 8.426  ; 8.996  ; 8.876  ;
+; Y4         ; S6          ; 8.648  ; 8.532  ; 9.131  ; 9.006  ;
+; Y4         ; S7          ; 9.472  ; 9.349  ; 9.970  ; 9.838  ;
+; Y4         ; S8          ; 11.059 ; 10.970 ; 11.564 ; 11.466 ;
+; Y4         ; S9          ; 10.928 ; 10.859 ; 11.440 ; 11.362 ;
+; Y5         ; Cout        ; 9.639  ;        ;        ; 9.946  ;
+; Y5         ; S5          ; 7.589  ; 7.474  ; 8.016  ; 7.892  ;
+; Y5         ; S6          ; 7.723  ; 7.607  ; 8.156  ; 8.031  ;
+; Y5         ; S7          ; 8.547  ; 8.424  ; 8.995  ; 8.863  ;
+; Y5         ; S8          ; 10.134 ; 10.045 ; 10.589 ; 10.491 ;
+; Y5         ; S9          ; 10.003 ; 9.934  ; 10.465 ; 10.387 ;
+; Y6         ; Cout        ; 9.490  ;        ;        ; 9.832  ;
+; Y6         ; S6          ; 7.579  ; 7.503  ; 8.052  ; 7.915  ;
+; Y6         ; S7          ; 8.398  ; 8.275  ; 8.881  ; 8.749  ;
+; Y6         ; S8          ; 9.985  ; 9.896  ; 10.475 ; 10.377 ;
+; Y6         ; S9          ; 9.854  ; 9.785  ; 10.351 ; 10.273 ;
+; Y7         ; Cout        ; 7.926  ;        ;        ; 8.213  ;
+; Y7         ; S7          ; 6.839  ; 6.714  ; 7.230  ; 7.136  ;
+; Y7         ; S8          ; 8.421  ; 8.332  ; 8.856  ; 8.758  ;
+; Y7         ; S9          ; 8.290  ; 8.221  ; 8.732  ; 8.654  ;
+; Y8         ; Cout        ; 7.578  ;        ;        ; 7.866  ;
+; Y8         ; S8          ; 8.064  ; 7.973  ; 8.462  ; 8.402  ;
+; Y8         ; S9          ; 7.942  ; 7.873  ; 8.385  ; 8.307  ;
+; Y9         ; Cout        ; 5.025  ;        ;        ; 5.088  ;
+; Y9         ; S9          ; 5.391  ; 5.362  ; 5.605  ; 5.528  ;
++------------+-------------+--------+--------+--------+--------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; ENY        ; Cout        ; 9.921  ;        ;        ; 9.978  ;
+; ENY        ; S0          ; 5.794  ; 5.690  ; 5.929  ; 5.790  ;
+; ENY        ; S1          ; 6.046  ; 5.964  ; 6.209  ; 6.100  ;
+; ENY        ; S2          ; 6.380  ; 6.259  ; 6.560  ; 6.425  ;
+; ENY        ; S3          ; 7.813  ; 7.730  ; 8.023  ; 7.926  ;
+; ENY        ; S4          ; 7.490  ; 7.377  ; 7.717  ; 7.590  ;
+; ENY        ; S5          ; 7.944  ; 7.851  ; 8.214  ; 8.074  ;
+; ENY        ; S6          ; 8.059  ; 7.943  ; 8.348  ; 8.224  ;
+; ENY        ; S7          ; 8.852  ; 8.737  ; 9.102  ; 8.979  ;
+; ENY        ; S8          ; 10.294 ; 10.190 ; 10.544 ; 10.432 ;
+; ENY        ; S9          ; 10.163 ; 10.089 ; 10.412 ; 10.330 ;
+; X0         ; Cout        ; 11.489 ;        ;        ; 11.785 ;
+; X0         ; S0          ; 7.657  ; 7.521  ; 8.011  ; 7.906  ;
+; X0         ; S1          ; 7.619  ; 7.538  ; 8.009  ; 7.906  ;
+; X0         ; S2          ; 7.948  ; 7.827  ; 8.367  ; 8.232  ;
+; X0         ; S3          ; 9.381  ; 9.298  ; 9.830  ; 9.733  ;
+; X0         ; S4          ; 9.058  ; 8.945  ; 9.524  ; 9.397  ;
+; X0         ; S5          ; 9.512  ; 9.419  ; 10.021 ; 9.881  ;
+; X0         ; S6          ; 9.627  ; 9.511  ; 10.155 ; 10.031 ;
+; X0         ; S7          ; 10.420 ; 10.305 ; 10.909 ; 10.786 ;
+; X0         ; S8          ; 11.862 ; 11.758 ; 12.351 ; 12.239 ;
+; X0         ; S9          ; 11.731 ; 11.657 ; 12.219 ; 12.137 ;
+; X1         ; Cout        ; 11.254 ;        ;        ; 11.511 ;
+; X1         ; S1          ; 7.369  ; 7.248  ; 7.738  ; 7.609  ;
+; X1         ; S2          ; 7.713  ; 7.592  ; 8.093  ; 7.958  ;
+; X1         ; S3          ; 9.146  ; 9.063  ; 9.556  ; 9.459  ;
+; X1         ; S4          ; 8.823  ; 8.710  ; 9.250  ; 9.123  ;
+; X1         ; S5          ; 9.277  ; 9.184  ; 9.747  ; 9.607  ;
+; X1         ; S6          ; 9.392  ; 9.276  ; 9.881  ; 9.757  ;
+; X1         ; S7          ; 10.185 ; 10.070 ; 10.635 ; 10.512 ;
+; X1         ; S8          ; 11.627 ; 11.523 ; 12.077 ; 11.965 ;
+; X1         ; S9          ; 11.496 ; 11.422 ; 11.945 ; 11.863 ;
+; X2         ; Cout        ; 9.051  ;        ;        ; 9.073  ;
+; X2         ; S2          ; 5.485  ; 5.338  ; 5.650  ; 5.495  ;
+; X2         ; S3          ; 6.943  ; 6.860  ; 7.118  ; 7.021  ;
+; X2         ; S4          ; 6.620  ; 6.507  ; 6.812  ; 6.685  ;
+; X2         ; S5          ; 7.074  ; 6.981  ; 7.309  ; 7.169  ;
+; X2         ; S6          ; 7.189  ; 7.073  ; 7.443  ; 7.319  ;
+; X2         ; S7          ; 7.982  ; 7.867  ; 8.197  ; 8.074  ;
+; X2         ; S8          ; 9.424  ; 9.320  ; 9.639  ; 9.527  ;
+; X2         ; S9          ; 9.293  ; 9.219  ; 9.507  ; 9.425  ;
+; X3         ; Cout        ; 8.609  ;        ;        ; 8.636  ;
+; X3         ; S3          ; 6.489  ; 6.378  ; 6.640  ; 6.558  ;
+; X3         ; S4          ; 6.178  ; 6.065  ; 6.375  ; 6.248  ;
+; X3         ; S5          ; 6.632  ; 6.539  ; 6.872  ; 6.732  ;
+; X3         ; S6          ; 6.747  ; 6.631  ; 7.006  ; 6.882  ;
+; X3         ; S7          ; 7.540  ; 7.425  ; 7.760  ; 7.637  ;
+; X3         ; S8          ; 8.982  ; 8.878  ; 9.202  ; 9.090  ;
+; X3         ; S9          ; 8.851  ; 8.777  ; 9.070  ; 8.988  ;
+; X4         ; Cout        ; 9.447  ;        ;        ; 9.609  ;
+; X4         ; S4          ; 6.996  ; 6.857  ; 7.348  ; 7.201  ;
+; X4         ; S5          ; 7.470  ; 7.377  ; 7.845  ; 7.705  ;
+; X4         ; S6          ; 7.585  ; 7.469  ; 7.979  ; 7.855  ;
+; X4         ; S7          ; 8.378  ; 8.263  ; 8.733  ; 8.610  ;
+; X4         ; S8          ; 9.820  ; 9.716  ; 10.175 ; 10.063 ;
+; X4         ; S9          ; 9.689  ; 9.615  ; 10.043 ; 9.961  ;
+; X5         ; Cout        ; 9.053  ;        ;        ; 9.224  ;
+; X5         ; S5          ; 7.079  ; 6.982  ; 7.451  ; 7.318  ;
+; X5         ; S6          ; 7.191  ; 7.075  ; 7.594  ; 7.470  ;
+; X5         ; S7          ; 7.984  ; 7.869  ; 8.348  ; 8.225  ;
+; X5         ; S8          ; 9.426  ; 9.322  ; 9.790  ; 9.678  ;
+; X5         ; S9          ; 9.295  ; 9.221  ; 9.658  ; 9.576  ;
+; X6         ; Cout        ; 8.823  ;        ;        ; 8.957  ;
+; X6         ; S6          ; 6.960  ; 6.842  ; 7.290  ; 7.201  ;
+; X6         ; S7          ; 7.754  ; 7.639  ; 8.081  ; 7.958  ;
+; X6         ; S8          ; 9.196  ; 9.092  ; 9.523  ; 9.411  ;
+; X6         ; S9          ; 9.065  ; 8.991  ; 9.391  ; 9.309  ;
+; X7         ; Cout        ; 7.339  ;        ;        ; 7.515  ;
+; X7         ; S7          ; 6.297  ; 6.204  ; 6.631  ; 6.534  ;
+; X7         ; S8          ; 7.712  ; 7.608  ; 8.081  ; 7.969  ;
+; X7         ; S9          ; 7.581  ; 7.507  ; 7.949  ; 7.867  ;
+; X8         ; Cout        ; 7.095  ;        ;        ; 7.278  ;
+; X8         ; S8          ; 7.493  ; 7.411  ; 7.833  ; 7.747  ;
+; X8         ; S9          ; 7.337  ; 7.263  ; 7.712  ; 7.630  ;
+; X9         ; Cout        ; 6.882  ;        ;        ; 7.016  ;
+; X9         ; S9          ; 7.122  ; 7.046  ; 7.413  ; 7.366  ;
+; Y0         ; Cout        ; 11.665 ;        ;        ; 11.988 ;
+; Y0         ; S0          ; 7.445  ; 7.311  ; 7.849  ; 7.707  ;
+; Y0         ; S1          ; 7.790  ; 7.708  ; 8.219  ; 8.110  ;
+; Y0         ; S2          ; 8.124  ; 8.003  ; 8.570  ; 8.435  ;
+; Y0         ; S3          ; 9.557  ; 9.474  ; 10.033 ; 9.936  ;
+; Y0         ; S4          ; 9.234  ; 9.121  ; 9.727  ; 9.600  ;
+; Y0         ; S5          ; 9.688  ; 9.595  ; 10.224 ; 10.084 ;
+; Y0         ; S6          ; 9.803  ; 9.687  ; 10.358 ; 10.234 ;
+; Y0         ; S7          ; 10.596 ; 10.481 ; 11.112 ; 10.989 ;
+; Y0         ; S8          ; 12.038 ; 11.934 ; 12.554 ; 12.442 ;
+; Y0         ; S9          ; 11.907 ; 11.833 ; 12.422 ; 12.340 ;
+; Y1         ; Cout        ; 11.474 ;        ;        ; 11.736 ;
+; Y1         ; S1          ; 7.593  ; 7.470  ; 7.933  ; 7.839  ;
+; Y1         ; S2          ; 7.933  ; 7.812  ; 8.318  ; 8.183  ;
+; Y1         ; S3          ; 9.366  ; 9.283  ; 9.781  ; 9.684  ;
+; Y1         ; S4          ; 9.043  ; 8.930  ; 9.475  ; 9.348  ;
+; Y1         ; S5          ; 9.497  ; 9.404  ; 9.972  ; 9.832  ;
+; Y1         ; S6          ; 9.612  ; 9.496  ; 10.106 ; 9.982  ;
+; Y1         ; S7          ; 10.405 ; 10.290 ; 10.860 ; 10.737 ;
+; Y1         ; S8          ; 11.847 ; 11.743 ; 12.302 ; 12.190 ;
+; Y1         ; S9          ; 11.716 ; 11.642 ; 12.170 ; 12.088 ;
+; Y2         ; Cout        ; 10.908 ;        ;        ; 11.155 ;
+; Y2         ; S2          ; 7.359  ; 7.245  ; 7.723  ; 7.551  ;
+; Y2         ; S3          ; 8.800  ; 8.717  ; 9.200  ; 9.103  ;
+; Y2         ; S4          ; 8.477  ; 8.364  ; 8.894  ; 8.767  ;
+; Y2         ; S5          ; 8.931  ; 8.838  ; 9.391  ; 9.251  ;
+; Y2         ; S6          ; 9.046  ; 8.930  ; 9.525  ; 9.401  ;
+; Y2         ; S7          ; 9.839  ; 9.724  ; 10.279 ; 10.156 ;
+; Y2         ; S8          ; 11.281 ; 11.177 ; 11.721 ; 11.609 ;
+; Y2         ; S9          ; 11.150 ; 11.076 ; 11.589 ; 11.507 ;
+; Y3         ; Cout        ; 9.863  ;        ;        ; 10.078 ;
+; Y3         ; S3          ; 7.747  ; 7.638  ; 8.121  ; 8.004  ;
+; Y3         ; S4          ; 7.432  ; 7.319  ; 7.817  ; 7.690  ;
+; Y3         ; S5          ; 7.886  ; 7.793  ; 8.314  ; 8.174  ;
+; Y3         ; S6          ; 8.001  ; 7.885  ; 8.448  ; 8.324  ;
+; Y3         ; S7          ; 8.794  ; 8.679  ; 9.202  ; 9.079  ;
+; Y3         ; S8          ; 10.236 ; 10.132 ; 10.644 ; 10.532 ;
+; Y3         ; S9          ; 10.105 ; 10.031 ; 10.512 ; 10.430 ;
+; Y4         ; Cout        ; 9.890  ;        ;        ; 10.112 ;
+; Y4         ; S4          ; 7.451  ; 7.345  ; 7.837  ; 7.673  ;
+; Y4         ; S5          ; 7.913  ; 7.820  ; 8.348  ; 8.208  ;
+; Y4         ; S6          ; 8.028  ; 7.912  ; 8.482  ; 8.358  ;
+; Y4         ; S7          ; 8.821  ; 8.706  ; 9.236  ; 9.113  ;
+; Y4         ; S8          ; 10.263 ; 10.159 ; 10.678 ; 10.566 ;
+; Y4         ; S9          ; 10.132 ; 10.058 ; 10.546 ; 10.464 ;
+; Y5         ; Cout        ; 8.954  ;        ;        ; 9.070  ;
+; Y5         ; S5          ; 6.961  ; 6.837  ; 7.312  ; 7.180  ;
+; Y5         ; S6          ; 7.092  ; 6.976  ; 7.440  ; 7.316  ;
+; Y5         ; S7          ; 7.885  ; 7.770  ; 8.194  ; 8.071  ;
+; Y5         ; S8          ; 9.327  ; 9.223  ; 9.636  ; 9.524  ;
+; Y5         ; S9          ; 9.196  ; 9.122  ; 9.504  ; 9.422  ;
+; Y6         ; Cout        ; 8.843  ;        ;        ; 8.988  ;
+; Y6         ; S6          ; 6.996  ; 6.919  ; 7.366  ; 7.262  ;
+; Y6         ; S7          ; 7.774  ; 7.659  ; 8.112  ; 7.989  ;
+; Y6         ; S8          ; 9.216  ; 9.112  ; 9.554  ; 9.442  ;
+; Y6         ; S9          ; 9.085  ; 9.011  ; 9.422  ; 9.340  ;
+; Y7         ; Cout        ; 7.292  ;        ;        ; 7.459  ;
+; Y7         ; S7          ; 6.227  ; 6.110  ; 6.555  ; 6.467  ;
+; Y7         ; S8          ; 7.665  ; 7.561  ; 8.025  ; 7.913  ;
+; Y7         ; S9          ; 7.534  ; 7.460  ; 7.893  ; 7.811  ;
+; Y8         ; Cout        ; 6.972  ;        ;        ; 7.136  ;
+; Y8         ; S8          ; 7.336  ; 7.230  ; 7.656  ; 7.579  ;
+; Y8         ; S9          ; 7.214  ; 7.140  ; 7.570  ; 7.488  ;
+; Y9         ; Cout        ; 4.696  ;        ;        ; 4.719  ;
+; Y9         ; S9          ; 4.949  ; 4.915  ; 5.145  ; 5.089  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++--------------------------------------------------------------+
+; Minimum Propagation Delay                                    ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; ENY        ; Cout        ; 4.554  ;        ;        ; 4.567  ;
+; ENY        ; S0          ; 5.598  ; 5.491  ; 5.730  ; 5.594  ;
+; ENY        ; S1          ; 5.734  ; 5.613  ; 5.861  ; 5.768  ;
+; ENY        ; S2          ; 5.202  ; 5.054  ; 5.306  ; 5.186  ;
+; ENY        ; S3          ; 6.184  ; 6.099  ; 6.315  ; 6.202  ;
+; ENY        ; S4          ; 5.310  ; 5.170  ; 5.415  ; 5.303  ;
+; ENY        ; S5          ; 5.264  ; 5.142  ; 5.368  ; 5.273  ;
+; ENY        ; S6          ; 5.195  ; 5.115  ; 5.346  ; 5.226  ;
+; ENY        ; S7          ; 4.071  ; 3.982  ; 4.248  ; 4.147  ;
+; ENY        ; S8          ; 5.206  ; 5.129  ; 5.384  ; 5.295  ;
+; ENY        ; S9          ; 4.811  ; 4.773  ; 5.015  ; 4.928  ;
+; X0         ; Cout        ; 10.887 ;        ;        ; 11.095 ;
+; X0         ; S0          ; 7.395  ; 7.263  ; 7.744  ; 7.638  ;
+; X0         ; S1          ; 7.312  ; 7.228  ; 7.704  ; 7.580  ;
+; X0         ; S2          ; 7.590  ; 7.469  ; 7.991  ; 7.860  ;
+; X0         ; S3          ; 8.932  ; 8.848  ; 9.345  ; 9.232  ;
+; X0         ; S4          ; 8.577  ; 8.464  ; 8.998  ; 8.875  ;
+; X0         ; S5          ; 8.974  ; 8.877  ; 9.409  ; 9.283  ;
+; X0         ; S6          ; 9.094  ; 8.979  ; 9.528  ; 9.407  ;
+; X0         ; S7          ; 9.855  ; 9.741  ; 10.253 ; 10.133 ;
+; X0         ; S8          ; 11.269 ; 11.167 ; 11.667 ; 11.559 ;
+; X0         ; S9          ; 11.145 ; 11.072 ; 11.540 ; 11.461 ;
+; X1         ; Cout        ; 10.694 ;        ;        ; 10.869 ;
+; X1         ; S1          ; 7.114  ; 6.995  ; 7.474  ; 7.349  ;
+; X1         ; S2          ; 7.397  ; 7.276  ; 7.765  ; 7.634  ;
+; X1         ; S3          ; 8.739  ; 8.655  ; 9.119  ; 9.006  ;
+; X1         ; S4          ; 8.384  ; 8.271  ; 8.772  ; 8.649  ;
+; X1         ; S5          ; 8.781  ; 8.684  ; 9.183  ; 9.057  ;
+; X1         ; S6          ; 8.901  ; 8.786  ; 9.302  ; 9.181  ;
+; X1         ; S7          ; 9.662  ; 9.548  ; 10.027 ; 9.907  ;
+; X1         ; S8          ; 11.076 ; 10.974 ; 11.441 ; 11.333 ;
+; X1         ; S9          ; 10.952 ; 10.879 ; 11.314 ; 11.235 ;
+; X2         ; Cout        ; 8.617  ;        ;        ; 8.586  ;
+; X2         ; S2          ; 5.316  ; 5.170  ; 5.481  ; 5.329  ;
+; X2         ; S3          ; 6.662  ; 6.578  ; 6.836  ; 6.723  ;
+; X2         ; S4          ; 6.307  ; 6.194  ; 6.489  ; 6.366  ;
+; X2         ; S5          ; 6.704  ; 6.607  ; 6.900  ; 6.774  ;
+; X2         ; S6          ; 6.824  ; 6.709  ; 7.019  ; 6.898  ;
+; X2         ; S7          ; 7.585  ; 7.471  ; 7.744  ; 7.624  ;
+; X2         ; S8          ; 8.999  ; 8.897  ; 9.158  ; 9.050  ;
+; X2         ; S9          ; 8.875  ; 8.802  ; 9.031  ; 8.952  ;
+; X3         ; Cout        ; 8.236  ;        ;        ; 8.216  ;
+; X3         ; S3          ; 6.278  ; 6.167  ; 6.430  ; 6.347  ;
+; X3         ; S4          ; 5.926  ; 5.813  ; 6.119  ; 5.996  ;
+; X3         ; S5          ; 6.323  ; 6.226  ; 6.530  ; 6.404  ;
+; X3         ; S6          ; 6.443  ; 6.328  ; 6.649  ; 6.528  ;
+; X3         ; S7          ; 7.204  ; 7.090  ; 7.374  ; 7.254  ;
+; X3         ; S8          ; 8.618  ; 8.516  ; 8.788  ; 8.680  ;
+; X3         ; S9          ; 8.494  ; 8.421  ; 8.661  ; 8.582  ;
+; X4         ; Cout        ; 9.070  ;        ;        ; 9.199  ;
+; X4         ; S4          ; 6.762  ; 6.624  ; 7.106  ; 6.962  ;
+; X4         ; S5          ; 7.157  ; 7.060  ; 7.513  ; 7.387  ;
+; X4         ; S6          ; 7.277  ; 7.162  ; 7.632  ; 7.511  ;
+; X4         ; S7          ; 8.038  ; 7.924  ; 8.357  ; 8.237  ;
+; X4         ; S8          ; 9.452  ; 9.350  ; 9.771  ; 9.663  ;
+; X4         ; S9          ; 9.328  ; 9.255  ; 9.644  ; 9.565  ;
+; X5         ; Cout        ; 8.693  ;        ;        ; 8.827  ;
+; X5         ; S5          ; 6.776  ; 6.678  ; 7.139  ; 7.013  ;
+; X5         ; S6          ; 6.900  ; 6.785  ; 7.260  ; 7.139  ;
+; X5         ; S7          ; 7.661  ; 7.547  ; 7.985  ; 7.865  ;
+; X5         ; S8          ; 9.075  ; 8.973  ; 9.399  ; 9.291  ;
+; X5         ; S9          ; 8.951  ; 8.878  ; 9.272  ; 9.193  ;
+; X6         ; Cout        ; 8.513  ;        ;        ; 8.643  ;
+; X6         ; S6          ; 6.718  ; 6.601  ; 7.042  ; 6.953  ;
+; X6         ; S7          ; 7.481  ; 7.367  ; 7.801  ; 7.681  ;
+; X6         ; S8          ; 8.895  ; 8.793  ; 9.215  ; 9.107  ;
+; X6         ; S9          ; 8.771  ; 8.698  ; 9.088  ; 9.009  ;
+; X7         ; Cout        ; 7.057  ;        ;        ; 7.202  ;
+; X7         ; S7          ; 6.026  ; 5.936  ; 6.361  ; 6.263  ;
+; X7         ; S8          ; 7.439  ; 7.337  ; 7.774  ; 7.666  ;
+; X7         ; S9          ; 7.315  ; 7.242  ; 7.647  ; 7.568  ;
+; X8         ; Cout        ; 6.823  ;        ;        ; 6.974  ;
+; X8         ; S8          ; 7.205  ; 7.127  ; 7.544  ; 7.458  ;
+; X8         ; S9          ; 7.081  ; 7.008  ; 7.419  ; 7.340  ;
+; X9         ; Cout        ; 6.648  ;        ;        ; 6.778  ;
+; X9         ; S9          ; 6.904  ; 6.829  ; 7.190  ; 7.143  ;
+; Y0         ; Cout        ; 11.054 ;        ;        ; 11.298 ;
+; Y0         ; S0          ; 7.193  ; 7.061  ; 7.586  ; 7.448  ;
+; Y0         ; S1          ; 7.475  ; 7.391  ; 7.907  ; 7.774  ;
+; Y0         ; S2          ; 7.757  ; 7.636  ; 8.194  ; 8.063  ;
+; Y0         ; S3          ; 9.099  ; 9.015  ; 9.548  ; 9.435  ;
+; Y0         ; S4          ; 8.744  ; 8.631  ; 9.201  ; 9.078  ;
+; Y0         ; S5          ; 9.141  ; 9.044  ; 9.612  ; 9.486  ;
+; Y0         ; S6          ; 9.261  ; 9.146  ; 9.731  ; 9.610  ;
+; Y0         ; S7          ; 10.022 ; 9.908  ; 10.456 ; 10.336 ;
+; Y0         ; S8          ; 11.436 ; 11.334 ; 11.870 ; 11.762 ;
+; Y0         ; S9          ; 11.312 ; 11.239 ; 11.743 ; 11.664 ;
+; Y1         ; Cout        ; 10.901 ;        ;        ; 11.082 ;
+; Y1         ; S1          ; 7.325  ; 7.204  ; 7.659  ; 7.566  ;
+; Y1         ; S2          ; 7.604  ; 7.483  ; 7.978  ; 7.847  ;
+; Y1         ; S3          ; 8.946  ; 8.862  ; 9.332  ; 9.219  ;
+; Y1         ; S4          ; 8.591  ; 8.478  ; 8.985  ; 8.862  ;
+; Y1         ; S5          ; 8.988  ; 8.891  ; 9.396  ; 9.270  ;
+; Y1         ; S6          ; 9.108  ; 8.993  ; 9.515  ; 9.394  ;
+; Y1         ; S7          ; 9.869  ; 9.755  ; 10.240 ; 10.120 ;
+; Y1         ; S8          ; 11.283 ; 11.181 ; 11.654 ; 11.546 ;
+; Y1         ; S9          ; 11.159 ; 11.086 ; 11.527 ; 11.448 ;
+; Y2         ; Cout        ; 10.379 ;        ;        ; 10.521 ;
+; Y2         ; S2          ; 7.065  ; 6.943  ; 7.419  ; 7.287  ;
+; Y2         ; S3          ; 8.424  ; 8.340  ; 8.771  ; 8.658  ;
+; Y2         ; S4          ; 8.069  ; 7.956  ; 8.424  ; 8.301  ;
+; Y2         ; S5          ; 8.466  ; 8.369  ; 8.835  ; 8.709  ;
+; Y2         ; S6          ; 8.586  ; 8.471  ; 8.954  ; 8.833  ;
+; Y2         ; S7          ; 9.347  ; 9.233  ; 9.679  ; 9.559  ;
+; Y2         ; S8          ; 10.761 ; 10.659 ; 11.093 ; 10.985 ;
+; Y2         ; S9          ; 10.637 ; 10.564 ; 10.966 ; 10.887 ;
+; Y3         ; Cout        ; 9.435  ;        ;        ; 9.596  ;
+; Y3         ; S3          ; 7.481  ; 7.372  ; 7.846  ; 7.731  ;
+; Y3         ; S4          ; 7.125  ; 7.012  ; 7.499  ; 7.376  ;
+; Y3         ; S5          ; 7.522  ; 7.425  ; 7.910  ; 7.784  ;
+; Y3         ; S6          ; 7.642  ; 7.527  ; 8.029  ; 7.908  ;
+; Y3         ; S7          ; 8.403  ; 8.289  ; 8.754  ; 8.634  ;
+; Y3         ; S8          ; 9.817  ; 9.715  ; 10.168 ; 10.060 ;
+; Y3         ; S9          ; 9.693  ; 9.620  ; 10.041 ; 9.962  ;
+; Y4         ; Cout        ; 9.478  ;        ;        ; 9.622  ;
+; Y4         ; S4          ; 7.151  ; 7.037  ; 7.527  ; 7.403  ;
+; Y4         ; S5          ; 7.565  ; 7.468  ; 7.936  ; 7.810  ;
+; Y4         ; S6          ; 7.685  ; 7.570  ; 8.055  ; 7.934  ;
+; Y4         ; S7          ; 8.446  ; 8.332  ; 8.780  ; 8.660  ;
+; Y4         ; S8          ; 9.860  ; 9.758  ; 10.194 ; 10.086 ;
+; Y4         ; S9          ; 9.736  ; 9.663  ; 10.067 ; 9.988  ;
+; Y5         ; Cout        ; 8.642  ;        ;        ; 8.757  ;
+; Y5         ; S5          ; 6.724  ; 6.602  ; 7.066  ; 6.938  ;
+; Y5         ; S6          ; 6.849  ; 6.734  ; 7.190  ; 7.069  ;
+; Y5         ; S7          ; 7.610  ; 7.496  ; 7.915  ; 7.795  ;
+; Y5         ; S8          ; 9.024  ; 8.922  ; 9.329  ; 9.221  ;
+; Y5         ; S9          ; 8.900  ; 8.827  ; 9.202  ; 9.123  ;
+; Y6         ; Cout        ; 8.501  ;        ;        ; 8.646  ;
+; Y6         ; S6          ; 6.713  ; 6.633  ; 7.088  ; 6.959  ;
+; Y6         ; S7          ; 7.469  ; 7.355  ; 7.804  ; 7.684  ;
+; Y6         ; S8          ; 8.883  ; 8.781  ; 9.218  ; 9.110  ;
+; Y6         ; S9          ; 8.759  ; 8.686  ; 9.091  ; 9.012  ;
+; Y7         ; Cout        ; 7.042  ;        ;        ; 7.205  ;
+; Y7         ; S7          ; 6.016  ; 5.900  ; 6.337  ; 6.249  ;
+; Y7         ; S8          ; 7.424  ; 7.322  ; 7.777  ; 7.669  ;
+; Y7         ; S9          ; 7.300  ; 7.227  ; 7.650  ; 7.571  ;
+; Y8         ; Cout        ; 6.736  ;        ;        ; 6.895  ;
+; Y8         ; S8          ; 7.109  ; 7.005  ; 7.424  ; 7.348  ;
+; Y8         ; S9          ; 6.994  ; 6.921  ; 7.340  ; 7.261  ;
+; Y9         ; Cout        ; 4.526  ;        ;        ; 4.546  ;
+; Y9         ; S9          ; 4.785  ; 4.747  ; 4.991  ; 4.913  ;
++------------+-------------+--------+--------+--------+--------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; ENY        ; Cout        ; 6.167 ;       ;       ; 6.797 ;
+; ENY        ; S0          ; 3.841 ; 3.884 ; 4.127 ; 4.142 ;
+; ENY        ; S1          ; 3.925 ; 3.996 ; 4.244 ; 4.296 ;
+; ENY        ; S2          ; 4.100 ; 4.160 ; 4.452 ; 4.499 ;
+; ENY        ; S3          ; 5.048 ; 5.152 ; 5.437 ; 5.528 ;
+; ENY        ; S4          ; 4.836 ; 4.856 ; 5.256 ; 5.263 ;
+; ENY        ; S5          ; 5.055 ; 5.111 ; 5.522 ; 5.538 ;
+; ENY        ; S6          ; 5.124 ; 5.155 ; 5.608 ; 5.632 ;
+; ENY        ; S7          ; 5.566 ; 5.556 ; 6.150 ; 6.133 ;
+; ENY        ; S8          ; 6.605 ; 6.636 ; 7.204 ; 7.228 ;
+; ENY        ; S9          ; 6.527 ; 6.536 ; 7.142 ; 7.144 ;
+; X0         ; Cout        ; 7.200 ;       ;       ; 8.159 ;
+; X0         ; S0          ; 5.041 ; 5.064 ; 5.653 ; 5.695 ;
+; X0         ; S1          ; 4.961 ; 5.032 ; 5.606 ; 5.661 ;
+; X0         ; S2          ; 5.133 ; 5.193 ; 5.814 ; 5.861 ;
+; X0         ; S3          ; 6.081 ; 6.185 ; 6.799 ; 6.890 ;
+; X0         ; S4          ; 5.869 ; 5.889 ; 6.618 ; 6.625 ;
+; X0         ; S5          ; 6.088 ; 6.144 ; 6.884 ; 6.900 ;
+; X0         ; S6          ; 6.157 ; 6.188 ; 6.970 ; 6.994 ;
+; X0         ; S7          ; 6.599 ; 6.589 ; 7.512 ; 7.495 ;
+; X0         ; S8          ; 7.638 ; 7.669 ; 8.566 ; 8.590 ;
+; X0         ; S9          ; 7.560 ; 7.569 ; 8.504 ; 8.506 ;
+; X1         ; Cout        ; 7.050 ;       ;       ; 7.983 ;
+; X1         ; S1          ; 4.800 ; 4.854 ; 5.422 ; 5.469 ;
+; X1         ; S2          ; 4.983 ; 5.043 ; 5.638 ; 5.685 ;
+; X1         ; S3          ; 5.931 ; 6.035 ; 6.623 ; 6.714 ;
+; X1         ; S4          ; 5.719 ; 5.739 ; 6.442 ; 6.449 ;
+; X1         ; S5          ; 5.938 ; 5.994 ; 6.708 ; 6.724 ;
+; X1         ; S6          ; 6.007 ; 6.038 ; 6.794 ; 6.818 ;
+; X1         ; S7          ; 6.449 ; 6.439 ; 7.336 ; 7.319 ;
+; X1         ; S8          ; 7.488 ; 7.519 ; 8.390 ; 8.414 ;
+; X1         ; S9          ; 7.410 ; 7.419 ; 8.328 ; 8.330 ;
+; X2         ; Cout        ; 5.666 ;       ;       ; 6.226 ;
+; X2         ; S2          ; 3.583 ; 3.632 ; 3.870 ; 3.912 ;
+; X2         ; S3          ; 4.547 ; 4.651 ; 4.866 ; 4.957 ;
+; X2         ; S4          ; 4.335 ; 4.355 ; 4.685 ; 4.692 ;
+; X2         ; S5          ; 4.554 ; 4.610 ; 4.951 ; 4.967 ;
+; X2         ; S6          ; 4.623 ; 4.654 ; 5.037 ; 5.061 ;
+; X2         ; S7          ; 5.065 ; 5.055 ; 5.579 ; 5.562 ;
+; X2         ; S8          ; 6.104 ; 6.135 ; 6.633 ; 6.657 ;
+; X2         ; S9          ; 6.026 ; 6.035 ; 6.571 ; 6.573 ;
+; X3         ; Cout        ; 5.404 ;       ;       ; 5.949 ;
+; X3         ; S3          ; 4.276 ; 4.366 ; 4.557 ; 4.665 ;
+; X3         ; S4          ; 4.073 ; 4.093 ; 4.408 ; 4.415 ;
+; X3         ; S5          ; 4.292 ; 4.348 ; 4.674 ; 4.690 ;
+; X3         ; S6          ; 4.361 ; 4.392 ; 4.760 ; 4.784 ;
+; X3         ; S7          ; 4.803 ; 4.793 ; 5.302 ; 5.285 ;
+; X3         ; S8          ; 5.842 ; 5.873 ; 6.356 ; 6.380 ;
+; X3         ; S9          ; 5.764 ; 5.773 ; 6.294 ; 6.296 ;
+; X4         ; Cout        ; 5.963 ;       ;       ; 6.751 ;
+; X4         ; S4          ; 4.621 ; 4.630 ; 5.205 ; 5.207 ;
+; X4         ; S5          ; 4.851 ; 4.907 ; 5.476 ; 5.492 ;
+; X4         ; S6          ; 4.920 ; 4.951 ; 5.562 ; 5.586 ;
+; X4         ; S7          ; 5.362 ; 5.352 ; 6.104 ; 6.087 ;
+; X4         ; S8          ; 6.401 ; 6.432 ; 7.158 ; 7.182 ;
+; X4         ; S9          ; 6.323 ; 6.332 ; 7.096 ; 7.098 ;
+; X5         ; Cout        ; 5.738 ;       ;       ; 6.502 ;
+; X5         ; S5          ; 4.624 ; 4.679 ; 5.220 ; 5.243 ;
+; X5         ; S6          ; 4.695 ; 4.726 ; 5.313 ; 5.337 ;
+; X5         ; S7          ; 5.137 ; 5.127 ; 5.855 ; 5.838 ;
+; X5         ; S8          ; 6.176 ; 6.207 ; 6.909 ; 6.933 ;
+; X5         ; S9          ; 6.098 ; 6.107 ; 6.847 ; 6.849 ;
+; X6         ; Cout        ; 5.591 ;       ;       ; 6.335 ;
+; X6         ; S6          ; 4.546 ; 4.574 ; 5.123 ; 5.169 ;
+; X6         ; S7          ; 4.990 ; 4.980 ; 5.688 ; 5.671 ;
+; X6         ; S8          ; 6.029 ; 6.060 ; 6.742 ; 6.766 ;
+; X6         ; S9          ; 5.951 ; 5.960 ; 6.680 ; 6.682 ;
+; X7         ; Cout        ; 4.727 ;       ;       ; 5.355 ;
+; X7         ; S7          ; 4.140 ; 4.140 ; 4.711 ; 4.702 ;
+; X7         ; S8          ; 5.165 ; 5.196 ; 5.762 ; 5.786 ;
+; X7         ; S9          ; 5.087 ; 5.096 ; 5.700 ; 5.702 ;
+; X8         ; Cout        ; 4.593 ;       ;       ; 5.212 ;
+; X8         ; S8          ; 5.042 ; 5.083 ; 5.620 ; 5.652 ;
+; X8         ; S9          ; 4.953 ; 4.962 ; 5.557 ; 5.559 ;
+; X9         ; Cout        ; 4.450 ;       ;       ; 5.041 ;
+; X9         ; S9          ; 4.809 ; 4.815 ; 5.362 ; 5.386 ;
+; Y0         ; Cout        ; 7.311 ;       ;       ; 8.290 ;
+; Y0         ; S0          ; 4.925 ; 4.951 ; 5.554 ; 5.573 ;
+; Y0         ; S1          ; 5.069 ; 5.140 ; 5.737 ; 5.789 ;
+; Y0         ; S2          ; 5.244 ; 5.304 ; 5.945 ; 5.992 ;
+; Y0         ; S3          ; 6.192 ; 6.296 ; 6.930 ; 7.021 ;
+; Y0         ; S4          ; 5.980 ; 6.000 ; 6.749 ; 6.756 ;
+; Y0         ; S5          ; 6.199 ; 6.255 ; 7.015 ; 7.031 ;
+; Y0         ; S6          ; 6.268 ; 6.299 ; 7.101 ; 7.125 ;
+; Y0         ; S7          ; 6.710 ; 6.700 ; 7.643 ; 7.626 ;
+; Y0         ; S8          ; 7.749 ; 7.780 ; 8.697 ; 8.721 ;
+; Y0         ; S9          ; 7.671 ; 7.680 ; 8.635 ; 8.637 ;
+; Y1         ; Cout        ; 7.173 ;       ;       ; 8.113 ;
+; Y1         ; S1          ; 4.927 ; 4.978 ; 5.534 ; 5.603 ;
+; Y1         ; S2          ; 5.106 ; 5.166 ; 5.768 ; 5.815 ;
+; Y1         ; S3          ; 6.054 ; 6.158 ; 6.753 ; 6.844 ;
+; Y1         ; S4          ; 5.842 ; 5.862 ; 6.572 ; 6.579 ;
+; Y1         ; S5          ; 6.061 ; 6.117 ; 6.838 ; 6.854 ;
+; Y1         ; S6          ; 6.130 ; 6.161 ; 6.924 ; 6.948 ;
+; Y1         ; S7          ; 6.572 ; 6.562 ; 7.466 ; 7.449 ;
+; Y1         ; S8          ; 7.611 ; 7.642 ; 8.520 ; 8.544 ;
+; Y1         ; S9          ; 7.533 ; 7.542 ; 8.458 ; 8.460 ;
+; Y2         ; Cout        ; 6.864 ;       ;       ; 7.757 ;
+; Y2         ; S2          ; 4.789 ; 4.855 ; 5.404 ; 5.429 ;
+; Y2         ; S3          ; 5.745 ; 5.849 ; 6.397 ; 6.488 ;
+; Y2         ; S4          ; 5.533 ; 5.553 ; 6.216 ; 6.223 ;
+; Y2         ; S5          ; 5.752 ; 5.808 ; 6.482 ; 6.498 ;
+; Y2         ; S6          ; 5.821 ; 5.852 ; 6.568 ; 6.592 ;
+; Y2         ; S7          ; 6.263 ; 6.253 ; 7.110 ; 7.093 ;
+; Y2         ; S8          ; 7.302 ; 7.333 ; 8.164 ; 8.188 ;
+; Y2         ; S9          ; 7.224 ; 7.233 ; 8.102 ; 8.104 ;
+; Y3         ; Cout        ; 6.224 ;       ;       ; 7.059 ;
+; Y3         ; S3          ; 5.100 ; 5.193 ; 5.693 ; 5.779 ;
+; Y3         ; S4          ; 4.893 ; 4.913 ; 5.518 ; 5.525 ;
+; Y3         ; S5          ; 5.112 ; 5.168 ; 5.784 ; 5.800 ;
+; Y3         ; S6          ; 5.181 ; 5.212 ; 5.870 ; 5.894 ;
+; Y3         ; S7          ; 5.623 ; 5.613 ; 6.412 ; 6.395 ;
+; Y3         ; S8          ; 6.662 ; 6.693 ; 7.466 ; 7.490 ;
+; Y3         ; S9          ; 6.584 ; 6.593 ; 7.404 ; 7.406 ;
+; Y4         ; Cout        ; 6.250 ;       ;       ; 7.100 ;
+; Y4         ; S4          ; 4.911 ; 4.937 ; 5.552 ; 5.537 ;
+; Y4         ; S5          ; 5.138 ; 5.194 ; 5.825 ; 5.841 ;
+; Y4         ; S6          ; 5.207 ; 5.238 ; 5.911 ; 5.935 ;
+; Y4         ; S7          ; 5.649 ; 5.639 ; 6.453 ; 6.436 ;
+; Y4         ; S8          ; 6.688 ; 6.719 ; 7.507 ; 7.531 ;
+; Y4         ; S9          ; 6.610 ; 6.619 ; 7.445 ; 7.447 ;
+; Y5         ; Cout        ; 5.672 ;       ;       ; 6.415 ;
+; Y5         ; S5          ; 4.551 ; 4.592 ; 5.134 ; 5.168 ;
+; Y5         ; S6          ; 4.629 ; 4.660 ; 5.226 ; 5.250 ;
+; Y5         ; S7          ; 5.071 ; 5.061 ; 5.768 ; 5.751 ;
+; Y5         ; S8          ; 6.110 ; 6.141 ; 6.822 ; 6.846 ;
+; Y5         ; S9          ; 6.032 ; 6.041 ; 6.760 ; 6.762 ;
+; Y6         ; Cout        ; 5.624 ;       ;       ; 6.371 ;
+; Y6         ; S6          ; 4.593 ; 4.641 ; 5.195 ; 5.224 ;
+; Y6         ; S7          ; 5.023 ; 5.013 ; 5.724 ; 5.707 ;
+; Y6         ; S8          ; 6.062 ; 6.093 ; 6.778 ; 6.802 ;
+; Y6         ; S9          ; 5.984 ; 5.993 ; 6.716 ; 6.718 ;
+; Y7         ; Cout        ; 4.696 ;       ;       ; 5.320 ;
+; Y7         ; S7          ; 4.100 ; 4.087 ; 4.657 ; 4.662 ;
+; Y7         ; S8          ; 5.134 ; 5.165 ; 5.727 ; 5.751 ;
+; Y7         ; S9          ; 5.056 ; 5.065 ; 5.665 ; 5.667 ;
+; Y8         ; Cout        ; 4.508 ;       ;       ; 5.116 ;
+; Y8         ; S8          ; 4.936 ; 4.964 ; 5.490 ; 5.536 ;
+; Y8         ; S9          ; 4.868 ; 4.877 ; 5.461 ; 5.463 ;
+; Y9         ; Cout        ; 3.019 ;       ;       ; 3.401 ;
+; Y9         ; S9          ; 3.388 ; 3.414 ; 3.750 ; 3.760 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; ENY        ; Cout        ; 2.926 ;       ;       ; 3.305 ;
+; ENY        ; S0          ; 3.713 ; 3.743 ; 3.995 ; 4.008 ;
+; ENY        ; S1          ; 3.720 ; 3.767 ; 4.006 ; 4.073 ;
+; ENY        ; S2          ; 3.384 ; 3.426 ; 3.646 ; 3.708 ;
+; ENY        ; S3          ; 4.070 ; 4.163 ; 4.352 ; 4.429 ;
+; ENY        ; S4          ; 3.522 ; 3.524 ; 3.785 ; 3.807 ;
+; ENY        ; S5          ; 3.442 ; 3.477 ; 3.704 ; 3.758 ;
+; ENY        ; S6          ; 3.415 ; 3.461 ; 3.711 ; 3.729 ;
+; ENY        ; S7          ; 2.664 ; 2.661 ; 3.012 ; 3.008 ;
+; ENY        ; S8          ; 3.523 ; 3.560 ; 3.871 ; 3.907 ;
+; ENY        ; S9          ; 3.294 ; 3.319 ; 3.665 ; 3.657 ;
+; X0         ; Cout        ; 6.819 ;       ;       ; 7.702 ;
+; X0         ; S0          ; 4.868 ; 4.888 ; 5.470 ; 5.509 ;
+; X0         ; S1          ; 4.757 ; 4.825 ; 5.401 ; 5.441 ;
+; X0         ; S2          ; 4.900 ; 4.954 ; 5.562 ; 5.616 ;
+; X0         ; S3          ; 5.790 ; 5.885 ; 6.475 ; 6.554 ;
+; X0         ; S4          ; 5.559 ; 5.573 ; 6.266 ; 6.280 ;
+; X0         ; S5          ; 5.745 ; 5.791 ; 6.475 ; 6.505 ;
+; X0         ; S6          ; 5.815 ; 5.845 ; 6.556 ; 6.579 ;
+; X0         ; S7          ; 6.241 ; 6.231 ; 7.079 ; 7.062 ;
+; X0         ; S8          ; 7.263 ; 7.293 ; 8.116 ; 8.139 ;
+; X0         ; S9          ; 7.189 ; 7.198 ; 8.056 ; 8.058 ;
+; X1         ; Cout        ; 6.697 ;       ;       ; 7.553 ;
+; X1         ; S1          ; 4.631 ; 4.683 ; 5.242 ; 5.287 ;
+; X1         ; S2          ; 4.778 ; 4.832 ; 5.413 ; 5.467 ;
+; X1         ; S3          ; 5.668 ; 5.763 ; 6.326 ; 6.405 ;
+; X1         ; S4          ; 5.437 ; 5.451 ; 6.117 ; 6.131 ;
+; X1         ; S5          ; 5.623 ; 5.669 ; 6.326 ; 6.356 ;
+; X1         ; S6          ; 5.693 ; 5.723 ; 6.407 ; 6.430 ;
+; X1         ; S7          ; 6.119 ; 6.109 ; 6.930 ; 6.913 ;
+; X1         ; S8          ; 7.141 ; 7.171 ; 7.967 ; 7.990 ;
+; X1         ; S9          ; 7.067 ; 7.076 ; 7.907 ; 7.909 ;
+; X2         ; Cout        ; 5.393 ;       ;       ; 5.906 ;
+; X2         ; S2          ; 3.471 ; 3.518 ; 3.761 ; 3.801 ;
+; X2         ; S3          ; 4.364 ; 4.459 ; 4.679 ; 4.758 ;
+; X2         ; S4          ; 4.133 ; 4.147 ; 4.470 ; 4.484 ;
+; X2         ; S5          ; 4.319 ; 4.365 ; 4.679 ; 4.709 ;
+; X2         ; S6          ; 4.389 ; 4.419 ; 4.760 ; 4.783 ;
+; X2         ; S7          ; 4.815 ; 4.805 ; 5.283 ; 5.266 ;
+; X2         ; S8          ; 5.837 ; 5.867 ; 6.320 ; 6.343 ;
+; X2         ; S9          ; 5.763 ; 5.772 ; 6.260 ; 6.262 ;
+; X3         ; Cout        ; 5.169 ;       ;       ; 5.674 ;
+; X3         ; S3          ; 4.137 ; 4.220 ; 4.420 ; 4.523 ;
+; X3         ; S4          ; 3.909 ; 3.923 ; 4.238 ; 4.252 ;
+; X3         ; S5          ; 4.095 ; 4.141 ; 4.447 ; 4.477 ;
+; X3         ; S6          ; 4.165 ; 4.195 ; 4.528 ; 4.551 ;
+; X3         ; S7          ; 4.591 ; 4.581 ; 5.051 ; 5.034 ;
+; X3         ; S8          ; 5.613 ; 5.643 ; 6.088 ; 6.111 ;
+; X3         ; S9          ; 5.539 ; 5.548 ; 6.028 ; 6.030 ;
+; X4         ; Cout        ; 5.722 ;       ;       ; 6.475 ;
+; X4         ; S4          ; 4.465 ; 4.472 ; 5.040 ; 5.040 ;
+; X4         ; S5          ; 4.648 ; 4.694 ; 5.248 ; 5.278 ;
+; X4         ; S6          ; 4.718 ; 4.748 ; 5.329 ; 5.352 ;
+; X4         ; S7          ; 5.144 ; 5.134 ; 5.852 ; 5.835 ;
+; X4         ; S8          ; 6.166 ; 6.196 ; 6.889 ; 6.912 ;
+; X4         ; S9          ; 6.092 ; 6.101 ; 6.829 ; 6.831 ;
+; X5         ; Cout        ; 5.504 ;       ;       ; 6.238 ;
+; X5         ; S5          ; 4.428 ; 4.472 ; 5.011 ; 5.039 ;
+; X5         ; S6          ; 4.500 ; 4.530 ; 5.092 ; 5.115 ;
+; X5         ; S7          ; 4.926 ; 4.916 ; 5.615 ; 5.598 ;
+; X5         ; S8          ; 5.948 ; 5.978 ; 6.652 ; 6.675 ;
+; X5         ; S9          ; 5.874 ; 5.883 ; 6.592 ; 6.594 ;
+; X6         ; Cout        ; 5.392 ;       ;       ; 6.124 ;
+; X6         ; S6          ; 4.387 ; 4.412 ; 4.954 ; 4.999 ;
+; X6         ; S7          ; 4.814 ; 4.804 ; 5.501 ; 5.484 ;
+; X6         ; S8          ; 5.836 ; 5.866 ; 6.538 ; 6.561 ;
+; X6         ; S9          ; 5.762 ; 5.771 ; 6.478 ; 6.480 ;
+; X7         ; Cout        ; 4.541 ;       ;       ; 5.147 ;
+; X7         ; S7          ; 3.964 ; 3.959 ; 4.528 ; 4.522 ;
+; X7         ; S8          ; 4.985 ; 5.015 ; 5.561 ; 5.584 ;
+; X7         ; S9          ; 4.911 ; 4.920 ; 5.501 ; 5.503 ;
+; X8         ; Cout        ; 4.413 ;       ;       ; 5.011 ;
+; X8         ; S8          ; 4.856 ; 4.891 ; 5.426 ; 5.460 ;
+; X8         ; S9          ; 4.783 ; 4.792 ; 5.365 ; 5.367 ;
+; X9         ; Cout        ; 4.296 ;       ;       ; 4.880 ;
+; X9         ; S9          ; 4.665 ; 4.669 ; 5.210 ; 5.234 ;
+; Y0         ; Cout        ; 6.926 ;       ;       ; 7.832 ;
+; Y0         ; S0          ; 4.756 ; 4.780 ; 5.376 ; 5.393 ;
+; Y0         ; S1          ; 4.860 ; 4.928 ; 5.528 ; 5.563 ;
+; Y0         ; S2          ; 5.007 ; 5.061 ; 5.692 ; 5.746 ;
+; Y0         ; S3          ; 5.897 ; 5.992 ; 6.605 ; 6.684 ;
+; Y0         ; S4          ; 5.666 ; 5.680 ; 6.396 ; 6.410 ;
+; Y0         ; S5          ; 5.852 ; 5.898 ; 6.605 ; 6.635 ;
+; Y0         ; S6          ; 5.922 ; 5.952 ; 6.686 ; 6.709 ;
+; Y0         ; S7          ; 6.348 ; 6.338 ; 7.209 ; 7.192 ;
+; Y0         ; S8          ; 7.370 ; 7.400 ; 8.246 ; 8.269 ;
+; Y0         ; S9          ; 7.296 ; 7.305 ; 8.186 ; 8.188 ;
+; Y1         ; Cout        ; 6.814 ;       ;       ; 7.677 ;
+; Y1         ; S1          ; 4.751 ; 4.798 ; 5.348 ; 5.415 ;
+; Y1         ; S2          ; 4.895 ; 4.949 ; 5.537 ; 5.591 ;
+; Y1         ; S3          ; 5.785 ; 5.880 ; 6.450 ; 6.529 ;
+; Y1         ; S4          ; 5.554 ; 5.568 ; 6.241 ; 6.255 ;
+; Y1         ; S5          ; 5.740 ; 5.786 ; 6.450 ; 6.480 ;
+; Y1         ; S6          ; 5.810 ; 5.840 ; 6.531 ; 6.554 ;
+; Y1         ; S7          ; 6.236 ; 6.226 ; 7.054 ; 7.037 ;
+; Y1         ; S8          ; 7.258 ; 7.288 ; 8.091 ; 8.114 ;
+; Y1         ; S9          ; 7.184 ; 7.193 ; 8.031 ; 8.033 ;
+; Y2         ; Cout        ; 6.527 ;       ;       ; 7.336 ;
+; Y2         ; S2          ; 4.598 ; 4.650 ; 5.198 ; 5.247 ;
+; Y2         ; S3          ; 5.498 ; 5.593 ; 6.109 ; 6.188 ;
+; Y2         ; S4          ; 5.267 ; 5.281 ; 5.900 ; 5.914 ;
+; Y2         ; S5          ; 5.453 ; 5.499 ; 6.109 ; 6.139 ;
+; Y2         ; S6          ; 5.523 ; 5.553 ; 6.190 ; 6.213 ;
+; Y2         ; S7          ; 5.949 ; 5.939 ; 6.713 ; 6.696 ;
+; Y2         ; S8          ; 6.971 ; 7.001 ; 7.750 ; 7.773 ;
+; Y2         ; S9          ; 6.897 ; 6.906 ; 7.690 ; 7.692 ;
+; Y3         ; Cout        ; 5.951 ;       ;       ; 6.736 ;
+; Y3         ; S3          ; 4.923 ; 5.011 ; 5.508 ; 5.589 ;
+; Y3         ; S4          ; 4.691 ; 4.705 ; 5.300 ; 5.314 ;
+; Y3         ; S5          ; 4.877 ; 4.923 ; 5.509 ; 5.539 ;
+; Y3         ; S6          ; 4.947 ; 4.977 ; 5.590 ; 5.613 ;
+; Y3         ; S7          ; 5.373 ; 5.363 ; 6.113 ; 6.096 ;
+; Y3         ; S8          ; 6.395 ; 6.425 ; 7.150 ; 7.173 ;
+; Y3         ; S9          ; 6.321 ; 6.330 ; 7.090 ; 7.092 ;
+; Y4         ; Cout        ; 5.983 ;       ;       ; 6.776 ;
+; Y4         ; S4          ; 4.715 ; 4.727 ; 5.342 ; 5.351 ;
+; Y4         ; S5          ; 4.909 ; 4.955 ; 5.549 ; 5.579 ;
+; Y4         ; S6          ; 4.979 ; 5.009 ; 5.630 ; 5.653 ;
+; Y4         ; S7          ; 5.405 ; 5.395 ; 6.153 ; 6.136 ;
+; Y4         ; S8          ; 6.427 ; 6.457 ; 7.190 ; 7.213 ;
+; Y4         ; S9          ; 6.353 ; 6.362 ; 7.130 ; 7.132 ;
+; Y5         ; Cout        ; 5.471 ;       ;       ; 6.201 ;
+; Y5         ; S5          ; 4.393 ; 4.432 ; 4.968 ; 5.000 ;
+; Y5         ; S6          ; 4.467 ; 4.497 ; 5.055 ; 5.078 ;
+; Y5         ; S7          ; 4.893 ; 4.883 ; 5.578 ; 5.561 ;
+; Y5         ; S8          ; 5.915 ; 5.945 ; 6.615 ; 6.638 ;
+; Y5         ; S9          ; 5.841 ; 5.850 ; 6.555 ; 6.557 ;
+; Y6         ; Cout        ; 5.403 ;       ;       ; 6.141 ;
+; Y6         ; S6          ; 4.404 ; 4.450 ; 5.007 ; 5.020 ;
+; Y6         ; S7          ; 4.825 ; 4.815 ; 5.518 ; 5.501 ;
+; Y6         ; S8          ; 5.847 ; 5.877 ; 6.555 ; 6.578 ;
+; Y6         ; S9          ; 5.773 ; 5.782 ; 6.495 ; 6.497 ;
+; Y7         ; Cout        ; 4.533 ;       ;       ; 5.148 ;
+; Y7         ; S7          ; 3.960 ; 3.945 ; 4.509 ; 4.514 ;
+; Y7         ; S8          ; 4.977 ; 5.007 ; 5.562 ; 5.585 ;
+; Y7         ; S9          ; 4.903 ; 4.912 ; 5.502 ; 5.504 ;
+; Y8         ; Cout        ; 4.353 ;       ;       ; 4.952 ;
+; Y8         ; S8          ; 4.788 ; 4.813 ; 5.334 ; 5.379 ;
+; Y8         ; S9          ; 4.723 ; 4.732 ; 5.306 ; 5.308 ;
+; Y9         ; Cout        ; 2.906 ;       ;       ; 3.291 ;
+; Y9         ; S9          ; 3.278 ; 3.303 ; 3.650 ; 3.647 ;
++------------+-------------+-------+-------+-------+-------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------+
+; Propagation Delay                                            ;
++------------+-------------+--------+--------+--------+--------+
+; Input Port ; Output Port ; RR     ; RF     ; FR     ; FF     ;
++------------+-------------+--------+--------+--------+--------+
+; ENY        ; Cout        ; 10.944 ;        ;        ; 11.182 ;
+; ENY        ; S0          ; 6.434  ; 6.385  ; 6.552  ; 6.462  ;
+; ENY        ; S1          ; 6.742  ; 6.661  ; 6.899  ; 6.793  ;
+; ENY        ; S2          ; 7.083  ; 6.997  ; 7.276  ; 7.176  ;
+; ENY        ; S3          ; 8.653  ; 8.639  ; 8.891  ; 8.863  ;
+; ENY        ; S4          ; 8.304  ; 8.235  ; 8.578  ; 8.495  ;
+; ENY        ; S5          ; 8.829  ; 8.747  ; 9.167  ; 9.028  ;
+; ENY        ; S6          ; 8.958  ; 8.841  ; 9.320  ; 9.194  ;
+; ENY        ; S7          ; 9.811  ; 9.686  ; 10.190 ; 10.056 ;
+; ENY        ; S8          ; 11.429 ; 11.338 ; 11.816 ; 11.716 ;
+; ENY        ; S9          ; 11.292 ; 11.223 ; 11.686 ; 11.608 ;
+; X0         ; Cout        ; 12.785 ;        ;        ; 13.371 ;
+; X0         ; S0          ; 8.593  ; 8.507  ; 9.044  ; 8.991  ;
+; X0         ; S1          ; 8.587  ; 8.506  ; 9.079  ; 8.980  ;
+; X0         ; S2          ; 8.924  ; 8.838  ; 9.465  ; 9.365  ;
+; X0         ; S3          ; 10.494 ; 10.480 ; 11.080 ; 11.052 ;
+; X0         ; S4          ; 10.145 ; 10.076 ; 10.767 ; 10.684 ;
+; X0         ; S5          ; 10.670 ; 10.588 ; 11.356 ; 11.217 ;
+; X0         ; S6          ; 10.799 ; 10.682 ; 11.509 ; 11.383 ;
+; X0         ; S7          ; 11.652 ; 11.527 ; 12.379 ; 12.245 ;
+; X0         ; S8          ; 13.270 ; 13.179 ; 14.005 ; 13.905 ;
+; X0         ; S9          ; 13.133 ; 13.064 ; 13.875 ; 13.797 ;
+; X1         ; Cout        ; 12.518 ;        ;        ; 13.065 ;
+; X1         ; S1          ; 8.303  ; 8.183  ; 8.778  ; 8.649  ;
+; X1         ; S2          ; 8.657  ; 8.571  ; 9.159  ; 9.059  ;
+; X1         ; S3          ; 10.227 ; 10.213 ; 10.774 ; 10.746 ;
+; X1         ; S4          ; 9.878  ; 9.809  ; 10.461 ; 10.378 ;
+; X1         ; S5          ; 10.403 ; 10.321 ; 11.050 ; 10.911 ;
+; X1         ; S6          ; 10.532 ; 10.415 ; 11.203 ; 11.077 ;
+; X1         ; S7          ; 11.385 ; 11.260 ; 12.073 ; 11.939 ;
+; X1         ; S8          ; 13.003 ; 12.912 ; 13.699 ; 13.599 ;
+; X1         ; S9          ; 12.866 ; 12.797 ; 13.569 ; 13.491 ;
+; X2         ; Cout        ; 9.971  ;        ;        ; 10.145 ;
+; X2         ; S2          ; 6.084  ; 5.970  ; 6.232  ; 6.109  ;
+; X2         ; S3          ; 7.680  ; 7.666  ; 7.854  ; 7.826  ;
+; X2         ; S4          ; 7.331  ; 7.262  ; 7.541  ; 7.458  ;
+; X2         ; S5          ; 7.856  ; 7.774  ; 8.130  ; 7.991  ;
+; X2         ; S6          ; 7.985  ; 7.868  ; 8.283  ; 8.157  ;
+; X2         ; S7          ; 8.838  ; 8.713  ; 9.153  ; 9.019  ;
+; X2         ; S8          ; 10.456 ; 10.365 ; 10.779 ; 10.679 ;
+; X2         ; S9          ; 10.319 ; 10.250 ; 10.649 ; 10.571 ;
+; X3         ; Cout        ; 9.487  ;        ;        ; 9.659  ;
+; X3         ; S3          ; 7.182  ; 7.138  ; 7.324  ; 7.312  ;
+; X3         ; S4          ; 6.847  ; 6.778  ; 7.055  ; 6.972  ;
+; X3         ; S5          ; 7.372  ; 7.290  ; 7.644  ; 7.505  ;
+; X3         ; S6          ; 7.501  ; 7.384  ; 7.797  ; 7.671  ;
+; X3         ; S7          ; 8.354  ; 8.229  ; 8.667  ; 8.533  ;
+; X3         ; S8          ; 9.972  ; 9.881  ; 10.293 ; 10.193 ;
+; X3         ; S9          ; 9.835  ; 9.766  ; 10.163 ; 10.085 ;
+; X4         ; Cout        ; 10.527 ;        ;        ; 10.918 ;
+; X4         ; S4          ; 7.866  ; 7.769  ; 8.314  ; 8.208  ;
+; X4         ; S5          ; 8.412  ; 8.330  ; 8.903  ; 8.764  ;
+; X4         ; S6          ; 8.541  ; 8.424  ; 9.056  ; 8.930  ;
+; X4         ; S7          ; 9.394  ; 9.269  ; 9.926  ; 9.792  ;
+; X4         ; S8          ; 11.012 ; 10.921 ; 11.552 ; 11.452 ;
+; X4         ; S9          ; 10.875 ; 10.806 ; 11.422 ; 11.344 ;
+; X5         ; Cout        ; 10.115 ;        ;        ; 10.488 ;
+; X5         ; S5          ; 8.000  ; 7.915  ; 8.461  ; 8.332  ;
+; X5         ; S6          ; 8.129  ; 8.012  ; 8.626  ; 8.500  ;
+; X5         ; S7          ; 8.982  ; 8.857  ; 9.496  ; 9.362  ;
+; X5         ; S8          ; 10.600 ; 10.509 ; 11.122 ; 11.022 ;
+; X5         ; S9          ; 10.463 ; 10.394 ; 10.992 ; 10.914 ;
+; X6         ; Cout        ; 9.844  ;        ;        ; 10.186 ;
+; X6         ; S6          ; 7.857  ; 7.738  ; 8.283  ; 8.196  ;
+; X6         ; S7          ; 8.711  ; 8.586  ; 9.194  ; 9.060  ;
+; X6         ; S8          ; 10.329 ; 10.238 ; 10.820 ; 10.720 ;
+; X6         ; S9          ; 10.192 ; 10.123 ; 10.690 ; 10.612 ;
+; X7         ; Cout        ; 8.257  ;        ;        ; 8.571  ;
+; X7         ; S7          ; 7.151  ; 7.050  ; 7.569  ; 7.465  ;
+; X7         ; S8          ; 8.742  ; 8.651  ; 9.205  ; 9.105  ;
+; X7         ; S9          ; 8.605  ; 8.536  ; 9.075  ; 8.997  ;
+; X8         ; Cout        ; 7.986  ;        ;        ; 8.302  ;
+; X8         ; S8          ; 8.497  ; 8.430  ; 8.924  ; 8.854  ;
+; X8         ; S9          ; 8.334  ; 8.265  ; 8.806  ; 8.728  ;
+; X9         ; Cout        ; 7.751  ;        ;        ; 8.004  ;
+; X9         ; S9          ; 8.097  ; 8.026  ; 8.467  ; 8.428  ;
+; Y0         ; Cout        ; 12.977 ;        ;        ; 13.606 ;
+; Y0         ; S0          ; 8.360  ; 8.276  ; 8.869  ; 8.776  ;
+; Y0         ; S1          ; 8.775  ; 8.694  ; 9.323  ; 9.217  ;
+; Y0         ; S2          ; 9.116  ; 9.030  ; 9.700  ; 9.600  ;
+; Y0         ; S3          ; 10.686 ; 10.672 ; 11.315 ; 11.287 ;
+; Y0         ; S4          ; 10.337 ; 10.268 ; 11.002 ; 10.919 ;
+; Y0         ; S5          ; 10.862 ; 10.780 ; 11.591 ; 11.452 ;
+; Y0         ; S6          ; 10.991 ; 10.874 ; 11.744 ; 11.618 ;
+; Y0         ; S7          ; 11.844 ; 11.719 ; 12.614 ; 12.480 ;
+; Y0         ; S8          ; 13.462 ; 13.371 ; 14.240 ; 14.140 ;
+; Y0         ; S9          ; 13.325 ; 13.256 ; 14.110 ; 14.032 ;
+; Y1         ; Cout        ; 12.770 ;        ;        ; 13.318 ;
+; Y1         ; S1          ; 8.559  ; 8.437  ; 8.996  ; 8.906  ;
+; Y1         ; S2          ; 8.909  ; 8.823  ; 9.412  ; 9.312  ;
+; Y1         ; S3          ; 10.479 ; 10.465 ; 11.027 ; 10.999 ;
+; Y1         ; S4          ; 10.130 ; 10.061 ; 10.714 ; 10.631 ;
+; Y1         ; S5          ; 10.655 ; 10.573 ; 11.303 ; 11.164 ;
+; Y1         ; S6          ; 10.784 ; 10.667 ; 11.456 ; 11.330 ;
+; Y1         ; S7          ; 11.637 ; 11.512 ; 12.326 ; 12.192 ;
+; Y1         ; S8          ; 13.255 ; 13.164 ; 13.952 ; 13.852 ;
+; Y1         ; S9          ; 13.118 ; 13.049 ; 13.822 ; 13.744 ;
+; Y2         ; Cout        ; 12.146 ;        ;        ; 12.658 ;
+; Y2         ; S2          ; 8.273  ; 8.196  ; 8.736  ; 8.595  ;
+; Y2         ; S3          ; 9.855  ; 9.841  ; 10.367 ; 10.339 ;
+; Y2         ; S4          ; 9.506  ; 9.437  ; 10.054 ; 9.971  ;
+; Y2         ; S5          ; 10.031 ; 9.949  ; 10.643 ; 10.504 ;
+; Y2         ; S6          ; 10.160 ; 10.043 ; 10.796 ; 10.670 ;
+; Y2         ; S7          ; 11.013 ; 10.888 ; 11.666 ; 11.532 ;
+; Y2         ; S8          ; 12.631 ; 12.540 ; 13.292 ; 13.192 ;
+; Y2         ; S9          ; 12.494 ; 12.425 ; 13.162 ; 13.084 ;
+; Y3         ; Cout        ; 10.994 ;        ;        ; 11.449 ;
+; Y3         ; S3          ; 8.693  ; 8.651  ; 9.157  ; 9.106  ;
+; Y3         ; S4          ; 8.354  ; 8.285  ; 8.845  ; 8.762  ;
+; Y3         ; S5          ; 8.879  ; 8.797  ; 9.434  ; 9.295  ;
+; Y3         ; S6          ; 9.008  ; 8.891  ; 9.587  ; 9.461  ;
+; Y3         ; S7          ; 9.861  ; 9.736  ; 10.457 ; 10.323 ;
+; Y3         ; S8          ; 11.479 ; 11.388 ; 12.083 ; 11.983 ;
+; Y3         ; S9          ; 11.342 ; 11.273 ; 11.953 ; 11.875 ;
+; Y4         ; Cout        ; 11.026 ;        ;        ; 11.478 ;
+; Y4         ; S4          ; 8.375  ; 8.315  ; 8.858  ; 8.734  ;
+; Y4         ; S5          ; 8.911  ; 8.829  ; 9.463  ; 9.324  ;
+; Y4         ; S6          ; 9.040  ; 8.923  ; 9.616  ; 9.490  ;
+; Y4         ; S7          ; 9.893  ; 9.768  ; 10.486 ; 10.352 ;
+; Y4         ; S8          ; 11.511 ; 11.420 ; 12.112 ; 12.012 ;
+; Y4         ; S9          ; 11.374 ; 11.305 ; 11.982 ; 11.904 ;
+; Y5         ; Cout        ; 9.982  ;        ;        ; 10.305 ;
+; Y5         ; S5          ; 7.853  ; 7.736  ; 8.293  ; 8.167  ;
+; Y5         ; S6          ; 7.996  ; 7.879  ; 8.443  ; 8.317  ;
+; Y5         ; S7          ; 8.849  ; 8.724  ; 9.313  ; 9.179  ;
+; Y5         ; S8          ; 10.467 ; 10.376 ; 10.939 ; 10.839 ;
+; Y5         ; S9          ; 10.330 ; 10.261 ; 10.809 ; 10.731 ;
+; Y6         ; Cout        ; 9.872  ;        ;        ; 10.219 ;
+; Y6         ; S6          ; 7.902  ; 7.824  ; 8.365  ; 8.262  ;
+; Y6         ; S7          ; 8.739  ; 8.614  ; 9.227  ; 9.093  ;
+; Y6         ; S8          ; 10.357 ; 10.266 ; 10.853 ; 10.753 ;
+; Y6         ; S9          ; 10.220 ; 10.151 ; 10.723 ; 10.645 ;
+; Y7         ; Cout        ; 8.206  ;        ;        ; 8.503  ;
+; Y7         ; S7          ; 7.078  ; 6.951  ; 7.477  ; 7.382  ;
+; Y7         ; S8          ; 8.691  ; 8.600  ; 9.137  ; 9.037  ;
+; Y7         ; S9          ; 8.554  ; 8.485  ; 9.007  ; 8.929  ;
+; Y8         ; Cout        ; 7.843  ;        ;        ; 8.140  ;
+; Y8         ; S8          ; 8.319  ; 8.226  ; 8.725  ; 8.664  ;
+; Y8         ; S9          ; 8.191  ; 8.122  ; 8.644  ; 8.566  ;
+; Y9         ; Cout        ; 5.214  ;        ;        ; 5.277  ;
+; Y9         ; S9          ; 5.574  ; 5.544  ; 5.771  ; 5.723  ;
++------------+-------------+--------+--------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; ENY        ; Cout        ; 2.926 ;       ;       ; 3.305 ;
+; ENY        ; S0          ; 3.713 ; 3.743 ; 3.995 ; 4.008 ;
+; ENY        ; S1          ; 3.720 ; 3.767 ; 4.006 ; 4.073 ;
+; ENY        ; S2          ; 3.384 ; 3.426 ; 3.646 ; 3.708 ;
+; ENY        ; S3          ; 4.070 ; 4.163 ; 4.352 ; 4.429 ;
+; ENY        ; S4          ; 3.522 ; 3.524 ; 3.785 ; 3.807 ;
+; ENY        ; S5          ; 3.442 ; 3.477 ; 3.704 ; 3.758 ;
+; ENY        ; S6          ; 3.415 ; 3.461 ; 3.711 ; 3.729 ;
+; ENY        ; S7          ; 2.664 ; 2.661 ; 3.012 ; 3.008 ;
+; ENY        ; S8          ; 3.523 ; 3.560 ; 3.871 ; 3.907 ;
+; ENY        ; S9          ; 3.294 ; 3.319 ; 3.665 ; 3.657 ;
+; X0         ; Cout        ; 6.819 ;       ;       ; 7.702 ;
+; X0         ; S0          ; 4.868 ; 4.888 ; 5.470 ; 5.509 ;
+; X0         ; S1          ; 4.757 ; 4.825 ; 5.401 ; 5.441 ;
+; X0         ; S2          ; 4.900 ; 4.954 ; 5.562 ; 5.616 ;
+; X0         ; S3          ; 5.790 ; 5.885 ; 6.475 ; 6.554 ;
+; X0         ; S4          ; 5.559 ; 5.573 ; 6.266 ; 6.280 ;
+; X0         ; S5          ; 5.745 ; 5.791 ; 6.475 ; 6.505 ;
+; X0         ; S6          ; 5.815 ; 5.845 ; 6.556 ; 6.579 ;
+; X0         ; S7          ; 6.241 ; 6.231 ; 7.079 ; 7.062 ;
+; X0         ; S8          ; 7.263 ; 7.293 ; 8.116 ; 8.139 ;
+; X0         ; S9          ; 7.189 ; 7.198 ; 8.056 ; 8.058 ;
+; X1         ; Cout        ; 6.697 ;       ;       ; 7.553 ;
+; X1         ; S1          ; 4.631 ; 4.683 ; 5.242 ; 5.287 ;
+; X1         ; S2          ; 4.778 ; 4.832 ; 5.413 ; 5.467 ;
+; X1         ; S3          ; 5.668 ; 5.763 ; 6.326 ; 6.405 ;
+; X1         ; S4          ; 5.437 ; 5.451 ; 6.117 ; 6.131 ;
+; X1         ; S5          ; 5.623 ; 5.669 ; 6.326 ; 6.356 ;
+; X1         ; S6          ; 5.693 ; 5.723 ; 6.407 ; 6.430 ;
+; X1         ; S7          ; 6.119 ; 6.109 ; 6.930 ; 6.913 ;
+; X1         ; S8          ; 7.141 ; 7.171 ; 7.967 ; 7.990 ;
+; X1         ; S9          ; 7.067 ; 7.076 ; 7.907 ; 7.909 ;
+; X2         ; Cout        ; 5.393 ;       ;       ; 5.906 ;
+; X2         ; S2          ; 3.471 ; 3.518 ; 3.761 ; 3.801 ;
+; X2         ; S3          ; 4.364 ; 4.459 ; 4.679 ; 4.758 ;
+; X2         ; S4          ; 4.133 ; 4.147 ; 4.470 ; 4.484 ;
+; X2         ; S5          ; 4.319 ; 4.365 ; 4.679 ; 4.709 ;
+; X2         ; S6          ; 4.389 ; 4.419 ; 4.760 ; 4.783 ;
+; X2         ; S7          ; 4.815 ; 4.805 ; 5.283 ; 5.266 ;
+; X2         ; S8          ; 5.837 ; 5.867 ; 6.320 ; 6.343 ;
+; X2         ; S9          ; 5.763 ; 5.772 ; 6.260 ; 6.262 ;
+; X3         ; Cout        ; 5.169 ;       ;       ; 5.674 ;
+; X3         ; S3          ; 4.137 ; 4.220 ; 4.420 ; 4.523 ;
+; X3         ; S4          ; 3.909 ; 3.923 ; 4.238 ; 4.252 ;
+; X3         ; S5          ; 4.095 ; 4.141 ; 4.447 ; 4.477 ;
+; X3         ; S6          ; 4.165 ; 4.195 ; 4.528 ; 4.551 ;
+; X3         ; S7          ; 4.591 ; 4.581 ; 5.051 ; 5.034 ;
+; X3         ; S8          ; 5.613 ; 5.643 ; 6.088 ; 6.111 ;
+; X3         ; S9          ; 5.539 ; 5.548 ; 6.028 ; 6.030 ;
+; X4         ; Cout        ; 5.722 ;       ;       ; 6.475 ;
+; X4         ; S4          ; 4.465 ; 4.472 ; 5.040 ; 5.040 ;
+; X4         ; S5          ; 4.648 ; 4.694 ; 5.248 ; 5.278 ;
+; X4         ; S6          ; 4.718 ; 4.748 ; 5.329 ; 5.352 ;
+; X4         ; S7          ; 5.144 ; 5.134 ; 5.852 ; 5.835 ;
+; X4         ; S8          ; 6.166 ; 6.196 ; 6.889 ; 6.912 ;
+; X4         ; S9          ; 6.092 ; 6.101 ; 6.829 ; 6.831 ;
+; X5         ; Cout        ; 5.504 ;       ;       ; 6.238 ;
+; X5         ; S5          ; 4.428 ; 4.472 ; 5.011 ; 5.039 ;
+; X5         ; S6          ; 4.500 ; 4.530 ; 5.092 ; 5.115 ;
+; X5         ; S7          ; 4.926 ; 4.916 ; 5.615 ; 5.598 ;
+; X5         ; S8          ; 5.948 ; 5.978 ; 6.652 ; 6.675 ;
+; X5         ; S9          ; 5.874 ; 5.883 ; 6.592 ; 6.594 ;
+; X6         ; Cout        ; 5.392 ;       ;       ; 6.124 ;
+; X6         ; S6          ; 4.387 ; 4.412 ; 4.954 ; 4.999 ;
+; X6         ; S7          ; 4.814 ; 4.804 ; 5.501 ; 5.484 ;
+; X6         ; S8          ; 5.836 ; 5.866 ; 6.538 ; 6.561 ;
+; X6         ; S9          ; 5.762 ; 5.771 ; 6.478 ; 6.480 ;
+; X7         ; Cout        ; 4.541 ;       ;       ; 5.147 ;
+; X7         ; S7          ; 3.964 ; 3.959 ; 4.528 ; 4.522 ;
+; X7         ; S8          ; 4.985 ; 5.015 ; 5.561 ; 5.584 ;
+; X7         ; S9          ; 4.911 ; 4.920 ; 5.501 ; 5.503 ;
+; X8         ; Cout        ; 4.413 ;       ;       ; 5.011 ;
+; X8         ; S8          ; 4.856 ; 4.891 ; 5.426 ; 5.460 ;
+; X8         ; S9          ; 4.783 ; 4.792 ; 5.365 ; 5.367 ;
+; X9         ; Cout        ; 4.296 ;       ;       ; 4.880 ;
+; X9         ; S9          ; 4.665 ; 4.669 ; 5.210 ; 5.234 ;
+; Y0         ; Cout        ; 6.926 ;       ;       ; 7.832 ;
+; Y0         ; S0          ; 4.756 ; 4.780 ; 5.376 ; 5.393 ;
+; Y0         ; S1          ; 4.860 ; 4.928 ; 5.528 ; 5.563 ;
+; Y0         ; S2          ; 5.007 ; 5.061 ; 5.692 ; 5.746 ;
+; Y0         ; S3          ; 5.897 ; 5.992 ; 6.605 ; 6.684 ;
+; Y0         ; S4          ; 5.666 ; 5.680 ; 6.396 ; 6.410 ;
+; Y0         ; S5          ; 5.852 ; 5.898 ; 6.605 ; 6.635 ;
+; Y0         ; S6          ; 5.922 ; 5.952 ; 6.686 ; 6.709 ;
+; Y0         ; S7          ; 6.348 ; 6.338 ; 7.209 ; 7.192 ;
+; Y0         ; S8          ; 7.370 ; 7.400 ; 8.246 ; 8.269 ;
+; Y0         ; S9          ; 7.296 ; 7.305 ; 8.186 ; 8.188 ;
+; Y1         ; Cout        ; 6.814 ;       ;       ; 7.677 ;
+; Y1         ; S1          ; 4.751 ; 4.798 ; 5.348 ; 5.415 ;
+; Y1         ; S2          ; 4.895 ; 4.949 ; 5.537 ; 5.591 ;
+; Y1         ; S3          ; 5.785 ; 5.880 ; 6.450 ; 6.529 ;
+; Y1         ; S4          ; 5.554 ; 5.568 ; 6.241 ; 6.255 ;
+; Y1         ; S5          ; 5.740 ; 5.786 ; 6.450 ; 6.480 ;
+; Y1         ; S6          ; 5.810 ; 5.840 ; 6.531 ; 6.554 ;
+; Y1         ; S7          ; 6.236 ; 6.226 ; 7.054 ; 7.037 ;
+; Y1         ; S8          ; 7.258 ; 7.288 ; 8.091 ; 8.114 ;
+; Y1         ; S9          ; 7.184 ; 7.193 ; 8.031 ; 8.033 ;
+; Y2         ; Cout        ; 6.527 ;       ;       ; 7.336 ;
+; Y2         ; S2          ; 4.598 ; 4.650 ; 5.198 ; 5.247 ;
+; Y2         ; S3          ; 5.498 ; 5.593 ; 6.109 ; 6.188 ;
+; Y2         ; S4          ; 5.267 ; 5.281 ; 5.900 ; 5.914 ;
+; Y2         ; S5          ; 5.453 ; 5.499 ; 6.109 ; 6.139 ;
+; Y2         ; S6          ; 5.523 ; 5.553 ; 6.190 ; 6.213 ;
+; Y2         ; S7          ; 5.949 ; 5.939 ; 6.713 ; 6.696 ;
+; Y2         ; S8          ; 6.971 ; 7.001 ; 7.750 ; 7.773 ;
+; Y2         ; S9          ; 6.897 ; 6.906 ; 7.690 ; 7.692 ;
+; Y3         ; Cout        ; 5.951 ;       ;       ; 6.736 ;
+; Y3         ; S3          ; 4.923 ; 5.011 ; 5.508 ; 5.589 ;
+; Y3         ; S4          ; 4.691 ; 4.705 ; 5.300 ; 5.314 ;
+; Y3         ; S5          ; 4.877 ; 4.923 ; 5.509 ; 5.539 ;
+; Y3         ; S6          ; 4.947 ; 4.977 ; 5.590 ; 5.613 ;
+; Y3         ; S7          ; 5.373 ; 5.363 ; 6.113 ; 6.096 ;
+; Y3         ; S8          ; 6.395 ; 6.425 ; 7.150 ; 7.173 ;
+; Y3         ; S9          ; 6.321 ; 6.330 ; 7.090 ; 7.092 ;
+; Y4         ; Cout        ; 5.983 ;       ;       ; 6.776 ;
+; Y4         ; S4          ; 4.715 ; 4.727 ; 5.342 ; 5.351 ;
+; Y4         ; S5          ; 4.909 ; 4.955 ; 5.549 ; 5.579 ;
+; Y4         ; S6          ; 4.979 ; 5.009 ; 5.630 ; 5.653 ;
+; Y4         ; S7          ; 5.405 ; 5.395 ; 6.153 ; 6.136 ;
+; Y4         ; S8          ; 6.427 ; 6.457 ; 7.190 ; 7.213 ;
+; Y4         ; S9          ; 6.353 ; 6.362 ; 7.130 ; 7.132 ;
+; Y5         ; Cout        ; 5.471 ;       ;       ; 6.201 ;
+; Y5         ; S5          ; 4.393 ; 4.432 ; 4.968 ; 5.000 ;
+; Y5         ; S6          ; 4.467 ; 4.497 ; 5.055 ; 5.078 ;
+; Y5         ; S7          ; 4.893 ; 4.883 ; 5.578 ; 5.561 ;
+; Y5         ; S8          ; 5.915 ; 5.945 ; 6.615 ; 6.638 ;
+; Y5         ; S9          ; 5.841 ; 5.850 ; 6.555 ; 6.557 ;
+; Y6         ; Cout        ; 5.403 ;       ;       ; 6.141 ;
+; Y6         ; S6          ; 4.404 ; 4.450 ; 5.007 ; 5.020 ;
+; Y6         ; S7          ; 4.825 ; 4.815 ; 5.518 ; 5.501 ;
+; Y6         ; S8          ; 5.847 ; 5.877 ; 6.555 ; 6.578 ;
+; Y6         ; S9          ; 5.773 ; 5.782 ; 6.495 ; 6.497 ;
+; Y7         ; Cout        ; 4.533 ;       ;       ; 5.148 ;
+; Y7         ; S7          ; 3.960 ; 3.945 ; 4.509 ; 4.514 ;
+; Y7         ; S8          ; 4.977 ; 5.007 ; 5.562 ; 5.585 ;
+; Y7         ; S9          ; 4.903 ; 4.912 ; 5.502 ; 5.504 ;
+; Y8         ; Cout        ; 4.353 ;       ;       ; 4.952 ;
+; Y8         ; S8          ; 4.788 ; 4.813 ; 5.334 ; 5.379 ;
+; Y8         ; S9          ; 4.723 ; 4.732 ; 5.306 ; 5.308 ;
+; Y9         ; Cout        ; 2.906 ;       ;       ; 3.291 ;
+; Y9         ; S9          ; 3.278 ; 3.303 ; 3.650 ; 3.647 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Cout          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S0            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S1            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S2            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S3            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S4            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S5            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S6            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S7            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S8            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; S9            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------------+
+; Input Transition Times                                            ;
++----------------+--------------+-----------------+-----------------+
+; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------------+--------------+-----------------+-----------------+
+; Y9             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ENY            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y8             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y7             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y6             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y5             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y4             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y3             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y2             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y0             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X0             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; Y1             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X1             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X2             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X3             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X4             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X5             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X6             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X7             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X8             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; X9             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; S0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.4 V               ; -0.00557 V          ; 0.238 V                              ; 0.014 V                              ; 2.9e-10 s                   ; 3.48e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.4 V              ; -0.00557 V         ; 0.238 V                             ; 0.014 V                             ; 2.9e-10 s                  ; 3.48e-10 s                 ; No                        ; Yes                       ;
+; S2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; S3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; S5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; S6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.4 V               ; -0.00557 V          ; 0.238 V                              ; 0.014 V                              ; 2.9e-10 s                   ; 3.48e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.4 V              ; -0.00557 V         ; 0.238 V                             ; 0.014 V                             ; 2.9e-10 s                  ; 3.48e-10 s                 ; No                        ; Yes                       ;
+; S7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; S8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.34 V              ; -0.00668 V          ; 0.218 V                              ; 0.076 V                              ; 1.92e-09 s                  ; 1.81e-09 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.34 V             ; -0.00668 V         ; 0.218 V                             ; 0.076 V                             ; 1.92e-09 s                 ; 1.81e-09 s                 ; No                        ; Yes                       ;
+; S9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.34 V              ; -0.00668 V          ; 0.218 V                              ; 0.076 V                              ; 1.92e-09 s                  ; 1.81e-09 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.34 V             ; -0.00668 V         ; 0.218 V                             ; 0.076 V                             ; 1.92e-09 s                 ; 1.81e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.94e-09 V                   ; 2.39 V              ; -0.0344 V           ; 0.156 V                              ; 0.089 V                              ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.94e-09 V                  ; 2.39 V             ; -0.0344 V          ; 0.156 V                             ; 0.089 V                             ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; S0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.36 V              ; -0.00623 V          ; 0.121 V                              ; 0.03 V                               ; 4.4e-10 s                   ; 4.28e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.36 V             ; -0.00623 V         ; 0.121 V                             ; 0.03 V                              ; 4.4e-10 s                  ; 4.28e-10 s                 ; Yes                       ; Yes                       ;
+; S2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; S3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; S5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; S6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.36 V              ; -0.00623 V          ; 0.121 V                              ; 0.03 V                               ; 4.4e-10 s                   ; 4.28e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.36 V             ; -0.00623 V         ; 0.121 V                             ; 0.03 V                              ; 4.4e-10 s                  ; 4.28e-10 s                 ; Yes                       ; Yes                       ;
+; S7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; S8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.33 V              ; -0.00286 V          ; 0.193 V                              ; 0.042 V                              ; 2.32e-09 s                  ; 2.21e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.33 V             ; -0.00286 V         ; 0.193 V                             ; 0.042 V                             ; 2.32e-09 s                 ; 2.21e-09 s                 ; Yes                       ; Yes                       ;
+; S9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.33 V              ; -0.00286 V          ; 0.193 V                              ; 0.042 V                              ; 2.32e-09 s                  ; 2.21e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.33 V             ; -0.00286 V         ; 0.193 V                             ; 0.042 V                             ; 2.32e-09 s                 ; 2.21e-09 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00439 V          ; 0.088 V                              ; 0.007 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00439 V         ; 0.088 V                             ; 0.007 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; S0            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S1            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.72 V              ; -0.0199 V           ; 0.186 V                              ; 0.027 V                              ; 2.63e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.72 V             ; -0.0199 V          ; 0.186 V                             ; 0.027 V                             ; 2.63e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; S2            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; S3            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S4            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; S5            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; S6            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.72 V              ; -0.0199 V           ; 0.186 V                              ; 0.027 V                              ; 2.63e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.72 V             ; -0.0199 V          ; 0.186 V                             ; 0.027 V                             ; 2.63e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; S7            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; S8            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.65 V              ; -0.0115 V           ; 0.219 V                              ; 0.115 V                              ; 1.64e-09 s                  ; 1.57e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.65 V             ; -0.0115 V          ; 0.219 V                             ; 0.115 V                             ; 1.64e-09 s                 ; 1.57e-09 s                 ; No                        ; Yes                       ;
+; S9            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.65 V              ; -0.0115 V           ; 0.219 V                              ; 0.115 V                              ; 1.64e-09 s                  ; 1.57e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.65 V             ; -0.0115 V          ; 0.219 V                             ; 0.115 V                             ; 1.64e-09 s                 ; 1.57e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0542 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0542 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 21    ; 21   ;
+; Unconstrained Input Port Paths  ; 141   ; 141  ;
+; Unconstrained Output Ports      ; 11    ; 11   ;
+; Unconstrained Output Port Paths ; 141   ; 141  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Thu Feb 18 22:56:48 2016
+Info: Command: quartus_sta ten_bit_adder_NO_BUS -c ten_bit_adder_NO_BUS
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_bit_adder_NO_BUS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 528 megabytes
+    Info: Processing ended: Thu Feb 18 22:56:50 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.summary b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.sft b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.sft
new file mode 100644
index 0000000..eecd25d
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.vho b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.vho
new file mode 100644
index 0000000..65f689a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS.vho
@@ -0,0 +1,978 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:56:52"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder_NO_BUS IS
+    PORT (
+	Cout : OUT std_logic;
+	X9 : IN std_logic;
+	Y9 : IN std_logic;
+	ENY : IN std_logic;
+	X8 : IN std_logic;
+	Y8 : IN std_logic;
+	X7 : IN std_logic;
+	Y7 : IN std_logic;
+	X6 : IN std_logic;
+	Y6 : IN std_logic;
+	X5 : IN std_logic;
+	Y5 : IN std_logic;
+	X4 : IN std_logic;
+	Y4 : IN std_logic;
+	X3 : IN std_logic;
+	Y3 : IN std_logic;
+	X2 : IN std_logic;
+	Y2 : IN std_logic;
+	X1 : IN std_logic;
+	Y1 : IN std_logic;
+	X0 : IN std_logic;
+	Y0 : IN std_logic;
+	S0 : OUT std_logic;
+	S1 : OUT std_logic;
+	S2 : OUT std_logic;
+	S3 : OUT std_logic;
+	S4 : OUT std_logic;
+	S5 : OUT std_logic;
+	S6 : OUT std_logic;
+	S7 : OUT std_logic;
+	S8 : OUT std_logic;
+	S9 : OUT std_logic
+	);
+END ten_bit_adder_NO_BUS;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S0	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S1	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S2	=>  Location: PIN_N11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S3	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S4	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S5	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S6	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S7	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S8	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S9	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y9	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENY	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y8	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y7	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y6	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y5	=>  Location: PIN_M13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y4	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y3	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y2	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y0	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X0	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y1	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X1	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X2	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X3	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X4	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X5	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X6	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X7	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X8	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X9	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder_NO_BUS IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X9 : std_logic;
+SIGNAL ww_Y9 : std_logic;
+SIGNAL ww_ENY : std_logic;
+SIGNAL ww_X8 : std_logic;
+SIGNAL ww_Y8 : std_logic;
+SIGNAL ww_X7 : std_logic;
+SIGNAL ww_Y7 : std_logic;
+SIGNAL ww_X6 : std_logic;
+SIGNAL ww_Y6 : std_logic;
+SIGNAL ww_X5 : std_logic;
+SIGNAL ww_Y5 : std_logic;
+SIGNAL ww_X4 : std_logic;
+SIGNAL ww_Y4 : std_logic;
+SIGNAL ww_X3 : std_logic;
+SIGNAL ww_Y3 : std_logic;
+SIGNAL ww_X2 : std_logic;
+SIGNAL ww_Y2 : std_logic;
+SIGNAL ww_X1 : std_logic;
+SIGNAL ww_Y1 : std_logic;
+SIGNAL ww_X0 : std_logic;
+SIGNAL ww_Y0 : std_logic;
+SIGNAL ww_S0 : std_logic;
+SIGNAL ww_S1 : std_logic;
+SIGNAL ww_S2 : std_logic;
+SIGNAL ww_S3 : std_logic;
+SIGNAL ww_S4 : std_logic;
+SIGNAL ww_S5 : std_logic;
+SIGNAL ww_S6 : std_logic;
+SIGNAL ww_S7 : std_logic;
+SIGNAL ww_S8 : std_logic;
+SIGNAL ww_S9 : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S0~output_o\ : std_logic;
+SIGNAL \S1~output_o\ : std_logic;
+SIGNAL \S2~output_o\ : std_logic;
+SIGNAL \S3~output_o\ : std_logic;
+SIGNAL \S4~output_o\ : std_logic;
+SIGNAL \S5~output_o\ : std_logic;
+SIGNAL \S6~output_o\ : std_logic;
+SIGNAL \S7~output_o\ : std_logic;
+SIGNAL \S8~output_o\ : std_logic;
+SIGNAL \S9~output_o\ : std_logic;
+SIGNAL \Y9~input_o\ : std_logic;
+SIGNAL \ENY~input_o\ : std_logic;
+SIGNAL \X9~input_o\ : std_logic;
+SIGNAL \X8~input_o\ : std_logic;
+SIGNAL \Y8~input_o\ : std_logic;
+SIGNAL \X7~input_o\ : std_logic;
+SIGNAL \Y7~input_o\ : std_logic;
+SIGNAL \Y6~input_o\ : std_logic;
+SIGNAL \X6~input_o\ : std_logic;
+SIGNAL \X5~input_o\ : std_logic;
+SIGNAL \Y4~input_o\ : std_logic;
+SIGNAL \Y2~input_o\ : std_logic;
+SIGNAL \X0~input_o\ : std_logic;
+SIGNAL \Y0~input_o\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+SIGNAL \Y1~input_o\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \X1~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \X2~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \X3~input_o\ : std_logic;
+SIGNAL \Y3~input_o\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \X4~input_o\ : std_logic;
+SIGNAL \inst12|inst3~0_combout\ : std_logic;
+SIGNAL \Y5~input_o\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \inst8|inst~combout\ : std_logic;
+SIGNAL \inst9|inst2~combout\ : std_logic;
+SIGNAL \inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst16|inst2~0_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X9 <= X9;
+ww_Y9 <= Y9;
+ww_ENY <= ENY;
+ww_X8 <= X8;
+ww_Y8 <= Y8;
+ww_X7 <= X7;
+ww_Y7 <= Y7;
+ww_X6 <= X6;
+ww_Y6 <= Y6;
+ww_X5 <= X5;
+ww_Y5 <= Y5;
+ww_X4 <= X4;
+ww_Y4 <= Y4;
+ww_X3 <= X3;
+ww_Y3 <= Y3;
+ww_X2 <= X2;
+ww_Y2 <= Y2;
+ww_X1 <= X1;
+ww_Y1 <= Y1;
+ww_X0 <= X0;
+ww_Y0 <= Y0;
+S0 <= ww_S0;
+S1 <= ww_S1;
+S2 <= ww_S2;
+S3 <= ww_S3;
+S4 <= ww_S4;
+S5 <= ww_S5;
+S6 <= ww_S6;
+S7 <= ww_S7;
+S8 <= ww_S8;
+S9 <= ww_S9;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X20_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\S0~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8|inst~combout\,
+	devoe => ww_devoe,
+	o => \S0~output_o\);
+
+-- Location: IOOBUF_X33_Y14_N2
+\S1~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9|inst2~combout\,
+	devoe => ww_devoe,
+	o => \S1~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N2
+\S2~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst10|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S2~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N9
+\S3~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst11|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S3~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S4~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst12|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S4~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\S5~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst13|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S5~output_o\);
+
+-- Location: IOOBUF_X33_Y10_N9
+\S6~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S6~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N9
+\S7~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S7~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N9
+\S8~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst16|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S8~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N2
+\S9~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S9~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y9,
+	o => \Y9~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\ENY~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_ENY,
+	o => \ENY~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\X9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X9,
+	o => \X9~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\X8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X8,
+	o => \X8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\Y8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y8,
+	o => \Y8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\X7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X7,
+	o => \X7~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y7,
+	o => \Y7~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N1
+\Y6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y6,
+	o => \Y6~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N1
+\X6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X6,
+	o => \X6~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N8
+\X5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X5,
+	o => \X5~input_o\);
+
+-- Location: IOIBUF_X29_Y0_N1
+\Y4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y4,
+	o => \Y4~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\Y2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y2,
+	o => \Y2~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N8
+\X0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X0,
+	o => \X0~input_o\);
+
+-- Location: IOIBUF_X26_Y31_N1
+\Y0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y0,
+	o => \Y0~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N0
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\ENY~input_o\ & \Y0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst6~combout\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y1,
+	o => \Y1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N26
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\ENY~input_o\ & \Y1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y1~input_o\,
+	combout => \inst7~combout\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\X1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X1,
+	o => \X1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N20
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\inst7~combout\ & ((\X1~input_o\) # ((\X0~input_o\ & \inst6~combout\)))) # (!\inst7~combout\ & (\X0~input_o\ & (\inst6~combout\ & \X1~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X2,
+	o => \X2~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N14
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\inst9|inst3~0_combout\ & ((\X2~input_o\) # ((\Y2~input_o\ & \ENY~input_o\)))) # (!\inst9|inst3~0_combout\ & (\Y2~input_o\ & (\ENY~input_o\ & \X2~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X3,
+	o => \X3~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Y3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y3,
+	o => \Y3~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N24
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\inst10|inst3~0_combout\ & ((\X3~input_o\) # ((\ENY~input_o\ & \Y3~input_o\)))) # (!\inst10|inst3~0_combout\ & (\ENY~input_o\ & (\X3~input_o\ & \Y3~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\X4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X4,
+	o => \X4~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N2
+\inst12|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst3~0_combout\ = (\inst11|inst3~0_combout\ & ((\X4~input_o\) # ((\Y4~input_o\ & \ENY~input_o\)))) # (!\inst11|inst3~0_combout\ & (\Y4~input_o\ & (\ENY~input_o\ & \X4~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y10_N1
+\Y5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y5,
+	o => \Y5~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N12
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X5~input_o\ & ((\inst12|inst3~0_combout\) # ((\ENY~input_o\ & \Y5~input_o\)))) # (!\X5~input_o\ & (\inst12|inst3~0_combout\ & (\ENY~input_o\ & \Y5~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N22
+\inst14|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst3~0_combout\ = (\X6~input_o\ & ((\inst13|inst3~0_combout\) # ((\ENY~input_o\ & \Y6~input_o\)))) # (!\X6~input_o\ & (\ENY~input_o\ & (\Y6~input_o\ & \inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N0
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\X7~input_o\ & ((\inst14|inst3~0_combout\) # ((\ENY~input_o\ & \Y7~input_o\)))) # (!\X7~input_o\ & (\ENY~input_o\ & (\Y7~input_o\ & \inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N2
+\inst16|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst3~0_combout\ = (\X8~input_o\ & ((\inst15|inst3~0_combout\) # ((\ENY~input_o\ & \Y8~input_o\)))) # (!\X8~input_o\ & (\ENY~input_o\ & (\Y8~input_o\ & \inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N20
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\X9~input_o\ & ((\inst16|inst3~0_combout\) # ((\Y9~input_o\ & \ENY~input_o\)))) # (!\X9~input_o\ & (\Y9~input_o\ & (\ENY~input_o\ & \inst16|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N8
+\inst8|inst\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst8|inst~combout\ = \X0~input_o\ $ (((\ENY~input_o\ & \Y0~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datac => \X0~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst8|inst~combout\);
+
+-- Location: LCCOMB_X25_Y7_N10
+\inst9|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~combout\ = \inst7~combout\ $ (\X1~input_o\ $ (((\X0~input_o\ & \inst6~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst2~combout\);
+
+-- Location: LCCOMB_X25_Y7_N28
+\inst10|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst2~0_combout\ = \inst9|inst3~0_combout\ $ (\X2~input_o\ $ (((\Y2~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N6
+\inst11|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~0_combout\ = \inst10|inst3~0_combout\ $ (\X3~input_o\ $ (((\ENY~input_o\ & \Y3~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N16
+\inst12|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst2~0_combout\ = \inst11|inst3~0_combout\ $ (\X4~input_o\ $ (((\Y4~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N18
+\inst13|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst2~0_combout\ = \X5~input_o\ $ (\inst12|inst3~0_combout\ $ (((\ENY~input_o\ & \Y5~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001100110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N4
+\inst14|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst2~0_combout\ = \X6~input_o\ $ (\inst13|inst3~0_combout\ $ (((\ENY~input_o\ & \Y6~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N22
+\inst15|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst2~0_combout\ = \X7~input_o\ $ (\inst14|inst3~0_combout\ $ (((\ENY~input_o\ & \Y7~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N24
+\inst16|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst2~0_combout\ = \X8~input_o\ $ (\inst15|inst3~0_combout\ $ (((\ENY~input_o\ & \Y8~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N26
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X9~input_o\ $ (\inst16|inst3~0_combout\ $ (((\Y9~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S0 <= \S0~output_o\;
+
+ww_S1 <= \S1~output_o\;
+
+ww_S2 <= \S2~output_o\;
+
+ww_S3 <= \S3~output_o\;
+
+ww_S4 <= \S4~output_o\;
+
+ww_S5 <= \S5~output_o\;
+
+ww_S6 <= \S6~output_o\;
+
+ww_S7 <= \S7~output_o\;
+
+ww_S8 <= \S8~output_o\;
+
+ww_S9 <= \S9~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..65f689a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_slow.vho
@@ -0,0 +1,978 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:56:52"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder_NO_BUS IS
+    PORT (
+	Cout : OUT std_logic;
+	X9 : IN std_logic;
+	Y9 : IN std_logic;
+	ENY : IN std_logic;
+	X8 : IN std_logic;
+	Y8 : IN std_logic;
+	X7 : IN std_logic;
+	Y7 : IN std_logic;
+	X6 : IN std_logic;
+	Y6 : IN std_logic;
+	X5 : IN std_logic;
+	Y5 : IN std_logic;
+	X4 : IN std_logic;
+	Y4 : IN std_logic;
+	X3 : IN std_logic;
+	Y3 : IN std_logic;
+	X2 : IN std_logic;
+	Y2 : IN std_logic;
+	X1 : IN std_logic;
+	Y1 : IN std_logic;
+	X0 : IN std_logic;
+	Y0 : IN std_logic;
+	S0 : OUT std_logic;
+	S1 : OUT std_logic;
+	S2 : OUT std_logic;
+	S3 : OUT std_logic;
+	S4 : OUT std_logic;
+	S5 : OUT std_logic;
+	S6 : OUT std_logic;
+	S7 : OUT std_logic;
+	S8 : OUT std_logic;
+	S9 : OUT std_logic
+	);
+END ten_bit_adder_NO_BUS;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S0	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S1	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S2	=>  Location: PIN_N11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S3	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S4	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S5	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S6	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S7	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S8	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S9	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y9	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENY	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y8	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y7	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y6	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y5	=>  Location: PIN_M13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y4	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y3	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y2	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y0	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X0	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y1	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X1	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X2	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X3	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X4	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X5	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X6	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X7	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X8	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X9	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder_NO_BUS IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X9 : std_logic;
+SIGNAL ww_Y9 : std_logic;
+SIGNAL ww_ENY : std_logic;
+SIGNAL ww_X8 : std_logic;
+SIGNAL ww_Y8 : std_logic;
+SIGNAL ww_X7 : std_logic;
+SIGNAL ww_Y7 : std_logic;
+SIGNAL ww_X6 : std_logic;
+SIGNAL ww_Y6 : std_logic;
+SIGNAL ww_X5 : std_logic;
+SIGNAL ww_Y5 : std_logic;
+SIGNAL ww_X4 : std_logic;
+SIGNAL ww_Y4 : std_logic;
+SIGNAL ww_X3 : std_logic;
+SIGNAL ww_Y3 : std_logic;
+SIGNAL ww_X2 : std_logic;
+SIGNAL ww_Y2 : std_logic;
+SIGNAL ww_X1 : std_logic;
+SIGNAL ww_Y1 : std_logic;
+SIGNAL ww_X0 : std_logic;
+SIGNAL ww_Y0 : std_logic;
+SIGNAL ww_S0 : std_logic;
+SIGNAL ww_S1 : std_logic;
+SIGNAL ww_S2 : std_logic;
+SIGNAL ww_S3 : std_logic;
+SIGNAL ww_S4 : std_logic;
+SIGNAL ww_S5 : std_logic;
+SIGNAL ww_S6 : std_logic;
+SIGNAL ww_S7 : std_logic;
+SIGNAL ww_S8 : std_logic;
+SIGNAL ww_S9 : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S0~output_o\ : std_logic;
+SIGNAL \S1~output_o\ : std_logic;
+SIGNAL \S2~output_o\ : std_logic;
+SIGNAL \S3~output_o\ : std_logic;
+SIGNAL \S4~output_o\ : std_logic;
+SIGNAL \S5~output_o\ : std_logic;
+SIGNAL \S6~output_o\ : std_logic;
+SIGNAL \S7~output_o\ : std_logic;
+SIGNAL \S8~output_o\ : std_logic;
+SIGNAL \S9~output_o\ : std_logic;
+SIGNAL \Y9~input_o\ : std_logic;
+SIGNAL \ENY~input_o\ : std_logic;
+SIGNAL \X9~input_o\ : std_logic;
+SIGNAL \X8~input_o\ : std_logic;
+SIGNAL \Y8~input_o\ : std_logic;
+SIGNAL \X7~input_o\ : std_logic;
+SIGNAL \Y7~input_o\ : std_logic;
+SIGNAL \Y6~input_o\ : std_logic;
+SIGNAL \X6~input_o\ : std_logic;
+SIGNAL \X5~input_o\ : std_logic;
+SIGNAL \Y4~input_o\ : std_logic;
+SIGNAL \Y2~input_o\ : std_logic;
+SIGNAL \X0~input_o\ : std_logic;
+SIGNAL \Y0~input_o\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+SIGNAL \Y1~input_o\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \X1~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \X2~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \X3~input_o\ : std_logic;
+SIGNAL \Y3~input_o\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \X4~input_o\ : std_logic;
+SIGNAL \inst12|inst3~0_combout\ : std_logic;
+SIGNAL \Y5~input_o\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \inst8|inst~combout\ : std_logic;
+SIGNAL \inst9|inst2~combout\ : std_logic;
+SIGNAL \inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst16|inst2~0_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X9 <= X9;
+ww_Y9 <= Y9;
+ww_ENY <= ENY;
+ww_X8 <= X8;
+ww_Y8 <= Y8;
+ww_X7 <= X7;
+ww_Y7 <= Y7;
+ww_X6 <= X6;
+ww_Y6 <= Y6;
+ww_X5 <= X5;
+ww_Y5 <= Y5;
+ww_X4 <= X4;
+ww_Y4 <= Y4;
+ww_X3 <= X3;
+ww_Y3 <= Y3;
+ww_X2 <= X2;
+ww_Y2 <= Y2;
+ww_X1 <= X1;
+ww_Y1 <= Y1;
+ww_X0 <= X0;
+ww_Y0 <= Y0;
+S0 <= ww_S0;
+S1 <= ww_S1;
+S2 <= ww_S2;
+S3 <= ww_S3;
+S4 <= ww_S4;
+S5 <= ww_S5;
+S6 <= ww_S6;
+S7 <= ww_S7;
+S8 <= ww_S8;
+S9 <= ww_S9;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X20_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\S0~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8|inst~combout\,
+	devoe => ww_devoe,
+	o => \S0~output_o\);
+
+-- Location: IOOBUF_X33_Y14_N2
+\S1~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9|inst2~combout\,
+	devoe => ww_devoe,
+	o => \S1~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N2
+\S2~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst10|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S2~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N9
+\S3~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst11|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S3~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S4~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst12|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S4~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\S5~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst13|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S5~output_o\);
+
+-- Location: IOOBUF_X33_Y10_N9
+\S6~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S6~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N9
+\S7~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S7~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N9
+\S8~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst16|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S8~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N2
+\S9~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S9~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y9,
+	o => \Y9~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\ENY~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_ENY,
+	o => \ENY~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\X9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X9,
+	o => \X9~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\X8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X8,
+	o => \X8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\Y8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y8,
+	o => \Y8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\X7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X7,
+	o => \X7~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y7,
+	o => \Y7~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N1
+\Y6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y6,
+	o => \Y6~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N1
+\X6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X6,
+	o => \X6~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N8
+\X5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X5,
+	o => \X5~input_o\);
+
+-- Location: IOIBUF_X29_Y0_N1
+\Y4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y4,
+	o => \Y4~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\Y2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y2,
+	o => \Y2~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N8
+\X0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X0,
+	o => \X0~input_o\);
+
+-- Location: IOIBUF_X26_Y31_N1
+\Y0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y0,
+	o => \Y0~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N0
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\ENY~input_o\ & \Y0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst6~combout\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y1,
+	o => \Y1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N26
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\ENY~input_o\ & \Y1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y1~input_o\,
+	combout => \inst7~combout\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\X1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X1,
+	o => \X1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N20
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\inst7~combout\ & ((\X1~input_o\) # ((\X0~input_o\ & \inst6~combout\)))) # (!\inst7~combout\ & (\X0~input_o\ & (\inst6~combout\ & \X1~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X2,
+	o => \X2~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N14
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\inst9|inst3~0_combout\ & ((\X2~input_o\) # ((\Y2~input_o\ & \ENY~input_o\)))) # (!\inst9|inst3~0_combout\ & (\Y2~input_o\ & (\ENY~input_o\ & \X2~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X3,
+	o => \X3~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Y3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y3,
+	o => \Y3~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N24
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\inst10|inst3~0_combout\ & ((\X3~input_o\) # ((\ENY~input_o\ & \Y3~input_o\)))) # (!\inst10|inst3~0_combout\ & (\ENY~input_o\ & (\X3~input_o\ & \Y3~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\X4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X4,
+	o => \X4~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N2
+\inst12|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst3~0_combout\ = (\inst11|inst3~0_combout\ & ((\X4~input_o\) # ((\Y4~input_o\ & \ENY~input_o\)))) # (!\inst11|inst3~0_combout\ & (\Y4~input_o\ & (\ENY~input_o\ & \X4~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y10_N1
+\Y5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y5,
+	o => \Y5~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N12
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X5~input_o\ & ((\inst12|inst3~0_combout\) # ((\ENY~input_o\ & \Y5~input_o\)))) # (!\X5~input_o\ & (\inst12|inst3~0_combout\ & (\ENY~input_o\ & \Y5~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N22
+\inst14|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst3~0_combout\ = (\X6~input_o\ & ((\inst13|inst3~0_combout\) # ((\ENY~input_o\ & \Y6~input_o\)))) # (!\X6~input_o\ & (\ENY~input_o\ & (\Y6~input_o\ & \inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N0
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\X7~input_o\ & ((\inst14|inst3~0_combout\) # ((\ENY~input_o\ & \Y7~input_o\)))) # (!\X7~input_o\ & (\ENY~input_o\ & (\Y7~input_o\ & \inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N2
+\inst16|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst3~0_combout\ = (\X8~input_o\ & ((\inst15|inst3~0_combout\) # ((\ENY~input_o\ & \Y8~input_o\)))) # (!\X8~input_o\ & (\ENY~input_o\ & (\Y8~input_o\ & \inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N20
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\X9~input_o\ & ((\inst16|inst3~0_combout\) # ((\Y9~input_o\ & \ENY~input_o\)))) # (!\X9~input_o\ & (\Y9~input_o\ & (\ENY~input_o\ & \inst16|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N8
+\inst8|inst\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst8|inst~combout\ = \X0~input_o\ $ (((\ENY~input_o\ & \Y0~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datac => \X0~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst8|inst~combout\);
+
+-- Location: LCCOMB_X25_Y7_N10
+\inst9|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~combout\ = \inst7~combout\ $ (\X1~input_o\ $ (((\X0~input_o\ & \inst6~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst2~combout\);
+
+-- Location: LCCOMB_X25_Y7_N28
+\inst10|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst2~0_combout\ = \inst9|inst3~0_combout\ $ (\X2~input_o\ $ (((\Y2~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N6
+\inst11|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~0_combout\ = \inst10|inst3~0_combout\ $ (\X3~input_o\ $ (((\ENY~input_o\ & \Y3~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N16
+\inst12|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst2~0_combout\ = \inst11|inst3~0_combout\ $ (\X4~input_o\ $ (((\Y4~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N18
+\inst13|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst2~0_combout\ = \X5~input_o\ $ (\inst12|inst3~0_combout\ $ (((\ENY~input_o\ & \Y5~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001100110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N4
+\inst14|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst2~0_combout\ = \X6~input_o\ $ (\inst13|inst3~0_combout\ $ (((\ENY~input_o\ & \Y6~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N22
+\inst15|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst2~0_combout\ = \X7~input_o\ $ (\inst14|inst3~0_combout\ $ (((\ENY~input_o\ & \Y7~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N24
+\inst16|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst2~0_combout\ = \X8~input_o\ $ (\inst15|inst3~0_combout\ $ (((\ENY~input_o\ & \Y8~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N26
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X9~input_o\ $ (\inst16|inst3~0_combout\ $ (((\Y9~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S0 <= \S0~output_o\;
+
+ww_S1 <= \S1~output_o\;
+
+ww_S2 <= \S2~output_o\;
+
+ww_S3 <= \S3~output_o\;
+
+ww_S4 <= \S4~output_o\;
+
+ww_S5 <= \S5~output_o\;
+
+ww_S6 <= \S6~output_o\;
+
+ww_S7 <= \S7~output_o\;
+
+ww_S8 <= \S8~output_o\;
+
+ww_S9 <= \S9~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..096e32e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,664 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder_NO_BUS")
+  (DATE "02/18/2016 22:56:52")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (825:825:825) (761:761:761))
+        (IOPATH i o (2324:2324:2324) (2217:2217:2217))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S0\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1226:1226:1226) (1193:1193:1193))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1248:1248:1248) (1213:1213:1213))
+        (IOPATH i o (2251:2251:2251) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S2\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (991:991:991) (964:964:964))
+        (IOPATH i o (2334:2334:2334) (2227:2227:2227))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S3\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1846:1846:1846) (1838:1838:1838))
+        (IOPATH i o (2419:2419:2419) (2331:2331:2331))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S4\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1007:1007:1007) (969:969:969))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S5\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1183:1183:1183) (1143:1143:1143))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S6\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (959:959:959) (929:929:929))
+        (IOPATH i o (2281:2281:2281) (2208:2208:2208))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S7\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (428:428:428) (397:397:397))
+        (IOPATH i o (2221:2221:2221) (2150:2150:2150))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S8\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (853:853:853) (791:791:791))
+        (IOPATH i o (2949:2949:2949) (2920:2920:2920))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S9\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (441:441:441) (409:409:409))
+        (IOPATH i o (2949:2949:2949) (2920:2920:2920))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\ENY\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (508:508:508) (664:664:664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (478:478:478) (634:634:634))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (689:689:689))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (669:669:669))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (508:508:508) (664:664:664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1339:1339:1339) (1302:1302:1302))
+        (PORT datad (3162:3162:3162) (3413:3413:3413))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (488:488:488) (644:644:644))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1335:1335:1335) (1298:1298:1298))
+        (PORT datad (3098:3098:3098) (3298:3298:3298))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (679:679:679))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3302:3302:3302) (3520:3520:3520))
+        (PORT datab (199:199:199) (226:226:226))
+        (PORT datac (167:167:167) (193:193:193))
+        (PORT datad (3228:3228:3228) (3447:3447:3447))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3194:3194:3194) (3393:3393:3393))
+        (PORT datab (198:198:198) (223:223:223))
+        (PORT datac (1337:1337:1337) (1300:1300:1300))
+        (PORT datad (1538:1538:1538) (1552:1552:1552))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (495:495:495) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1376:1376:1376) (1341:1341:1341))
+        (PORT datab (198:198:198) (222:222:222))
+        (PORT datac (1511:1511:1511) (1526:1526:1526))
+        (PORT datad (2863:2863:2863) (3084:3084:3084))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3214:3214:3214) (3433:3433:3433))
+        (PORT datab (200:200:200) (226:226:226))
+        (PORT datac (1339:1339:1339) (1302:1302:1302))
+        (PORT datad (2935:2935:2935) (3136:3136:3136))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (679:679:679))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2890:2890:2890) (3096:3096:3096))
+        (PORT datab (197:197:197) (224:224:224))
+        (PORT datac (1338:1338:1338) (1300:1300:1300))
+        (PORT datad (2925:2925:2925) (3125:3125:3125))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1376:1376:1376) (1341:1341:1341))
+        (PORT datab (2959:2959:2959) (3154:3154:3154))
+        (PORT datac (3014:3014:3014) (3207:3207:3207))
+        (PORT datad (165:165:165) (186:186:186))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2846:2846:2846) (3024:3024:3024))
+        (PORT datab (803:803:803) (819:819:819))
+        (PORT datac (2869:2869:2869) (3058:3058:3058))
+        (PORT datad (1267:1267:1267) (1254:1254:1254))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2863:2863:2863) (3046:3046:3046))
+        (PORT datab (802:802:802) (818:818:818))
+        (PORT datac (2820:2820:2820) (3004:3004:3004))
+        (PORT datad (162:162:162) (184:184:184))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (769:769:769) (791:791:791))
+        (PORT datab (795:795:795) (811:811:811))
+        (PORT datac (3025:3025:3025) (3178:3178:3178))
+        (PORT datad (166:166:166) (189:189:189))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst8\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1379:1379:1379) (1343:1343:1343))
+        (PORT datac (3267:3267:3267) (3487:3487:3487))
+        (PORT datad (3163:3163:3163) (3414:3414:3414))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3305:3305:3305) (3523:3523:3523))
+        (PORT datab (196:196:196) (223:223:223))
+        (PORT datac (169:169:169) (195:195:195))
+        (PORT datad (3226:3226:3226) (3444:3444:3444))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3192:3192:3192) (3391:3391:3391))
+        (PORT datab (197:197:197) (222:222:222))
+        (PORT datac (1335:1335:1335) (1298:1298:1298))
+        (PORT datad (1536:1536:1536) (1550:1550:1550))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1379:1379:1379) (1343:1343:1343))
+        (PORT datab (197:197:197) (222:222:222))
+        (PORT datac (1509:1509:1509) (1524:1524:1524))
+        (PORT datad (2865:2865:2865) (3086:3086:3086))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3210:3210:3210) (3429:3429:3429))
+        (PORT datab (197:197:197) (223:223:223))
+        (PORT datac (1337:1337:1337) (1300:1300:1300))
+        (PORT datad (2936:2936:2936) (3137:3137:3137))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2889:2889:2889) (3094:3094:3094))
+        (PORT datab (198:198:198) (225:225:225))
+        (PORT datac (1336:1336:1336) (1299:1299:1299))
+        (PORT datad (2923:2923:2923) (3123:3123:3123))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1379:1379:1379) (1343:1343:1343))
+        (PORT datab (2962:2962:2962) (3157:3157:3157))
+        (PORT datac (3012:3012:3012) (3204:3204:3204))
+        (PORT datad (164:164:164) (185:185:185))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2842:2842:2842) (3020:3020:3020))
+        (PORT datab (794:794:794) (811:811:811))
+        (PORT datac (2870:2870:2870) (3060:3060:3060))
+        (PORT datad (1264:1264:1264) (1249:1249:1249))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2865:2865:2865) (3049:3049:3049))
+        (PORT datab (793:793:793) (810:810:810))
+        (PORT datac (2816:2816:2816) (2998:2998:2998))
+        (PORT datad (167:167:167) (189:189:189))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (771:771:771) (793:793:793))
+        (PORT datab (792:792:792) (809:809:809))
+        (PORT datac (3024:3024:3024) (3177:3177:3177))
+        (PORT datad (167:167:167) (190:190:190))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..65f689a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_slow.vho
@@ -0,0 +1,978 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:56:52"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder_NO_BUS IS
+    PORT (
+	Cout : OUT std_logic;
+	X9 : IN std_logic;
+	Y9 : IN std_logic;
+	ENY : IN std_logic;
+	X8 : IN std_logic;
+	Y8 : IN std_logic;
+	X7 : IN std_logic;
+	Y7 : IN std_logic;
+	X6 : IN std_logic;
+	Y6 : IN std_logic;
+	X5 : IN std_logic;
+	Y5 : IN std_logic;
+	X4 : IN std_logic;
+	Y4 : IN std_logic;
+	X3 : IN std_logic;
+	Y3 : IN std_logic;
+	X2 : IN std_logic;
+	Y2 : IN std_logic;
+	X1 : IN std_logic;
+	Y1 : IN std_logic;
+	X0 : IN std_logic;
+	Y0 : IN std_logic;
+	S0 : OUT std_logic;
+	S1 : OUT std_logic;
+	S2 : OUT std_logic;
+	S3 : OUT std_logic;
+	S4 : OUT std_logic;
+	S5 : OUT std_logic;
+	S6 : OUT std_logic;
+	S7 : OUT std_logic;
+	S8 : OUT std_logic;
+	S9 : OUT std_logic
+	);
+END ten_bit_adder_NO_BUS;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S0	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S1	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S2	=>  Location: PIN_N11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S3	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S4	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S5	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S6	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S7	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S8	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S9	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y9	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENY	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y8	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y7	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y6	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y5	=>  Location: PIN_M13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y4	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y3	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y2	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y0	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X0	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y1	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X1	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X2	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X3	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X4	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X5	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X6	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X7	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X8	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X9	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder_NO_BUS IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X9 : std_logic;
+SIGNAL ww_Y9 : std_logic;
+SIGNAL ww_ENY : std_logic;
+SIGNAL ww_X8 : std_logic;
+SIGNAL ww_Y8 : std_logic;
+SIGNAL ww_X7 : std_logic;
+SIGNAL ww_Y7 : std_logic;
+SIGNAL ww_X6 : std_logic;
+SIGNAL ww_Y6 : std_logic;
+SIGNAL ww_X5 : std_logic;
+SIGNAL ww_Y5 : std_logic;
+SIGNAL ww_X4 : std_logic;
+SIGNAL ww_Y4 : std_logic;
+SIGNAL ww_X3 : std_logic;
+SIGNAL ww_Y3 : std_logic;
+SIGNAL ww_X2 : std_logic;
+SIGNAL ww_Y2 : std_logic;
+SIGNAL ww_X1 : std_logic;
+SIGNAL ww_Y1 : std_logic;
+SIGNAL ww_X0 : std_logic;
+SIGNAL ww_Y0 : std_logic;
+SIGNAL ww_S0 : std_logic;
+SIGNAL ww_S1 : std_logic;
+SIGNAL ww_S2 : std_logic;
+SIGNAL ww_S3 : std_logic;
+SIGNAL ww_S4 : std_logic;
+SIGNAL ww_S5 : std_logic;
+SIGNAL ww_S6 : std_logic;
+SIGNAL ww_S7 : std_logic;
+SIGNAL ww_S8 : std_logic;
+SIGNAL ww_S9 : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S0~output_o\ : std_logic;
+SIGNAL \S1~output_o\ : std_logic;
+SIGNAL \S2~output_o\ : std_logic;
+SIGNAL \S3~output_o\ : std_logic;
+SIGNAL \S4~output_o\ : std_logic;
+SIGNAL \S5~output_o\ : std_logic;
+SIGNAL \S6~output_o\ : std_logic;
+SIGNAL \S7~output_o\ : std_logic;
+SIGNAL \S8~output_o\ : std_logic;
+SIGNAL \S9~output_o\ : std_logic;
+SIGNAL \Y9~input_o\ : std_logic;
+SIGNAL \ENY~input_o\ : std_logic;
+SIGNAL \X9~input_o\ : std_logic;
+SIGNAL \X8~input_o\ : std_logic;
+SIGNAL \Y8~input_o\ : std_logic;
+SIGNAL \X7~input_o\ : std_logic;
+SIGNAL \Y7~input_o\ : std_logic;
+SIGNAL \Y6~input_o\ : std_logic;
+SIGNAL \X6~input_o\ : std_logic;
+SIGNAL \X5~input_o\ : std_logic;
+SIGNAL \Y4~input_o\ : std_logic;
+SIGNAL \Y2~input_o\ : std_logic;
+SIGNAL \X0~input_o\ : std_logic;
+SIGNAL \Y0~input_o\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+SIGNAL \Y1~input_o\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \X1~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \X2~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \X3~input_o\ : std_logic;
+SIGNAL \Y3~input_o\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \X4~input_o\ : std_logic;
+SIGNAL \inst12|inst3~0_combout\ : std_logic;
+SIGNAL \Y5~input_o\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \inst8|inst~combout\ : std_logic;
+SIGNAL \inst9|inst2~combout\ : std_logic;
+SIGNAL \inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst16|inst2~0_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X9 <= X9;
+ww_Y9 <= Y9;
+ww_ENY <= ENY;
+ww_X8 <= X8;
+ww_Y8 <= Y8;
+ww_X7 <= X7;
+ww_Y7 <= Y7;
+ww_X6 <= X6;
+ww_Y6 <= Y6;
+ww_X5 <= X5;
+ww_Y5 <= Y5;
+ww_X4 <= X4;
+ww_Y4 <= Y4;
+ww_X3 <= X3;
+ww_Y3 <= Y3;
+ww_X2 <= X2;
+ww_Y2 <= Y2;
+ww_X1 <= X1;
+ww_Y1 <= Y1;
+ww_X0 <= X0;
+ww_Y0 <= Y0;
+S0 <= ww_S0;
+S1 <= ww_S1;
+S2 <= ww_S2;
+S3 <= ww_S3;
+S4 <= ww_S4;
+S5 <= ww_S5;
+S6 <= ww_S6;
+S7 <= ww_S7;
+S8 <= ww_S8;
+S9 <= ww_S9;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X20_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\S0~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8|inst~combout\,
+	devoe => ww_devoe,
+	o => \S0~output_o\);
+
+-- Location: IOOBUF_X33_Y14_N2
+\S1~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9|inst2~combout\,
+	devoe => ww_devoe,
+	o => \S1~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N2
+\S2~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst10|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S2~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N9
+\S3~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst11|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S3~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S4~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst12|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S4~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\S5~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst13|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S5~output_o\);
+
+-- Location: IOOBUF_X33_Y10_N9
+\S6~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S6~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N9
+\S7~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S7~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N9
+\S8~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst16|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S8~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N2
+\S9~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S9~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y9,
+	o => \Y9~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\ENY~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_ENY,
+	o => \ENY~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\X9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X9,
+	o => \X9~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\X8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X8,
+	o => \X8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\Y8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y8,
+	o => \Y8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\X7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X7,
+	o => \X7~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y7,
+	o => \Y7~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N1
+\Y6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y6,
+	o => \Y6~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N1
+\X6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X6,
+	o => \X6~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N8
+\X5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X5,
+	o => \X5~input_o\);
+
+-- Location: IOIBUF_X29_Y0_N1
+\Y4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y4,
+	o => \Y4~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\Y2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y2,
+	o => \Y2~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N8
+\X0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X0,
+	o => \X0~input_o\);
+
+-- Location: IOIBUF_X26_Y31_N1
+\Y0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y0,
+	o => \Y0~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N0
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\ENY~input_o\ & \Y0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst6~combout\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y1,
+	o => \Y1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N26
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\ENY~input_o\ & \Y1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y1~input_o\,
+	combout => \inst7~combout\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\X1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X1,
+	o => \X1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N20
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\inst7~combout\ & ((\X1~input_o\) # ((\X0~input_o\ & \inst6~combout\)))) # (!\inst7~combout\ & (\X0~input_o\ & (\inst6~combout\ & \X1~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X2,
+	o => \X2~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N14
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\inst9|inst3~0_combout\ & ((\X2~input_o\) # ((\Y2~input_o\ & \ENY~input_o\)))) # (!\inst9|inst3~0_combout\ & (\Y2~input_o\ & (\ENY~input_o\ & \X2~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X3,
+	o => \X3~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Y3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y3,
+	o => \Y3~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N24
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\inst10|inst3~0_combout\ & ((\X3~input_o\) # ((\ENY~input_o\ & \Y3~input_o\)))) # (!\inst10|inst3~0_combout\ & (\ENY~input_o\ & (\X3~input_o\ & \Y3~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\X4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X4,
+	o => \X4~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N2
+\inst12|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst3~0_combout\ = (\inst11|inst3~0_combout\ & ((\X4~input_o\) # ((\Y4~input_o\ & \ENY~input_o\)))) # (!\inst11|inst3~0_combout\ & (\Y4~input_o\ & (\ENY~input_o\ & \X4~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y10_N1
+\Y5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y5,
+	o => \Y5~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N12
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X5~input_o\ & ((\inst12|inst3~0_combout\) # ((\ENY~input_o\ & \Y5~input_o\)))) # (!\X5~input_o\ & (\inst12|inst3~0_combout\ & (\ENY~input_o\ & \Y5~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N22
+\inst14|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst3~0_combout\ = (\X6~input_o\ & ((\inst13|inst3~0_combout\) # ((\ENY~input_o\ & \Y6~input_o\)))) # (!\X6~input_o\ & (\ENY~input_o\ & (\Y6~input_o\ & \inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N0
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\X7~input_o\ & ((\inst14|inst3~0_combout\) # ((\ENY~input_o\ & \Y7~input_o\)))) # (!\X7~input_o\ & (\ENY~input_o\ & (\Y7~input_o\ & \inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N2
+\inst16|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst3~0_combout\ = (\X8~input_o\ & ((\inst15|inst3~0_combout\) # ((\ENY~input_o\ & \Y8~input_o\)))) # (!\X8~input_o\ & (\ENY~input_o\ & (\Y8~input_o\ & \inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N20
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\X9~input_o\ & ((\inst16|inst3~0_combout\) # ((\Y9~input_o\ & \ENY~input_o\)))) # (!\X9~input_o\ & (\Y9~input_o\ & (\ENY~input_o\ & \inst16|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N8
+\inst8|inst\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst8|inst~combout\ = \X0~input_o\ $ (((\ENY~input_o\ & \Y0~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datac => \X0~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst8|inst~combout\);
+
+-- Location: LCCOMB_X25_Y7_N10
+\inst9|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~combout\ = \inst7~combout\ $ (\X1~input_o\ $ (((\X0~input_o\ & \inst6~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst2~combout\);
+
+-- Location: LCCOMB_X25_Y7_N28
+\inst10|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst2~0_combout\ = \inst9|inst3~0_combout\ $ (\X2~input_o\ $ (((\Y2~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N6
+\inst11|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~0_combout\ = \inst10|inst3~0_combout\ $ (\X3~input_o\ $ (((\ENY~input_o\ & \Y3~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N16
+\inst12|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst2~0_combout\ = \inst11|inst3~0_combout\ $ (\X4~input_o\ $ (((\Y4~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N18
+\inst13|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst2~0_combout\ = \X5~input_o\ $ (\inst12|inst3~0_combout\ $ (((\ENY~input_o\ & \Y5~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001100110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N4
+\inst14|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst2~0_combout\ = \X6~input_o\ $ (\inst13|inst3~0_combout\ $ (((\ENY~input_o\ & \Y6~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N22
+\inst15|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst2~0_combout\ = \X7~input_o\ $ (\inst14|inst3~0_combout\ $ (((\ENY~input_o\ & \Y7~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N24
+\inst16|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst2~0_combout\ = \X8~input_o\ $ (\inst15|inst3~0_combout\ $ (((\ENY~input_o\ & \Y8~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N26
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X9~input_o\ $ (\inst16|inst3~0_combout\ $ (((\Y9~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S0 <= \S0~output_o\;
+
+ww_S1 <= \S1~output_o\;
+
+ww_S2 <= \S2~output_o\;
+
+ww_S3 <= \S3~output_o\;
+
+ww_S4 <= \S4~output_o\;
+
+ww_S5 <= \S5~output_o\;
+
+ww_S6 <= \S6~output_o\;
+
+ww_S7 <= \S7~output_o\;
+
+ww_S8 <= \S8~output_o\;
+
+ww_S9 <= \S9~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..8762708
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,664 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder_NO_BUS")
+  (DATE "02/18/2016 22:56:52")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (887:887:887) (852:852:852))
+        (IOPATH i o (2629:2629:2629) (2527:2527:2527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S0\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1329:1329:1329) (1326:1326:1326))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1354:1354:1354) (1347:1347:1347))
+        (IOPATH i o (2579:2579:2579) (2476:2476:2476))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S2\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1078:1078:1078) (1076:1076:1076))
+        (IOPATH i o (2639:2639:2639) (2537:2537:2537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S3\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2007:2007:2007) (2046:2046:2046))
+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S4\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1091:1091:1091) (1075:1075:1075))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S5\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1279:1279:1279) (1270:1270:1270))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S6\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1036:1036:1036) (1032:1032:1032))
+        (IOPATH i o (2609:2609:2609) (2506:2506:2506))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S7\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (463:463:463) (446:446:446))
+        (IOPATH i o (2544:2544:2544) (2446:2446:2446))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S8\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (922:922:922) (884:884:884))
+        (IOPATH i o (3387:3387:3387) (3344:3344:3344))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S9\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (476:476:476) (460:460:460))
+        (IOPATH i o (3387:3387:3387) (3344:3344:3344))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\ENY\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (497:497:497) (671:671:671))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (555:555:555) (728:728:728))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1504:1504:1504) (1428:1428:1428))
+        (PORT datad (3628:3628:3628) (3964:3964:3964))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1500:1500:1500) (1425:1425:1425))
+        (PORT datad (3561:3561:3561) (3833:3833:3833))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (545:545:545) (718:718:718))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3777:3777:3777) (4079:4079:4079))
+        (PORT datab (215:215:215) (252:252:252))
+        (PORT datac (183:183:183) (215:215:215))
+        (PORT datad (3697:3697:3697) (4000:4000:4000))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3663:3663:3663) (3937:3937:3937))
+        (PORT datab (214:214:214) (249:249:249))
+        (PORT datac (1502:1502:1502) (1426:1426:1426))
+        (PORT datad (1715:1715:1715) (1691:1691:1691))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1547:1547:1547) (1471:1471:1471))
+        (PORT datab (214:214:214) (249:249:249))
+        (PORT datac (1684:1684:1684) (1674:1674:1674))
+        (PORT datad (3302:3302:3302) (3593:3593:3593))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3684:3684:3684) (3979:3979:3979))
+        (PORT datab (216:216:216) (252:252:252))
+        (PORT datac (1504:1504:1504) (1428:1428:1428))
+        (PORT datad (3374:3374:3374) (3649:3649:3649))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (545:545:545) (718:718:718))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3338:3338:3338) (3608:3608:3608))
+        (PORT datab (213:213:213) (250:250:250))
+        (PORT datac (1503:1503:1503) (1427:1427:1427))
+        (PORT datad (3366:3366:3366) (3635:3635:3635))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1547:1547:1547) (1471:1471:1471))
+        (PORT datab (3404:3404:3404) (3671:3671:3671))
+        (PORT datac (3464:3464:3464) (3738:3738:3738))
+        (PORT datad (181:181:181) (207:207:207))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3287:3287:3287) (3529:3529:3529))
+        (PORT datab (901:901:901) (898:898:898))
+        (PORT datac (3320:3320:3320) (3566:3566:3566))
+        (PORT datad (1364:1364:1364) (1401:1401:1401))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3304:3304:3304) (3555:3555:3555))
+        (PORT datab (901:901:901) (897:897:897))
+        (PORT datac (3255:3255:3255) (3508:3508:3508))
+        (PORT datad (178:178:178) (205:205:205))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (864:864:864) (870:870:870))
+        (PORT datab (893:893:893) (891:891:891))
+        (PORT datac (3485:3485:3485) (3702:3702:3702))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst8\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1473:1473:1473))
+        (PORT datac (3741:3741:3741) (4041:4041:4041))
+        (PORT datad (3629:3629:3629) (3965:3965:3965))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3780:3780:3780) (4082:4082:4082))
+        (PORT datab (213:213:213) (250:250:250))
+        (PORT datac (185:185:185) (217:217:217))
+        (PORT datad (3695:3695:3695) (3998:3998:3998))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3660:3660:3660) (3935:3935:3935))
+        (PORT datab (213:213:213) (249:249:249))
+        (PORT datac (1500:1500:1500) (1424:1424:1424))
+        (PORT datad (1712:1712:1712) (1688:1688:1688))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1473:1473:1473))
+        (PORT datab (213:213:213) (248:248:248))
+        (PORT datac (1682:1682:1682) (1672:1672:1672))
+        (PORT datad (3304:3304:3304) (3595:3595:3595))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3681:3681:3681) (3975:3975:3975))
+        (PORT datab (214:214:214) (250:250:250))
+        (PORT datac (1502:1502:1502) (1426:1426:1426))
+        (PORT datad (3375:3375:3375) (3651:3651:3651))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3336:3336:3336) (3606:3606:3606))
+        (PORT datab (215:215:215) (252:252:252))
+        (PORT datac (1501:1501:1501) (1425:1425:1425))
+        (PORT datad (3365:3365:3365) (3633:3633:3633))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1474:1474:1474))
+        (PORT datab (3406:3406:3406) (3674:3674:3674))
+        (PORT datac (3462:3462:3462) (3735:3735:3735))
+        (PORT datad (180:180:180) (206:206:206))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3283:3283:3283) (3525:3525:3525))
+        (PORT datab (893:893:893) (890:890:890))
+        (PORT datac (3321:3321:3321) (3567:3567:3567))
+        (PORT datad (1360:1360:1360) (1397:1397:1397))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3307:3307:3307) (3558:3558:3558))
+        (PORT datab (892:892:892) (890:890:890))
+        (PORT datac (3250:3250:3250) (3503:3503:3503))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (865:865:865) (871:871:871))
+        (PORT datab (891:891:891) (889:889:889))
+        (PORT datac (3484:3484:3484) (3701:3701:3701))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..65f689a
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_fast.vho
@@ -0,0 +1,978 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/18/2016 22:56:52"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_bit_adder_NO_BUS IS
+    PORT (
+	Cout : OUT std_logic;
+	X9 : IN std_logic;
+	Y9 : IN std_logic;
+	ENY : IN std_logic;
+	X8 : IN std_logic;
+	Y8 : IN std_logic;
+	X7 : IN std_logic;
+	Y7 : IN std_logic;
+	X6 : IN std_logic;
+	Y6 : IN std_logic;
+	X5 : IN std_logic;
+	Y5 : IN std_logic;
+	X4 : IN std_logic;
+	Y4 : IN std_logic;
+	X3 : IN std_logic;
+	Y3 : IN std_logic;
+	X2 : IN std_logic;
+	Y2 : IN std_logic;
+	X1 : IN std_logic;
+	Y1 : IN std_logic;
+	X0 : IN std_logic;
+	Y0 : IN std_logic;
+	S0 : OUT std_logic;
+	S1 : OUT std_logic;
+	S2 : OUT std_logic;
+	S3 : OUT std_logic;
+	S4 : OUT std_logic;
+	S5 : OUT std_logic;
+	S6 : OUT std_logic;
+	S7 : OUT std_logic;
+	S8 : OUT std_logic;
+	S9 : OUT std_logic
+	);
+END ten_bit_adder_NO_BUS;
+
+-- Design Ports Information
+-- Cout	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S0	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S1	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S2	=>  Location: PIN_N11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S3	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S4	=>  Location: PIN_K11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S5	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S6	=>  Location: PIN_N13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S7	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S8	=>  Location: PIN_K8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- S9	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y9	=>  Location: PIN_M7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENY	=>  Location: PIN_N7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y8	=>  Location: PIN_N6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y7	=>  Location: PIN_N8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y6	=>  Location: PIN_M9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y5	=>  Location: PIN_M13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y4	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y3	=>  Location: PIN_N10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y2	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y0	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X0	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Y1	=>  Location: PIN_K10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X1	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X2	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X3	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X4	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X5	=>  Location: PIN_L9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X6	=>  Location: PIN_K9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X7	=>  Location: PIN_M6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X8	=>  Location: PIN_N4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- X9	=>  Location: PIN_L4,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_bit_adder_NO_BUS IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Cout : std_logic;
+SIGNAL ww_X9 : std_logic;
+SIGNAL ww_Y9 : std_logic;
+SIGNAL ww_ENY : std_logic;
+SIGNAL ww_X8 : std_logic;
+SIGNAL ww_Y8 : std_logic;
+SIGNAL ww_X7 : std_logic;
+SIGNAL ww_Y7 : std_logic;
+SIGNAL ww_X6 : std_logic;
+SIGNAL ww_Y6 : std_logic;
+SIGNAL ww_X5 : std_logic;
+SIGNAL ww_Y5 : std_logic;
+SIGNAL ww_X4 : std_logic;
+SIGNAL ww_Y4 : std_logic;
+SIGNAL ww_X3 : std_logic;
+SIGNAL ww_Y3 : std_logic;
+SIGNAL ww_X2 : std_logic;
+SIGNAL ww_Y2 : std_logic;
+SIGNAL ww_X1 : std_logic;
+SIGNAL ww_Y1 : std_logic;
+SIGNAL ww_X0 : std_logic;
+SIGNAL ww_Y0 : std_logic;
+SIGNAL ww_S0 : std_logic;
+SIGNAL ww_S1 : std_logic;
+SIGNAL ww_S2 : std_logic;
+SIGNAL ww_S3 : std_logic;
+SIGNAL ww_S4 : std_logic;
+SIGNAL ww_S5 : std_logic;
+SIGNAL ww_S6 : std_logic;
+SIGNAL ww_S7 : std_logic;
+SIGNAL ww_S8 : std_logic;
+SIGNAL ww_S9 : std_logic;
+SIGNAL \Cout~output_o\ : std_logic;
+SIGNAL \S0~output_o\ : std_logic;
+SIGNAL \S1~output_o\ : std_logic;
+SIGNAL \S2~output_o\ : std_logic;
+SIGNAL \S3~output_o\ : std_logic;
+SIGNAL \S4~output_o\ : std_logic;
+SIGNAL \S5~output_o\ : std_logic;
+SIGNAL \S6~output_o\ : std_logic;
+SIGNAL \S7~output_o\ : std_logic;
+SIGNAL \S8~output_o\ : std_logic;
+SIGNAL \S9~output_o\ : std_logic;
+SIGNAL \Y9~input_o\ : std_logic;
+SIGNAL \ENY~input_o\ : std_logic;
+SIGNAL \X9~input_o\ : std_logic;
+SIGNAL \X8~input_o\ : std_logic;
+SIGNAL \Y8~input_o\ : std_logic;
+SIGNAL \X7~input_o\ : std_logic;
+SIGNAL \Y7~input_o\ : std_logic;
+SIGNAL \Y6~input_o\ : std_logic;
+SIGNAL \X6~input_o\ : std_logic;
+SIGNAL \X5~input_o\ : std_logic;
+SIGNAL \Y4~input_o\ : std_logic;
+SIGNAL \Y2~input_o\ : std_logic;
+SIGNAL \X0~input_o\ : std_logic;
+SIGNAL \Y0~input_o\ : std_logic;
+SIGNAL \inst6~combout\ : std_logic;
+SIGNAL \Y1~input_o\ : std_logic;
+SIGNAL \inst7~combout\ : std_logic;
+SIGNAL \X1~input_o\ : std_logic;
+SIGNAL \inst9|inst3~0_combout\ : std_logic;
+SIGNAL \X2~input_o\ : std_logic;
+SIGNAL \inst10|inst3~0_combout\ : std_logic;
+SIGNAL \X3~input_o\ : std_logic;
+SIGNAL \Y3~input_o\ : std_logic;
+SIGNAL \inst11|inst3~0_combout\ : std_logic;
+SIGNAL \X4~input_o\ : std_logic;
+SIGNAL \inst12|inst3~0_combout\ : std_logic;
+SIGNAL \Y5~input_o\ : std_logic;
+SIGNAL \inst13|inst3~0_combout\ : std_logic;
+SIGNAL \inst14|inst3~0_combout\ : std_logic;
+SIGNAL \inst15|inst3~0_combout\ : std_logic;
+SIGNAL \inst16|inst3~0_combout\ : std_logic;
+SIGNAL \inst17|inst3~0_combout\ : std_logic;
+SIGNAL \inst8|inst~combout\ : std_logic;
+SIGNAL \inst9|inst2~combout\ : std_logic;
+SIGNAL \inst10|inst2~0_combout\ : std_logic;
+SIGNAL \inst11|inst2~0_combout\ : std_logic;
+SIGNAL \inst12|inst2~0_combout\ : std_logic;
+SIGNAL \inst13|inst2~0_combout\ : std_logic;
+SIGNAL \inst14|inst2~0_combout\ : std_logic;
+SIGNAL \inst15|inst2~0_combout\ : std_logic;
+SIGNAL \inst16|inst2~0_combout\ : std_logic;
+SIGNAL \inst17|inst2~0_combout\ : std_logic;
+
+BEGIN
+
+Cout <= ww_Cout;
+ww_X9 <= X9;
+ww_Y9 <= Y9;
+ww_ENY <= ENY;
+ww_X8 <= X8;
+ww_Y8 <= Y8;
+ww_X7 <= X7;
+ww_Y7 <= Y7;
+ww_X6 <= X6;
+ww_Y6 <= Y6;
+ww_X5 <= X5;
+ww_Y5 <= Y5;
+ww_X4 <= X4;
+ww_Y4 <= Y4;
+ww_X3 <= X3;
+ww_Y3 <= Y3;
+ww_X2 <= X2;
+ww_Y2 <= Y2;
+ww_X1 <= X1;
+ww_Y1 <= Y1;
+ww_X0 <= X0;
+ww_Y0 <= Y0;
+S0 <= ww_S0;
+S1 <= ww_S1;
+S2 <= ww_S2;
+S3 <= ww_S3;
+S4 <= ww_S4;
+S5 <= ww_S5;
+S6 <= ww_S6;
+S7 <= ww_S7;
+S8 <= ww_S8;
+S9 <= ww_S9;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+-- Location: IOOBUF_X20_Y0_N2
+\Cout~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst3~0_combout\,
+	devoe => ww_devoe,
+	o => \Cout~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\S0~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8|inst~combout\,
+	devoe => ww_devoe,
+	o => \S0~output_o\);
+
+-- Location: IOOBUF_X33_Y14_N2
+\S1~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9|inst2~combout\,
+	devoe => ww_devoe,
+	o => \S1~output_o\);
+
+-- Location: IOOBUF_X26_Y0_N2
+\S2~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst10|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S2~output_o\);
+
+-- Location: IOOBUF_X33_Y24_N9
+\S3~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst11|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S3~output_o\);
+
+-- Location: IOOBUF_X33_Y11_N2
+\S4~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst12|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S4~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\S5~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst13|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S5~output_o\);
+
+-- Location: IOOBUF_X33_Y10_N9
+\S6~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst14|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S6~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N9
+\S7~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst15|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S7~output_o\);
+
+-- Location: IOOBUF_X22_Y0_N9
+\S8~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst16|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S8~output_o\);
+
+-- Location: IOOBUF_X14_Y0_N2
+\S9~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst17|inst2~0_combout\,
+	devoe => ww_devoe,
+	o => \S9~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N8
+\Y9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y9,
+	o => \Y9~input_o\);
+
+-- Location: IOIBUF_X16_Y0_N1
+\ENY~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_ENY,
+	o => \ENY~input_o\);
+
+-- Location: IOIBUF_X8_Y0_N8
+\X9~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X9,
+	o => \X9~input_o\);
+
+-- Location: IOIBUF_X10_Y0_N8
+\X8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X8,
+	o => \X8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N1
+\Y8~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y8,
+	o => \Y8~input_o\);
+
+-- Location: IOIBUF_X12_Y0_N8
+\X7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X7,
+	o => \X7~input_o\);
+
+-- Location: IOIBUF_X20_Y0_N8
+\Y7~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y7,
+	o => \Y7~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N1
+\Y6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y6,
+	o => \Y6~input_o\);
+
+-- Location: IOIBUF_X22_Y0_N1
+\X6~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X6,
+	o => \X6~input_o\);
+
+-- Location: IOIBUF_X24_Y0_N8
+\X5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X5,
+	o => \X5~input_o\);
+
+-- Location: IOIBUF_X29_Y0_N1
+\Y4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y4,
+	o => \Y4~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N1
+\Y2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y2,
+	o => \Y2~input_o\);
+
+-- Location: IOIBUF_X33_Y12_N8
+\X0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X0,
+	o => \X0~input_o\);
+
+-- Location: IOIBUF_X26_Y31_N1
+\Y0~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y0,
+	o => \Y0~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N0
+inst6 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~combout\ = (\ENY~input_o\ & \Y0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst6~combout\);
+
+-- Location: IOIBUF_X31_Y0_N8
+\Y1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y1,
+	o => \Y1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N26
+inst7 : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst7~combout\ = (\ENY~input_o\ & \Y1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \ENY~input_o\,
+	datad => \Y1~input_o\,
+	combout => \inst7~combout\);
+
+-- Location: IOIBUF_X33_Y15_N1
+\X1~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X1,
+	o => \X1~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N20
+\inst9|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst3~0_combout\ = (\inst7~combout\ & ((\X1~input_o\) # ((\X0~input_o\ & \inst6~combout\)))) # (!\inst7~combout\ & (\X0~input_o\ & (\inst6~combout\ & \X1~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\X2~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X2,
+	o => \X2~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N14
+\inst10|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst3~0_combout\ = (\inst9|inst3~0_combout\ & ((\X2~input_o\) # ((\Y2~input_o\ & \ENY~input_o\)))) # (!\inst9|inst3~0_combout\ & (\Y2~input_o\ & (\ENY~input_o\ & \X2~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\X3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X3,
+	o => \X3~input_o\);
+
+-- Location: IOIBUF_X26_Y0_N8
+\Y3~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y3,
+	o => \Y3~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N24
+\inst11|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst3~0_combout\ = (\inst10|inst3~0_combout\ & ((\X3~input_o\) # ((\ENY~input_o\ & \Y3~input_o\)))) # (!\inst10|inst3~0_combout\ & (\ENY~input_o\ & (\X3~input_o\ & \Y3~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\X4~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_X4,
+	o => \X4~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N2
+\inst12|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst3~0_combout\ = (\inst11|inst3~0_combout\ & ((\X4~input_o\) # ((\Y4~input_o\ & \ENY~input_o\)))) # (!\inst11|inst3~0_combout\ & (\Y4~input_o\ & (\ENY~input_o\ & \X4~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110110010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst3~0_combout\);
+
+-- Location: IOIBUF_X33_Y10_N1
+\Y5~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_Y5,
+	o => \Y5~input_o\);
+
+-- Location: LCCOMB_X25_Y7_N12
+\inst13|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst3~0_combout\ = (\X5~input_o\ & ((\inst12|inst3~0_combout\) # ((\ENY~input_o\ & \Y5~input_o\)))) # (!\X5~input_o\ & (\inst12|inst3~0_combout\ & (\ENY~input_o\ & \Y5~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110100010001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N22
+\inst14|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst3~0_combout\ = (\X6~input_o\ & ((\inst13|inst3~0_combout\) # ((\ENY~input_o\ & \Y6~input_o\)))) # (!\X6~input_o\ & (\ENY~input_o\ & (\Y6~input_o\ & \inst13|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N0
+\inst15|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst3~0_combout\ = (\X7~input_o\ & ((\inst14|inst3~0_combout\) # ((\ENY~input_o\ & \Y7~input_o\)))) # (!\X7~input_o\ & (\ENY~input_o\ & (\Y7~input_o\ & \inst14|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N2
+\inst16|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst3~0_combout\ = (\X8~input_o\ & ((\inst15|inst3~0_combout\) # ((\ENY~input_o\ & \Y8~input_o\)))) # (!\X8~input_o\ & (\ENY~input_o\ & (\Y8~input_o\ & \inst15|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst3~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N20
+\inst17|inst3~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst3~0_combout\ = (\X9~input_o\ & ((\inst16|inst3~0_combout\) # ((\Y9~input_o\ & \ENY~input_o\)))) # (!\X9~input_o\ & (\Y9~input_o\ & (\ENY~input_o\ & \inst16|inst3~0_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111100010000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst3~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N8
+\inst8|inst\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst8|inst~combout\ = \X0~input_o\ $ (((\ENY~input_o\ & \Y0~input_o\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datac => \X0~input_o\,
+	datad => \Y0~input_o\,
+	combout => \inst8|inst~combout\);
+
+-- Location: LCCOMB_X25_Y7_N10
+\inst9|inst2\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst9|inst2~combout\ = \inst7~combout\ $ (\X1~input_o\ $ (((\X0~input_o\ & \inst6~combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X0~input_o\,
+	datab => \inst6~combout\,
+	datac => \inst7~combout\,
+	datad => \X1~input_o\,
+	combout => \inst9|inst2~combout\);
+
+-- Location: LCCOMB_X25_Y7_N28
+\inst10|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst10|inst2~0_combout\ = \inst9|inst3~0_combout\ $ (\X2~input_o\ $ (((\Y2~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y2~input_o\,
+	datab => \inst9|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X2~input_o\,
+	combout => \inst10|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N6
+\inst11|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst11|inst2~0_combout\ = \inst10|inst3~0_combout\ $ (\X3~input_o\ $ (((\ENY~input_o\ & \Y3~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011000111100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \inst10|inst3~0_combout\,
+	datac => \X3~input_o\,
+	datad => \Y3~input_o\,
+	combout => \inst11|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N16
+\inst12|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst12|inst2~0_combout\ = \inst11|inst3~0_combout\ $ (\X4~input_o\ $ (((\Y4~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001001101101100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y4~input_o\,
+	datab => \inst11|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \X4~input_o\,
+	combout => \inst12|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N18
+\inst13|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst13|inst2~0_combout\ = \X5~input_o\ $ (\inst12|inst3~0_combout\ $ (((\ENY~input_o\ & \Y5~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001011001100110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X5~input_o\,
+	datab => \inst12|inst3~0_combout\,
+	datac => \ENY~input_o\,
+	datad => \Y5~input_o\,
+	combout => \inst13|inst2~0_combout\);
+
+-- Location: LCCOMB_X25_Y7_N4
+\inst14|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst14|inst2~0_combout\ = \X6~input_o\ $ (\inst13|inst3~0_combout\ $ (((\ENY~input_o\ & \Y6~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \ENY~input_o\,
+	datab => \Y6~input_o\,
+	datac => \X6~input_o\,
+	datad => \inst13|inst3~0_combout\,
+	combout => \inst14|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N22
+\inst15|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst15|inst2~0_combout\ = \X7~input_o\ $ (\inst14|inst3~0_combout\ $ (((\ENY~input_o\ & \Y7~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X7~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y7~input_o\,
+	datad => \inst14|inst3~0_combout\,
+	combout => \inst15|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N24
+\inst16|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst16|inst2~0_combout\ = \X8~input_o\ $ (\inst15|inst3~0_combout\ $ (((\ENY~input_o\ & \Y8~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1001010101101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \X8~input_o\,
+	datab => \ENY~input_o\,
+	datac => \Y8~input_o\,
+	datad => \inst15|inst3~0_combout\,
+	combout => \inst16|inst2~0_combout\);
+
+-- Location: LCCOMB_X16_Y1_N26
+\inst17|inst2~0\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst17|inst2~0_combout\ = \X9~input_o\ $ (\inst16|inst3~0_combout\ $ (((\Y9~input_o\ & \ENY~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000011101111000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \Y9~input_o\,
+	datab => \ENY~input_o\,
+	datac => \X9~input_o\,
+	datad => \inst16|inst3~0_combout\,
+	combout => \inst17|inst2~0_combout\);
+
+ww_Cout <= \Cout~output_o\;
+
+ww_S0 <= \S0~output_o\;
+
+ww_S1 <= \S1~output_o\;
+
+ww_S2 <= \S2~output_o\;
+
+ww_S3 <= \S3~output_o\;
+
+ww_S4 <= \S4~output_o\;
+
+ww_S5 <= \S5~output_o\;
+
+ww_S6 <= \S6~output_o\;
+
+ww_S7 <= \S7~output_o\;
+
+ww_S8 <= \S8~output_o\;
+
+ww_S9 <= \S9~output_o\;
+END structure;
+
+
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..9cb0d42
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,664 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder_NO_BUS")
+  (DATE "02/18/2016 22:56:52")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (463:463:463) (499:499:499))
+        (IOPATH i o (1600:1600:1600) (1589:1589:1589))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S0\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (741:741:741) (817:817:817))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (753:753:753) (832:832:832))
+        (IOPATH i o (1564:1564:1564) (1541:1541:1541))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S2\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (581:581:581) (643:643:643))
+        (IOPATH i o (1610:1610:1610) (1599:1599:1599))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S3\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1122:1122:1122) (1265:1265:1265))
+        (IOPATH i o (1723:1723:1723) (1675:1675:1675))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S4\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (599:599:599) (658:658:658))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S5\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (708:708:708) (778:778:778))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S6\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (574:574:574) (630:630:630))
+        (IOPATH i o (1594:1594:1594) (1571:1571:1571))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S7\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (236:236:236) (255:255:255))
+        (IOPATH i o (1555:1555:1555) (1528:1528:1528))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S8\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (481:481:481) (523:523:523))
+        (IOPATH i o (2180:2180:2180) (2171:2171:2171))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S9\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (243:243:243) (263:263:263))
+        (IOPATH i o (2180:2180:2180) (2171:2171:2171))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\ENY\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X9\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (272:272:272) (647:647:647))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y8\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y7\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X6\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (242:242:242) (617:617:617))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (293:293:293) (668:668:668))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (273:273:273) (648:648:648))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (272:272:272) (647:647:647))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (924:924:924) (817:817:817))
+        (PORT datad (2110:2110:2110) (2360:2360:2360))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (252:252:252) (627:627:627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (920:920:920) (814:814:814))
+        (PORT datad (2061:2061:2061) (2287:2287:2287))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (283:283:283) (658:658:658))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2181:2181:2181) (2433:2433:2433))
+        (PORT datab (114:114:114) (142:142:142))
+        (PORT datac (97:97:97) (118:118:118))
+        (PORT datad (2134:2134:2134) (2377:2377:2377))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2119:2119:2119) (2342:2342:2342))
+        (PORT datab (112:112:112) (138:138:138))
+        (PORT datac (922:922:922) (816:816:816))
+        (PORT datad (1064:1064:1064) (971:971:971))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (253:253:253) (628:628:628))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (838:838:838))
+        (PORT datab (112:112:112) (138:138:138))
+        (PORT datac (1050:1050:1050) (965:965:965))
+        (PORT datad (1923:1923:1923) (2136:2136:2136))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2132:2132:2132) (2382:2382:2382))
+        (PORT datab (114:114:114) (142:142:142))
+        (PORT datac (924:924:924) (817:817:817))
+        (PORT datad (1957:1957:1957) (2162:2162:2162))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (283:283:283) (658:658:658))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1935:1935:1935) (2139:2139:2139))
+        (PORT datab (112:112:112) (139:139:139))
+        (PORT datac (922:922:922) (816:816:816))
+        (PORT datad (1948:1948:1948) (2152:2152:2152))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (838:838:838))
+        (PORT datab (1980:1980:1980) (2186:2186:2186))
+        (PORT datac (1999:1999:1999) (2210:2210:2210))
+        (PORT datad (95:95:95) (114:114:114))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1906:1906:1906) (2092:2092:2092))
+        (PORT datab (549:549:549) (512:512:512))
+        (PORT datac (1926:1926:1926) (2117:2117:2117))
+        (PORT datad (754:754:754) (859:859:859))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1912:1912:1912) (2104:2104:2104))
+        (PORT datab (548:548:548) (512:512:512))
+        (PORT datac (1888:1888:1888) (2078:2078:2078))
+        (PORT datad (92:92:92) (112:112:112))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (523:523:523) (493:493:493))
+        (PORT datab (541:541:541) (506:506:506))
+        (PORT datac (2005:2005:2005) (2193:2193:2193))
+        (PORT datad (97:97:97) (117:117:117))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst8\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (840:840:840))
+        (PORT datac (2164:2164:2164) (2412:2412:2412))
+        (PORT datad (2111:2111:2111) (2361:2361:2361))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2183:2183:2183) (2436:2436:2436))
+        (PORT datab (112:112:112) (139:139:139))
+        (PORT datac (99:99:99) (120:120:120))
+        (PORT datad (2132:2132:2132) (2375:2375:2375))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2117:2117:2117) (2340:2340:2340))
+        (PORT datab (111:111:111) (138:138:138))
+        (PORT datac (920:920:920) (814:814:814))
+        (PORT datad (1061:1061:1061) (969:969:969))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (840:840:840))
+        (PORT datab (111:111:111) (138:138:138))
+        (PORT datac (1048:1048:1048) (964:964:964))
+        (PORT datad (1925:1925:1925) (2139:2139:2139))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2129:2129:2129) (2378:2378:2378))
+        (PORT datab (112:112:112) (139:139:139))
+        (PORT datac (921:921:921) (815:815:815))
+        (PORT datad (1958:1958:1958) (2163:2163:2163))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1934:1934:1934) (2137:2137:2137))
+        (PORT datab (114:114:114) (141:141:141))
+        (PORT datac (921:921:921) (815:815:815))
+        (PORT datad (1947:1947:1947) (2151:2151:2151))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (840:840:840))
+        (PORT datab (1983:1983:1983) (2189:2189:2189))
+        (PORT datac (1996:1996:1996) (2208:2208:2208))
+        (PORT datad (94:94:94) (113:113:113))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1902:1902:1902) (2088:2088:2088))
+        (PORT datab (541:541:541) (505:505:505))
+        (PORT datac (1927:1927:1927) (2119:2119:2119))
+        (PORT datad (750:750:750) (855:855:855))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1914:1914:1914) (2107:2107:2107))
+        (PORT datab (540:540:540) (504:504:504))
+        (PORT datac (1883:1883:1883) (2072:2072:2072))
+        (PORT datad (97:97:97) (117:117:117))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (525:525:525) (495:495:495))
+        (PORT datab (539:539:539) (504:504:504))
+        (PORT datac (2004:2004:2004) (2192:2192:2192))
+        (PORT datad (97:97:97) (118:118:118))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_modelsim.xrf b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_modelsim.xrf
new file mode 100644
index 0000000..33c4f5e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_modelsim.xrf
@@ -0,0 +1,57 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bsf
+source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cbx.xml
+design_name = ten_bit_adder_NO_BUS
+instance = comp, \Cout~output\, Cout~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S0~output\, S0~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S1~output\, S1~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S2~output\, S2~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S3~output\, S3~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S4~output\, S4~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S5~output\, S5~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S6~output\, S6~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S7~output\, S7~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S8~output\, S8~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \S9~output\, S9~output, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y9~input\, Y9~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \ENY~input\, ENY~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X9~input\, X9~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X8~input\, X8~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y8~input\, Y8~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X7~input\, X7~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y7~input\, Y7~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y6~input\, Y6~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X6~input\, X6~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X5~input\, X5~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y4~input\, Y4~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y2~input\, Y2~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X0~input\, X0~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y0~input\, Y0~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y1~input\, Y1~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \X1~input\, X1~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst9|inst3~0\, inst9|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \X2~input\, X2~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst10|inst3~0\, inst10|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \X3~input\, X3~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y3~input\, Y3~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst11|inst3~0\, inst11|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \X4~input\, X4~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst12|inst3~0\, inst12|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \Y5~input\, Y5~input, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst13|inst3~0\, inst13|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst14|inst3~0\, inst14|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst15|inst3~0\, inst15|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst16|inst3~0\, inst16|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst17|inst3~0\, inst17|inst3~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst8|inst\, inst8|inst, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst9|inst2\, inst9|inst2, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst10|inst2~0\, inst10|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst11|inst2~0\, inst11|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst12|inst2~0\, inst12|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst13|inst2~0\, inst13|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst14|inst2~0\, inst14|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst15|inst2~0\, inst15|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst16|inst2~0\, inst16|inst2~0, ten_bit_adder_NO_BUS, 1
+instance = comp, \inst17|inst2~0\, inst17|inst2~0, ten_bit_adder_NO_BUS, 1
diff --git a/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_vhd.sdo b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_vhd.sdo
new file mode 100644
index 0000000..8762708
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/simulation/modelsim/ten_bit_adder_NO_BUS_vhd.sdo
@@ -0,0 +1,664 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_bit_adder_NO_BUS")
+  (DATE "02/18/2016 22:56:52")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (887:887:887) (852:852:852))
+        (IOPATH i o (2629:2629:2629) (2527:2527:2527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S0\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1329:1329:1329) (1326:1326:1326))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S1\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1354:1354:1354) (1347:1347:1347))
+        (IOPATH i o (2579:2579:2579) (2476:2476:2476))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S2\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1078:1078:1078) (1076:1076:1076))
+        (IOPATH i o (2639:2639:2639) (2537:2537:2537))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S3\~output\\)
+    (DELAY
+      (ABSOLUTE
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+        (IOPATH i o (2735:2735:2735) (2664:2664:2664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S4\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1091:1091:1091) (1075:1075:1075))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
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+    (INSTANCE \\S5\~output\\)
+    (DELAY
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+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
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+    (DELAY
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+    (INSTANCE \\S8\~output\\)
+    (DELAY
+      (ABSOLUTE
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+        (IOPATH i o (3387:3387:3387) (3344:3344:3344))
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+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\S9\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (476:476:476) (460:460:460))
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+    (DELAY
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+    (INSTANCE \\X9\~input\\)
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+    (DELAY
+      (ABSOLUTE
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+    (DELAY
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+    (DELAY
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+    )
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+  (CELL
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+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1504:1504:1504) (1428:1428:1428))
+        (PORT datad (3628:3628:3628) (3964:3964:3964))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (507:507:507) (681:681:681))
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+    )
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+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1500:1500:1500) (1425:1425:1425))
+        (PORT datad (3561:3561:3561) (3833:3833:3833))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (545:545:545) (718:718:718))
+      )
+    )
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+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3777:3777:3777) (4079:4079:4079))
+        (PORT datab (215:215:215) (252:252:252))
+        (PORT datac (183:183:183) (215:215:215))
+        (PORT datad (3697:3697:3697) (4000:4000:4000))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3663:3663:3663) (3937:3937:3937))
+        (PORT datab (214:214:214) (249:249:249))
+        (PORT datac (1502:1502:1502) (1426:1426:1426))
+        (PORT datad (1715:1715:1715) (1691:1691:1691))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y3\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1547:1547:1547) (1471:1471:1471))
+        (PORT datab (214:214:214) (249:249:249))
+        (PORT datac (1684:1684:1684) (1674:1674:1674))
+        (PORT datad (3302:3302:3302) (3593:3593:3593))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\X4\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3684:3684:3684) (3979:3979:3979))
+        (PORT datab (216:216:216) (252:252:252))
+        (PORT datac (1504:1504:1504) (1428:1428:1428))
+        (PORT datad (3374:3374:3374) (3649:3649:3649))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\Y5\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (545:545:545) (718:718:718))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3338:3338:3338) (3608:3608:3608))
+        (PORT datab (213:213:213) (250:250:250))
+        (PORT datac (1503:1503:1503) (1427:1427:1427))
+        (PORT datad (3366:3366:3366) (3635:3635:3635))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1547:1547:1547) (1471:1471:1471))
+        (PORT datab (3404:3404:3404) (3671:3671:3671))
+        (PORT datac (3464:3464:3464) (3738:3738:3738))
+        (PORT datad (181:181:181) (207:207:207))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3287:3287:3287) (3529:3529:3529))
+        (PORT datab (901:901:901) (898:898:898))
+        (PORT datac (3320:3320:3320) (3566:3566:3566))
+        (PORT datad (1364:1364:1364) (1401:1401:1401))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3304:3304:3304) (3555:3555:3555))
+        (PORT datab (901:901:901) (897:897:897))
+        (PORT datac (3255:3255:3255) (3508:3508:3508))
+        (PORT datad (178:178:178) (205:205:205))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (864:864:864) (870:870:870))
+        (PORT datab (893:893:893) (891:891:891))
+        (PORT datac (3485:3485:3485) (3702:3702:3702))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst8\|inst\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1473:1473:1473))
+        (PORT datac (3741:3741:3741) (4041:4041:4041))
+        (PORT datad (3629:3629:3629) (3965:3965:3965))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst9\|inst2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3780:3780:3780) (4082:4082:4082))
+        (PORT datab (213:213:213) (250:250:250))
+        (PORT datac (185:185:185) (217:217:217))
+        (PORT datad (3695:3695:3695) (3998:3998:3998))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst10\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3660:3660:3660) (3935:3935:3935))
+        (PORT datab (213:213:213) (249:249:249))
+        (PORT datac (1500:1500:1500) (1424:1424:1424))
+        (PORT datad (1712:1712:1712) (1688:1688:1688))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst11\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1473:1473:1473))
+        (PORT datab (213:213:213) (248:248:248))
+        (PORT datac (1682:1682:1682) (1672:1672:1672))
+        (PORT datad (3304:3304:3304) (3595:3595:3595))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst12\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3681:3681:3681) (3975:3975:3975))
+        (PORT datab (214:214:214) (250:250:250))
+        (PORT datac (1502:1502:1502) (1426:1426:1426))
+        (PORT datad (3375:3375:3375) (3651:3651:3651))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst13\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3336:3336:3336) (3606:3606:3606))
+        (PORT datab (215:215:215) (252:252:252))
+        (PORT datac (1501:1501:1501) (1425:1425:1425))
+        (PORT datad (3365:3365:3365) (3633:3633:3633))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst14\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1550:1550:1550) (1474:1474:1474))
+        (PORT datab (3406:3406:3406) (3674:3674:3674))
+        (PORT datac (3462:3462:3462) (3735:3735:3735))
+        (PORT datad (180:180:180) (206:206:206))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst15\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3283:3283:3283) (3525:3525:3525))
+        (PORT datab (893:893:893) (890:890:890))
+        (PORT datac (3321:3321:3321) (3567:3567:3567))
+        (PORT datad (1360:1360:1360) (1397:1397:1397))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst16\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3307:3307:3307) (3558:3558:3558))
+        (PORT datab (892:892:892) (890:890:890))
+        (PORT datac (3250:3250:3250) (3503:3503:3503))
+        (PORT datad (182:182:182) (210:210:210))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst17\|inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (865:865:865) (871:871:871))
+        (PORT datab (891:891:891) (889:889:889))
+        (PORT datac (3484:3484:3484) (3701:3701:3701))
+        (PORT datad (183:183:183) (211:211:211))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
new file mode 100644
index 0000000..c4364be
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
@@ -0,0 +1,1872 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 320 448 488 464)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y0" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 464 488 480)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y1" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 480 488 496)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y2" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 496 488 512)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y3" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 512 488 528)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y4" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 528 488 544)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y5" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 84 12)(pt 84 4))
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 544 488 560)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y6" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 560 488 576)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y7" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 576 488 592)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y8" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 84 12)(pt 84 4))
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 592 488 608)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "Y9" (rect 5 0 19 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 280 488 296)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "X0" (rect 5 0 16 12)(font "Arial" ))
+	(pt 168 8)
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
+	(rect 320 296 488 312)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "X1" (rect 5 0 16 12)(font "Arial" ))
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 312 488 328)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "X2" (rect 5 0 16 12)(font "Arial" ))
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
+	(rect 320 328 488 344)
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+	(text "X3" (rect 5 0 16 12)(font "Arial" ))
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
+	(rect 320 344 488 360)
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+	(text "X4" (rect 5 0 16 12)(font "Arial" ))
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+		(line (pt 84 12)(pt 109 12))
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
+	(rect 320 360 488 376)
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
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+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 320 424 488 440)
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+	(pt 168 8)
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+		(line (pt 109 12)(pt 113 8))
+	)
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+)
+(pin
+	(input)
+	(rect 320 248 488 264)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "ENY" (rect 5 -2 29 10)(font "Arial" ))
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+)
+(pin
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+(connector
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+	(pt 648 1368)
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+	(pt 648 1368)
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diff --git a/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bsf b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bsf
new file mode 100644
index 0000000..3bd5c50
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bsf
@@ -0,0 +1,253 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 112 400)
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+	(text "inst" (rect 8 368 25 380)(font "Arial" ))
+	(port
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+		(input)
+		(text "ENY" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "ENY" (rect 21 27 45 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
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+		(input)
+		(text "X0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
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+		(input)
+		(text "X1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X1" (rect 21 59 36 73)(font "Arial" (font_size 8)))
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+	)
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+		(input)
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+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "X3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X3" (rect 21 91 36 105)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "X4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X4" (rect 21 107 36 121)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "X5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X5" (rect 21 123 36 137)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "X6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X6" (rect 21 139 36 153)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "X7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X7" (rect 21 155 36 169)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 16 160))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "X8" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "X8" (rect 21 171 36 185)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 16 176))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "X9" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 192)(pt 16 192))
+	)
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+		(pt 0 208)
+		(input)
+		(text "Y0" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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+	)
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+		(input)
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+	(port
+		(pt 0 240)
+		(input)
+		(text "Y2" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 240)(pt 16 240))
+	)
+	(port
+		(pt 0 256)
+		(input)
+		(text "Y3" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y3" (rect 21 251 37 265)(font "Arial" (font_size 8)))
+		(line (pt 0 256)(pt 16 256))
+	)
+	(port
+		(pt 0 272)
+		(input)
+		(text "Y4" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y4" (rect 21 267 37 281)(font "Arial" (font_size 8)))
+		(line (pt 0 272)(pt 16 272))
+	)
+	(port
+		(pt 0 288)
+		(input)
+		(text "Y5" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y5" (rect 21 283 37 297)(font "Arial" (font_size 8)))
+		(line (pt 0 288)(pt 16 288))
+	)
+	(port
+		(pt 0 304)
+		(input)
+		(text "Y6" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "Y6" (rect 21 299 37 313)(font "Arial" (font_size 8)))
+		(line (pt 0 304)(pt 16 304))
+	)
+	(port
+		(pt 0 320)
+		(input)
+		(text "Y7" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 320)(pt 16 320))
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+		(text "Y8" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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+	)
+	(port
+		(pt 0 352)
+		(input)
+		(text "Y9" (rect 0 0 16 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 352)(pt 16 352))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "S0" (rect 0 0 15 14)(font "Arial" (font_size 8)))
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+		(line (pt 96 32)(pt 80 32))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "S1" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S1" (rect 60 43 75 57)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 80 48))
+	)
+	(port
+		(pt 96 64)
+		(output)
+		(text "S2" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S2" (rect 60 59 75 73)(font "Arial" (font_size 8)))
+		(line (pt 96 64)(pt 80 64))
+	)
+	(port
+		(pt 96 80)
+		(output)
+		(text "S3" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S3" (rect 60 75 75 89)(font "Arial" (font_size 8)))
+		(line (pt 96 80)(pt 80 80))
+	)
+	(port
+		(pt 96 96)
+		(output)
+		(text "S4" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S4" (rect 60 91 75 105)(font "Arial" (font_size 8)))
+		(line (pt 96 96)(pt 80 96))
+	)
+	(port
+		(pt 96 112)
+		(output)
+		(text "S5" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S5" (rect 60 107 75 121)(font "Arial" (font_size 8)))
+		(line (pt 96 112)(pt 80 112))
+	)
+	(port
+		(pt 96 128)
+		(output)
+		(text "S6" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S6" (rect 60 123 75 137)(font "Arial" (font_size 8)))
+		(line (pt 96 128)(pt 80 128))
+	)
+	(port
+		(pt 96 144)
+		(output)
+		(text "S7" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S7" (rect 60 139 75 153)(font "Arial" (font_size 8)))
+		(line (pt 96 144)(pt 80 144))
+	)
+	(port
+		(pt 96 160)
+		(output)
+		(text "S8" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S8" (rect 60 155 75 169)(font "Arial" (font_size 8)))
+		(line (pt 96 160)(pt 80 160))
+	)
+	(port
+		(pt 96 176)
+		(output)
+		(text "S9" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+		(text "S9" (rect 60 171 75 185)(font "Arial" (font_size 8)))
+		(line (pt 96 176)(pt 80 176))
+	)
+	(port
+		(pt 96 192)
+		(output)
+		(text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8)))
+		(text "Cout" (rect 50 187 75 201)(font "Arial" (font_size 8)))
+		(line (pt 96 192)(pt 80 192))
+	)
+	(drawing
+		(rectangle (rect 16 16 80 368))
+	)
+)
diff --git a/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qpf b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qpf
new file mode 100644
index 0000000..e560bf8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 22:55:32  February 18, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "22:55:32  February 18, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ten_bit_adder_NO_BUS"
diff --git a/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qsf b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qsf
new file mode 100644
index 0000000..10b75d8
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qsf
@@ -0,0 +1,55 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 22:55:32  February 18, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ten_bit_adder_NO_BUS_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name DEVICE auto
+set_global_assignment -name TOP_LEVEL_ENTITY ten_bit_adder_NO_BUS
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:55:32  FEBRUARY 18, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name BSF_FILE ../adder/full_adder.bsf
+set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE ten_bit_adder_NO_BUS.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
\ No newline at end of file
diff --git a/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qws b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qws
new file mode 100644
index 0000000..f67251e
--- /dev/null
+++ b/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.qws
diff --git a/ten_counter/Waveform.vwf b/ten_counter/Waveform.vwf
new file mode 100644
index 0000000..2388809
--- /dev/null
+++ b/ten_counter/Waveform.vwf
@@ -0,0 +1,265 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("CLK")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("CLR")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("count")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 4;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("count[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("cout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("CLK")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 50;
+			LEVEL 0 FOR 10.0;
+			LEVEL 1 FOR 10.0;
+		}
+	}
+}
+
+TRANSITION_LIST("CLR")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("count[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("count[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("count[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("count[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("cout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "CLK";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "CLR";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+	CHILDREN = 3, 4, 5, 6;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
diff --git a/ten_counter/db/.cmp.kpt b/ten_counter/db/.cmp.kpt
new file mode 100644
index 0000000..ab1ef01
--- /dev/null
+++ b/ten_counter/db/.cmp.kpt
diff --git a/ten_counter/db/logic_util_heursitic.dat b/ten_counter/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..4f8acec
--- /dev/null
+++ b/ten_counter/db/logic_util_heursitic.dat
diff --git a/ten_counter/db/prev_cmp_ten_counter.qmsg b/ten_counter/db/prev_cmp_ten_counter.qmsg
new file mode 100644
index 0000000..f096c8d
--- /dev/null
+++ b/ten_counter/db/prev_cmp_ten_counter.qmsg
@@ -0,0 +1,114 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456502991325 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456502991326 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:09:51 2016 " "Processing started: Fri Feb 26 16:09:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456502991326 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456502991326 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456502991326 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456502991535 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_counter " "Found entity 1: ten_counter" {  } { { "ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456502991571 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456502991571 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_counter " "Elaborating entity \"ten_counter\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456502991588 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456502991975 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456502992121 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456502992121 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456502992139 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456502992139 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Implemented 5 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456502992139 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456502992139 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "464 " "Peak virtual memory: 464 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456502992150 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:09:52 2016 " "Processing ended: Fri Feb 26 16:09:52 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456502992150 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456502992150 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456502992150 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456502992150 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456502993294 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456502993295 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:09:52 2016 " "Processing started: Fri Feb 26 16:09:52 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456502993295 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1456502993295 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1456502993295 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1456502993361 ""}
+{ "Info" "0" "" "Project  = ten_counter" {  } {  } 0 0 "Project  = ten_counter" 0 0 "Fitter" 0 0 1456502993361 ""}
+{ "Info" "0" "" "Revision = ten_counter" {  } {  } 0 0 "Revision = ten_counter" 0 0 "Fitter" 0 0 1456502993361 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456502993404 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ten_counter EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"ten_counter\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456502993628 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456502993672 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456502993672 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456502993672 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456502993734 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456502993913 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456502993913 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456502993913 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456502993913 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456502993915 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456502993915 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 37 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456502993915 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456502993915 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456502993915 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456502993915 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456502993915 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_counter.sdc " "Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456502994647 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456502994647 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456502994648 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456502994648 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456502994648 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456502994652 ""}  } { { "ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { { -80 752 768 88 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 27 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456502994652 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456502994752 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456502994752 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456502994752 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456502994752 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456502994752 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456502994753 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456502994753 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456502994753 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456502994761 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456502994761 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456502994761 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456502994767 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456502995156 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456502995198 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456502995204 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456502995393 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456502995393 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456502995530 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" {  } { { "loc" "" { Generic "C:/Git/ten_counter/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456502995851 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456502995851 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456502996223 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456502996224 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1456502996224 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456502996224 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456502996228 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456502996254 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456502996463 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456502996487 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456502996555 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456502996822 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Git/ten_counter/output_files/ten_counter.fit.smsg " "Generated suppressed messages file C:/Git/ten_counter/output_files/ten_counter.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456502997456 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1089 " "Peak virtual memory: 1089 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456502997598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:09:57 2016 " "Processing ended: Fri Feb 26 16:09:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456502997598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456502997598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456502997598 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456502997598 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1456502998625 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456502998627 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:09:58 2016 " "Processing started: Fri Feb 26 16:09:58 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456502998627 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456502998627 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456502998627 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456502999241 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456502999260 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456502999483 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:09:59 2016 " "Processing ended: Fri Feb 26 16:09:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456502999483 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456502999483 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456502999483 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456502999483 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1456503000062 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1456503000614 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503000615 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:10:00 2016 " "Processing started: Fri Feb 26 16:10:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503000615 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503000615 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_counter -c ten_counter " "Command: quartus_sta ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503000615 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456503000674 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456503000760 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503000760 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503000804 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503000804 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_counter.sdc " "Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456503000920 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456503000920 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456503000920 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456503000920 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456503001020 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001020 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456503001021 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456503001026 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503001031 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503001031 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.073 " "Worst-case setup slack is -0.073" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.073        -0.183 CLK  " "   -0.073        -0.183 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001032 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.359 " "Worst-case hold slack is 0.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359         0.000 CLK  " "    0.359         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001034 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001034 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001036 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001037 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.000 CLK  " "   -3.000        -7.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001039 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001039 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456503001051 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456503001068 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456503001358 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001377 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.038 " "Worst-case setup slack is 0.038" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.038         0.000 CLK  " "    0.038         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001382 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001382 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.312 " "Worst-case hold slack is 0.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLK  " "    0.312         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001384 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001384 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001386 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001389 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503001389 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503001389 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001391 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001391 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.000 CLK  " "   -3.000        -7.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001391 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001391 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456503001404 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001458 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.396 " "Worst-case setup slack is 0.396" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001461 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.396         0.000 CLK  " "    0.396         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001461 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001461 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.188 " "Worst-case hold slack is 0.188" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188         0.000 CLK  " "    0.188         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001463 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001463 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001465 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503001467 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503001467 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503001467 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.220 CLK  " "   -3.000        -7.220 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503001468 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503001468 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456503001568 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456503001568 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "476 " "Peak virtual memory: 476 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503001596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:10:01 2016 " "Processing ended: Fri Feb 26 16:10:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503001596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503001596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503001596 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503001596 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503002684 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503002686 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:10:02 2016 " "Processing started: Fri Feb 26 16:10:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503002686 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503002686 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503002686 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_counter.vo C:/Git/ten_counter/simulation/modelsim/ simulation " "Generated file ten_counter.vo in folder \"C:/Git/ten_counter/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456503002931 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503002953 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:10:02 2016 " "Processing ended: Fri Feb 26 16:10:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503002953 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503002953 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503002953 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503002953 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 6 s " "Quartus II Full Compilation was successful. 0 errors, 6 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503003546 ""}
diff --git a/ten_counter/db/ten_counter.(0).cnf.cdb b/ten_counter/db/ten_counter.(0).cnf.cdb
new file mode 100644
index 0000000..fb34cf8
--- /dev/null
+++ b/ten_counter/db/ten_counter.(0).cnf.cdb
diff --git a/ten_counter/db/ten_counter.(0).cnf.hdb b/ten_counter/db/ten_counter.(0).cnf.hdb
new file mode 100644
index 0000000..a97abfb
--- /dev/null
+++ b/ten_counter/db/ten_counter.(0).cnf.hdb
diff --git a/ten_counter/db/ten_counter.asm.qmsg b/ten_counter/db/ten_counter.asm.qmsg
new file mode 100644
index 0000000..7ba2214
--- /dev/null
+++ b/ten_counter/db/ten_counter.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503320658 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503320660 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:15:19 2016 " "Processing started: Fri Feb 26 16:15:19 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503320660 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456503320660 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456503320660 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456503321278 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456503321296 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "420 " "Peak virtual memory: 420 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503321518 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:15:21 2016 " "Processing ended: Fri Feb 26 16:15:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503321518 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503321518 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503321518 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456503321518 ""}
diff --git a/ten_counter/db/ten_counter.asm.rdb b/ten_counter/db/ten_counter.asm.rdb
new file mode 100644
index 0000000..c738909
--- /dev/null
+++ b/ten_counter/db/ten_counter.asm.rdb
diff --git a/ten_counter/db/ten_counter.asm_labs.ddb b/ten_counter/db/ten_counter.asm_labs.ddb
new file mode 100644
index 0000000..10f0dfc
--- /dev/null
+++ b/ten_counter/db/ten_counter.asm_labs.ddb
diff --git a/ten_counter/db/ten_counter.cbx.xml b/ten_counter/db/ten_counter.cbx.xml
new file mode 100644
index 0000000..993fc3a
--- /dev/null
+++ b/ten_counter/db/ten_counter.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ten_counter">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/ten_counter/db/ten_counter.cmp.bpm b/ten_counter/db/ten_counter.cmp.bpm
new file mode 100644
index 0000000..9512a7d
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.bpm
diff --git a/ten_counter/db/ten_counter.cmp.cdb b/ten_counter/db/ten_counter.cmp.cdb
new file mode 100644
index 0000000..8fb6ccc
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.cdb
diff --git a/ten_counter/db/ten_counter.cmp.hdb b/ten_counter/db/ten_counter.cmp.hdb
new file mode 100644
index 0000000..65b9602
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.hdb
diff --git a/ten_counter/db/ten_counter.cmp.idb b/ten_counter/db/ten_counter.cmp.idb
new file mode 100644
index 0000000..9d5c614
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.idb
diff --git a/ten_counter/db/ten_counter.cmp.kpt b/ten_counter/db/ten_counter.cmp.kpt
new file mode 100644
index 0000000..0fd8d06
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.kpt
diff --git a/ten_counter/db/ten_counter.cmp.logdb b/ten_counter/db/ten_counter.cmp.logdb
new file mode 100644
index 0000000..f4b537c
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.logdb
@@ -0,0 +1,49 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,7;0;7;0;0;7;7;0;7;7;0;5;0;0;2;0;5;2;0;0;0;5;0;0;0;0;0;7;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;7;0;7;7;0;0;7;0;0;7;2;7;7;5;7;2;5;7;7;7;2;7;7;7;7;7;0;7;7,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,cout,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,count[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,count[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,count[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,count[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLR,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/ten_counter/db/ten_counter.cmp.rdb b/ten_counter/db/ten_counter.cmp.rdb
new file mode 100644
index 0000000..641b4d9
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp.rdb
diff --git a/ten_counter/db/ten_counter.cmp_merge.kpt b/ten_counter/db/ten_counter.cmp_merge.kpt
new file mode 100644
index 0000000..3c40da9
--- /dev/null
+++ b/ten_counter/db/ten_counter.cmp_merge.kpt
diff --git a/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..c86ea3e
--- /dev/null
+++ b/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..ab8d5bc
--- /dev/null
+++ b/ten_counter/db/ten_counter.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/ten_counter/db/ten_counter.db_info b/ten_counter/db/ten_counter.db_info
new file mode 100644
index 0000000..740da6f
--- /dev/null
+++ b/ten_counter/db/ten_counter.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 15:55:29 2016
diff --git a/ten_counter/db/ten_counter.eda.qmsg b/ten_counter/db/ten_counter.eda.qmsg
new file mode 100644
index 0000000..e7f8f1a
--- /dev/null
+++ b/ten_counter/db/ten_counter.eda.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503342429 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503342430 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:15:42 2016 " "Processing started: Fri Feb 26 16:15:42 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503342430 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503342430 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog ten_counter -c ten_counter " "Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503342430 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_counter.vo C:/Git/ten_counter/simulation/modelsim/ simulation " "Generated file ten_counter.vo in folder \"C:/Git/ten_counter/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456503342656 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503342683 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:15:42 2016 " "Processing ended: Fri Feb 26 16:15:42 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503342683 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503342683 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503342683 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503342683 ""}
diff --git a/ten_counter/db/ten_counter.fit.qmsg b/ten_counter/db/ten_counter.fit.qmsg
new file mode 100644
index 0000000..b544d3c
--- /dev/null
+++ b/ten_counter/db/ten_counter.fit.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456503314375 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ten_counter EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"ten_counter\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456503314612 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456503314659 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456503314660 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456503314660 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456503314721 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456503314901 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456503314901 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456503314901 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456503314901 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456503314902 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456503314902 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 37 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456503314902 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456503314902 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456503314902 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456503314902 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456503314903 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_counter.sdc " "Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456503315631 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456503315631 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456503315632 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456503315632 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456503315632 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456503315636 ""}  } { { "ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { { -80 752 768 88 "CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Git/ten_counter/" { { 0 { 0 ""} 0 27 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456503315636 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456503315736 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456503315736 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456503315736 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456503315737 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456503315737 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456503315737 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456503315737 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456503315737 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456503315746 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456503315746 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456503315746 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456503315752 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456503316153 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456503316198 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456503316204 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456503316394 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456503316394 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456503316530 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X9_Y19 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19" {  } { { "loc" "" { Generic "C:/Git/ten_counter/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19"} 0 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456503316853 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456503316853 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456503317216 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456503317217 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1456503317217 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456503317217 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456503317221 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456503317247 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456503317459 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456503317484 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456503317549 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456503317815 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Git/ten_counter/output_files/ten_counter.fit.smsg " "Generated suppressed messages file C:/Git/ten_counter/output_files/ten_counter.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456503318454 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1089 " "Peak virtual memory: 1089 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503318598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:15:18 2016 " "Processing ended: Fri Feb 26 16:15:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503318598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503318598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503318598 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456503318598 ""}
diff --git a/ten_counter/db/ten_counter.hier_info b/ten_counter/db/ten_counter.hier_info
new file mode 100644
index 0000000..e47522b
--- /dev/null
+++ b/ten_counter/db/ten_counter.hier_info
@@ -0,0 +1,13 @@
+|ten_counter
+cout <= inst23.DB_MAX_OUTPUT_PORT_TYPE
+CLR => inst22.IN0
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst3.CLK
+CLK => inst2.CLK
+count[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/ten_counter/db/ten_counter.hif b/ten_counter/db/ten_counter.hif
new file mode 100644
index 0000000..cae4e8d
--- /dev/null
+++ b/ten_counter/db/ten_counter.hif
diff --git a/ten_counter/db/ten_counter.ipinfo b/ten_counter/db/ten_counter.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/ten_counter/db/ten_counter.ipinfo
diff --git a/ten_counter/db/ten_counter.lpc.html b/ten_counter/db/ten_counter.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/ten_counter/db/ten_counter.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/ten_counter/db/ten_counter.lpc.rdb b/ten_counter/db/ten_counter.lpc.rdb
new file mode 100644
index 0000000..da6029a
--- /dev/null
+++ b/ten_counter/db/ten_counter.lpc.rdb
diff --git a/ten_counter/db/ten_counter.lpc.txt b/ten_counter/db/ten_counter.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/ten_counter/db/ten_counter.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/ten_counter/db/ten_counter.map.ammdb b/ten_counter/db/ten_counter.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.ammdb
diff --git a/ten_counter/db/ten_counter.map.bpm b/ten_counter/db/ten_counter.map.bpm
new file mode 100644
index 0000000..71a2140
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.bpm
diff --git a/ten_counter/db/ten_counter.map.cdb b/ten_counter/db/ten_counter.map.cdb
new file mode 100644
index 0000000..1e5e967
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.cdb
diff --git a/ten_counter/db/ten_counter.map.hdb b/ten_counter/db/ten_counter.map.hdb
new file mode 100644
index 0000000..d836bbf
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.hdb
diff --git a/ten_counter/db/ten_counter.map.kpt b/ten_counter/db/ten_counter.map.kpt
new file mode 100644
index 0000000..79a2a64
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.kpt
diff --git a/ten_counter/db/ten_counter.map.logdb b/ten_counter/db/ten_counter.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_counter/db/ten_counter.map.qmsg b/ten_counter/db/ten_counter.map.qmsg
new file mode 100644
index 0000000..3722d38
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503312300 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503312302 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:15:11 2016 " "Processing started: Fri Feb 26 16:15:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503312302 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503312302 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503312302 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456503312538 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_counter.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_counter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_counter " "Found entity 1: ten_counter" {  } { { "ten_counter.bdf" "" { Schematic "C:/Git/ten_counter/ten_counter.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456503312579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456503312579 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_counter " "Elaborating entity \"ten_counter\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456503312598 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456503312979 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456503313129 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456503313129 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456503313149 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456503313149 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Implemented 5 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456503313149 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456503313149 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "464 " "Peak virtual memory: 464 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503313159 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:15:13 2016 " "Processing ended: Fri Feb 26 16:15:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503313159 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503313159 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503313159 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503313159 ""}
diff --git a/ten_counter/db/ten_counter.map.rdb b/ten_counter/db/ten_counter.map.rdb
new file mode 100644
index 0000000..bb770dd
--- /dev/null
+++ b/ten_counter/db/ten_counter.map.rdb
diff --git a/ten_counter/db/ten_counter.map_bb.cdb b/ten_counter/db/ten_counter.map_bb.cdb
new file mode 100644
index 0000000..bb2ca78
--- /dev/null
+++ b/ten_counter/db/ten_counter.map_bb.cdb
diff --git a/ten_counter/db/ten_counter.map_bb.hdb b/ten_counter/db/ten_counter.map_bb.hdb
new file mode 100644
index 0000000..de93763
--- /dev/null
+++ b/ten_counter/db/ten_counter.map_bb.hdb
diff --git a/ten_counter/db/ten_counter.map_bb.logdb b/ten_counter/db/ten_counter.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_counter/db/ten_counter.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_counter/db/ten_counter.pplq.rdb b/ten_counter/db/ten_counter.pplq.rdb
new file mode 100644
index 0000000..8502917
--- /dev/null
+++ b/ten_counter/db/ten_counter.pplq.rdb
diff --git a/ten_counter/db/ten_counter.pre_map.hdb b/ten_counter/db/ten_counter.pre_map.hdb
new file mode 100644
index 0000000..88a6fd8
--- /dev/null
+++ b/ten_counter/db/ten_counter.pre_map.hdb
diff --git a/ten_counter/db/ten_counter.pti_db_list.ddb b/ten_counter/db/ten_counter.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/ten_counter/db/ten_counter.pti_db_list.ddb
diff --git a/ten_counter/db/ten_counter.root_partition.map.reg_db.cdb b/ten_counter/db/ten_counter.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..b79c9ad
--- /dev/null
+++ b/ten_counter/db/ten_counter.root_partition.map.reg_db.cdb
diff --git a/ten_counter/db/ten_counter.routing.rdb b/ten_counter/db/ten_counter.routing.rdb
new file mode 100644
index 0000000..4a012f8
--- /dev/null
+++ b/ten_counter/db/ten_counter.routing.rdb
diff --git a/ten_counter/db/ten_counter.rtlv.hdb b/ten_counter/db/ten_counter.rtlv.hdb
new file mode 100644
index 0000000..f1c50cb
--- /dev/null
+++ b/ten_counter/db/ten_counter.rtlv.hdb
diff --git a/ten_counter/db/ten_counter.rtlv_sg.cdb b/ten_counter/db/ten_counter.rtlv_sg.cdb
new file mode 100644
index 0000000..d2018cf
--- /dev/null
+++ b/ten_counter/db/ten_counter.rtlv_sg.cdb
diff --git a/ten_counter/db/ten_counter.rtlv_sg_swap.cdb b/ten_counter/db/ten_counter.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..c194c18
--- /dev/null
+++ b/ten_counter/db/ten_counter.rtlv_sg_swap.cdb
diff --git a/ten_counter/db/ten_counter.sgdiff.cdb b/ten_counter/db/ten_counter.sgdiff.cdb
new file mode 100644
index 0000000..a5af0c9
--- /dev/null
+++ b/ten_counter/db/ten_counter.sgdiff.cdb
diff --git a/ten_counter/db/ten_counter.sgdiff.hdb b/ten_counter/db/ten_counter.sgdiff.hdb
new file mode 100644
index 0000000..f699066
--- /dev/null
+++ b/ten_counter/db/ten_counter.sgdiff.hdb
diff --git a/ten_counter/db/ten_counter.sld_design_entry.sci b/ten_counter/db/ten_counter.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/ten_counter/db/ten_counter.sld_design_entry.sci
diff --git a/ten_counter/db/ten_counter.sld_design_entry_dsc.sci b/ten_counter/db/ten_counter.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/ten_counter/db/ten_counter.sld_design_entry_dsc.sci
diff --git a/ten_counter/db/ten_counter.smart_action.txt b/ten_counter/db/ten_counter.smart_action.txt
new file mode 100644
index 0000000..11b531f
--- /dev/null
+++ b/ten_counter/db/ten_counter.smart_action.txt
@@ -0,0 +1 @@
+SOURCE
diff --git a/ten_counter/db/ten_counter.sta.qmsg b/ten_counter/db/ten_counter.sta.qmsg
new file mode 100644
index 0000000..798b8a7
--- /dev/null
+++ b/ten_counter/db/ten_counter.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456503322709 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456503322710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 26 16:15:22 2016 " "Processing started: Fri Feb 26 16:15:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456503322710 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456503322710 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_counter -c ten_counter " "Command: quartus_sta ten_counter -c ten_counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456503322710 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456503322770 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456503322860 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503322860 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503322902 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456503322902 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_counter.sdc " "Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456503323018 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456503323019 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323019 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323019 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456503323117 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323117 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456503323118 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456503323123 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503323128 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503323128 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.073 " "Worst-case setup slack is -0.073" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.073        -0.178 CLK  " "   -0.073        -0.178 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323130 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323130 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.359 " "Worst-case hold slack is 0.359" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359         0.000 CLK  " "    0.359         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323132 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323132 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323134 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323136 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.000 CLK  " "   -3.000        -7.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323137 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323137 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456503323150 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456503323168 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456503323456 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323475 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.038 " "Worst-case setup slack is 0.038" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323480 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.038         0.000 CLK  " "    0.038         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323480 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323480 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.312 " "Worst-case hold slack is 0.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLK  " "    0.312         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323482 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323482 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323486 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323488 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503323488 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503323488 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323490 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323490 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.000 CLK  " "   -3.000        -7.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323490 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323490 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456503323506 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323560 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.396 " "Worst-case setup slack is 0.396" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.396         0.000 CLK  " "    0.396         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323562 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323562 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.188 " "Worst-case hold slack is 0.188" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188         0.000 CLK  " "    0.188         0.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323565 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323565 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323567 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456503323569 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456503323569 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456503323569 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323571 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323571 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -7.220 CLK  " "   -3.000        -7.220 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456503323571 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456503323571 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456503323670 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456503323670 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "488 " "Peak virtual memory: 488 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456503323699 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 26 16:15:23 2016 " "Processing ended: Fri Feb 26 16:15:23 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456503323699 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456503323699 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456503323699 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456503323699 ""}
diff --git a/ten_counter/db/ten_counter.sta.rdb b/ten_counter/db/ten_counter.sta.rdb
new file mode 100644
index 0000000..0b09978
--- /dev/null
+++ b/ten_counter/db/ten_counter.sta.rdb
diff --git a/ten_counter/db/ten_counter.sta_cmp.6_slow_1200mv_85c.tdb b/ten_counter/db/ten_counter.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..a8c3340
--- /dev/null
+++ b/ten_counter/db/ten_counter.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/ten_counter/db/ten_counter.syn_hier_info b/ten_counter/db/ten_counter.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/ten_counter/db/ten_counter.syn_hier_info
diff --git a/ten_counter/db/ten_counter.tis_db_list.ddb b/ten_counter/db/ten_counter.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/ten_counter/db/ten_counter.tis_db_list.ddb
diff --git a/ten_counter/db/ten_counter.tiscmp.fast_1200mv_0c.ddb b/ten_counter/db/ten_counter.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..e300dc1
--- /dev/null
+++ b/ten_counter/db/ten_counter.tiscmp.fast_1200mv_0c.ddb
diff --git a/ten_counter/db/ten_counter.tiscmp.slow_1200mv_0c.ddb b/ten_counter/db/ten_counter.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..7a6a3c1
--- /dev/null
+++ b/ten_counter/db/ten_counter.tiscmp.slow_1200mv_0c.ddb
diff --git a/ten_counter/db/ten_counter.tiscmp.slow_1200mv_85c.ddb b/ten_counter/db/ten_counter.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..be431ae
--- /dev/null
+++ b/ten_counter/db/ten_counter.tiscmp.slow_1200mv_85c.ddb
diff --git a/ten_counter/db/ten_counter.tmw_info b/ten_counter/db/ten_counter.tmw_info
new file mode 100644
index 0000000..c0b8754
--- /dev/null
+++ b/ten_counter/db/ten_counter.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:23
+start_analysis_synthesis:s:00:00:04-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:10-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/ten_counter/db/ten_counter.vpr.ammdb b/ten_counter/db/ten_counter.vpr.ammdb
new file mode 100644
index 0000000..fc456d1
--- /dev/null
+++ b/ten_counter/db/ten_counter.vpr.ammdb
diff --git a/ten_counter/incremental_db/README b/ten_counter/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/ten_counter/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.db_info b/ten_counter/incremental_db/compiled_partitions/ten_counter.db_info
new file mode 100644
index 0000000..16a1962
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Fri Feb 26 14:09:10 2016
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.ammdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.ammdb
new file mode 100644
index 0000000..91efd78
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.ammdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.cdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.cdb
new file mode 100644
index 0000000..f7558f8
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.cdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.dfp b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.dfp
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.hdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.hdb
new file mode 100644
index 0000000..d0150c2
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.hdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.kpt b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.kpt
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.logdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.rcfdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..9d4f1c9
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.cmp.rcfdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.cdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.cdb
new file mode 100644
index 0000000..0b072cf
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.cdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.dpi b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.dpi
new file mode 100644
index 0000000..5259285
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.dpi
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.cdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..1d2ebdf
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.cdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hb_info b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hb_info
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..5c53f32
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.hdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.sig b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hdb b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hdb
new file mode 100644
index 0000000..0eac619
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.hdb
diff --git a/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.kpt b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.kpt
new file mode 100644
index 0000000..d997dfc
--- /dev/null
+++ b/ten_counter/incremental_db/compiled_partitions/ten_counter.root_partition.map.kpt
diff --git a/ten_counter/output_files/ten_counter.asm.rpt b/ten_counter/output_files/ten_counter.asm.rpt
new file mode 100644
index 0000000..39e9e9c
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ten_counter
+Fri Feb 26 16:15:21 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Git/ten_counter/output_files/ten_counter.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 26 16:15:21 2016 ;
+; Revision Name         ; ten_counter                           ;
+; Top-level Entity Name ; ten_counter                           ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16U484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------------------+
+; Assembler Generated Files                       ;
++-------------------------------------------------+
+; File Name                                       ;
++-------------------------------------------------+
+; C:/Git/ten_counter/output_files/ten_counter.sof ;
++-------------------------------------------------+
+
+
++---------------------------------------------------------------------------+
+; Assembler Device Options: C:/Git/ten_counter/output_files/ten_counter.sof ;
++----------------+----------------------------------------------------------+
+; Option         ; Setting                                                  ;
++----------------+----------------------------------------------------------+
+; Device         ; EP3C16U484C6                                             ;
+; JTAG usercode  ; 0x000C88FD                                               ;
+; Checksum       ; 0x000C88FD                                               ;
++----------------+----------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:15:19 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 420 megabytes
+    Info: Processing ended: Fri Feb 26 16:15:21 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_counter/output_files/ten_counter.done b/ten_counter/output_files/ten_counter.done
new file mode 100644
index 0000000..f924a5d
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.done
@@ -0,0 +1 @@
+Fri Feb 26 16:15:25 2016
diff --git a/ten_counter/output_files/ten_counter.eda.rpt b/ten_counter/output_files/ten_counter.eda.rpt
new file mode 100644
index 0000000..2a14a3b
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.eda.rpt
@@ -0,0 +1,92 @@
+EDA Netlist Writer report for ten_counter
+Fri Feb 26 16:15:42 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb 26 16:15:42 2016 ;
+; Revision Name             ; ten_counter                           ;
+; Top-level Entity Name     ; ten_counter                           ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate netlist for functional simulation only                                                   ; On                        ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++-------------------------------------------------------+
+; Simulation Generated Files                            ;
++-------------------------------------------------------+
+; Generated Files                                       ;
++-------------------------------------------------------+
+; C:/Git/ten_counter/simulation/modelsim/ten_counter.vo ;
++-------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:15:42 2016
+Info: Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog ten_counter -c ten_counter
+Info (204019): Generated file ten_counter.vo in folder "C:/Git/ten_counter/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 385 megabytes
+    Info: Processing ended: Fri Feb 26 16:15:42 2016
+    Info: Elapsed time: 00:00:00
+    Info: Total CPU time (on all processors): 00:00:00
+
+
diff --git a/ten_counter/output_files/ten_counter.fit.rpt b/ten_counter/output_files/ten_counter.fit.rpt
new file mode 100644
index 0000000..5551de2
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.fit.rpt
@@ -0,0 +1,1234 @@
+Fitter report for ten_counter
+Fri Feb 26 16:15:18 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Other Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Fitter Messages
+ 35. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 26 16:15:18 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ten_counter                                      ;
+; Top-level Entity Name              ; ten_counter                                      ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16U484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 5 / 15,408 ( < 1 % )                             ;
+;     Total combinational functions  ; 5 / 15,408 ( < 1 % )                             ;
+;     Dedicated logic registers      ; 4 / 15,408 ( < 1 % )                             ;
+; Total registers                    ; 4                                                ;
+; Total pins                         ; 7 / 347 ( 2 % )                                  ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16U484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; cout     ; Missing drive strength and slew rate ;
+; count[3] ; Missing drive strength and slew rate ;
+; count[2] ; Missing drive strength and slew rate ;
+; count[1] ; Missing drive strength and slew rate ;
+; count[0] ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 35 ( 0.00 % )      ;
+;     -- Achieved     ; 0 / 35 ( 0.00 % )      ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 25      ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 10      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Git/ten_counter/output_files/ten_counter.pin.
+
+
++--------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                      ;
++---------------------------------------------+----------------------+
+; Resource                                    ; Usage                ;
++---------------------------------------------+----------------------+
+; Total logic elements                        ; 5 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 1                    ;
+;     -- Register only                        ; 0                    ;
+;     -- Combinational with a register        ; 4                    ;
+;                                             ;                      ;
+; Logic element usage by number of LUT inputs ;                      ;
+;     -- 4 input functions                    ; 2                    ;
+;     -- 3 input functions                    ; 2                    ;
+;     -- <=2 input functions                  ; 1                    ;
+;     -- Register only                        ; 0                    ;
+;                                             ;                      ;
+; Logic elements by mode                      ;                      ;
+;     -- normal mode                          ; 5                    ;
+;     -- arithmetic mode                      ; 0                    ;
+;                                             ;                      ;
+; Total registers*                            ; 4 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 4 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )    ;
+;                                             ;                      ;
+; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )    ;
+; Virtual pins                                ; 0                    ;
+; I/O pins                                    ; 7 / 347 ( 2 % )      ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )       ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )        ;
+;                                             ;                      ;
+; Global signals                              ; 1                    ;
+; M9Ks                                        ; 0 / 56 ( 0 % )       ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
+; PLLs                                        ; 0 / 4 ( 0 % )        ;
+; Global clocks                               ; 1 / 20 ( 5 % )       ;
+; JTAGs                                       ; 0 / 1 ( 0 % )        ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
+; Maximum fan-out                             ; 6                    ;
+; Highest non-global fan-out                  ; 6                    ;
+; Total fan-out                               ; 45                   ;
+; Average fan-out                             ; 1.32                 ;
++---------------------------------------------+----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                        ;
++---------------------------------------------+---------------------+--------------------------------+
+; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
++---------------------------------------------+---------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                 ; Low                            ;
+;                                             ;                     ;                                ;
+; Total logic elements                        ; 5 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 1                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;     -- Combinational with a register        ; 4                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic element usage by number of LUT inputs ;                     ;                                ;
+;     -- 4 input functions                    ; 2                   ; 0                              ;
+;     -- 3 input functions                    ; 2                   ; 0                              ;
+;     -- <=2 input functions                  ; 1                   ; 0                              ;
+;     -- Register only                        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Logic elements by mode                      ;                     ;                                ;
+;     -- normal mode                          ; 5                   ; 0                              ;
+;     -- arithmetic mode                      ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Total registers                             ; 4                   ; 0                              ;
+;     -- Dedicated logic registers            ; 4 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                     ;                                ;
+; Total LABs:  partially or completely used   ; 1 / 963 ( < 1 % )   ; 0 / 963 ( 0 % )                ;
+;                                             ;                     ;                                ;
+; Virtual pins                                ; 0                   ; 0                              ;
+; I/O pins                                    ; 7                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                   ; 0                              ;
+; Total RAM block bits                        ; 0                   ; 0                              ;
+; Clock control block                         ; 1 / 24 ( 4 % )      ; 0 / 24 ( 0 % )                 ;
+;                                             ;                     ;                                ;
+; Connections                                 ;                     ;                                ;
+;     -- Input Connections                    ; 0                   ; 0                              ;
+;     -- Registered Input Connections         ; 0                   ; 0                              ;
+;     -- Output Connections                   ; 0                   ; 0                              ;
+;     -- Registered Output Connections        ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Internal Connections                        ;                     ;                                ;
+;     -- Total Connections                    ; 40                  ; 5                              ;
+;     -- Registered Connections               ; 19                  ; 0                              ;
+;                                             ;                     ;                                ;
+; External Connections                        ;                     ;                                ;
+;     -- Top                                  ; 0                   ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Partition Interface                         ;                     ;                                ;
+;     -- Input Ports                          ; 2                   ; 0                              ;
+;     -- Output Ports                         ; 5                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Registered Ports                            ;                     ;                                ;
+;     -- Registered Input Ports               ; 0                   ; 0                              ;
+;     -- Registered Output Ports              ; 0                   ; 0                              ;
+;                                             ;                     ;                                ;
+; Port Connectivity                           ;                     ;                                ;
+;     -- Input Ports driven by GND            ; 0                   ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                   ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
++---------------------------------------------+---------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLK  ; G21   ; 6        ; 41           ; 15           ; 0            ; 4                     ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; CLR  ; G3    ; 1        ; 0            ; 23           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; count[0] ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; count[1] ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; count[2] ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; count[3] ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; cout     ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                         ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                    ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO     ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                        ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                       ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                     ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                         ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                       ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO           ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 10 / 33 ( 30 % ) ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
+; 7        ; 0 / 47 ( 0 % )   ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; cout                                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F12      ; 302        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F13      ; 306        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; CLR                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLK                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; count[0]                                                  ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H13      ; 303        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; count[3]                                                  ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; count[2]                                                  ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; count[1]                                                  ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |ten_counter               ; 5 (5)       ; 4 (4)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 7    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; |ten_counter        ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                      ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+; Name     ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+; cout     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; count[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; count[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; count[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; count[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; CLK      ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; CLR      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++----------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; CLK                 ;                   ;         ;
+; CLR                 ;                   ;         ;
+;      - inst         ; 0                 ; 6       ;
+;      - inst1        ; 0                 ; 6       ;
+;      - inst3        ; 0                 ; 6       ;
+;      - inst2        ; 0                 ; 6       ;
++---------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                         ;
++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_G21  ; 4       ; Clock        ; yes    ; Global Clock         ; GCLK9            ; --                        ;
+; CLR  ; PIN_G3   ; 4       ; Async. clear ; no     ; --                   ; --               ; --                        ;
++------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                            ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_G21  ; 4       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------+---------------------+
+; Name      ; Fan-Out             ;
++-----------+---------------------+
+; inst      ; 6                   ;
+; inst1     ; 5                   ;
+; CLR~input ; 4                   ;
+; inst2     ; 4                   ;
+; inst3     ; 4                   ;
+; inst~0    ; 1                   ;
+; inst2~0   ; 1                   ;
+; inst17    ; 1                   ;
+; inst5~0   ; 1                   ;
+; inst23~0  ; 1                   ;
++-----------+---------------------+
+
+
++-----------------------------------------------------+
+; Other Routing Usage Summary                         ;
++-----------------------------+-----------------------+
+; Other Routing Resource Type ; Usage                 ;
++-----------------------------+-----------------------+
+; Block interconnects         ; 10 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects            ; 5 / 31,272 ( < 1 % )  ;
+; Direct links                ; 4 / 47,787 ( < 1 % )  ;
+; Global clocks               ; 1 / 20 ( 5 % )        ;
+; Local interconnects         ; 4 / 15,408 ( < 1 % )  ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects            ; 1 / 41,310 ( < 1 % )  ;
++-----------------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements                                                       ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 5.00) ; Number of LABs  (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1                                          ; 0                           ;
+; 2                                          ; 0                           ;
+; 3                                          ; 0                           ;
+; 4                                          ; 0                           ;
+; 5                                          ; 1                           ;
+; 6                                          ; 0                           ;
+; 7                                          ; 0                           ;
+; 8                                          ; 0                           ;
+; 9                                          ; 0                           ;
+; 10                                         ; 0                           ;
+; 11                                         ; 0                           ;
+; 12                                         ; 0                           ;
+; 13                                         ; 0                           ;
+; 14                                         ; 0                           ;
+; 15                                         ; 0                           ;
+; 16                                         ; 0                           ;
++--------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 2.00) ; Number of LABs  (Total = 1) ;
++------------------------------------+-----------------------------+
+; 1 Async. clear                     ; 1                           ;
+; 1 Clock                            ; 1                           ;
++------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Signals Sourced                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 9.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 0                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 5.00) ; Number of LABs  (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 0                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 1) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 0                           ;
+; 2                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 7         ; 0            ; 7         ; 0            ; 0            ; 7         ; 7         ; 0            ; 7         ; 7         ; 0            ; 5            ; 0            ; 0            ; 2            ; 0            ; 5            ; 2            ; 0            ; 0            ; 0            ; 5            ; 0            ; 0            ; 0            ; 0            ; 0            ; 7         ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 7            ; 0         ; 7            ; 7            ; 0         ; 0         ; 7            ; 0         ; 0         ; 7            ; 2            ; 7            ; 7            ; 5            ; 7            ; 2            ; 5            ; 7            ; 7            ; 7            ; 2            ; 7            ; 7            ; 7            ; 7            ; 7            ; 0         ; 7            ; 7            ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; cout               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; count[3]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; count[2]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; count[1]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; count[0]           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLR                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16U484C6 for design "ten_counter"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40U484C6 is compatible
+    Info (176445): Device EP3C55U484C6 is compatible
+    Info (176445): Device EP3C80U484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node CLK~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X9_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
+Info (144001): Generated suppressed messages file C:/Git/ten_counter/output_files/ten_counter.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 1089 megabytes
+    Info: Processing ended: Fri Feb 26 16:15:18 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Git/ten_counter/output_files/ten_counter.fit.smsg.
+
+
diff --git a/ten_counter/output_files/ten_counter.fit.smsg b/ten_counter/output_files/ten_counter.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/ten_counter/output_files/ten_counter.fit.summary b/ten_counter/output_files/ten_counter.fit.summary
new file mode 100644
index 0000000..dc73199
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Fri Feb 26 16:15:18 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ten_counter
+Top-level Entity Name : ten_counter
+Family : Cyclone III
+Device : EP3C16U484C6
+Timing Models : Final
+Total logic elements : 5 / 15,408 ( < 1 % )
+    Total combinational functions : 5 / 15,408 ( < 1 % )
+    Dedicated logic registers : 4 / 15,408 ( < 1 % )
+Total registers : 4
+Total pins : 7 / 347 ( 2 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/ten_counter/output_files/ten_counter.flow.rpt b/ten_counter/output_files/ten_counter.flow.rpt
new file mode 100644
index 0000000..cb32e0a
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.flow.rpt
@@ -0,0 +1,135 @@
+Flow report for ten_counter
+Fri Feb 26 16:15:42 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 26 16:15:42 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ten_counter                                      ;
+; Top-level Entity Name              ; ten_counter                                      ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16U484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 5 / 15,408 ( < 1 % )                             ;
+;     Total combinational functions  ; 5 / 15,408 ( < 1 % )                             ;
+;     Dedicated logic registers      ; 4 / 15,408 ( < 1 % )                             ;
+; Total registers                    ; 4                                                ;
+; Total pins                         ; 7 / 347 ( 2 % )                                  ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/26/2016 16:15:12 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ten_counter         ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297093.145650331206744 ; --            ; --          ; --             ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST     ; On                              ; --            ; --          ; eda_simulation ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                     ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)       ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 464 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:05     ; 1.0                     ; 1089 MB             ; 00:00:05                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 420 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:01     ; 1.0                     ; 488 MB              ; 00:00:01                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 372 MB              ; 00:00:00                           ;
+; EDA Netlist Writer        ; 00:00:00     ; 1.0                     ; 380 MB              ; 00:00:00                           ;
+; EDA Netlist Writer        ; 00:00:00     ; 1.0                     ; 380 MB              ; 00:00:00                           ;
+; Total                     ; 00:00:11     ; --                      ; --                  ; 00:00:08                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-008     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter
+quartus_fit --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter
+quartus_asm --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter
+quartus_sta ten_counter -c ten_counter
+quartus_eda --read_settings_files=off --write_settings_files=off ten_counter -c ten_counter
+quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog ten_counter -c ten_counter --vector_source=C:/Git/ten_counter/Waveform.vwf --testbench_file=./simulation/qsim/ten_counter.vt
+quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog ten_counter -c ten_counter
+
+
+
diff --git a/ten_counter/output_files/ten_counter.jdi b/ten_counter/output_files/ten_counter.jdi
new file mode 100644
index 0000000..bf8f933
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="1551b5862981899db51e"/>
+  </project>
+  <file_info>
+    <file device="EP3C16U484C6" path="ten_counter.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/ten_counter/output_files/ten_counter.map.rpt b/ten_counter/output_files/ten_counter.map.rpt
new file mode 100644
index 0000000..4020ba4
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.map.rpt
@@ -0,0 +1,263 @@
+Analysis & Synthesis report for ten_counter
+Fri Feb 26 16:15:13 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 26 16:15:13 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ten_counter                                      ;
+; Top-level Entity Name              ; ten_counter                                      ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 5                                                ;
+;     Total combinational functions  ; 5                                                ;
+;     Dedicated logic registers      ; 4                                                ;
+; Total registers                    ; 4                                                ;
+; Total pins                         ; 7                                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16U484C6       ;                    ;
+; Top-level entity name                                                      ; ten_counter        ; ten_counter        ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                 ;
++----------------------------------+-----------------+------------------------------------+------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path       ; Library ;
++----------------------------------+-----------------+------------------------------------+------------------------------------+---------+
+; ten_counter.bdf                  ; yes             ; User Block Diagram/Schematic File  ; C:/Git/ten_counter/ten_counter.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary         ;
++---------------------------------------------+-------+
+; Resource                                    ; Usage ;
++---------------------------------------------+-------+
+; Estimated Total logic elements              ; 5     ;
+;                                             ;       ;
+; Total combinational functions               ; 5     ;
+; Logic element usage by number of LUT inputs ;       ;
+;     -- 4 input functions                    ; 2     ;
+;     -- 3 input functions                    ; 2     ;
+;     -- <=2 input functions                  ; 1     ;
+;                                             ;       ;
+; Logic elements by mode                      ;       ;
+;     -- normal mode                          ; 5     ;
+;     -- arithmetic mode                      ; 0     ;
+;                                             ;       ;
+; Total registers                             ; 4     ;
+;     -- Dedicated logic registers            ; 4     ;
+;     -- I/O registers                        ; 0     ;
+;                                             ;       ;
+; I/O pins                                    ; 7     ;
+; Embedded Multiplier 9-bit elements          ; 0     ;
+; Maximum fan-out node                        ; inst  ;
+; Maximum fan-out                             ; 6     ;
+; Total fan-out                               ; 39    ;
+; Average fan-out                             ; 1.70  ;
++---------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |ten_counter               ; 5 (5)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |ten_counter        ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 4     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 4     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:15:11 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ten_counter -c ten_counter
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file ten_counter.bdf
+    Info (12023): Found entity 1: ten_counter
+Info (12127): Elaborating entity "ten_counter" for the top level hierarchy
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 12 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 2 input pins
+    Info (21059): Implemented 5 output pins
+    Info (21061): Implemented 5 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 464 megabytes
+    Info: Processing ended: Fri Feb 26 16:15:13 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_counter/output_files/ten_counter.map.summary b/ten_counter/output_files/ten_counter.map.summary
new file mode 100644
index 0000000..7f5289a
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Fri Feb 26 16:15:13 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ten_counter
+Top-level Entity Name : ten_counter
+Family : Cyclone III
+Total logic elements : 5
+    Total combinational functions : 5
+    Dedicated logic registers : 4
+Total registers : 4
+Total pins : 7
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/ten_counter/output_files/ten_counter.pin b/ten_counter/output_files/ten_counter.pin
new file mode 100644
index 0000000..1730b07
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "ten_counter"  ASSIGNED TO AN: EP3C16U484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+cout                         : B1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+CLR                          : G3        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLK                          : G21       : input  : 2.5 V             :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+count[0]                     : H1        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H2        :        :                   :         : 1         :                
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+count[3]                     : J1        : output : 2.5 V             :         : 1         : Y              
+count[2]                     : J2        : output : 2.5 V             :         : 1         : Y              
+count[1]                     : J3        : output : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/ten_counter/output_files/ten_counter.sof b/ten_counter/output_files/ten_counter.sof
new file mode 100644
index 0000000..070cdc1
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.sof
diff --git a/ten_counter/output_files/ten_counter.sta.rpt b/ten_counter/output_files/ten_counter.sta.rpt
new file mode 100644
index 0000000..3d62226
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.sta.rpt
@@ -0,0 +1,821 @@
+TimeQuest Timing Analyzer report for ten_counter
+Fri Feb 26 16:15:23 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'CLK'
+ 13. Slow 1200mV 85C Model Hold: 'CLK'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'
+ 15. Clock to Output Times
+ 16. Minimum Clock to Output Times
+ 17. Slow 1200mV 85C Model Metastability Report
+ 18. Slow 1200mV 0C Model Fmax Summary
+ 19. Slow 1200mV 0C Model Setup Summary
+ 20. Slow 1200mV 0C Model Hold Summary
+ 21. Slow 1200mV 0C Model Recovery Summary
+ 22. Slow 1200mV 0C Model Removal Summary
+ 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 24. Slow 1200mV 0C Model Setup: 'CLK'
+ 25. Slow 1200mV 0C Model Hold: 'CLK'
+ 26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 27. Clock to Output Times
+ 28. Minimum Clock to Output Times
+ 29. Slow 1200mV 0C Model Metastability Report
+ 30. Fast 1200mV 0C Model Setup Summary
+ 31. Fast 1200mV 0C Model Hold Summary
+ 32. Fast 1200mV 0C Model Recovery Summary
+ 33. Fast 1200mV 0C Model Removal Summary
+ 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 35. Fast 1200mV 0C Model Setup: 'CLK'
+ 36. Fast 1200mV 0C Model Hold: 'CLK'
+ 37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 38. Clock to Output Times
+ 39. Minimum Clock to Output Times
+ 40. Fast 1200mV 0C Model Metastability Report
+ 41. Multicorner Timing Analysis Summary
+ 42. Clock to Output Times
+ 43. Minimum Clock to Output Times
+ 44. Board Trace Model Assignments
+ 45. Input Transition Times
+ 46. Slow Corner Signal Integrity Metrics
+ 47. Fast Corner Signal Integrity Metrics
+ 48. Setup Transfers
+ 49. Hold Transfers
+ 50. Report TCCS
+ 51. Report RSKM
+ 52. Unconstrained Paths
+ 53. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; ten_counter                                                        ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16U484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; CLK        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                        ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 931.97 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-------+--------+--------------------+
+; Clock ; Slack  ; End Point TNS      ;
++-------+--------+--------------------+
+; CLK   ; -0.073 ; -0.178             ;
++-------+--------+--------------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; CLK   ; 0.359 ; 0.000              ;
++-------+-------+--------------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-------+--------+----------------------------------+
+; Clock ; Slack  ; End Point TNS                    ;
++-------+--------+----------------------------------+
+; CLK   ; -3.000 ; -7.000                           ;
++-------+--------+----------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLK'                                                                 ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; -0.073 ; inst      ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 1.007      ;
+; -0.053 ; inst3     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.987      ;
+; -0.052 ; inst1     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.986      ;
+; -0.017 ; inst2     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.951      ;
+; 0.193  ; inst1     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.741      ;
+; 0.199  ; inst      ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.735      ;
+; 0.200  ; inst      ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.734      ;
+; 0.275  ; inst      ; inst    ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.659      ;
+; 0.275  ; inst2     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.659      ;
+; 0.275  ; inst1     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.659      ;
+; 0.297  ; inst3     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.061     ; 0.637      ;
++--------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLK'                                                                 ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.359 ; inst2     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst3     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; inst1     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.577      ;
+; 0.362 ; inst      ; inst    ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.580      ;
+; 0.406 ; inst      ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.624      ;
+; 0.407 ; inst      ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.625      ;
+; 0.418 ; inst1     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.636      ;
+; 0.576 ; inst2     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.794      ;
+; 0.589 ; inst      ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.807      ;
+; 0.598 ; inst3     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.816      ;
+; 0.602 ; inst1     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.061      ; 0.820      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'                                                           ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; 0.188  ; 0.372        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; 0.188  ; 0.372        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; 0.188  ; 0.372        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; 0.188  ; 0.372        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.650  ; 0.650        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.650  ; 0.650        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.650  ; 0.650        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.650  ; 0.650        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 6.713 ; 6.882 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 5.670 ; 5.715 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 6.713 ; 6.882 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 5.520 ; 5.583 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 5.510 ; 5.575 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 6.269 ; 6.226 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 5.399 ; 5.461 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 5.552 ; 5.595 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 6.601 ; 6.768 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 5.408 ; 5.468 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 5.399 ; 5.461 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 5.866 ; 5.817 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                         ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 1039.5 MHz ; 250.0 MHz       ; CLK        ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; CLK   ; 0.038 ; 0.000              ;
++-------+-------+--------------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.312 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -7.000                          ;
++-------+--------+---------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLK'                                                                 ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.038 ; inst      ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.902      ;
+; 0.057 ; inst3     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.883      ;
+; 0.058 ; inst1     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.882      ;
+; 0.099 ; inst2     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.841      ;
+; 0.274 ; inst1     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.666      ;
+; 0.278 ; inst      ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.662      ;
+; 0.279 ; inst      ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.661      ;
+; 0.357 ; inst      ; inst    ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.583      ;
+; 0.357 ; inst2     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.583      ;
+; 0.357 ; inst1     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.583      ;
+; 0.378 ; inst3     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.055     ; 0.562      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLK'                                                                  ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; inst2     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst3     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; inst1     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.511      ;
+; 0.320 ; inst      ; inst    ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.519      ;
+; 0.361 ; inst      ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.560      ;
+; 0.362 ; inst      ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.561      ;
+; 0.371 ; inst1     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.570      ;
+; 0.517 ; inst2     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.716      ;
+; 0.528 ; inst      ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.727      ;
+; 0.534 ; inst3     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.733      ;
+; 0.540 ; inst1     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.055      ; 0.739      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 6.443 ; 6.589 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 5.400 ; 5.402 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 6.443 ; 6.589 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 5.253 ; 5.290 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 5.244 ; 5.282 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 5.916 ; 5.878 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 5.144 ; 5.180 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 5.294 ; 5.295 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 6.343 ; 6.488 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 5.153 ; 5.187 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 5.144 ; 5.180 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 5.555 ; 5.507 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-------+-------+--------------------+
+; Clock ; Slack ; End Point TNS      ;
++-------+-------+--------------------+
+; CLK   ; 0.396 ; 0.000              ;
++-------+-------+--------------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++-------+-------+-------------------+
+; Clock ; Slack ; End Point TNS     ;
++-------+-------+-------------------+
+; CLK   ; 0.188 ; 0.000             ;
++-------+-------+-------------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -7.220                          ;
++-------+--------+---------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLK'                                                                 ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.396 ; inst      ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.556      ;
+; 0.407 ; inst3     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.545      ;
+; 0.410 ; inst1     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.542      ;
+; 0.428 ; inst2     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.524      ;
+; 0.550 ; inst1     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.402      ;
+; 0.554 ; inst      ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.398      ;
+; 0.556 ; inst      ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.396      ;
+; 0.593 ; inst      ; inst    ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.359      ;
+; 0.593 ; inst2     ; inst2   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.359      ;
+; 0.593 ; inst1     ; inst1   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.359      ;
+; 0.602 ; inst3     ; inst3   ; CLK          ; CLK         ; 1.000        ; -0.035     ; 0.350      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLK'                                                                  ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+; 0.188 ; inst2     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst3     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; inst1     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; inst      ; inst    ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.314      ;
+; 0.215 ; inst      ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.334      ;
+; 0.215 ; inst      ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.334      ;
+; 0.223 ; inst1     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.342      ;
+; 0.308 ; inst2     ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.427      ;
+; 0.315 ; inst      ; inst3   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.434      ;
+; 0.319 ; inst3     ; inst1   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.438      ;
+; 0.323 ; inst1     ; inst2   ; CLK          ; CLK         ; 0.000        ; 0.035      ; 0.442      ;
++-------+-----------+---------+--------------+-------------+--------------+------------+------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; -0.055 ; 0.129        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 4.135 ; 4.340 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 3.403 ; 3.465 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 4.135 ; 4.340 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 3.345 ; 3.397 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 3.339 ; 3.391 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 3.772 ; 3.734 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 3.274 ; 3.323 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 3.335 ; 3.395 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 4.070 ; 4.273 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 3.280 ; 3.329 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 3.274 ; 3.323 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 3.538 ; 3.511 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                          ;
++------------------+--------+-------+----------+---------+---------------------+
+; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+--------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -0.073 ; 0.188 ; N/A      ; N/A     ; -3.000              ;
+;  CLK             ; -0.073 ; 0.188 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -0.178 ; 0.0   ; 0.0      ; 0.0     ; -7.22               ;
+;  CLK             ; -0.178 ; 0.000 ; N/A      ; N/A     ; -7.220              ;
++------------------+--------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 6.713 ; 6.882 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 5.670 ; 5.715 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 6.713 ; 6.882 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 5.520 ; 5.583 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 5.510 ; 5.575 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 6.269 ; 6.226 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; count[*]  ; CLK        ; 3.274 ; 3.323 ; Rise       ; CLK             ;
+;  count[0] ; CLK        ; 3.335 ; 3.395 ; Rise       ; CLK             ;
+;  count[1] ; CLK        ; 4.070 ; 4.273 ; Rise       ; CLK             ;
+;  count[2] ; CLK        ; 3.280 ; 3.329 ; Rise       ; CLK             ;
+;  count[3] ; CLK        ; 3.274 ; 3.323 ; Rise       ; CLK             ;
+; cout      ; CLK        ; 3.538 ; 3.511 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; cout          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; count[3]      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; count[2]      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; count[1]      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; count[0]      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; CLK                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; CLR                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; count[3]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; count[2]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; count[1]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.33 V              ; -0.00317 V          ; 0.162 V                              ; 0.063 V                              ; 3.54e-09 s                  ; 3.41e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.33 V             ; -0.00317 V         ; 0.162 V                             ; 0.063 V                             ; 3.54e-09 s                 ; 3.41e-09 s                 ; Yes                       ; Yes                       ;
+; count[0]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.25e-07 V                   ; 2.35 V              ; -0.0111 V           ; 0.113 V                              ; 0.035 V                              ; 7.76e-10 s                  ; 8.04e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.25e-07 V                  ; 2.35 V             ; -0.0111 V          ; 0.113 V                             ; 0.035 V                             ; 7.76e-10 s                 ; 8.04e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; cout          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; count[3]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; count[2]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; count[1]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.64 V              ; -0.0109 V           ; 0.244 V                              ; 0.16 V                               ; 2.42e-09 s                  ; 2.37e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.64 V             ; -0.0109 V          ; 0.244 V                             ; 0.16 V                              ; 2.42e-09 s                 ; 2.37e-09 s                 ; No                        ; Yes                       ;
+; count[0]      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.78e-08 V                   ; 2.71 V              ; -0.0349 V           ; 0.253 V                              ; 0.069 V                              ; 4.96e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.78e-08 V                  ; 2.71 V             ; -0.0349 V          ; 0.253 V                             ; 0.069 V                             ; 4.96e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 11       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLK        ; CLK      ; 11       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 4     ; 4    ;
+; Unconstrained Output Ports      ; 5     ; 5    ;
+; Unconstrained Output Port Paths ; 8     ; 8    ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Fri Feb 26 16:15:22 2016
+Info: Command: quartus_sta ten_counter -c ten_counter
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_counter.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLK CLK
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.073
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.073        -0.178 CLK 
+Info (332146): Worst-case hold slack is 0.359
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.359         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000        -7.000 CLK 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 0.038
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.038         0.000 CLK 
+Info (332146): Worst-case hold slack is 0.312
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.312         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000        -7.000 CLK 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 0.396
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.396         0.000 CLK 
+Info (332146): Worst-case hold slack is 0.188
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.188         0.000 CLK 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000        -7.220 CLK 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 488 megabytes
+    Info: Processing ended: Fri Feb 26 16:15:23 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_counter/output_files/ten_counter.sta.summary b/ten_counter/output_files/ten_counter.sta.summary
new file mode 100644
index 0000000..55a9cea
--- /dev/null
+++ b/ten_counter/output_files/ten_counter.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'CLK'
+Slack : -0.073
+TNS   : -0.178
+
+Type  : Slow 1200mV 85C Model Hold 'CLK'
+Slack : 0.359
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -7.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLK'
+Slack : 0.038
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLK'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -7.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLK'
+Slack : 0.396
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLK'
+Slack : 0.188
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -7.220
+
+------------------------------------------------------------
diff --git a/ten_counter/simulation/modelsim/ten_counter.sft b/ten_counter/simulation/modelsim/ten_counter.sft
new file mode 100644
index 0000000..06a2ca4
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/ten_counter/simulation/modelsim/ten_counter.vho b/ten_counter/simulation/modelsim/ten_counter.vho
new file mode 100644
index 0000000..17860be
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter.vho
@@ -0,0 +1,365 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 14:45:46"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_counter IS
+    PORT (
+	cout : OUT std_logic;
+	CLR : IN std_logic;
+	CLK : IN std_logic;
+	count : OUT std_logic_vector(3 DOWNTO 0)
+	);
+END ten_counter;
+
+-- Design Ports Information
+-- cout	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[3]	=>  Location: PIN_R7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[2]	=>  Location: PIN_R8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[1]	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[0]	=>  Location: PIN_P8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLR	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_counter IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_cout : std_logic;
+SIGNAL ww_CLR : std_logic;
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_count : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLR~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \cout~output_o\ : std_logic;
+SIGNAL \count[3]~output_o\ : std_logic;
+SIGNAL \count[2]~output_o\ : std_logic;
+SIGNAL \count[1]~output_o\ : std_logic;
+SIGNAL \count[0]~output_o\ : std_logic;
+SIGNAL \inst~0_combout\ : std_logic;
+SIGNAL \CLR~input_o\ : std_logic;
+SIGNAL \CLR~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \inst5~0_combout\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \inst17~combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \ALT_INV_CLR~inputclkctrl_outclk\ : std_logic;
+
+BEGIN
+
+cout <= ww_cout;
+ww_CLR <= CLR;
+ww_CLK <= CLK;
+count <= ww_count;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+\CLR~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLR~input_o\);
+\ALT_INV_CLR~inputclkctrl_outclk\ <= NOT \CLR~inputclkctrl_outclk\;
+
+-- Location: IOIBUF_X0_Y14_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOOBUF_X0_Y3_N2
+\cout~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \cout~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N2
+\count[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \count[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N23
+\count[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \count[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N9
+\count[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \count[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N16
+\count[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \count[0]~output_o\);
+
+-- Location: LCCOMB_X1_Y2_N28
+\inst~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst~0_combout\ = !\inst~q\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst~q\,
+	combout => \inst~0_combout\);
+
+-- Location: IOIBUF_X0_Y14_N8
+\CLR~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLR,
+	o => \CLR~input_o\);
+
+-- Location: CLKCTRL_G2
+\CLR~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLR~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLR~inputclkctrl_outclk\);
+
+-- Location: FF_X1_Y2_N29
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+-- Location: LCCOMB_X1_Y2_N10
+\inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \inst2~q\ $ (((\inst1~q\ & \inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1~q\,
+	datac => \inst2~q\,
+	datad => \inst~q\,
+	combout => \inst2~0_combout\);
+
+-- Location: FF_X1_Y2_N11
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: LCCOMB_X1_Y2_N6
+\inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~0_combout\ = (\inst3~q\ & (\inst1~q\ $ (\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst5~0_combout\);
+
+-- Location: FF_X1_Y2_N7
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst5~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: LCCOMB_X1_Y2_N24
+inst17 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst17~combout\ = (\inst~q\ & (\inst2~q\ & ((\inst1~q\)))) # (!\inst~q\ & (((\inst3~q\ & !\inst1~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst~q\,
+	datac => \inst3~q\,
+	datad => \inst1~q\,
+	combout => \inst17~combout\);
+
+-- Location: FF_X1_Y2_N25
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst17~combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: LCCOMB_X1_Y2_N0
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (!\inst2~q\ & (!\inst3~q\ & (!\inst1~q\ & !\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst23~0_combout\);
+
+ww_cout <= \cout~output_o\;
+
+ww_count(3) <= \count[3]~output_o\;
+
+ww_count(2) <= \count[2]~output_o\;
+
+ww_count(1) <= \count[1]~output_o\;
+
+ww_count(0) <= \count[0]~output_o\;
+END structure;
+
+
diff --git a/ten_counter/simulation/modelsim/ten_counter.vo b/ten_counter/simulation/modelsim/ten_counter.vo
new file mode 100644
index 0000000..09cf7ca
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter.vo
@@ -0,0 +1,350 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "02/26/2016 16:15:42"
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module ten_counter (
+	cout,
+	CLR,
+	CLK,
+	count);
+output 	cout;
+input 	CLR;
+input 	CLK;
+output 	[3:0] count;
+
+// Design Ports Information
+// cout	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[3]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[2]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[1]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[0]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// CLK	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// CLR	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \CLK~input_o ;
+wire \CLK~inputclkctrl_outclk ;
+wire \cout~output_o ;
+wire \count[3]~output_o ;
+wire \count[2]~output_o ;
+wire \count[1]~output_o ;
+wire \count[0]~output_o ;
+wire \inst~0_combout ;
+wire \CLR~input_o ;
+wire \inst~q ;
+wire \inst2~0_combout ;
+wire \inst2~q ;
+wire \inst17~combout ;
+wire \inst3~q ;
+wire \inst5~0_combout ;
+wire \inst1~q ;
+wire \inst23~0_combout ;
+
+
+// Location: IOIBUF_X41_Y15_N1
+cycloneiii_io_ibuf \CLK~input (
+	.i(CLK),
+	.ibar(gnd),
+	.o(\CLK~input_o ));
+// synopsys translate_off
+defparam \CLK~input .bus_hold = "false";
+defparam \CLK~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneiii_clkctrl \CLK~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLK~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLK~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLK~inputclkctrl .clock_type = "global clock";
+defparam \CLK~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N16
+cycloneiii_io_obuf \cout~output (
+	.i(\inst23~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\cout~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \cout~output .bus_hold = "false";
+defparam \cout~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneiii_io_obuf \count[3]~output (
+	.i(\inst3~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[3]~output .bus_hold = "false";
+defparam \count[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneiii_io_obuf \count[2]~output (
+	.i(\inst2~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[2]~output .bus_hold = "false";
+defparam \count[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N23
+cycloneiii_io_obuf \count[1]~output (
+	.i(\inst1~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[1]~output .bus_hold = "false";
+defparam \count[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N16
+cycloneiii_io_obuf \count[0]~output (
+	.i(\inst~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[0]~output .bus_hold = "false";
+defparam \count[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N12
+cycloneiii_lcell_comb \inst~0 (
+// Equation(s):
+// \inst~0_combout  = !\inst~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\inst~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\inst~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst~0 .lut_mask = 16'h0F0F;
+defparam \inst~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y23_N15
+cycloneiii_io_ibuf \CLR~input (
+	.i(CLR),
+	.ibar(gnd),
+	.o(\CLR~input_o ));
+// synopsys translate_off
+defparam \CLR~input .bus_hold = "false";
+defparam \CLR~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N13
+dffeas inst(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst.is_wysiwyg = "true";
+defparam inst.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N14
+cycloneiii_lcell_comb \inst2~0 (
+// Equation(s):
+// \inst2~0_combout  = \inst2~q  $ (((\inst1~q  & \inst~q )))
+
+	.dataa(gnd),
+	.datab(\inst1~q ),
+	.datac(\inst2~q ),
+	.datad(\inst~q ),
+	.cin(gnd),
+	.combout(\inst2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst2~0 .lut_mask = 16'h3CF0;
+defparam \inst2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N15
+dffeas inst2(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst2.is_wysiwyg = "true";
+defparam inst2.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N28
+cycloneiii_lcell_comb inst17(
+// Equation(s):
+// \inst17~combout  = (\inst~q  & (\inst2~q  & ((\inst1~q )))) # (!\inst~q  & (((\inst3~q  & !\inst1~q ))))
+
+	.dataa(\inst~q ),
+	.datab(\inst2~q ),
+	.datac(\inst3~q ),
+	.datad(\inst1~q ),
+	.cin(gnd),
+	.combout(\inst17~combout ),
+	.cout());
+// synopsys translate_off
+defparam inst17.lut_mask = 16'h8850;
+defparam inst17.sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N29
+dffeas inst3(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst17~combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst3.is_wysiwyg = "true";
+defparam inst3.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N18
+cycloneiii_lcell_comb \inst5~0 (
+// Equation(s):
+// \inst5~0_combout  = (!\inst3~q  & (\inst1~q  $ (\inst~q )))
+
+	.dataa(gnd),
+	.datab(\inst3~q ),
+	.datac(\inst1~q ),
+	.datad(\inst~q ),
+	.cin(gnd),
+	.combout(\inst5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst5~0 .lut_mask = 16'h0330;
+defparam \inst5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N19
+dffeas inst1(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst1.is_wysiwyg = "true";
+defparam inst1.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N20
+cycloneiii_lcell_comb \inst23~0 (
+// Equation(s):
+// \inst23~0_combout  = (!\inst1~q  & (!\inst~q  & (!\inst3~q  & !\inst2~q )))
+
+	.dataa(\inst1~q ),
+	.datab(\inst~q ),
+	.datac(\inst3~q ),
+	.datad(\inst2~q ),
+	.cin(gnd),
+	.combout(\inst23~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst23~0 .lut_mask = 16'h0001;
+defparam \inst23~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+assign cout = \cout~output_o ;
+
+assign count[3] = \count[3]~output_o ;
+
+assign count[2] = \count[2]~output_o ;
+
+assign count[1] = \count[1]~output_o ;
+
+assign count[0] = \count[0]~output_o ;
+
+endmodule
diff --git a/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_slow.vho b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..17860be
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_slow.vho
@@ -0,0 +1,365 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 14:45:46"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_counter IS
+    PORT (
+	cout : OUT std_logic;
+	CLR : IN std_logic;
+	CLK : IN std_logic;
+	count : OUT std_logic_vector(3 DOWNTO 0)
+	);
+END ten_counter;
+
+-- Design Ports Information
+-- cout	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[3]	=>  Location: PIN_R7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[2]	=>  Location: PIN_R8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[1]	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[0]	=>  Location: PIN_P8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLR	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_counter IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_cout : std_logic;
+SIGNAL ww_CLR : std_logic;
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_count : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLR~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \cout~output_o\ : std_logic;
+SIGNAL \count[3]~output_o\ : std_logic;
+SIGNAL \count[2]~output_o\ : std_logic;
+SIGNAL \count[1]~output_o\ : std_logic;
+SIGNAL \count[0]~output_o\ : std_logic;
+SIGNAL \inst~0_combout\ : std_logic;
+SIGNAL \CLR~input_o\ : std_logic;
+SIGNAL \CLR~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \inst5~0_combout\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \inst17~combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \ALT_INV_CLR~inputclkctrl_outclk\ : std_logic;
+
+BEGIN
+
+cout <= ww_cout;
+ww_CLR <= CLR;
+ww_CLK <= CLK;
+count <= ww_count;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+\CLR~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLR~input_o\);
+\ALT_INV_CLR~inputclkctrl_outclk\ <= NOT \CLR~inputclkctrl_outclk\;
+
+-- Location: IOIBUF_X0_Y14_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOOBUF_X0_Y3_N2
+\cout~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \cout~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N2
+\count[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \count[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N23
+\count[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \count[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N9
+\count[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \count[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N16
+\count[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \count[0]~output_o\);
+
+-- Location: LCCOMB_X1_Y2_N28
+\inst~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst~0_combout\ = !\inst~q\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst~q\,
+	combout => \inst~0_combout\);
+
+-- Location: IOIBUF_X0_Y14_N8
+\CLR~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLR,
+	o => \CLR~input_o\);
+
+-- Location: CLKCTRL_G2
+\CLR~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLR~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLR~inputclkctrl_outclk\);
+
+-- Location: FF_X1_Y2_N29
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+-- Location: LCCOMB_X1_Y2_N10
+\inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \inst2~q\ $ (((\inst1~q\ & \inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1~q\,
+	datac => \inst2~q\,
+	datad => \inst~q\,
+	combout => \inst2~0_combout\);
+
+-- Location: FF_X1_Y2_N11
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: LCCOMB_X1_Y2_N6
+\inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~0_combout\ = (\inst3~q\ & (\inst1~q\ $ (\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst5~0_combout\);
+
+-- Location: FF_X1_Y2_N7
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst5~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: LCCOMB_X1_Y2_N24
+inst17 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst17~combout\ = (\inst~q\ & (\inst2~q\ & ((\inst1~q\)))) # (!\inst~q\ & (((\inst3~q\ & !\inst1~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst~q\,
+	datac => \inst3~q\,
+	datad => \inst1~q\,
+	combout => \inst17~combout\);
+
+-- Location: FF_X1_Y2_N25
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst17~combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: LCCOMB_X1_Y2_N0
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (!\inst2~q\ & (!\inst3~q\ & (!\inst1~q\ & !\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst23~0_combout\);
+
+ww_cout <= \cout~output_o\;
+
+ww_count(3) <= \count[3]~output_o\;
+
+ww_count(2) <= \count[2]~output_o\;
+
+ww_count(1) <= \count[1]~output_o\;
+
+ww_count(0) <= \count[0]~output_o\;
+END structure;
+
+
diff --git a/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..e5c50ae
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,255 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_counter")
+  (DATE "02/26/2016 14:45:46")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (140:140:140) (130:130:130))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (444:444:444) (403:403:403))
+        (IOPATH i o (2196:2196:2196) (2184:2184:2184))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (487:487:487) (481:481:481))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (354:354:354) (379:379:379))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (360:360:360) (388:388:388))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (358:358:358) (389:389:389))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLR\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLR\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (140:140:140) (130:130:130))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1322:1322:1322) (1342:1342:1342))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT clrn (1355:1355:1355) (1338:1338:1338))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+        (IOPATH (negedge clrn) q (173:173:173) (173:173:173))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (326:326:326))
+        (PORT datad (232:232:232) (297:297:297))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1322:1322:1322) (1342:1342:1342))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT clrn (1355:1355:1355) (1338:1338:1338))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+        (IOPATH (negedge clrn) q (173:173:173) (173:173:173))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (322:322:322))
+        (PORT datad (230:230:230) (295:295:295))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1322:1322:1322) (1342:1342:1342))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT clrn (1355:1355:1355) (1338:1338:1338))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+        (IOPATH (negedge clrn) q (173:173:173) (173:173:173))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (327:327:327))
+        (PORT datab (254:254:254) (327:327:327))
+        (PORT datad (225:225:225) (287:287:287))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1322:1322:1322) (1342:1342:1342))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT clrn (1355:1355:1355) (1338:1338:1338))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+        (IOPATH (negedge clrn) q (173:173:173) (173:173:173))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (324:324:324))
+        (PORT datab (247:247:247) (322:322:322))
+        (PORT datac (361:361:361) (397:397:397))
+        (PORT datad (357:357:357) (398:398:398))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_slow.vho b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..17860be
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_slow.vho
@@ -0,0 +1,365 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 14:45:46"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_counter IS
+    PORT (
+	cout : OUT std_logic;
+	CLR : IN std_logic;
+	CLK : IN std_logic;
+	count : OUT std_logic_vector(3 DOWNTO 0)
+	);
+END ten_counter;
+
+-- Design Ports Information
+-- cout	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[3]	=>  Location: PIN_R7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[2]	=>  Location: PIN_R8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[1]	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[0]	=>  Location: PIN_P8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLR	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_counter IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_cout : std_logic;
+SIGNAL ww_CLR : std_logic;
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_count : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLR~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \cout~output_o\ : std_logic;
+SIGNAL \count[3]~output_o\ : std_logic;
+SIGNAL \count[2]~output_o\ : std_logic;
+SIGNAL \count[1]~output_o\ : std_logic;
+SIGNAL \count[0]~output_o\ : std_logic;
+SIGNAL \inst~0_combout\ : std_logic;
+SIGNAL \CLR~input_o\ : std_logic;
+SIGNAL \CLR~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \inst5~0_combout\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \inst17~combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \ALT_INV_CLR~inputclkctrl_outclk\ : std_logic;
+
+BEGIN
+
+cout <= ww_cout;
+ww_CLR <= CLR;
+ww_CLK <= CLK;
+count <= ww_count;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+\CLR~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLR~input_o\);
+\ALT_INV_CLR~inputclkctrl_outclk\ <= NOT \CLR~inputclkctrl_outclk\;
+
+-- Location: IOIBUF_X0_Y14_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOOBUF_X0_Y3_N2
+\cout~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \cout~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N2
+\count[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \count[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N23
+\count[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \count[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N9
+\count[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \count[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N16
+\count[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \count[0]~output_o\);
+
+-- Location: LCCOMB_X1_Y2_N28
+\inst~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst~0_combout\ = !\inst~q\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst~q\,
+	combout => \inst~0_combout\);
+
+-- Location: IOIBUF_X0_Y14_N8
+\CLR~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLR,
+	o => \CLR~input_o\);
+
+-- Location: CLKCTRL_G2
+\CLR~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLR~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLR~inputclkctrl_outclk\);
+
+-- Location: FF_X1_Y2_N29
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+-- Location: LCCOMB_X1_Y2_N10
+\inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \inst2~q\ $ (((\inst1~q\ & \inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1~q\,
+	datac => \inst2~q\,
+	datad => \inst~q\,
+	combout => \inst2~0_combout\);
+
+-- Location: FF_X1_Y2_N11
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: LCCOMB_X1_Y2_N6
+\inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~0_combout\ = (\inst3~q\ & (\inst1~q\ $ (\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst5~0_combout\);
+
+-- Location: FF_X1_Y2_N7
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst5~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: LCCOMB_X1_Y2_N24
+inst17 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst17~combout\ = (\inst~q\ & (\inst2~q\ & ((\inst1~q\)))) # (!\inst~q\ & (((\inst3~q\ & !\inst1~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst~q\,
+	datac => \inst3~q\,
+	datad => \inst1~q\,
+	combout => \inst17~combout\);
+
+-- Location: FF_X1_Y2_N25
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst17~combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: LCCOMB_X1_Y2_N0
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (!\inst2~q\ & (!\inst3~q\ & (!\inst1~q\ & !\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst23~0_combout\);
+
+ww_cout <= \cout~output_o\;
+
+ww_count(3) <= \count[3]~output_o\;
+
+ww_count(2) <= \count[2]~output_o\;
+
+ww_count(1) <= \count[1]~output_o\;
+
+ww_count(0) <= \count[0]~output_o\;
+END structure;
+
+
diff --git a/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_vhd_slow.sdo b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..d1471e0
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,255 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_counter")
+  (DATE "02/26/2016 14:45:46")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (469:469:469) (453:453:453))
+        (IOPATH i o (2196:2196:2196) (2184:2184:2184))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (521:521:521) (545:545:545))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (387:387:387) (431:431:431))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (393:393:393) (441:441:441))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (392:392:392) (441:441:441))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLR\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLR\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (366:366:366))
+        (PORT datad (256:256:256) (333:333:333))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (274:274:274) (360:360:360))
+        (PORT datad (255:255:255) (331:331:331))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (366:366:366))
+        (PORT datab (279:279:279) (367:367:367))
+        (PORT datad (247:247:247) (321:321:321))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (362:362:362))
+        (PORT datab (274:274:274) (360:360:360))
+        (PORT datac (389:389:389) (450:450:450))
+        (PORT datad (388:388:388) (450:450:450))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_fast.vho b/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..17860be
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_fast.vho
@@ -0,0 +1,365 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+-- DATE "02/26/2016 14:45:46"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_counter IS
+    PORT (
+	cout : OUT std_logic;
+	CLR : IN std_logic;
+	CLK : IN std_logic;
+	count : OUT std_logic_vector(3 DOWNTO 0)
+	);
+END ten_counter;
+
+-- Design Ports Information
+-- cout	=>  Location: PIN_T5,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[3]	=>  Location: PIN_R7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[2]	=>  Location: PIN_R8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[1]	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- count[0]	=>  Location: PIN_P8,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_G2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLR	=>  Location: PIN_G1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_counter IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_cout : std_logic;
+SIGNAL ww_CLR : std_logic;
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_count : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLR~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \cout~output_o\ : std_logic;
+SIGNAL \count[3]~output_o\ : std_logic;
+SIGNAL \count[2]~output_o\ : std_logic;
+SIGNAL \count[1]~output_o\ : std_logic;
+SIGNAL \count[0]~output_o\ : std_logic;
+SIGNAL \inst~0_combout\ : std_logic;
+SIGNAL \CLR~input_o\ : std_logic;
+SIGNAL \CLR~inputclkctrl_outclk\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+SIGNAL \inst2~0_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \inst5~0_combout\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \inst17~combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \inst23~0_combout\ : std_logic;
+SIGNAL \ALT_INV_CLR~inputclkctrl_outclk\ : std_logic;
+
+BEGIN
+
+cout <= ww_cout;
+ww_CLR <= CLR;
+ww_CLK <= CLK;
+count <= ww_count;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+\CLR~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLR~input_o\);
+\ALT_INV_CLR~inputclkctrl_outclk\ <= NOT \CLR~inputclkctrl_outclk\;
+
+-- Location: IOIBUF_X0_Y14_N1
+\CLK~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G4
+\CLK~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOOBUF_X0_Y3_N2
+\cout~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst23~0_combout\,
+	devoe => ww_devoe,
+	o => \cout~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N2
+\count[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \count[3]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N23
+\count[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \count[2]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N9
+\count[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \count[1]~output_o\);
+
+-- Location: IOOBUF_X0_Y2_N16
+\count[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \count[0]~output_o\);
+
+-- Location: LCCOMB_X1_Y2_N28
+\inst~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst~0_combout\ = !\inst~q\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111100001111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datac => \inst~q\,
+	combout => \inst~0_combout\);
+
+-- Location: IOIBUF_X0_Y14_N8
+\CLR~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLR,
+	o => \CLR~input_o\);
+
+-- Location: CLKCTRL_G2
+\CLR~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLR~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLR~inputclkctrl_outclk\);
+
+-- Location: FF_X1_Y2_N29
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+-- Location: LCCOMB_X1_Y2_N10
+\inst2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst2~0_combout\ = \inst2~q\ $ (((\inst1~q\ & \inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst1~q\,
+	datac => \inst2~q\,
+	datad => \inst~q\,
+	combout => \inst2~0_combout\);
+
+-- Location: FF_X1_Y2_N11
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: LCCOMB_X1_Y2_N6
+\inst5~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst5~0_combout\ = (\inst3~q\ & (\inst1~q\ $ (\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst5~0_combout\);
+
+-- Location: FF_X1_Y2_N7
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst5~0_combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: LCCOMB_X1_Y2_N24
+inst17 : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst17~combout\ = (\inst~q\ & (\inst2~q\ & ((\inst1~q\)))) # (!\inst~q\ & (((\inst3~q\ & !\inst1~q\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000100000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst~q\,
+	datac => \inst3~q\,
+	datad => \inst1~q\,
+	combout => \inst17~combout\);
+
+-- Location: FF_X1_Y2_N25
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst17~combout\,
+	clrn => \ALT_INV_CLR~inputclkctrl_outclk\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: LCCOMB_X1_Y2_N0
+\inst23~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \inst23~0_combout\ = (!\inst2~q\ & (!\inst3~q\ & (!\inst1~q\ & !\inst~q\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \inst2~q\,
+	datab => \inst3~q\,
+	datac => \inst1~q\,
+	datad => \inst~q\,
+	combout => \inst23~0_combout\);
+
+ww_cout <= \cout~output_o\;
+
+ww_count(3) <= \count[3]~output_o\;
+
+ww_count(2) <= \count[2]~output_o\;
+
+ww_count(1) <= \count[1]~output_o\;
+
+ww_count(0) <= \count[0]~output_o\;
+END structure;
+
+
diff --git a/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_vhd_fast.sdo b/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..a3e3f8a
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,255 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16U484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_counter")
+  (DATE "02/26/2016 14:45:46")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (411:411:411) (793:793:793))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (97:97:97) (82:82:82))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (236:236:236) (256:256:256))
+        (IOPATH i o (1436:1436:1436) (1420:1420:1420))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (266:266:266) (302:302:302))
+        (IOPATH i o (1456:1456:1456) (1440:1440:1440))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (200:200:200) (238:238:238))
+        (IOPATH i o (1446:1446:1446) (1430:1430:1430))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (205:205:205) (244:244:244))
+        (IOPATH i o (1456:1456:1456) (1440:1440:1440))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (204:204:204) (244:244:244))
+        (IOPATH i o (1446:1446:1446) (1430:1430:1430))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLR\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (411:411:411) (793:793:793))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLR\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (97:97:97) (82:82:82))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (890:890:890) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (876:876:876) (881:881:881))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (200:200:200))
+        (PORT datad (139:139:139) (182:182:182))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (890:890:890) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (876:876:876) (881:881:881))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (150:150:150) (199:199:199))
+        (PORT datad (141:141:141) (180:180:180))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (890:890:890) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (876:876:876) (881:881:881))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (148:148:148) (202:202:202))
+        (PORT datab (150:150:150) (201:201:201))
+        (PORT datad (137:137:137) (175:175:175))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (890:890:890) (895:895:895))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT clrn (876:876:876) (881:881:881))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (200:200:200))
+        (PORT datab (150:150:150) (201:201:201))
+        (PORT datac (204:204:204) (250:250:250))
+        (PORT datad (206:206:206) (252:252:252))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/ten_counter/simulation/modelsim/ten_counter_modelsim.xrf b/ten_counter/simulation/modelsim/ten_counter_modelsim.xrf
new file mode 100644
index 0000000..bdcf83e
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_modelsim.xrf
@@ -0,0 +1,17 @@
+vendor_name = ModelSim
+source_file = 1, C:/Git/ten_counter/ten_counter.bdf
+source_file = 1, C:/Git/ten_counter/Waveform.vwf
+source_file = 1, C:/Git/ten_counter/db/ten_counter.cbx.xml
+design_name = ten_counter
+instance = comp, \CLK~input , CLK~input, ten_counter, 1
+instance = comp, \CLK~inputclkctrl , CLK~inputclkctrl, ten_counter, 1
+instance = comp, \cout~output , cout~output, ten_counter, 1
+instance = comp, \count[3]~output , count[3]~output, ten_counter, 1
+instance = comp, \count[2]~output , count[2]~output, ten_counter, 1
+instance = comp, \count[1]~output , count[1]~output, ten_counter, 1
+instance = comp, \count[0]~output , count[0]~output, ten_counter, 1
+instance = comp, \inst~0 , inst~0, ten_counter, 1
+instance = comp, \CLR~input , CLR~input, ten_counter, 1
+instance = comp, \inst2~0 , inst2~0, ten_counter, 1
+instance = comp, \inst5~0 , inst5~0, ten_counter, 1
+instance = comp, \inst23~0 , inst23~0, ten_counter, 1
diff --git a/ten_counter/simulation/modelsim/ten_counter_vhd.sdo b/ten_counter/simulation/modelsim/ten_counter_vhd.sdo
new file mode 100644
index 0000000..d1471e0
--- /dev/null
+++ b/ten_counter/simulation/modelsim/ten_counter_vhd.sdo
@@ -0,0 +1,255 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_counter")
+  (DATE "02/26/2016 14:45:46")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\cout\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (469:469:469) (453:453:453))
+        (IOPATH i o (2196:2196:2196) (2184:2184:2184))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (521:521:521) (545:545:545))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (387:387:387) (431:431:431))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (393:393:393) (441:441:441))
+        (IOPATH i o (2216:2216:2216) (2204:2204:2204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\count\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (392:392:392) (441:441:441))
+        (IOPATH i o (2206:2206:2206) (2194:2194:2194))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\CLR\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (755:755:755) (916:916:916))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\CLR\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (366:366:366))
+        (PORT datad (256:256:256) (333:333:333))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst5\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (274:274:274) (360:360:360))
+        (PORT datad (255:255:255) (331:331:331))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE inst17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (366:366:366))
+        (PORT datab (279:279:279) (367:367:367))
+        (PORT datad (247:247:247) (321:321:321))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1499:1499:1499) (1516:1516:1516))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT clrn (1531:1531:1531) (1526:1526:1526))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+        (IOPATH (negedge clrn) q (194:194:194) (194:194:194))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\inst23\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (272:272:272) (362:362:362))
+        (PORT datab (274:274:274) (360:360:360))
+        (PORT datac (389:389:389) (450:450:450))
+        (PORT datad (388:388:388) (450:450:450))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/ten_counter/simulation/qsim/ten_counter.do b/ten_counter/simulation/qsim/ten_counter.do
new file mode 100644
index 0000000..43db372
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.do
@@ -0,0 +1,10 @@
+onerror {quit -f}
+vlib work
+vlog -work work ten_counter.vo
+vlog -work work ten_counter.vt
+vsim -novopt -c -t 1ps -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.ten_counter_vlg_vec_tst
+vcd file -direction ten_counter.msim.vcd
+vcd add -internal ten_counter_vlg_vec_tst/*
+vcd add -internal ten_counter_vlg_vec_tst/i1/*
+add wave /*
+run -all
diff --git a/ten_counter/simulation/qsim/ten_counter.msim.vcd b/ten_counter/simulation/qsim/ten_counter.msim.vcd
new file mode 100644
index 0000000..25c9d6d
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.msim.vcd
@@ -0,0 +1,969 @@
+$comment
+	File created using the following command:
+		vcd file ten_counter.msim.vcd -direction
+$end
+$date
+	Fri Feb 26 16:15:43 2016
+$end
+$version
+	ModelSim Version 10.1d
+$end
+$timescale
+	1ps
+$end
+$scope module ten_counter_vlg_vec_tst $end
+$var reg 1 ! CLK $end
+$var reg 1 " CLR $end
+$var wire 1 # count [3] $end
+$var wire 1 $ count [2] $end
+$var wire 1 % count [1] $end
+$var wire 1 & count [0] $end
+$var wire 1 ' cout $end
+$var wire 1 ( sampler $end
+$scope module i1 $end
+$var wire 1 ) gnd $end
+$var wire 1 * vcc $end
+$var wire 1 + unknown $end
+$var tri1 1 , devclrn $end
+$var tri1 1 - devpor $end
+$var tri1 1 . devoe $end
+$var wire 1 / CLK~input_o $end
+$var wire 1 0 CLK~inputclkctrl_outclk $end
+$var wire 1 1 cout~output_o $end
+$var wire 1 2 count[3]~output_o $end
+$var wire 1 3 count[2]~output_o $end
+$var wire 1 4 count[1]~output_o $end
+$var wire 1 5 count[0]~output_o $end
+$var wire 1 6 inst~0_combout $end
+$var wire 1 7 CLR~input_o $end
+$var wire 1 8 inst~q $end
+$var wire 1 9 inst2~0_combout $end
+$var wire 1 : inst2~q $end
+$var wire 1 ; inst17~combout $end
+$var wire 1 < inst3~q $end
+$var wire 1 = inst5~0_combout $end
+$var wire 1 > inst1~q $end
+$var wire 1 ? inst23~0_combout $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0!
+0"
+0&
+0%
+0$
+0#
+1'
+x(
+0)
+1*
+x+
+1,
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+0:
+0;
+0<
+0=
+0>
+1?
+$end
+#10000
+1!
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+#20000
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diff --git a/ten_counter/simulation/qsim/ten_counter.msim.vwf b/ten_counter/simulation/qsim/ten_counter.msim.vwf
new file mode 100644
index 0000000..57d0e47
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.msim.vwf
@@ -0,0 +1,1688 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 0.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|CLK")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|CLR")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|count[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|count[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|count[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|count[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|cout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|sampler")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|gnd")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|vcc")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|unknown")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|devclrn")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|devpor")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|devoe")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|CLK~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|CLK~inputclkctrl_outclk")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|cout~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|count[3]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|count[2]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|count[1]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|count[0]~output_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|CLR~input_o")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst~q")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst2~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst2~q")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst17~combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst3~q")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst5~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst1~q")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("ten_counter_vlg_vec_tst|i1|inst23~0_combout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|CLK")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|CLR")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|count[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 150.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
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+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 10.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst2~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 50.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 70.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst2~q")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 70.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 50.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst17~combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 130.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 30.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst3~q")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 150.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 10.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst5~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 70.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst1~q")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 30.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 50.0;
+	}
+}
+
+TRANSITION_LIST("ten_counter_vlg_vec_tst|i1|inst23~0_combout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 10.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|CLK";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|CLR";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|count[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|count[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|count[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|count[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|cout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|sampler";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|gnd";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|vcc";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|unknown";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|devclrn";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 11;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|devpor";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 12;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|devoe";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 13;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|CLK~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 14;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|CLK~inputclkctrl_outclk";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 15;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|cout~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 16;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|count[3]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 17;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|count[2]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 18;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|count[1]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 19;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|count[0]~output_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 20;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 21;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|CLR~input_o";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 22;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst~q";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 23;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst2~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 24;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst2~q";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 25;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst17~combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 26;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst3~q";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 27;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst5~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 28;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst1~q";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 29;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "ten_counter_vlg_vec_tst|i1|inst23~0_combout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 30;
+	TREE_LEVEL = 0;
+}
+;
diff --git a/ten_counter/simulation/qsim/ten_counter.sim.vwf b/ten_counter/simulation/qsim/ten_counter.sim.vwf
new file mode 100644
index 0000000..7161203
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.sim.vwf
@@ -0,0 +1,456 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 0.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+
+
+
+SIGNAL("CLK")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("CLR")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("count")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 4;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("count[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("count[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "count";
+}
+
+SIGNAL("cout")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+TRANSITION_LIST("CLK")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 10.0;
+	}
+}
+TRANSITION_LIST("CLR")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+TRANSITION_LIST("count[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 150.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 160.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 10.0;
+	}
+}
+TRANSITION_LIST("count[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 70.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 120.0;
+		LEVEL 1 FOR 80.0;
+		LEVEL 0 FOR 50.0;
+	}
+}
+TRANSITION_LIST("count[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 30.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 80.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 40.0;
+		LEVEL 1 FOR 40.0;
+		LEVEL 0 FOR 50.0;
+	}
+}
+TRANSITION_LIST("count[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 10.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 20.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 10.0;
+	}
+}
+TRANSITION_LIST("cout")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 1 FOR 10.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 20.0;
+		LEVEL 0 FOR 180.0;
+		LEVEL 1 FOR 10.0;
+	}
+}
+
+
+DISPLAY_LINE
+{
+	CHANNEL = "CLK";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "CLR";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 0;
+	CHILDREN = 3, 4, 5, 6;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "count[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "cout";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 0;
+}
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;
diff --git a/ten_counter/simulation/qsim/ten_counter.vo b/ten_counter/simulation/qsim/ten_counter.vo
new file mode 100644
index 0000000..09cf7ca
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.vo
@@ -0,0 +1,350 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 64-Bit"
+// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
+
+// DATE "02/26/2016 16:15:42"
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module ten_counter (
+	cout,
+	CLR,
+	CLK,
+	count);
+output 	cout;
+input 	CLR;
+input 	CLK;
+output 	[3:0] count;
+
+// Design Ports Information
+// cout	=>  Location: PIN_B1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[3]	=>  Location: PIN_J1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[2]	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[1]	=>  Location: PIN_J3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// count[0]	=>  Location: PIN_H1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// CLK	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+// CLR	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \CLK~input_o ;
+wire \CLK~inputclkctrl_outclk ;
+wire \cout~output_o ;
+wire \count[3]~output_o ;
+wire \count[2]~output_o ;
+wire \count[1]~output_o ;
+wire \count[0]~output_o ;
+wire \inst~0_combout ;
+wire \CLR~input_o ;
+wire \inst~q ;
+wire \inst2~0_combout ;
+wire \inst2~q ;
+wire \inst17~combout ;
+wire \inst3~q ;
+wire \inst5~0_combout ;
+wire \inst1~q ;
+wire \inst23~0_combout ;
+
+
+// Location: IOIBUF_X41_Y15_N1
+cycloneiii_io_ibuf \CLK~input (
+	.i(CLK),
+	.ibar(gnd),
+	.o(\CLK~input_o ));
+// synopsys translate_off
+defparam \CLK~input .bus_hold = "false";
+defparam \CLK~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneiii_clkctrl \CLK~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLK~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLK~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLK~inputclkctrl .clock_type = "global clock";
+defparam \CLK~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N16
+cycloneiii_io_obuf \cout~output (
+	.i(\inst23~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\cout~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \cout~output .bus_hold = "false";
+defparam \cout~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneiii_io_obuf \count[3]~output (
+	.i(\inst3~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[3]~output .bus_hold = "false";
+defparam \count[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneiii_io_obuf \count[2]~output (
+	.i(\inst2~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[2]~output .bus_hold = "false";
+defparam \count[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N23
+cycloneiii_io_obuf \count[1]~output (
+	.i(\inst1~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[1]~output .bus_hold = "false";
+defparam \count[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N16
+cycloneiii_io_obuf \count[0]~output (
+	.i(\inst~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\count[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \count[0]~output .bus_hold = "false";
+defparam \count[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N12
+cycloneiii_lcell_comb \inst~0 (
+// Equation(s):
+// \inst~0_combout  = !\inst~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\inst~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\inst~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst~0 .lut_mask = 16'h0F0F;
+defparam \inst~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y23_N15
+cycloneiii_io_ibuf \CLR~input (
+	.i(CLR),
+	.ibar(gnd),
+	.o(\CLR~input_o ));
+// synopsys translate_off
+defparam \CLR~input .bus_hold = "false";
+defparam \CLR~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N13
+dffeas inst(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst.is_wysiwyg = "true";
+defparam inst.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N14
+cycloneiii_lcell_comb \inst2~0 (
+// Equation(s):
+// \inst2~0_combout  = \inst2~q  $ (((\inst1~q  & \inst~q )))
+
+	.dataa(gnd),
+	.datab(\inst1~q ),
+	.datac(\inst2~q ),
+	.datad(\inst~q ),
+	.cin(gnd),
+	.combout(\inst2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst2~0 .lut_mask = 16'h3CF0;
+defparam \inst2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N15
+dffeas inst2(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst2~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst2~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst2.is_wysiwyg = "true";
+defparam inst2.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N28
+cycloneiii_lcell_comb inst17(
+// Equation(s):
+// \inst17~combout  = (\inst~q  & (\inst2~q  & ((\inst1~q )))) # (!\inst~q  & (((\inst3~q  & !\inst1~q ))))
+
+	.dataa(\inst~q ),
+	.datab(\inst2~q ),
+	.datac(\inst3~q ),
+	.datad(\inst1~q ),
+	.cin(gnd),
+	.combout(\inst17~combout ),
+	.cout());
+// synopsys translate_off
+defparam inst17.lut_mask = 16'h8850;
+defparam inst17.sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N29
+dffeas inst3(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst17~combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst3~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst3.is_wysiwyg = "true";
+defparam inst3.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N18
+cycloneiii_lcell_comb \inst5~0 (
+// Equation(s):
+// \inst5~0_combout  = (!\inst3~q  & (\inst1~q  $ (\inst~q )))
+
+	.dataa(gnd),
+	.datab(\inst3~q ),
+	.datac(\inst1~q ),
+	.datad(\inst~q ),
+	.cin(gnd),
+	.combout(\inst5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst5~0 .lut_mask = 16'h0330;
+defparam \inst5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X1_Y23_N19
+dffeas inst1(
+	.clk(\CLK~inputclkctrl_outclk ),
+	.d(\inst5~0_combout ),
+	.asdata(vcc),
+	.clrn(!\CLR~input_o ),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\inst1~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam inst1.is_wysiwyg = "true";
+defparam inst1.power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X1_Y23_N20
+cycloneiii_lcell_comb \inst23~0 (
+// Equation(s):
+// \inst23~0_combout  = (!\inst1~q  & (!\inst~q  & (!\inst3~q  & !\inst2~q )))
+
+	.dataa(\inst1~q ),
+	.datab(\inst~q ),
+	.datac(\inst3~q ),
+	.datad(\inst2~q ),
+	.cin(gnd),
+	.combout(\inst23~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \inst23~0 .lut_mask = 16'h0001;
+defparam \inst23~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+assign cout = \cout~output_o ;
+
+assign count[3] = \count[3]~output_o ;
+
+assign count[2] = \count[2]~output_o ;
+
+assign count[1] = \count[1]~output_o ;
+
+assign count[0] = \count[0]~output_o ;
+
+endmodule
diff --git a/ten_counter/simulation/qsim/ten_counter.vt b/ten_counter/simulation/qsim/ten_counter.vt
new file mode 100644
index 0000000..21490d2
--- /dev/null
+++ b/ten_counter/simulation/qsim/ten_counter.vt
@@ -0,0 +1,280 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// *****************************************************************************
+// This file contains a Verilog test bench with test vectors .The test vectors  
+// are exported from a vector file in the Quartus Waveform Editor and apply to  
+// the top level entity of the current Quartus project .The user can use this   
+// testbench to simulate his design using a third-party simulation tool .       
+// *****************************************************************************
+// Generated on "02/26/2016 16:15:41"
+                                                                        
+// Verilog Self-Checking Test Bench (with test vectors) for design :    ten_counter
+// 
+// Simulation tool : 3rd Party
+// 
+
+`timescale 1 ps/ 1 ps
+module ten_counter_vlg_sample_tst(
+	CLK,
+	CLR,
+	sampler_tx
+);
+input  CLK;
+input  CLR;
+output sampler_tx;
+
+reg sample;
+time current_time;
+always @(CLK or CLR)
+                                                                                
+begin                                                 
+ if ($realtime > 0)                                   
+ begin                                                
+	if ($realtime == 0 || $realtime != current_time)  
+	begin									          
+		if (sample === 1'bx)                          
+			sample = 0;                               
+		else                                          
+			sample = ~sample;                         
+	end										          
+	current_time = $realtime;					      
+ end                                                  
+end                                                   
+
+assign sampler_tx = sample;
+endmodule
+
+module ten_counter_vlg_check_tst (
+	count,
+	cout,
+	sampler_rx
+);
+input [3:0] count;
+input  cout;
+input sampler_rx;
+
+reg [3:0] count_expected;
+reg  cout_expected;
+
+reg [3:0] count_prev;
+reg  cout_prev;
+
+reg [3:0] count_expected_prev;
+reg  cout_expected_prev;
+
+reg [3:0] last_count_exp;
+reg  last_cout_exp;
+
+reg trigger;
+
+integer i;
+integer nummismatches;
+
+reg [1:2] on_first_change ;
+
+
+initial
+begin
+trigger = 0;
+i = 0;
+nummismatches = 0;
+on_first_change = 2'b1;
+end
+
+// update real /o prevs
+
+always @(trigger)
+begin
+	count_prev = count;
+	cout_prev = cout;
+end
+
+// update expected /o prevs
+
+always @(trigger)
+begin
+	count_expected_prev = count_expected;
+	cout_expected_prev = cout_expected;
+end
+
+
+// expected count[ 3 ]
+initial
+begin
+	count_expected[3] = 1'bX;
+end 
+// expected count[ 2 ]
+initial
+begin
+	count_expected[2] = 1'bX;
+end 
+// expected count[ 1 ]
+initial
+begin
+	count_expected[1] = 1'bX;
+end 
+// expected count[ 0 ]
+initial
+begin
+	count_expected[0] = 1'bX;
+end 
+
+// expected cout
+initial
+begin
+	cout_expected = 1'bX;
+end 
+// generate trigger
+always @(count_expected or count or cout_expected or cout)
+begin
+	trigger <= ~trigger;
+end
+
+always @(posedge sampler_rx or negedge sampler_rx)
+begin
+`ifdef debug_tbench
+	$display("Scanning pattern %d @time = %t",i,$realtime );
+	i = i + 1;
+	$display("| expected count = %b | expected cout = %b | ",count_expected_prev,cout_expected_prev);
+	$display("| real count = %b | real cout = %b | ",count_prev,cout_prev);
+`endif
+	if (
+		( count_expected_prev[0] !== 1'bx ) && ( count_prev[0] !== count_expected_prev[0] )
+		&& ((count_expected_prev[0] !== last_count_exp[0]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port count[0] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", count_expected_prev);
+		$display ("     Real value = %b", count_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_count_exp[0] = count_expected_prev[0];
+	end
+	if (
+		( count_expected_prev[1] !== 1'bx ) && ( count_prev[1] !== count_expected_prev[1] )
+		&& ((count_expected_prev[1] !== last_count_exp[1]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port count[1] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", count_expected_prev);
+		$display ("     Real value = %b", count_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_count_exp[1] = count_expected_prev[1];
+	end
+	if (
+		( count_expected_prev[2] !== 1'bx ) && ( count_prev[2] !== count_expected_prev[2] )
+		&& ((count_expected_prev[2] !== last_count_exp[2]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port count[2] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", count_expected_prev);
+		$display ("     Real value = %b", count_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_count_exp[2] = count_expected_prev[2];
+	end
+	if (
+		( count_expected_prev[3] !== 1'bx ) && ( count_prev[3] !== count_expected_prev[3] )
+		&& ((count_expected_prev[3] !== last_count_exp[3]) ||
+			on_first_change[1])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port count[3] :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", count_expected_prev);
+		$display ("     Real value = %b", count_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[1] = 1'b0;
+		last_count_exp[3] = count_expected_prev[3];
+	end
+	if (
+		( cout_expected_prev !== 1'bx ) && ( cout_prev !== cout_expected_prev )
+		&& ((cout_expected_prev !== last_cout_exp) ||
+			on_first_change[2])
+	)
+	begin
+		$display ("ERROR! Vector Mismatch for output port cout :: @time = %t",  $realtime);
+		$display ("     Expected value = %b", cout_expected_prev);
+		$display ("     Real value = %b", cout_prev);
+		nummismatches = nummismatches + 1;
+		on_first_change[2] = 1'b0;
+		last_cout_exp = cout_expected_prev;
+	end
+
+	trigger <= ~trigger;
+end
+initial 
+
+begin 
+$timeformat(-12,3," ps",6);
+#1000000;
+if (nummismatches > 0)
+	$display ("%d mismatched vectors : Simulation failed !",nummismatches);
+else
+	$display ("Simulation passed !");
+$finish;
+end 
+endmodule
+
+module ten_counter_vlg_vec_tst();
+// constants                                           
+// general purpose registers
+reg CLK;
+reg CLR;
+// wires                                               
+wire [3:0] count;
+wire cout;
+
+wire sampler;                             
+
+// assign statements (if any)                          
+ten_counter i1 (
+// port map - connection between master ports and signals/registers   
+	.CLK(CLK),
+	.CLR(CLR),
+	.count(count),
+	.cout(cout)
+);
+
+// CLK
+always
+begin
+	CLK = 1'b0;
+	CLK = #10000 1'b1;
+	#10000;
+end 
+
+// CLR
+initial
+begin
+	CLR = 1'b0;
+end 
+
+ten_counter_vlg_sample_tst tb_sample (
+	.CLK(CLK),
+	.CLR(CLR),
+	.sampler_tx(sampler)
+);
+
+ten_counter_vlg_check_tst tb_out(
+	.count(count),
+	.cout(cout),
+	.sampler_rx(sampler)
+);
+endmodule
+
diff --git a/ten_counter/simulation/qsim/transcript b/ten_counter/simulation/qsim/transcript
new file mode 100644
index 0000000..c52feaa
--- /dev/null
+++ b/ten_counter/simulation/qsim/transcript
@@ -0,0 +1,31 @@
+# do ten_counter.do 
+# ** Warning: (vlib-34) Library already exists at "work".
+# 
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module ten_counter
+# 
+# Top level modules:
+# 	ten_counter
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module ten_counter_vlg_sample_tst
+# -- Compiling module ten_counter_vlg_check_tst
+# -- Compiling module ten_counter_vlg_vec_tst
+# 
+# Top level modules:
+# 	ten_counter_vlg_vec_tst
+# vsim -L cycloneiii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.ten_counter_vlg_vec_tst 
+# Loading work.ten_counter_vlg_vec_tst
+# Loading work.ten_counter
+# Loading cycloneiii_ver.cycloneiii_io_ibuf
+# Loading cycloneiii_ver.cycloneiii_clkctrl
+# Loading cycloneiii_ver.cycloneiii_mux41
+# Loading cycloneiii_ver.cycloneiii_ena_reg
+# Loading cycloneiii_ver.cycloneiii_io_obuf
+# Loading cycloneiii_ver.cycloneiii_lcell_comb
+# Loading altera_ver.dffeas
+# Loading work.ten_counter_vlg_sample_tst
+# Loading work.ten_counter_vlg_check_tst
+# Loading altera_ver.PRIM_GDFF_LOW
+# Simulation passed !
+# ** Note: $finish    : ten_counter.vt(230)
+#    Time: 1 us  Iteration: 0  Instance: /ten_counter_vlg_vec_tst/tb_out
diff --git a/ten_counter/simulation/qsim/vsim.wlf b/ten_counter/simulation/qsim/vsim.wlf
new file mode 100644
index 0000000..17abc4d
--- /dev/null
+++ b/ten_counter/simulation/qsim/vsim.wlf
diff --git a/ten_counter/simulation/qsim/work/_info b/ten_counter/simulation/qsim/work/_info
new file mode 100644
index 0000000..ad7c475
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/_info
@@ -0,0 +1,81 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Git\ten_counter\simulation\qsim
+vten_counter
+Z1 IbfjoJY8YHaMmeJLgDbn?K0
+Z2 V[7T]gjh:a7bhd@mRa6GnV2
+Z3 dC:\Git\ten_counter\simulation\qsim
+Z4 w1456503342
+Z5 8ten_counter.vo
+Z6 Ften_counter.vo
+L0 31
+Z7 OV;L;10.1d;51
+r1
+31
+Z8 !s90 -work|work|ten_counter.vo|
+Z9 o-work work -O0
+!i10b 1
+Z10 !s100 gmZF6S?c5Mi=@SH^azPFc2
+!s85 0
+Z11 !s108 1456503343.193000
+Z12 !s107 ten_counter.vo|
+!s101 -O0
+vten_counter_vlg_check_tst
+!i10b 1
+Z13 !s100 3375P]3YioomKlU7[^R@D1
+Z14 I_egOkM1H?S:H53XhNIJ@B2
+Z15 VAb>gh:a;S_YP^];fW5JO:0
+R3
+Z16 w1456503341
+Z17 8ten_counter.vt
+Z18 Ften_counter.vt
+L0 59
+R7
+r1
+!s85 0
+31
+Z19 !s108 1456503343.270000
+Z20 !s107 ten_counter.vt|
+Z21 !s90 -work|work|ten_counter.vt|
+!s101 -O0
+R9
+vten_counter_vlg_sample_tst
+!i10b 1
+Z22 !s100 ]`MG<[e;bgTZ8Wc5I_iAJ1
+Z23 I]9DXn@S4i_gJ=>A8iO@LG2
+Z24 VQYLh5:Q8kDHc2;41;hm=e3
+R3
+R16
+R17
+R18
+L0 29
+R7
+r1
+!s85 0
+31
+R19
+R20
+R21
+!s101 -O0
+R9
+vten_counter_vlg_vec_tst
+!i10b 1
+Z25 !s100 BN8;1W<VH9kPgY:8JZZUF3
+Z26 I0hZ_LmRbX2L^ALknlJk4T1
+Z27 VLBKFMjeS_HL=bJXC3^h^N3
+R3
+R16
+R17
+R18
+Z28 L0 234
+R7
+r1
+!s85 0
+31
+R19
+R20
+R21
+!s101 -O0
+R9
diff --git a/ten_counter/simulation/qsim/work/_vmake b/ten_counter/simulation/qsim/work/_vmake
new file mode 100644
index 0000000..2f7e729
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/ten_counter/simulation/qsim/work/ten_counter/_primary.dat b/ten_counter/simulation/qsim/work/ten_counter/_primary.dat
new file mode 100644
index 0000000..1edc91a
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter/_primary.dat
diff --git a/ten_counter/simulation/qsim/work/ten_counter/_primary.dbs b/ten_counter/simulation/qsim/work/ten_counter/_primary.dbs
new file mode 100644
index 0000000..4338486
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter/_primary.dbs
diff --git a/ten_counter/simulation/qsim/work/ten_counter/_primary.vhd b/ten_counter/simulation/qsim/work/ten_counter/_primary.vhd
new file mode 100644
index 0000000..d161ba0
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter/_primary.vhd
@@ -0,0 +1,10 @@
+library verilog;
+use verilog.vl_types.all;
+entity ten_counter is
+    port(
+        cout            : out    vl_logic;
+        CLR             : in     vl_logic;
+        CLK             : in     vl_logic;
+        count           : out    vl_logic_vector(3 downto 0)
+    );
+end ten_counter;
diff --git a/ten_counter/simulation/qsim/work/ten_counter/verilog.prw b/ten_counter/simulation/qsim/work/ten_counter/verilog.prw
new file mode 100644
index 0000000..3d27671
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter/verilog.prw
diff --git a/ten_counter/simulation/qsim/work/ten_counter/verilog.psm b/ten_counter/simulation/qsim/work/ten_counter/verilog.psm
new file mode 100644
index 0000000..7e62db5
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter/verilog.psm
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dat b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dat
new file mode 100644
index 0000000..c538e29
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dat
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dbs b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dbs
new file mode 100644
index 0000000..68e0505
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.dbs
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.vhd b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.vhd
new file mode 100644
index 0000000..05352a8
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/_primary.vhd
@@ -0,0 +1,9 @@
+library verilog;
+use verilog.vl_types.all;
+entity ten_counter_vlg_check_tst is
+    port(
+        count           : in     vl_logic_vector(3 downto 0);
+        cout            : in     vl_logic;
+        sampler_rx      : in     vl_logic
+    );
+end ten_counter_vlg_check_tst;
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.prw b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.prw
new file mode 100644
index 0000000..4c30e2b
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.prw
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.psm b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.psm
new file mode 100644
index 0000000..b4dd331
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_check_tst/verilog.psm
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dat b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dat
new file mode 100644
index 0000000..9aeb060
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dat
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dbs b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dbs
new file mode 100644
index 0000000..80257ce
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.dbs
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.vhd b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.vhd
new file mode 100644
index 0000000..3ae4329
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/_primary.vhd
@@ -0,0 +1,9 @@
+library verilog;
+use verilog.vl_types.all;
+entity ten_counter_vlg_sample_tst is
+    port(
+        CLK             : in     vl_logic;
+        CLR             : in     vl_logic;
+        sampler_tx      : out    vl_logic
+    );
+end ten_counter_vlg_sample_tst;
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.prw b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.prw
new file mode 100644
index 0000000..a110770
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.prw
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.psm b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.psm
new file mode 100644
index 0000000..3cf5a4c
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_sample_tst/verilog.psm
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dat b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dat
new file mode 100644
index 0000000..d4d802f
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dat
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dbs b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dbs
new file mode 100644
index 0000000..fe2901d
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.dbs
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.vhd b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.vhd
new file mode 100644
index 0000000..304d493
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/_primary.vhd
@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity ten_counter_vlg_vec_tst is
+end ten_counter_vlg_vec_tst;
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.prw b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.prw
new file mode 100644
index 0000000..1c67a5d
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.prw
diff --git a/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.psm b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.psm
new file mode 100644
index 0000000..2536f8d
--- /dev/null
+++ b/ten_counter/simulation/qsim/work/ten_counter_vlg_vec_tst/verilog.psm
diff --git a/ten_counter/ten_counter.bdf b/ten_counter/ten_counter.bdf
new file mode 100644
index 0000000..b198dba
--- /dev/null
+++ b/ten_counter/ten_counter.bdf
@@ -0,0 +1,1439 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 752 -80 768 88)
+	(text "INPUT" (rect 6 125 16 153)(font "Arial" (font_size 6))(vertical))
+	(text "CLK" (rect 4 5 16 26)(font "Arial" )(vertical))
+	(pt 8 168)
+	(drawing
+		(line (pt 4 84)(pt 4 109))
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+		(line (pt 4 109)(pt 8 113))
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+)
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+	(input)
+	(rect 880 40 1048 56)
+	(text "INPUT" (rect 15 6 43 16)(font "Arial" (font_size 6)))
+	(text "CLR" (rect 114 4 136 16)(font "Arial" ))
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+		(line (pt 59 4)(pt 55 8))
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+	(annotation_block (location)(rect 928 -16 984 0))
+)
+(pin
+	(output)
+	(rect 1112 200 1288 216)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "count[3..0]" (rect 90 0 143 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
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+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
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+)
+(pin
+	(output)
+	(rect 1208 392 1384 408)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "cout" (rect 90 0 111 12)(font "Arial" ))
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+	(drawing
+		(line (pt 0 8)(pt 52 8))
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+		(pt 0 40)
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+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
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+(symbol
+	(rect 792 200 856 280)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst1" (rect 3 68 26 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
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+		(pt 0 24)
+		(input)
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+	(text "Q[2]" (rect 393 288 414 300)(font "Arial" ))
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diff --git a/ten_counter/ten_counter.bsf b/ten_counter/ten_counter.bsf
new file mode 100644
index 0000000..4e3b0df
--- /dev/null
+++ b/ten_counter/ten_counter.bsf
@@ -0,0 +1,57 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 152 112)
+	(text "ten_counter" (rect 5 0 73 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLK" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "CLK" (rect 21 27 44 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "CLR" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "CLR" (rect 21 43 44 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "count[3..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "count[3..0]" (rect 55 27 115 41)(font "Arial" (font_size 8)))
+		(line (pt 136 32)(pt 120 32)(line_width 3))
+	)
+	(port
+		(pt 136 48)
+		(output)
+		(text "cout" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "cout" (rect 91 43 115 57)(font "Arial" (font_size 8)))
+		(line (pt 136 48)(pt 120 48))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 80))
+	)
+)
diff --git a/ten_counter/ten_counter.qpf b/ten_counter/ten_counter.qpf
new file mode 100644
index 0000000..1c5ac4f
--- /dev/null
+++ b/ten_counter/ten_counter.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 18:07:14  February 25, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "18:07:14  February 25, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ten_counter"
diff --git a/ten_counter/ten_counter.qsf b/ten_counter/ten_counter.qsf
new file mode 100644
index 0000000..94b85ec
--- /dev/null
+++ b/ten_counter/ten_counter.qsf
@@ -0,0 +1,68 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 18:07:15  February 25, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ten_counter_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16U484C6
+set_global_assignment -name TOP_LEVEL_ENTITY ten_counter
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:07:15  FEBRUARY 25, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name BDF_FILE ten_counter.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_global_assignment -name SIMULATION_MODE FUNCTIONAL
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_G21 -to CLK
+set_location_assignment PIN_G3 -to CLR
+set_location_assignment PIN_J1 -to count[3]
+set_location_assignment PIN_J2 -to count[2]
+set_location_assignment PIN_J3 -to count[1]
+set_location_assignment PIN_H1 -to count[0]
+set_location_assignment PIN_B1 -to cout
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Git/ten_counter/Waveform.vwf"
\ No newline at end of file
diff --git a/ten_counter/ten_counter.qws b/ten_counter/ten_counter.qws
new file mode 100644
index 0000000..129638f
--- /dev/null
+++ b/ten_counter/ten_counter.qws
diff --git a/ten_counter/ten_counter_nativelink_simulation.rpt b/ten_counter/ten_counter_nativelink_simulation.rpt
new file mode 100644
index 0000000..fbe9495
--- /dev/null
+++ b/ten_counter/ten_counter_nativelink_simulation.rpt
@@ -0,0 +1,16 @@
+Info: Start Nativelink Simulation process
+Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation
+Analysis and Synthesis should be completed successfully before starting RTL NativeLink Simulation
+Error: NativeLink simulation flow was NOT successful
+
+
+
+================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
+Nativelink TCL script failed with errorCode:  1
+Nativelink TCL script failed with errorInfo:  1
+    invoked from within
+"if ![qmap_successfully_completed] {
+	    nl_postmsg error "Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation"..."
+    (procedure "run_eda_simulation_tool" line 231)
+    invoked from within
+"run_eda_simulation_tool eda_opts_hash"
diff --git a/ten_d_flip_flop/db/.cmp.kpt b/ten_d_flip_flop/db/.cmp.kpt
new file mode 100644
index 0000000..6cf5381
--- /dev/null
+++ b/ten_d_flip_flop/db/.cmp.kpt
diff --git a/ten_d_flip_flop/db/logic_util_heursitic.dat b/ten_d_flip_flop/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..38da4a2
--- /dev/null
+++ b/ten_d_flip_flop/db/logic_util_heursitic.dat
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.cdb
new file mode 100644
index 0000000..1e2224f
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.hdb
new file mode 100644
index 0000000..c66fed3
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.(0).cnf.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.asm.qmsg b/ten_d_flip_flop/db/ten_d_flip_flop.asm.qmsg
new file mode 100644
index 0000000..ea8a643
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455900493848 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455900493849 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:48:13 2016 " "Processing started: Fri Feb 19 16:48:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455900493849 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455900493849 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455900493849 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455900494566 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455900494591 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "522 " "Peak virtual memory: 522 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455900494868 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:48:14 2016 " "Processing ended: Fri Feb 19 16:48:14 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455900494868 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455900494868 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455900494868 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455900494868 ""}
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.asm.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.asm.rdb
new file mode 100644
index 0000000..a649912
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.asm.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.asm_labs.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.asm_labs.ddb
new file mode 100644
index 0000000..171e4e3
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.asm_labs.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cbx.xml b/ten_d_flip_flop/db/ten_d_flip_flop.cbx.xml
new file mode 100644
index 0000000..295fe9d
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ten_d_flip_flop">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.bpm b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.bpm
new file mode 100644
index 0000000..44fa640
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.bpm
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.cdb
new file mode 100644
index 0000000..4b1fbb1
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.hdb
new file mode 100644
index 0000000..a21bbc8
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.idb b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.idb
new file mode 100644
index 0000000..b212a46
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.idb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.logdb b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.logdb
new file mode 100644
index 0000000..9138e95
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.logdb
@@ -0,0 +1,63 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;21;0;0;21;21;0;10;0;0;11;0;10;11;0;0;0;10;0;0;0;0;0;21;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,21;21;21;21;21;0;21;21;0;0;21;11;21;21;10;21;11;10;21;21;21;11;21;21;21;21;21;0;21;21,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Q[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,Q[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,D[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.rdb
new file mode 100644
index 0000000..9c93d56
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.cmp_merge.kpt b/ten_d_flip_flop/db/ten_d_flip_flop.cmp_merge.kpt
new file mode 100644
index 0000000..6be8bfa
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.cmp_merge.kpt
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.db_info b/ten_d_flip_flop/db/ten_d_flip_flop.db_info
new file mode 100644
index 0000000..66e383e
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 16:32:21 2016
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.eda.qmsg b/ten_d_flip_flop/db/ten_d_flip_flop.eda.qmsg
new file mode 100644
index 0000000..ee91c77
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455900500505 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455900500506 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:48:20 2016 " "Processing started: Fri Feb 19 16:48:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455900500506 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455900500506 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455900500506 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_6_1200mv_85c_slow.vho C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900500925 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_6_1200mv_0c_slow.vho C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900500949 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_min_1200mv_0c_fast.vho C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900500972 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop.vho C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop.vho in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900500995 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900501019 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900501046 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900501069 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ten_d_flip_flop_vhd.sdo C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ simulation " "Generated file ten_d_flip_flop_vhd.sdo in folder \"C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1455900501090 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "482 " "Peak virtual memory: 482 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455900501130 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:48:21 2016 " "Processing ended: Fri Feb 19 16:48:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455900501130 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455900501130 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455900501130 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455900501130 ""}
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.fit.qmsg b/ten_d_flip_flop/db/ten_d_flip_flop.fit.qmsg
new file mode 100644
index 0000000..6dbfb9b
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455900486034 ""}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "ten_d_flip_flop EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design ten_d_flip_flop" {  } {  } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455900486160 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455900486224 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455900486224 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455900486313 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455900486329 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455900486497 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455900486497 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455900486497 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 61 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455900486498 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 63 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455900486498 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 65 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455900486498 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 67 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455900486498 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 69 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455900486498 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455900486498 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455900486498 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "21 21 " "No exact pin location assignment(s) for 21 pins of 21 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[9\] " "Pin Q\[9\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[9] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 5 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[8\] " "Pin Q\[8\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[8] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 6 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[7\] " "Pin Q\[7\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[7] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 7 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[6\] " "Pin Q\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[6] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 8 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[5\] " "Pin Q\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[5] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 9 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[4\] " "Pin Q\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[4] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 10 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[3\] " "Pin Q\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[3] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 11 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[2\] " "Pin Q\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[2] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[1\] " "Pin Q\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[1] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Q\[0\] " "Pin Q\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Q[0] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 392 352 528 408 "Q" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Q[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[9\] " "Pin D\[9\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[9] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Pin CLK not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { CLK } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 344 264 432 360 "CLK" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[8\] " "Pin D\[8\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[8] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[7\] " "Pin D\[7\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[7] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 17 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[6\] " "Pin D\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[6] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[5\] " "Pin D\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[5] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 19 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[4\] " "Pin D\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[4] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 20 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[3\] " "Pin D\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[3] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[2\] " "Pin D\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[2] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 22 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[1\] " "Pin D\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[1] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "D\[0\] " "Pin D\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { D[0] } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 368 264 432 384 "D" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 24 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455900486827 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455900486827 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_d_flip_flop.sdc " "Synopsys Design Constraints File file not found: 'ten_d_flip_flop.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455900487062 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455900487063 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455900487064 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455900487064 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455900487064 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n)) " "Automatically promoted node CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1455900487072 ""}  } { { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 344 264 432 360 "CLK" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 47 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1455900487072 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455900487437 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455900487437 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455900487437 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455900487438 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455900487438 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455900487438 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455900487445 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455900487446 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455900487446 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "20 unused 2.5V 10 10 0 " "Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455900487447 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455900487447 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455900487447 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 1 1 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1455900487448 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455900487448 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455900487448 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455900487463 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455900488758 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455900488803 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455900488810 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455900488989 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455900488989 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455900489993 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X22_Y21 X33_Y31 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y21 to location X33_Y31" {  } { { "loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y21 to location X33_Y31"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y21 to location X33_Y31"} 22 21 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455900490409 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455900490409 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455900490534 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455900490535 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455900490535 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455900490535 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.09 " "Total time spent on timing analysis during the Fitter is 0.09 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455900490543 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455900490636 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455900490826 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455900490917 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455900491089 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455900491478 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV GX " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLK 2.5 V J7 " "Pin CLK uses I/O standard 2.5 V at J7" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { CLK } } } { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { { 344 264 432 360 "CLK" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1455900491807 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1455900491807 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg " "Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455900491854 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "915 " "Peak virtual memory: 915 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455900492175 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:48:12 2016 " "Processing ended: Fri Feb 19 16:48:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455900492175 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455900492175 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455900492175 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455900492175 ""}
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.hier_info b/ten_d_flip_flop/db/ten_d_flip_flop.hier_info
new file mode 100644
index 0000000..3b6575e
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.hier_info
@@ -0,0 +1,33 @@
+|ten_d_flip_flop
+Q[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
+Q[1] <= inst1.DB_MAX_OUTPUT_PORT_TYPE
+Q[2] <= inst2.DB_MAX_OUTPUT_PORT_TYPE
+Q[3] <= inst3.DB_MAX_OUTPUT_PORT_TYPE
+Q[4] <= inst4.DB_MAX_OUTPUT_PORT_TYPE
+Q[5] <= inst5.DB_MAX_OUTPUT_PORT_TYPE
+Q[6] <= inst6.DB_MAX_OUTPUT_PORT_TYPE
+Q[7] <= inst7.DB_MAX_OUTPUT_PORT_TYPE
+Q[8] <= inst8.DB_MAX_OUTPUT_PORT_TYPE
+Q[9] <= inst9.DB_MAX_OUTPUT_PORT_TYPE
+CLK => inst.CLK
+CLK => inst1.CLK
+CLK => inst2.CLK
+CLK => inst3.CLK
+CLK => inst4.CLK
+CLK => inst6.CLK
+CLK => inst7.CLK
+CLK => inst8.CLK
+CLK => inst9.CLK
+CLK => inst5.CLK
+D[0] => inst.DATAIN
+D[1] => inst1.DATAIN
+D[2] => inst2.DATAIN
+D[3] => inst3.DATAIN
+D[4] => inst4.DATAIN
+D[5] => inst5.DATAIN
+D[6] => inst6.DATAIN
+D[7] => inst7.DATAIN
+D[8] => inst8.DATAIN
+D[9] => inst9.DATAIN
+
+
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.hif b/ten_d_flip_flop/db/ten_d_flip_flop.hif
new file mode 100644
index 0000000..7802b70
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.hif
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.ipinfo b/ten_d_flip_flop/db/ten_d_flip_flop.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.ipinfo
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.lpc.html b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.lpc.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.rdb
new file mode 100644
index 0000000..547d515
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.lpc.txt b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.ammdb b/ten_d_flip_flop/db/ten_d_flip_flop.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.ammdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.bpm b/ten_d_flip_flop/db/ten_d_flip_flop.map.bpm
new file mode 100644
index 0000000..9398eb2
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.bpm
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.map.cdb
new file mode 100644
index 0000000..b7ca6de
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.map.hdb
new file mode 100644
index 0000000..533113f
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.kpt b/ten_d_flip_flop/db/ten_d_flip_flop.map.kpt
new file mode 100644
index 0000000..4833dfe
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.kpt
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.logdb b/ten_d_flip_flop/db/ten_d_flip_flop.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.qmsg b/ten_d_flip_flop/db/ten_d_flip_flop.map.qmsg
new file mode 100644
index 0000000..0556523
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.qmsg
@@ -0,0 +1,10 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455900482880 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455900482880 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:48:02 2016 " "Processing started: Fri Feb 19 16:48:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455900482880 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455900482880 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop " "Command: quartus_map --read_settings_files=on --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455900482881 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455900483155 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ten_d_flip_flop.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ten_d_flip_flop.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ten_d_flip_flop " "Found entity 1: ten_d_flip_flop" {  } { { "ten_d_flip_flop.bdf" "" { Schematic "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455900483202 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455900483202 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ten_d_flip_flop " "Elaborating entity \"ten_d_flip_flop\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455900483239 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455900483777 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455900483988 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455900483988 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "31 " "Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455900484036 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455900484036 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455900484036 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455900484036 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "560 " "Peak virtual memory: 560 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455900484053 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:48:04 2016 " "Processing ended: Fri Feb 19 16:48:04 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455900484053 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455900484053 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455900484053 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455900484053 ""}
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.map.rdb
new file mode 100644
index 0000000..c870baa
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.cdb
new file mode 100644
index 0000000..2d925aa
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.hdb
new file mode 100644
index 0000000..8bbba61
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.logdb b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.pre_map.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.pre_map.hdb
new file mode 100644
index 0000000..103c8ae
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.pre_map.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.pti_db_list.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.pti_db_list.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.root_partition.map.reg_db.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..9c5098a
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.root_partition.map.reg_db.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.routing.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.routing.rdb
new file mode 100644
index 0000000..5b7b30b
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.routing.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.rtlv.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv.hdb
new file mode 100644
index 0000000..515d634
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg.cdb
new file mode 100644
index 0000000..338bb4a
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg_swap.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..9bd828b
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.rtlv_sg_swap.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.cdb b/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.cdb
new file mode 100644
index 0000000..e82119c
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.cdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.hdb b/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.hdb
new file mode 100644
index 0000000..5ed62ed
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sgdiff.hdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry.sci b/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry.sci
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry_dsc.sci b/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sld_design_entry_dsc.sci
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.smart_action.txt b/ten_d_flip_flop/db/ten_d_flip_flop.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sta.qmsg b/ten_d_flip_flop/db/ten_d_flip_flop.sta.qmsg
new file mode 100644
index 0000000..f575363
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sta.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455900496654 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455900496655 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 19 16:48:16 2016 " "Processing started: Fri Feb 19 16:48:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455900496655 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455900496655 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ten_d_flip_flop -c ten_d_flip_flop " "Command: quartus_sta ten_d_flip_flop -c ten_d_flip_flop" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455900496655 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455900496723 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455900496839 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455900496897 ""}
+{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455900496898 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ten_d_flip_flop.sdc " "Synopsys Design Constraints File file not found: 'ten_d_flip_flop.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455900497187 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455900497188 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLK CLK " "create_clock -period 1.000 -name CLK CLK" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497188 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497188 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455900497189 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455900497189 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455900497190 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455900497197 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497198 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497205 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497209 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497213 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497217 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455900497217 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455900497217 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -13.000 CLK  " "   -3.000             -13.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497222 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455900497222 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455900497246 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455900497277 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455900497903 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455900497940 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497940 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497949 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497954 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497958 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900497963 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455900497964 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455900497964 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -13.000 CLK  " "   -3.000             -13.000 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900497968 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455900497968 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455900497999 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455900498187 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900498191 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900498195 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900498199 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455900498203 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1455900498203 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1455900498203 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900498206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900498206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -13.307 CLK  " "   -3.000             -13.307 CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1455900498206 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1455900498206 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455900498707 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455900498707 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "523 " "Peak virtual memory: 523 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455900498770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 19 16:48:18 2016 " "Processing ended: Fri Feb 19 16:48:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455900498770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455900498770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455900498770 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455900498770 ""}
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sta.rdb b/ten_d_flip_flop/db/ten_d_flip_flop.sta.rdb
new file mode 100644
index 0000000..675f0cd
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sta.rdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.sta_cmp.6_slow_1200mv_85c.tdb b/ten_d_flip_flop/db/ten_d_flip_flop.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..0e025c4
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..a413810
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
new file mode 100644
index 0000000..a546d32
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..c288b17
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.tis_db_list.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.tis_db_list.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.fast_1200mv_0c.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..c1eb4b0
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.fast_1200mv_0c.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_0c.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..1989b30
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_0c.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_85c.ddb b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..b1c6524
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.tiscmp.slow_1200mv_85c.ddb
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.tmw_info b/ten_d_flip_flop/db/ten_d_flip_flop.tmw_info
new file mode 100644
index 0000000..2a22bd1
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:20
+start_analysis_synthesis:s:00:00:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:08-start_full_compilation
+start_assembler:s:00:00:03-start_full_compilation
+start_timing_analyzer:s:00:00:04-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/ten_d_flip_flop/db/ten_d_flip_flop.vpr.ammdb b/ten_d_flip_flop/db/ten_d_flip_flop.vpr.ammdb
new file mode 100644
index 0000000..ef32e30
--- /dev/null
+++ b/ten_d_flip_flop/db/ten_d_flip_flop.vpr.ammdb
diff --git a/ten_d_flip_flop/incremental_db/README b/ten_d_flip_flop/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.db_info b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.db_info
new file mode 100644
index 0000000..26a86e2
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Fri Feb 19 16:48:03 2016
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.ammdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.ammdb
new file mode 100644
index 0000000..af6a86a
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.ammdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.cdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.cdb
new file mode 100644
index 0000000..064c954
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.cdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.dfp b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.dfp
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.hdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.hdb
new file mode 100644
index 0000000..669591e
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.hdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.logdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.rcfdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..e60f998
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.cmp.rcfdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.cdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.cdb
new file mode 100644
index 0000000..237691d
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.cdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.dpi b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.dpi
new file mode 100644
index 0000000..bc9e3f9
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.dpi
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.cdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..a4ed593
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.cdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hb_info b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hb_info
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..b9cc60f
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.hdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.sig b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..91e140d
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+6d99a1516c2e2beefe1f386eab1dd580
\ No newline at end of file
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hdb b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hdb
new file mode 100644
index 0000000..07e5ef2
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.hdb
diff --git a/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.kpt b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.kpt
new file mode 100644
index 0000000..b4a9d91
--- /dev/null
+++ b/ten_d_flip_flop/incremental_db/compiled_partitions/ten_d_flip_flop.root_partition.map.kpt
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.asm.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.asm.rpt
new file mode 100644
index 0000000..8584e13
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ten_d_flip_flop
+Fri Feb 19 16:48:14 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Feb 19 16:48:14 2016 ;
+; Revision Name         ; ten_d_flip_flop                       ;
+; Top-level Entity Name ; ten_d_flip_flop                       ;
+; Family                ; Cyclone IV GX                         ;
+; Device                ; EP4CGX15BF14C6                        ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------------------------------------------+
+; Assembler Generated Files                                                       ;
++---------------------------------------------------------------------------------+
+; File Name                                                                       ;
++---------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.sof ;
++---------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.sof ;
++----------------+------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                  ;
++----------------+------------------------------------------------------------------------------------------+
+; Device         ; EP4CGX15BF14C6                                                                           ;
+; JTAG usercode  ; 0x000BCFC1                                                                               ;
+; Checksum       ; 0x000BCFC1                                                                               ;
++----------------+------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:48:13 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 522 megabytes
+    Info: Processing ended: Fri Feb 19 16:48:14 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.done b/ten_d_flip_flop/output_files/ten_d_flip_flop.done
new file mode 100644
index 0000000..b7adb76
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.done
@@ -0,0 +1 @@
+Fri Feb 19 16:48:21 2016
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.eda.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.eda.rpt
new file mode 100644
index 0000000..a4dabcb
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for ten_d_flip_flop
+Fri Feb 19 16:48:21 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Feb 19 16:48:21 2016 ;
+; Revision Name             ; ten_d_flip_flop                       ;
+; Top-level Entity Name     ; ten_d_flip_flop                       ;
+; Family                    ; Cyclone IV GX                         ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                    ;
++---------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                               ;
++---------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.vho                        ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_vhd.sdo                    ;
++---------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:48:20 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+Info (204019): Generated file ten_d_flip_flop_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop.vho in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file ten_d_flip_flop_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 482 megabytes
+    Info: Processing ended: Fri Feb 19 16:48:21 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.rpt
new file mode 100644
index 0000000..ca3f4b3
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.rpt
@@ -0,0 +1,1030 @@
+Fitter report for ten_d_flip_flop
+Fri Feb 19 16:48:11 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Fitter Messages
+ 35. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Fri Feb 19 16:48:11 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_d_flip_flop                            ;
+; Top-level Entity Name              ; ten_d_flip_flop                            ;
+; Family                             ; Cyclone IV GX                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 10 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 0 / 14,400 ( 0 % )                         ;
+;     Dedicated logic registers      ; 10 / 14,400 ( < 1 % )                      ;
+; Total registers                    ; 10                                         ;
+; Total pins                         ; 21 / 81 ( 26 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; auto                                  ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Generate GXB Reconfig MIF                                                  ; Off                                   ; Off                                   ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_40MHz                            ; FREQ_40MHz                            ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; Q[9]     ; Incomplete set of assignments ;
+; Q[8]     ; Incomplete set of assignments ;
+; Q[7]     ; Incomplete set of assignments ;
+; Q[6]     ; Incomplete set of assignments ;
+; Q[5]     ; Incomplete set of assignments ;
+; Q[4]     ; Incomplete set of assignments ;
+; Q[3]     ; Incomplete set of assignments ;
+; Q[2]     ; Incomplete set of assignments ;
+; Q[1]     ; Incomplete set of assignments ;
+; Q[0]     ; Incomplete set of assignments ;
+; D[9]     ; Incomplete set of assignments ;
+; CLK      ; Incomplete set of assignments ;
+; D[8]     ; Incomplete set of assignments ;
+; D[7]     ; Incomplete set of assignments ;
+; D[6]     ; Incomplete set of assignments ;
+; D[5]     ; Incomplete set of assignments ;
+; D[4]     ; Incomplete set of assignments ;
+; D[3]     ; Incomplete set of assignments ;
+; D[2]     ; Incomplete set of assignments ;
+; D[1]     ; Incomplete set of assignments ;
+; D[0]     ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 )          ; 0.00 % ( 0 / 64 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 )          ; 0.00 % ( 0 / 64 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 54 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 10 / 14,400 ( < 1 % ) ;
+;     -- Combinational with no register       ; 0                     ;
+;     -- Register only                        ; 10                    ;
+;     -- Combinational with a register        ; 0                     ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 0                     ;
+;     -- 3 input functions                    ; 0                     ;
+;     -- <=2 input functions                  ; 0                     ;
+;     -- Register only                        ; 10                    ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 0                     ;
+;     -- arithmetic mode                      ; 0                     ;
+;                                             ;                       ;
+; Total registers*                            ; 10 / 14,733 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 10 / 14,400 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 333 ( 0 % )       ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 10 / 900 ( 1 % )      ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 21 / 81 ( 26 % )      ;
+;     -- Clock pins                           ; 2 / 6 ( 33 % )        ;
+;     -- Dedicated input pins                 ; 0 / 12 ( 0 % )        ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 60 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 552,960 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 552,960 ( 0 % )   ;
+; PLLs                                        ; 0 / 3 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; GXB Receiver channel PCSs                   ; 0 / 2 ( 0 % )         ;
+; GXB Receiver channel PMAs                   ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PCSs                ; 0 / 2 ( 0 % )         ;
+; GXB Transmitter channel PMAs                ; 0 / 2 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 3 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
+; Maximum fan-out                             ; 10                    ;
+; Highest non-global fan-out                  ; 1                     ;
+; Total fan-out                               ; 62                    ;
+; Average fan-out                             ; 0.91                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 10 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % )              ;
+;     -- Combinational with no register       ; 0                    ; 0                              ;
+;     -- Register only                        ; 10                   ; 0                              ;
+;     -- Combinational with a register        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 0                    ; 0                              ;
+;     -- 3 input functions                    ; 0                    ; 0                              ;
+;     -- <=2 input functions                  ; 0                    ; 0                              ;
+;     -- Register only                        ; 10                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 0                    ; 0                              ;
+;     -- arithmetic mode                      ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 10                   ; 0                              ;
+;     -- Dedicated logic registers            ; 10 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % )              ;
+;     -- I/O registers                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 10 / 900 ( 1 % )     ; 0 / 900 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 21                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0                    ; 0                              ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+; Clock control block                         ; 1 / 23 ( 4 % )       ; 0 / 23 ( 0 % )                 ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 57                   ; 5                              ;
+;     -- Registered Connections               ; 10                   ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 11                   ; 0                              ;
+;     -- Output Ports                         ; 10                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+; CLK  ; J7    ; 3A       ; 16           ; 0            ; 14           ; 10                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[0] ; E10   ; 6        ; 33           ; 27           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[1] ; F10   ; 6        ; 33           ; 24           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[2] ; B11   ; 7        ; 24           ; 31           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[3] ; D10   ; 6        ; 33           ; 27           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[4] ; K12   ; 5        ; 33           ; 11           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[5] ; D13   ; 7        ; 29           ; 31           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[6] ; F11   ; 6        ; 33           ; 24           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[7] ; B13   ; 7        ; 26           ; 31           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[8] ; F12   ; 6        ; 33           ; 16           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
+; D[9] ; F13   ; 6        ; 33           ; 16           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ;
++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Q[0] ; E13   ; 6        ; 33           ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[1] ; F9    ; 6        ; 33           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[2] ; A6    ; 8        ; 10           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[3] ; A13   ; 7        ; 26           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[4] ; L13   ; 5        ; 33           ; 12           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[5] ; N12   ; 4        ; 29           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[6] ; J13   ; 5        ; 33           ; 15           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[7] ; C13   ; 7        ; 29           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[8] ; G9    ; 6        ; 33           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; Q[9] ; M11   ; 4        ; 29           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                           ;
++----------+----------------------+--------------------------+------------------+---------------------------+
+; Location ; Pin Name             ; Reserved As              ; User Signal Name ; Pin Type                  ;
++----------+----------------------+--------------------------+------------------+---------------------------+
+; L3       ; MSEL2                ; -                        ; -                ; Dedicated Programming Pin ;
+; N3       ; MSEL1                ; -                        ; -                ; Dedicated Programming Pin ;
+; K5       ; MSEL0                ; -                        ; -                ; Dedicated Programming Pin ;
+; J5       ; CONF_DONE            ; -                        ; -                ; Dedicated Programming Pin ;
+; K6       ; nSTATUS              ; -                        ; -                ; Dedicated Programming Pin ;
+; N5       ; DIFFIO_B1n, NCEO     ; Use as programming pin   ; ~ALTERA_NCEO~    ; Dual Purpose Pin          ;
+; D10      ; DIFFIO_R2n, DEV_CLRn ; Use as regular IO        ; D[3]             ; Dual Purpose Pin          ;
+; A6       ; CLKUSR               ; Use as regular IO        ; Q[2]             ; Dual Purpose Pin          ;
+; A5       ; DATA0                ; As input tri-stated      ; ~ALTERA_DATA0~   ; Dual Purpose Pin          ;
+; B5       ; ASDO                 ; As input tri-stated      ; ~ALTERA_ASDO~    ; Dual Purpose Pin          ;
+; C5       ; NCSO                 ; As input tri-stated      ; ~ALTERA_NCSO~    ; Dual Purpose Pin          ;
+; A4       ; DCLK                 ; As output driving ground ; ~ALTERA_DCLK~    ; Dual Purpose Pin          ;
+; D5       ; nCONFIG              ; -                        ; -                ; Dedicated Programming Pin ;
+; C4       ; nCE                  ; -                        ; -                ; Dedicated Programming Pin ;
++----------+----------------------+--------------------------+------------------+---------------------------+
+
+
++------------------------------------------------------------------------------+
+; I/O Bank Usage                                                               ;
++----------+-----------------+---------------+--------------+------------------+
+; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ;
++----------+-----------------+---------------+--------------+------------------+
+; QL0      ; 0 / 8 ( 0 % )   ; --            ; --           ; --               ;
+; 3        ; 1 / 8 ( 13 % )  ; 2.5V          ; --           ; --               ;
+; 3A       ; 1 / 2 ( 50 % )  ; --            ; --           ; 2.5V             ;
+; 4        ; 2 / 14 ( 14 % ) ; 2.5V          ; --           ; --               ;
+; 5        ; 3 / 12 ( 25 % ) ; 2.5V          ; --           ; --               ;
+; 6        ; 9 / 12 ( 75 % ) ; 2.5V          ; --           ; --               ;
+; 7        ; 5 / 14 ( 36 % ) ; 2.5V          ; --           ; --               ;
+; 8A       ; 0 / 2 ( 0 % )   ; --            ; --           ; 2.5V             ;
+; 8        ; 1 / 5 ( 20 % )  ; 2.5V          ; --           ; --               ;
+; 9        ; 4 / 4 ( 100 % ) ; 2.5V          ; --           ; --               ;
++----------+-----------------+---------------+--------------+------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                               ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                   ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ; 99         ; 9        ; #TDO                                             ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ; 98         ; 9        ; #TMS                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A3       ; 96         ; 9        ; #TDI                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; A4       ; 93         ; 9        ; ~ALTERA_DCLK~                                    ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A5       ; 90         ; 9        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; A6       ; 89         ; 8        ; Q[2]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A7       ; 87         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 88         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 81         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A10      ; 82         ; 7        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A11      ; 79         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A12      ; 80         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A13      ; 73         ; 7        ; Q[3]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B3       ; 97         ; 9        ; #TCK                                             ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; B4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B5       ; 91         ; 9        ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; B6       ; 86         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B8       ; 77         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B10      ; 76         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B11      ; 75         ; 7        ; D[2]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; B12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B13      ; 74         ; 7        ; D[7]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; C1       ; 9          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C2       ; 8          ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C3       ;            ; 9        ; VCCIO9                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C4       ; 95         ; 9        ; ^nCE                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; C5       ; 92         ; 9        ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP  ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; On           ;
+; C6       ; 85         ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C7       ;            ; 8        ; VCCIO8                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C8       ; 78         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C10      ;            ; 7        ; VCCIO7                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; C11      ; 69         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C12      ; 70         ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C13      ; 71         ; 7        ; Q[7]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; D1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D3       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; D4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ; 94         ; 9        ; ^nCONFIG                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; D6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D7       ;            ; 8A       ; VCC_CLKIN8A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 65         ; 6        ; D[3]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; D11      ; 68         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D12      ; 67         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D13      ; 72         ; 7        ; D[5]                                             ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E1       ; 11         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E2       ; 10         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; E3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E6       ; 83         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E7       ; 84         ; 8A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E10      ; 66         ; 6        ; D[0]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; E11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E13      ; 63         ; 6        ; Q[0]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F9       ; 64         ; 6        ; Q[1]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F10      ; 62         ; 6        ; D[1]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F11      ; 61         ; 6        ; D[6]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F12      ; 58         ; 6        ; D[8]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; F13      ; 57         ; 6        ; D[9]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G1       ; 13         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G2       ; 12         ; QL0      ; GXB_NC                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; G3       ;            ; --       ; VCCH_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G4       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G6       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G7       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G9       ; 60         ; 6        ; Q[8]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; G10      ; 59         ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G11      ;            ; 6        ; VCCIO6                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G13      ; 55         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H3       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H4       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H5       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H6       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H7       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H10      ; 52         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H12      ; 51         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H13      ; 56         ; 5        ; GND+                                             ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J1       ; 15         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J2       ; 14         ; QL0      ; GXB_GND*                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J3       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J4       ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J5       ; 19         ; 3        ; ^CONF_DONE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 29         ; 3A       ; GXB_GND*                                         ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; J7       ; 30         ; 3A       ; CLK                                              ; input  ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                           ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCD_PLL                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ; 5        ; VCCIO5                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J13      ; 53         ; 5        ; Q[6]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K3       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; --       ; VCCA                                             ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 18         ; 3        ; ^MSEL0                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 20         ; 3        ; ^nSTATUS                                         ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ;            ; 3A       ; VCC_CLKIN3A                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K8       ; 35         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; K9       ; 36         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K10      ; 43         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; K11      ; 48         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K12      ; 47         ; 5        ; D[4]                                             ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K13      ; 54         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L1       ;            ;          ; RREF                                             ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 16         ; 3        ; ^MSEL2                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 21         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L5       ; 27         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L6       ;            ; 3        ; VCCIO3                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L7       ; 28         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; L8       ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L9       ; 37         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L10      ;            ; 4        ; VCCIO4                                           ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L11      ; 44         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; L12      ; 50         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L13      ; 49         ; 5        ; Q[4]                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; M1       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M2       ;            ; --       ; VCCA_GXB                                         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; M3       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M4       ; 22         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M5       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M6       ; 25         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M7       ; 31         ; 4        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; M8       ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M9       ; 38         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; M10      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ; 41         ; 4        ; Q[9]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; M12      ;            ;          ; GND                                              ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ; 46         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ;            ; --       ; VCCL_GXB                                         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N2       ;            ;          ; NC                                               ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N3       ; 17         ; 3        ; ^MSEL1                                           ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ; 23         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N5       ; 24         ; 3        ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN       ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N6       ; 26         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N7       ; 32         ; 4        ; GND+                                             ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; N8       ; 33         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N9       ; 34         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N10      ; 39         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N11      ; 40         ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; N12      ; 42         ; 4        ; Q[5]                                             ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; N13      ; 45         ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                  ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                       ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |ten_d_flip_flop           ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0         ; 21   ; 0            ; 0 (0)        ; 10 (10)           ; 0 (0)            ; |ten_d_flip_flop    ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                  ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+; Q[9] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[8] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[7] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[6] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[5] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[4] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[3] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[2] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; Q[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; D[9] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; CLK  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; D[8] ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; D[7] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; D[6] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; D[5] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; D[4] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; D[3] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; D[2] ; Input    ; (6) 1313 ps   ; --            ; --                    ; --  ; --   ;
+; D[1] ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; D[0] ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
++------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; D[9]                ;                   ;         ;
+; CLK                 ;                   ;         ;
+; D[8]                ;                   ;         ;
+; D[7]                ;                   ;         ;
+;      - inst7        ; 0                 ; 6       ;
+; D[6]                ;                   ;         ;
+;      - inst6~feeder ; 0                 ; 6       ;
+; D[5]                ;                   ;         ;
+;      - inst5        ; 0                 ; 6       ;
+; D[4]                ;                   ;         ;
+;      - inst4~feeder ; 0                 ; 6       ;
+; D[3]                ;                   ;         ;
+;      - inst3~feeder ; 0                 ; 6       ;
+; D[2]                ;                   ;         ;
+;      - inst2~feeder ; 0                 ; 6       ;
+; D[1]                ;                   ;         ;
+;      - inst1        ; 0                 ; 6       ;
+; D[0]                ;                   ;         ;
+;      - inst~feeder  ; 1                 ; 6       ;
++---------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                  ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_J7   ; 10      ; Clock ; yes    ; Global Clock         ; GCLK17           ; --                        ;
++------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                            ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLK  ; PIN_J7   ; 10      ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
++------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++------------+--------------------+
+; Name       ; Fan-Out            ;
++------------+--------------------+
+; D[0]~input ; 1                  ;
+; D[1]~input ; 1                  ;
+; D[2]~input ; 1                  ;
+; D[3]~input ; 1                  ;
+; D[4]~input ; 1                  ;
+; D[5]~input ; 1                  ;
+; D[6]~input ; 1                  ;
+; D[7]~input ; 1                  ;
+; D[8]~input ; 1                  ;
+; D[9]~input ; 1                  ;
+; inst       ; 1                  ;
+; inst1      ; 1                  ;
+; inst2      ; 1                  ;
+; inst3      ; 1                  ;
+; inst4      ; 1                  ;
+; inst5      ; 1                  ;
+; inst6      ; 1                  ;
+; inst7      ; 1                  ;
+; inst8      ; 1                  ;
+; inst9      ; 1                  ;
++------------+--------------------+
+
+
++-----------------------------------------------------------+
+; Routing Usage Summary                                     ;
++-----------------------------------+-----------------------+
+; Routing Resource Type             ; Usage                 ;
++-----------------------------------+-----------------------+
+; Block interconnects               ; 20 / 42,960 ( < 1 % ) ;
+; C16 interconnects                 ; 2 / 1,518 ( < 1 % )   ;
+; C4 interconnects                  ; 22 / 26,928 ( < 1 % ) ;
+; Direct links                      ; 2 / 42,960 ( < 1 % )  ;
+; GXB block output buffers          ; 0 / 1,200 ( 0 % )     ;
+; Global clocks                     ; 1 / 20 ( 5 % )        ;
+; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % )         ;
+; Interquad TXRX Clocks             ; 0 / 8 ( 0 % )         ;
+; Interquad TXRX PCSRX outputs      ; 0 / 4 ( 0 % )         ;
+; Interquad TXRX PCSTX outputs      ; 0 / 4 ( 0 % )         ;
+; Local interconnects               ; 0 / 14,400 ( 0 % )    ;
+; R24 interconnects                 ; 1 / 1,710 ( < 1 % )   ;
+; R4 interconnects                  ; 5 / 37,740 ( < 1 % )  ;
++-----------------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++--------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 1.00) ; Number of LABs  (Total = 10) ;
++--------------------------------------------+------------------------------+
+; 1                                          ; 10                           ;
+; 2                                          ; 0                            ;
+; 3                                          ; 0                            ;
+; 4                                          ; 0                            ;
+; 5                                          ; 0                            ;
+; 6                                          ; 0                            ;
+; 7                                          ; 0                            ;
+; 8                                          ; 0                            ;
+; 9                                          ; 0                            ;
+; 10                                         ; 0                            ;
+; 11                                         ; 0                            ;
+; 12                                         ; 0                            ;
+; 13                                         ; 0                            ;
+; 14                                         ; 0                            ;
+; 15                                         ; 0                            ;
+; 16                                         ; 0                            ;
++--------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 10) ;
++------------------------------------+------------------------------+
+; 1 Clock                            ; 10                           ;
++------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 1.50) ; Number of LABs  (Total = 10) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 5                            ;
+; 2                                           ; 5                            ;
++---------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 1.00) ; Number of LABs  (Total = 10) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 10                           ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 10) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 10                           ;
++---------------------------------------------+------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 21        ; 0            ; 0            ; 21        ; 21        ; 0            ; 10           ; 0            ; 0            ; 11           ; 0            ; 10           ; 11           ; 0            ; 0            ; 0            ; 10           ; 0            ; 0            ; 0            ; 0            ; 0            ; 21        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 21           ; 21           ; 21           ; 21           ; 21           ; 0         ; 21           ; 21           ; 0         ; 0         ; 21           ; 11           ; 21           ; 21           ; 10           ; 21           ; 11           ; 10           ; 21           ; 21           ; 21           ; 11           ; 21           ; 21           ; 21           ; 21           ; 21           ; 0         ; 21           ; 21           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Q[9]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[8]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[7]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[6]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[5]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[4]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[3]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[2]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[1]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; Q[0]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[9]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK                ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[8]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[7]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[6]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[5]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[4]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[3]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[2]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[1]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; D[0]               ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                         ;
++------------------------------------------------------------------+----------------------------+
+; Option                                                           ; Setting                    ;
++------------------------------------------------------------------+----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                        ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                        ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                        ;
+; Enable INIT_DONE output                                          ; Off                        ;
+; Configuration scheme                                             ; Active Serial              ;
+; Error detection CRC                                              ; Off                        ;
+; Enable input tri-state on active configuration pins in user mode ; Off                        ;
+; Active Serial clock source                                       ; 40 MHz Internal Oscillator ;
+; Configuration Voltage Level                                      ; Auto                       ;
+; Force Configuration Voltage Level                                ; Off                        ;
+; nCEO                                                             ; As output driving ground   ;
+; Data[0]                                                          ; As input tri-stated        ;
+; Data[1]/ASDO                                                     ; As input tri-stated        ;
+; Data[7..2]                                                       ; Unreserved                 ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated        ;
+; DCLK                                                             ; As output driving ground   ;
+; Base pin-out file on sameframe device                            ; Off                        ;
++------------------------------------------------------------------+----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119004): Automatically selected device EP4CGX15BF14C6 for design ten_d_flip_flop
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CGX30BF14C6 is compatible
+    Info (176445): Device EP4CGX22BF14C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5
+    Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5
+    Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 21 pins of 21 total pins
+    Info (169086): Pin Q[9] not assigned to an exact location on the device
+    Info (169086): Pin Q[8] not assigned to an exact location on the device
+    Info (169086): Pin Q[7] not assigned to an exact location on the device
+    Info (169086): Pin Q[6] not assigned to an exact location on the device
+    Info (169086): Pin Q[5] not assigned to an exact location on the device
+    Info (169086): Pin Q[4] not assigned to an exact location on the device
+    Info (169086): Pin Q[3] not assigned to an exact location on the device
+    Info (169086): Pin Q[2] not assigned to an exact location on the device
+    Info (169086): Pin Q[1] not assigned to an exact location on the device
+    Info (169086): Pin Q[0] not assigned to an exact location on the device
+    Info (169086): Pin D[9] not assigned to an exact location on the device
+    Info (169086): Pin CLK not assigned to an exact location on the device
+    Info (169086): Pin D[8] not assigned to an exact location on the device
+    Info (169086): Pin D[7] not assigned to an exact location on the device
+    Info (169086): Pin D[6] not assigned to an exact location on the device
+    Info (169086): Pin D[5] not assigned to an exact location on the device
+    Info (169086): Pin D[4] not assigned to an exact location on the device
+    Info (169086): Pin D[3] not assigned to an exact location on the device
+    Info (169086): Pin D[2] not assigned to an exact location on the device
+    Info (169086): Pin D[1] not assigned to an exact location on the device
+    Info (169086): Pin D[0] not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_d_flip_flop.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node CLK~input (placed in PIN J7 (CLK13, DIFFCLK_7n, REFCLK0n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 20 (unused VREF, 2.5V VCCIO, 10 input, 10 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available
+        Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  1 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
+        Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available
+        Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y21 to location X33_Y31
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.09 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin CLK uses I/O standard 2.5 V at J7
+Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 915 megabytes
+    Info: Processing ended: Fri Feb 19 16:48:12 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg.
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg
new file mode 100644
index 0000000..ed080d6
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.summary b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.summary
new file mode 100644
index 0000000..7623c80
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Feb 19 16:48:11 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_d_flip_flop
+Top-level Entity Name : ten_d_flip_flop
+Family : Cyclone IV GX
+Device : EP4CGX15BF14C6
+Timing Models : Final
+Total logic elements : 10 / 14,400 ( < 1 % )
+    Total combinational functions : 0 / 14,400 ( 0 % )
+    Dedicated logic registers : 10 / 14,400 ( < 1 % )
+Total registers : 10
+Total pins : 21 / 81 ( 26 % )
+Total virtual pins : 0
+Total memory bits : 0 / 552,960 ( 0 % )
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0 / 2 ( 0 % )
+Total GXB Receiver Channel PMA : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PCS : 0 / 2 ( 0 % )
+Total GXB Transmitter Channel PMA : 0 / 2 ( 0 % )
+Total PLLs : 0 / 3 ( 0 % )
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.flow.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.flow.rpt
new file mode 100644
index 0000000..d592e10
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for ten_d_flip_flop
+Fri Feb 19 16:48:21 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Fri Feb 19 16:48:21 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_d_flip_flop                            ;
+; Top-level Entity Name              ; ten_d_flip_flop                            ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 10 / 14,400 ( < 1 % )                      ;
+;     Total combinational functions  ; 0 / 14,400 ( 0 % )                         ;
+;     Dedicated logic registers      ; 10 / 14,400 ( < 1 % )                      ;
+; Total registers                    ; 10                                         ;
+; Total pins                         ; 21 / 81 ( 26 % )                           ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
+; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
+; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
+; Device                             ; EP4CGX15BF14C6                             ;
+; Timing Models                      ; Final                                      ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 02/19/2016 16:48:03 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ten_d_flip_flop     ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145590048306108 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 549 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:06     ; 1.0                     ; 915 MB              ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 514 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 523 MB              ; 00:00:02                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 471 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:11     ; --                      ; --                  ; 00:00:11                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+quartus_fit --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+quartus_asm --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+quartus_sta ten_d_flip_flop -c ten_d_flip_flop
+quartus_eda --read_settings_files=off --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.jdi b/ten_d_flip_flop/output_files/ten_d_flip_flop.jdi
new file mode 100644
index 0000000..c3d55ac
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="be7d2cd9de599405bab9"/>
+  </project>
+  <file_info>
+    <file device="EP4CGX15BF14C6" path="ten_d_flip_flop.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.map.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.map.rpt
new file mode 100644
index 0000000..694ce57
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.map.rpt
@@ -0,0 +1,244 @@
+Analysis & Synthesis report for ten_d_flip_flop
+Fri Feb 19 16:48:04 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Fri Feb 19 16:48:04 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; ten_d_flip_flop                            ;
+; Top-level Entity Name              ; ten_d_flip_flop                            ;
+; Family                             ; Cyclone IV GX                              ;
+; Total logic elements               ; 10                                         ;
+;     Total combinational functions  ; 0                                          ;
+;     Dedicated logic registers      ; 10                                         ;
+; Total registers                    ; 10                                         ;
+; Total pins                         ; 21                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total GXB Receiver Channel PCS     ; 0                                          ;
+; Total GXB Receiver Channel PMA     ; 0                                          ;
+; Total GXB Transmitter Channel PCS  ; 0                                          ;
+; Total GXB Transmitter Channel PMA  ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Top-level entity name                                                      ; ten_d_flip_flop    ; ten_d_flip_flop    ;
+; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                 ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ; Library ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+
+; ten_d_flip_flop.bdf              ; yes             ; User Block Diagram/Schematic File  ; C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf ;         ;
++----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+---------+
+
+
++---------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++--------------------------+------------------+
+; Resource                 ; Usage            ;
++--------------------------+------------------+
+; I/O pins                 ; 21               ;
+; DSP block 9-bit elements ; 0                ;
+; Maximum fan-out node     ; CLK~input        ;
+; Maximum fan-out          ; 10               ;
+; Total fan-out            ; 51               ;
+; Average fan-out          ; 0.98             ;
++--------------------------+------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+; |ten_d_flip_flop           ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 21   ; 0            ; |ten_d_flip_flop    ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 10    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:48:02 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ten_d_flip_flop -c ten_d_flip_flop
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file ten_d_flip_flop.bdf
+    Info (12023): Found entity 1: ten_d_flip_flop
+Info (12127): Elaborating entity "ten_d_flip_flop" for the top level hierarchy
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 31 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 11 input pins
+    Info (21059): Implemented 10 output pins
+    Info (21061): Implemented 10 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 560 megabytes
+    Info: Processing ended: Fri Feb 19 16:48:04 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.map.summary b/ten_d_flip_flop/output_files/ten_d_flip_flop.map.summary
new file mode 100644
index 0000000..0c1a1df
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.map.summary
@@ -0,0 +1,18 @@
+Analysis & Synthesis Status : Successful - Fri Feb 19 16:48:04 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : ten_d_flip_flop
+Top-level Entity Name : ten_d_flip_flop
+Family : Cyclone IV GX
+Total logic elements : 10
+    Total combinational functions : 0
+    Dedicated logic registers : 10
+Total registers : 10
+Total pins : 21
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total GXB Receiver Channel PCS : 0
+Total GXB Receiver Channel PMA : 0
+Total GXB Transmitter Channel PCS : 0
+Total GXB Transmitter Channel PMA : 0
+Total PLLs : 0
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.pin b/ten_d_flip_flop/output_files/ten_d_flip_flop.pin
new file mode 100644
index 0000000..91b3b00
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.pin
@@ -0,0 +1,246 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ --					Bank 9:	2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --           	    either individually through a 10k Ohm resistor to GND or tie all pins
+ --           	    together and connect through a single 10k Ohm resistor to GND.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_GND*      : Unused GXB Receiver or dedicated reference clock pin. This pin
+ --                 must be connected to GXB_GND through a 10k Ohm resistor.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "ten_d_flip_flop"  ASSIGNED TO AN: EP4CGX15BF14C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+TDO                          : A1        : output :                   :         : 9         :                
+TMS                          : A2        : input  :                   :         : 9         :                
+TDI                          : A3        : input  :                   :         : 9         :                
+~ALTERA_DCLK~                : A4        : output : 2.5 V             :         : 9         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : A5        : input  : 2.5 V             :         : 9         : N              
+Q[2]                         : A6        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+GND+                         : A10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+Q[3]                         : A13       : output : 2.5 V             :         : 7         : N              
+GND                          : B1        : gnd    :                   :         :           :                
+GND                          : B2        : gnd    :                   :         :           :                
+TCK                          : B3        : input  :                   :         : 9         :                
+GND                          : B4        : gnd    :                   :         :           :                
+~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : B5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+GND                          : B7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 7         :                
+GND                          : B9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+D[2]                         : B11       : input  : 2.5 V             :         : 7         : N              
+GND                          : B12       : gnd    :                   :         :           :                
+D[7]                         : B13       : input  : 2.5 V             :         : 7         : N              
+GXB_NC                       : C1        :        :                   :         : QL0       :                
+GXB_NC                       : C2        :        :                   :         : QL0       :                
+VCCIO9                       : C3        : power  :                   : 2.5V    : 9         :                
+nCE                          : C4        :        :                   :         : 9         :                
+~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C5        : input  : 2.5 V             :         : 9         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 7         :                
+VCCIO7                       : C9        : power  :                   : 2.5V    : 7         :                
+VCCIO7                       : C10       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 7         :                
+Q[7]                         : C13       : output : 2.5 V             :         : 7         : N              
+GND                          : D1        : gnd    :                   :         :           :                
+GND                          : D2        : gnd    :                   :         :           :                
+VCCD_PLL                     : D3        : power  :                   : 1.2V    :           :                
+VCCA                         : D4        : power  :                   : 2.5V    :           :                
+nCONFIG                      : D5        :        :                   :         : 9         :                
+GND                          : D6        : gnd    :                   :         :           :                
+VCC_CLKIN8A                  : D7        : power  :                   : 2.5V    : 8A        :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCA                         : D9        : power  :                   : 2.5V    :           :                
+D[3]                         : D10       : input  : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 6         :                
+D[5]                         : D13       : input  : 2.5 V             :         : 7         : N              
+GXB_GND*                     : E1        :        :                   :         : QL0       :                
+GXB_GND*                     : E2        :        :                   :         : QL0       :                
+GND                          : E3        : gnd    :                   :         :           :                
+VCCINT                       : E4        : power  :                   : 1.2V    :           :                
+GND                          : E5        : gnd    :                   :         :           :                
+GXB_GND*                     : E6        :        :                   :         : 8A        :                
+GXB_GND*                     : E7        :        :                   :         : 8A        :                
+VCCINT                       : E8        : power  :                   : 1.2V    :           :                
+GND                          : E9        : gnd    :                   :         :           :                
+D[0]                         : E10       : input  : 2.5 V             :         : 6         : N              
+VCCIO6                       : E11       : power  :                   : 2.5V    : 6         :                
+GND                          : E12       : gnd    :                   :         :           :                
+Q[0]                         : E13       : output : 2.5 V             :         : 6         : N              
+GND                          : F1        : gnd    :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+VCCL_GXB                     : F3        : power  :                   : 1.2V    :           :                
+GND                          : F4        : gnd    :                   :         :           :                
+VCCINT                       : F5        : power  :                   : 1.2V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+GND                          : F8        : gnd    :                   :         :           :                
+Q[1]                         : F9        : output : 2.5 V             :         : 6         : N              
+D[1]                         : F10       : input  : 2.5 V             :         : 6         : N              
+D[6]                         : F11       : input  : 2.5 V             :         : 6         : N              
+D[8]                         : F12       : input  : 2.5 V             :         : 6         : N              
+D[9]                         : F13       : input  : 2.5 V             :         : 6         : N              
+GXB_NC                       : G1        :        :                   :         : QL0       :                
+GXB_NC                       : G2        :        :                   :         : QL0       :                
+VCCH_GXB                     : G3        : power  :                   : 2.5V    :           :                
+VCCINT                       : G4        : power  :                   : 1.2V    :           :                
+GND                          : G5        : gnd    :                   :         :           :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+GND                          : G7        : gnd    :                   :         :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+Q[8]                         : G9        : output : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 6         :                
+VCCIO6                       : G11       : power  :                   : 2.5V    : 6         :                
+GND                          : G12       : gnd    :                   :         :           :                
+GND+                         : G13       :        :                   :         : 5         :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+VCCL_GXB                     : H3        : power  :                   : 1.2V    :           :                
+GND                          : H4        : gnd    :                   :         :           :                
+VCCINT                       : H5        : power  :                   : 1.2V    :           :                
+GND                          : H6        : gnd    :                   :         :           :                
+VCCINT                       : H7        : power  :                   : 1.2V    :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+VCCA                         : H9        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 5         :                
+VCCIO5                       : H11       : power  :                   : 2.5V    : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 5         :                
+GND+                         : H13       :        :                   :         : 5         :                
+GXB_GND*                     : J1        :        :                   :         : QL0       :                
+GXB_GND*                     : J2        :        :                   :         : QL0       :                
+VCCA_GXB                     : J3        : power  :                   : 2.5V    :           :                
+VCCD_PLL                     : J4        : power  :                   : 1.2V    :           :                
+CONF_DONE                    : J5        :        :                   :         : 3         :                
+GXB_GND*                     : J6        :        :                   :         : 3A        :                
+CLK                          : J7        : input  : 2.5 V             :         : 3A        : N              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCD_PLL                     : J10       : power  :                   : 1.2V    :           :                
+VCCIO5                       : J11       : power  :                   : 2.5V    : 5         :                
+GND                          : J12       : gnd    :                   :         :           :                
+Q[6]                         : J13       : output : 2.5 V             :         : 5         : N              
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+GND                          : K3        : gnd    :                   :         :           :                
+VCCA                         : K4        : power  :                   : 2.5V    :           :                
+MSEL0                        : K5        :        :                   :         : 3         :                
+nSTATUS                      : K6        :        :                   :         : 3         :                
+VCC_CLKIN3A                  : K7        : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K10       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K11       :        :                   :         : 5         :                
+D[4]                         : K12       : input  : 2.5 V             :         : 5         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K13       :        :                   :         : 5         :                
+RREF                         : L1        :        :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+MSEL2                        : L3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L4        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L5        :        :                   :         : 3         :                
+VCCIO3                       : L6        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 3         :                
+VCCIO4                       : L8        : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L9        :        :                   :         : 4         :                
+VCCIO4                       : L10       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L12       :        :                   :         : 5         :                
+Q[4]                         : L13       : output : 2.5 V             :         : 5         : N              
+GND                          : M1        : gnd    :                   :         :           :                
+VCCA_GXB                     : M2        : power  :                   : 2.5V    :           :                
+NC                           : M3        :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 3         :                
+GND                          : M5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3         :                
+GND+                         : M7        :        :                   :         : 4         :                
+GND                          : M8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 4         :                
+GND                          : M10       : gnd    :                   :         :           :                
+Q[9]                         : M11       : output : 2.5 V             :         : 4         : N              
+GND                          : M12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M13       :        :                   :         : 5         :                
+VCCL_GXB                     : N1        : power  :                   : 1.2V    :           :                
+NC                           : N2        :        :                   :         :           :                
+MSEL1                        : N3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N4        :        :                   :         : 3         :                
+~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : N5        : output : 2.5 V             :         : 3         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+GND+                         : N7        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N10       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
+Q[5]                         : N12       : output : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N13       :        :                   :         : 5         :                
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.sof b/ten_d_flip_flop/output_files/ten_d_flip_flop.sof
new file mode 100644
index 0000000..dd54c13
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.sof
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.rpt b/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.rpt
new file mode 100644
index 0000000..59feeb5
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.rpt
@@ -0,0 +1,971 @@
+TimeQuest Timing Analyzer report for ten_d_flip_flop
+Fri Feb 19 16:48:18 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'
+ 13. Setup Times
+ 14. Hold Times
+ 15. Clock to Output Times
+ 16. Minimum Clock to Output Times
+ 17. Slow 1200mV 85C Model Metastability Report
+ 18. Slow 1200mV 0C Model Fmax Summary
+ 19. Slow 1200mV 0C Model Setup Summary
+ 20. Slow 1200mV 0C Model Hold Summary
+ 21. Slow 1200mV 0C Model Recovery Summary
+ 22. Slow 1200mV 0C Model Removal Summary
+ 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 24. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 25. Setup Times
+ 26. Hold Times
+ 27. Clock to Output Times
+ 28. Minimum Clock to Output Times
+ 29. Slow 1200mV 0C Model Metastability Report
+ 30. Fast 1200mV 0C Model Setup Summary
+ 31. Fast 1200mV 0C Model Hold Summary
+ 32. Fast 1200mV 0C Model Recovery Summary
+ 33. Fast 1200mV 0C Model Removal Summary
+ 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 35. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'
+ 36. Setup Times
+ 37. Hold Times
+ 38. Clock to Output Times
+ 39. Minimum Clock to Output Times
+ 40. Fast 1200mV 0C Model Metastability Report
+ 41. Multicorner Timing Analysis Summary
+ 42. Setup Times
+ 43. Hold Times
+ 44. Clock to Output Times
+ 45. Minimum Clock to Output Times
+ 46. Board Trace Model Assignments
+ 47. Input Transition Times
+ 48. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 49. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 50. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 51. Clock Transfers
+ 52. Report TCCS
+ 53. Report RSKM
+ 54. Unconstrained Paths
+ 55. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; ten_d_flip_flop                                    ;
+; Device Family      ; Cyclone IV GX                                      ;
+; Device Name        ; EP4CGX15BF14C6                                     ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                          ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+; CLK        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLK } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-------+--------+----------------------------------+
+; Clock ; Slack  ; End Point TNS                    ;
++-------+--------+----------------------------------+
+; CLK   ; -3.000 ; -13.000                          ;
++-------+--------+----------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK'                                                           ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst5                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst6                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst7                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst8                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst9                     ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst8                     ;
+; 0.209  ; 0.393        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst5                     ;
+; 0.209  ; 0.393        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst7                     ;
+; 0.210  ; 0.394        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; 0.210  ; 0.394        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; 0.210  ; 0.394        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; 0.210  ; 0.394        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst6                     ;
+; 0.214  ; 0.398        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4                     ;
+; 0.214  ; 0.398        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst9                     ;
+; 0.326  ; 0.326        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.337  ; 0.337        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.369  ; 0.369        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.369  ; 0.369        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.370  ; 0.370        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.370  ; 0.370        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.370  ; 0.370        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.370  ; 0.370        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4                     ;
+; 0.386  ; 0.602        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst9                     ;
+; 0.389  ; 0.605        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.390  ; 0.606        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.390  ; 0.606        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.390  ; 0.606        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst5                     ;
+; 0.390  ; 0.606        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst6                     ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst7                     ;
+; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.392  ; 0.608        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst8                     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.624  ; 0.624        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.624  ; 0.624        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.627  ; 0.627        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.628  ; 0.628        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.628  ; 0.628        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.628  ; 0.628        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.628  ; 0.628        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.629  ; 0.629        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.630  ; 0.630        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.630  ; 0.630        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.662  ; 0.662        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.674  ; 0.674        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-------------------------------------------------------------------------+
+; Setup Times                                                             ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 2.003  ; 2.433  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; 1.547  ; 1.980  ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; 1.718  ; 2.161  ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; 1.495  ; 1.917  ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; 1.479  ; 1.902  ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; 1.541  ; 1.984  ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; 1.645  ; 2.059  ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; 1.850  ; 2.293  ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; 2.003  ; 2.433  ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; -0.285 ; -0.126 ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.037  ; 0.190  ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 0.576  ; 0.416  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; -1.168 ; -1.578 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; -1.344 ; -1.772 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; -1.110 ; -1.513 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; -1.102 ; -1.502 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; -1.162 ; -1.581 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; -1.268 ; -1.673 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; -1.459 ; -1.878 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; -1.612 ; -2.032 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; 0.576  ; 0.416  ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.266  ; 0.113  ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 6.580 ; 6.582 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 6.580 ; 6.582 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 5.476 ; 5.410 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 6.123 ; 6.073 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 6.071 ; 6.017 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 5.901 ; 5.860 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 6.369 ; 6.375 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 5.899 ; 5.874 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 5.745 ; 5.662 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 5.622 ; 5.588 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 6.111 ; 6.049 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 5.297 ; 5.229 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 6.390 ; 6.391 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 5.297 ; 5.229 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 5.922 ; 5.870 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 5.878 ; 5.822 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 5.712 ; 5.670 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 6.159 ; 6.161 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 5.710 ; 5.683 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 5.565 ; 5.481 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 5.443 ; 5.407 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 5.912 ; 5.848 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -13.000                         ;
++-------+--------+---------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst5                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst6                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst7                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst8                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst9                     ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst5                     ;
+; 0.208  ; 0.392        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst7                     ;
+; 0.209  ; 0.393        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; 0.213  ; 0.397        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; 0.214  ; 0.398        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; 0.214  ; 0.398        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; 0.214  ; 0.398        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst6                     ;
+; 0.215  ; 0.399        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst8                     ;
+; 0.217  ; 0.401        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4                     ;
+; 0.218  ; 0.402        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst9                     ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.346  ; 0.346        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.368  ; 0.368        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.369  ; 0.369        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.373  ; 0.373        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.374  ; 0.374        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.375  ; 0.375        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.377  ; 0.377        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.378  ; 0.378        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.380  ; 0.596        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst9                     ;
+; 0.381  ; 0.597        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4                     ;
+; 0.383  ; 0.599        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst8                     ;
+; 0.385  ; 0.601        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.385  ; 0.601        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.385  ; 0.601        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.385  ; 0.601        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst6                     ;
+; 0.390  ; 0.606        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst5                     ;
+; 0.391  ; 0.607        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst7                     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.620  ; 0.620        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.621  ; 0.621        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.623  ; 0.623        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.625  ; 0.625        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.625  ; 0.625        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.625  ; 0.625        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.625  ; 0.625        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.630  ; 0.630        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.631  ; 0.631        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.656  ; 0.656        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++-------------------------------------------------------------------------+
+; Setup Times                                                             ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 1.715  ; 2.066  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; 1.305  ; 1.648  ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; 1.457  ; 1.815  ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; 1.251  ; 1.591  ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; 1.252  ; 1.576  ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; 1.305  ; 1.648  ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; 1.384  ; 1.728  ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; 1.580  ; 1.932  ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; 1.715  ; 2.066  ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; -0.242 ; -0.083 ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.050  ; 0.203  ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 0.504  ; 0.345  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; -0.965 ; -1.294 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; -1.122 ; -1.471 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; -0.910 ; -1.237 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; -0.915 ; -1.226 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; -0.965 ; -1.294 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; -1.051 ; -1.387 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; -1.229 ; -1.567 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; -1.368 ; -1.710 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; 0.504  ; 0.345  ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.223  ; 0.071  ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 5.854 ; 5.838 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 5.854 ; 5.838 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 4.875 ; 4.824 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 5.477 ; 5.407 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 5.460 ; 5.367 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 5.292 ; 5.214 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 5.703 ; 5.685 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 5.291 ; 5.227 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 5.154 ; 5.043 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 5.035 ; 4.969 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 5.469 ; 5.395 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 4.716 ; 4.665 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 5.686 ; 5.669 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 4.716 ; 4.665 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 5.295 ; 5.225 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 5.284 ; 5.190 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 5.123 ; 5.045 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 5.513 ; 5.493 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 5.122 ; 5.057 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 4.991 ; 4.879 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 4.876 ; 4.810 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 5.288 ; 5.213 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-------+--------+---------------------------------+
+; Clock ; Slack  ; End Point TNS                   ;
++-------+--------+---------------------------------+
+; CLK   ; -3.000 ; -13.307                         ;
++-------+--------+---------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK'                                                            ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                    ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; CLK   ; Rise       ; CLK                       ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst                      ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst1                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst2                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst3                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst4                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst5                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst6                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst7                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst8                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; CLK   ; Rise       ; inst9                     ;
+; -0.033 ; 0.151        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst2                     ;
+; -0.033 ; 0.151        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst5                     ;
+; -0.033 ; 0.151        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst7                     ;
+; -0.032 ; 0.152        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst8                     ;
+; -0.031 ; 0.153        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst1                     ;
+; -0.031 ; 0.153        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst6                     ;
+; -0.030 ; 0.154        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst                      ;
+; -0.030 ; 0.154        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst3                     ;
+; -0.027 ; 0.157        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst4                     ;
+; -0.027 ; 0.157        ; 0.184          ; Low Pulse Width  ; CLK   ; Rise       ; inst9                     ;
+; 0.125  ; 0.125        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|o               ;
+; 0.139  ; 0.139        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.139  ; 0.139        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.147  ; 0.147        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.147  ; 0.147        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.147  ; 0.147        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.148  ; 0.148        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.148  ; 0.148        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.149  ; 0.149        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.149  ; 0.149        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.149  ; 0.149        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst|clk                  ;
+; 0.152  ; 0.152        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.152  ; 0.152        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; CLK   ; Rise       ; CLK~input|i               ;
+; 0.626  ; 0.842        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst4                     ;
+; 0.626  ; 0.842        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst9                     ;
+; 0.629  ; 0.845        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst                      ;
+; 0.629  ; 0.845        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst3                     ;
+; 0.629  ; 0.845        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst6                     ;
+; 0.629  ; 0.845        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst8                     ;
+; 0.630  ; 0.846        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst1                     ;
+; 0.631  ; 0.847        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst2                     ;
+; 0.631  ; 0.847        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst5                     ;
+; 0.631  ; 0.847        ; 0.216          ; High Pulse Width ; CLK   ; Rise       ; inst7                     ;
+; 0.847  ; 0.847        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst4|clk                 ;
+; 0.847  ; 0.847        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst9|clk                 ;
+; 0.850  ; 0.850        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst3|clk                 ;
+; 0.850  ; 0.850        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst|clk                  ;
+; 0.851  ; 0.851        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst1|clk                 ;
+; 0.851  ; 0.851        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst6|clk                 ;
+; 0.851  ; 0.851        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst8|clk                 ;
+; 0.853  ; 0.853        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst2|clk                 ;
+; 0.853  ; 0.853        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst5|clk                 ;
+; 0.853  ; 0.853        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; inst7|clk                 ;
+; 0.861  ; 0.861        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|inclk[0] ;
+; 0.861  ; 0.861        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~inputclkctrl|outclk   ;
+; 0.875  ; 0.875        ; 0.000          ; High Pulse Width ; CLK   ; Rise       ; CLK~input|o               ;
++--------+--------------+----------------+------------------+-------+------------+---------------------------+
+
+
++------------------------------------------------------------------------+
+; Setup Times                                                            ;
++-----------+------------+--------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+-------+------------+-----------------+
+; D[*]      ; CLK        ; 1.122  ; 1.704 ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; 0.853  ; 1.424 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; 0.938  ; 1.507 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; 0.833  ; 1.394 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; 0.814  ; 1.372 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; 0.853  ; 1.423 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; 0.927  ; 1.467 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; 1.032  ; 1.627 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; 1.122  ; 1.704 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; -0.177 ; 0.148 ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.032  ; 0.325 ; Rise       ; CLK             ;
++-----------+------------+--------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 0.340  ; 0.014  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; -0.639 ; -1.194 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; -0.724 ; -1.285 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; -0.618 ; -1.165 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; -0.601 ; -1.145 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; -0.639 ; -1.194 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; -0.714 ; -1.248 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; -0.810 ; -1.389 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; -0.901 ; -1.476 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; 0.340  ; 0.014  ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.140  ; -0.155 ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 3.982 ; 4.022 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 3.982 ; 4.022 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 3.203 ; 3.213 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 3.565 ; 3.619 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 3.563 ; 3.624 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 3.512 ; 3.512 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 3.732 ; 3.824 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 3.516 ; 3.523 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 3.364 ; 3.391 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 3.353 ; 3.338 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 3.561 ; 3.612 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 3.096 ; 3.105 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 3.869 ; 3.907 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 3.096 ; 3.105 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 3.446 ; 3.497 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 3.446 ; 3.505 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 3.399 ; 3.397 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 3.606 ; 3.694 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 3.403 ; 3.408 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 3.256 ; 3.282 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 3.247 ; 3.231 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 3.441 ; 3.489 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; -3.000              ;
+;  CLK             ; N/A   ; N/A  ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; -13.307             ;
+;  CLK             ; N/A   ; N/A  ; N/A      ; N/A     ; -13.307             ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------+
+; Setup Times                                                            ;
++-----------+------------+--------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+-------+------------+-----------------+
+; D[*]      ; CLK        ; 2.003  ; 2.433 ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; 1.547  ; 1.980 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; 1.718  ; 2.161 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; 1.495  ; 1.917 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; 1.479  ; 1.902 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; 1.541  ; 1.984 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; 1.645  ; 2.059 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; 1.850  ; 2.293 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; 2.003  ; 2.433 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; -0.177 ; 0.148 ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.050  ; 0.325 ; Rise       ; CLK             ;
++-----------+------------+--------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; D[*]      ; CLK        ; 0.576  ; 0.416  ; Rise       ; CLK             ;
+;  D[0]     ; CLK        ; -0.639 ; -1.194 ; Rise       ; CLK             ;
+;  D[1]     ; CLK        ; -0.724 ; -1.285 ; Rise       ; CLK             ;
+;  D[2]     ; CLK        ; -0.618 ; -1.165 ; Rise       ; CLK             ;
+;  D[3]     ; CLK        ; -0.601 ; -1.145 ; Rise       ; CLK             ;
+;  D[4]     ; CLK        ; -0.639 ; -1.194 ; Rise       ; CLK             ;
+;  D[5]     ; CLK        ; -0.714 ; -1.248 ; Rise       ; CLK             ;
+;  D[6]     ; CLK        ; -0.810 ; -1.389 ; Rise       ; CLK             ;
+;  D[7]     ; CLK        ; -0.901 ; -1.476 ; Rise       ; CLK             ;
+;  D[8]     ; CLK        ; 0.576  ; 0.416  ; Rise       ; CLK             ;
+;  D[9]     ; CLK        ; 0.266  ; 0.113  ; Rise       ; CLK             ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 6.580 ; 6.582 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 6.580 ; 6.582 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 5.476 ; 5.410 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 6.123 ; 6.073 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 6.071 ; 6.017 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 5.901 ; 5.860 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 6.369 ; 6.375 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 5.899 ; 5.874 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 5.745 ; 5.662 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 5.622 ; 5.588 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 6.111 ; 6.049 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; Q[*]      ; CLK        ; 3.096 ; 3.105 ; Rise       ; CLK             ;
+;  Q[0]     ; CLK        ; 3.869 ; 3.907 ; Rise       ; CLK             ;
+;  Q[1]     ; CLK        ; 3.096 ; 3.105 ; Rise       ; CLK             ;
+;  Q[2]     ; CLK        ; 3.446 ; 3.497 ; Rise       ; CLK             ;
+;  Q[3]     ; CLK        ; 3.446 ; 3.505 ; Rise       ; CLK             ;
+;  Q[4]     ; CLK        ; 3.399 ; 3.397 ; Rise       ; CLK             ;
+;  Q[5]     ; CLK        ; 3.606 ; 3.694 ; Rise       ; CLK             ;
+;  Q[6]     ; CLK        ; 3.403 ; 3.408 ; Rise       ; CLK             ;
+;  Q[7]     ; CLK        ; 3.256 ; 3.282 ; Rise       ; CLK             ;
+;  Q[8]     ; CLK        ; 3.247 ; 3.231 ; Rise       ; CLK             ;
+;  Q[9]     ; CLK        ; 3.441 ; 3.489 ; Rise       ; CLK             ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Q[9]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[8]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[7]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[6]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[5]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[4]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[3]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[2]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[1]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; Q[0]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------------+
+; Input Transition Times                                            ;
++----------------+--------------+-----------------+-----------------+
+; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------------+--------------+-----------------+-----------------+
+; D[9]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; CLK            ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[8]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[7]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[6]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[5]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[4]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[3]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[2]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[1]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; D[0]           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_NCSO~  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Q[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; Q[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; Q[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; Q[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; Q[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; Q[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.37 V              ; -0.00861 V          ; 0.168 V                              ; 0.038 V                              ; 6.79e-10 s                  ; 6.49e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.37 V             ; -0.00861 V         ; 0.168 V                             ; 0.038 V                             ; 6.79e-10 s                 ; 6.49e-10 s                 ; No                        ; Yes                       ;
+; Q[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00317 V          ; 0.179 V                              ; 0.007 V                              ; 4.7e-10 s                   ; 4.72e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00317 V         ; 0.179 V                             ; 0.007 V                             ; 4.7e-10 s                  ; 4.72e-10 s                 ; No                        ; Yes                       ;
+; Q[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.29e-09 V                   ; 2.39 V              ; -0.00339 V          ; 0.206 V                              ; 0.007 V                              ; 2.77e-10 s                  ; 3.24e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.29e-09 V                  ; 2.39 V             ; -0.00339 V         ; 0.206 V                             ; 0.007 V                             ; 2.77e-10 s                 ; 3.24e-10 s                 ; Yes                       ; Yes                       ;
+; Q[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.4 V               ; -0.00557 V          ; 0.238 V                              ; 0.014 V                              ; 2.9e-10 s                   ; 3.48e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.4 V              ; -0.00557 V         ; 0.238 V                             ; 0.014 V                             ; 2.9e-10 s                  ; 3.48e-10 s                 ; No                        ; Yes                       ;
+; Q[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.16e-09 V                   ; 2.34 V              ; -0.00633 V          ; 0.232 V                              ; 0.083 V                              ; 1.94e-09 s                  ; 1.83e-09 s                  ; No                         ; Yes                        ; 2.32 V                      ; 5.16e-09 V                  ; 2.34 V             ; -0.00633 V         ; 0.232 V                             ; 0.083 V                             ; 1.94e-09 s                 ; 1.83e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 4.76e-09 V                   ; 2.4 V               ; -0.034 V            ; 0.102 V                              ; 0.065 V                              ; 2.49e-10 s                  ; 3.49e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 4.76e-09 V                  ; 2.4 V              ; -0.034 V           ; 0.102 V                             ; 0.065 V                             ; 2.49e-10 s                 ; 3.49e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.94e-09 V                   ; 2.39 V              ; -0.0344 V           ; 0.156 V                              ; 0.089 V                              ; 2.68e-10 s                  ; 2.6e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 5.94e-09 V                  ; 2.39 V             ; -0.0344 V          ; 0.156 V                             ; 0.089 V                             ; 2.68e-10 s                 ; 2.6e-10 s                  ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Q[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; Q[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; Q[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; Q[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; Q[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; Q[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.35 V              ; -0.00662 V          ; 0.129 V                              ; 0.049 V                              ; 8.55e-10 s                  ; 8.01e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.35 V             ; -0.00662 V         ; 0.129 V                             ; 0.049 V                             ; 8.55e-10 s                 ; 8.01e-10 s                 ; No                        ; Yes                       ;
+; Q[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.36 V              ; -0.00833 V          ; 0.113 V                              ; 0.035 V                              ; 6.32e-10 s                  ; 5.89e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.36 V             ; -0.00833 V         ; 0.113 V                             ; 0.035 V                             ; 6.32e-10 s                 ; 5.89e-10 s                 ; No                        ; Yes                       ;
+; Q[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.21e-06 V                   ; 2.37 V              ; -0.00606 V          ; 0.107 V                              ; 0.021 V                              ; 4.26e-10 s                  ; 4.03e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.21e-06 V                  ; 2.37 V             ; -0.00606 V         ; 0.107 V                             ; 0.021 V                             ; 4.26e-10 s                 ; 4.03e-10 s                 ; Yes                       ; Yes                       ;
+; Q[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.36 V              ; -0.00623 V          ; 0.121 V                              ; 0.03 V                               ; 4.4e-10 s                   ; 4.28e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.36 V             ; -0.00623 V         ; 0.121 V                             ; 0.03 V                              ; 4.4e-10 s                  ; 4.28e-10 s                 ; Yes                       ; Yes                       ;
+; Q[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 8.13e-07 V                   ; 2.33 V              ; -0.00252 V          ; 0.203 V                              ; 0.046 V                              ; 2.34e-09 s                  ; 2.24e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 8.13e-07 V                  ; 2.33 V             ; -0.00252 V         ; 0.203 V                             ; 0.046 V                             ; 2.34e-09 s                 ; 2.24e-09 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 7.93e-07 V                   ; 2.37 V              ; -0.0278 V           ; 0.106 V                              ; 0.115 V                              ; 2.69e-10 s                  ; 4.05e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 7.93e-07 V                  ; 2.37 V             ; -0.0278 V          ; 0.106 V                             ; 0.115 V                             ; 2.69e-10 s                 ; 4.05e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.76e-07 V                   ; 2.36 V              ; -0.00439 V          ; 0.088 V                              ; 0.007 V                              ; 4.05e-10 s                  ; 3.35e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.76e-07 V                  ; 2.36 V             ; -0.00439 V         ; 0.088 V                             ; 0.007 V                             ; 4.05e-10 s                 ; 3.35e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Q[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; Q[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; Q[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; Q[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; Q[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; Q[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.71 V              ; -0.0171 V           ; 0.273 V                              ; 0.065 V                              ; 4.95e-10 s                  ; 5.37e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.71 V             ; -0.0171 V          ; 0.273 V                             ; 0.065 V                             ; 4.95e-10 s                 ; 5.37e-10 s                 ; No                        ; Yes                       ;
+; Q[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.72 V              ; -0.0215 V           ; 0.161 V                              ; 0.061 V                              ; 4.44e-10 s                  ; 4.06e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.72 V             ; -0.0215 V          ; 0.161 V                             ; 0.061 V                             ; 4.44e-10 s                 ; 4.06e-10 s                 ; No                        ; Yes                       ;
+; Q[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.66e-08 V                   ; 2.73 V              ; -0.0205 V           ; 0.17 V                               ; 0.027 V                              ; 2.58e-10 s                  ; 2.57e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.66e-08 V                  ; 2.73 V             ; -0.0205 V          ; 0.17 V                              ; 0.027 V                             ; 2.58e-10 s                 ; 2.57e-10 s                 ; Yes                       ; Yes                       ;
+; Q[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.72 V              ; -0.0199 V           ; 0.186 V                              ; 0.027 V                              ; 2.63e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.72 V             ; -0.0199 V          ; 0.186 V                             ; 0.027 V                             ; 2.63e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; Q[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.16e-08 V                   ; 2.65 V              ; -0.0109 V           ; 0.234 V                              ; 0.125 V                              ; 1.64e-09 s                  ; 1.59e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.16e-08 V                  ; 2.65 V             ; -0.0109 V          ; 0.234 V                             ; 0.125 V                             ; 1.64e-09 s                 ; 1.59e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_NCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.06e-08 V                   ; 2.86 V              ; -0.0341 V           ; 0.364 V                              ; 0.046 V                              ; 1.17e-10 s                  ; 2.6e-10 s                   ; No                         ; Yes                        ; 2.62 V                      ; 3.06e-08 V                  ; 2.86 V             ; -0.0341 V          ; 0.364 V                             ; 0.046 V                             ; 1.17e-10 s                 ; 2.6e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.81e-08 V                   ; 2.72 V              ; -0.0542 V           ; 0.144 V                              ; 0.087 V                              ; 2.55e-10 s                  ; 2.14e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 3.81e-08 V                  ; 2.72 V             ; -0.0542 V          ; 0.144 V                             ; 0.087 V                             ; 2.55e-10 s                 ; 2.14e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 10    ; 10   ;
+; Unconstrained Output Ports      ; 10    ; 10   ;
+; Unconstrained Output Port Paths ; 10    ; 10   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Fri Feb 19 16:48:16 2016
+Info: Command: quartus_sta ten_d_flip_flop -c ten_d_flip_flop
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_d_flip_flop.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLK CLK
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -13.000 CLK 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -13.000 CLK 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -13.307 CLK 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 523 megabytes
+    Info: Processing ended: Fri Feb 19 16:48:18 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.summary b/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.summary
new file mode 100644
index 0000000..d9a211f
--- /dev/null
+++ b/ten_d_flip_flop/output_files/ten_d_flip_flop.sta.summary
@@ -0,0 +1,17 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -13.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -13.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLK'
+Slack : -3.000
+TNS   : -13.307
+
+------------------------------------------------------------
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.sft b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.sft
new file mode 100644
index 0000000..1ebcb8b
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {ten_d_flip_flop_6_1200mv_85c_slow.vho ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {ten_d_flip_flop_6_1200mv_0c_slow.vho ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {ten_d_flip_flop_min_1200mv_0c_fast.vho ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.vho b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.vho
new file mode 100644
index 0000000..5ebc801
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop.vho
@@ -0,0 +1,621 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:48:20"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_d_flip_flop IS
+    PORT (
+	Q : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	D : IN std_logic_vector(9 DOWNTO 0)
+	);
+END ten_d_flip_flop;
+
+-- Design Ports Information
+-- Q[9]	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[8]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[7]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[6]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[5]	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[4]	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[3]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[2]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[1]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[0]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[9]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[8]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[7]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[6]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[5]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[4]	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[3]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[2]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[1]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[0]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_d_flip_flop IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Q : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_D : std_logic_vector(9 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Q[9]~output_o\ : std_logic;
+SIGNAL \Q[8]~output_o\ : std_logic;
+SIGNAL \Q[7]~output_o\ : std_logic;
+SIGNAL \Q[6]~output_o\ : std_logic;
+SIGNAL \Q[5]~output_o\ : std_logic;
+SIGNAL \Q[4]~output_o\ : std_logic;
+SIGNAL \Q[3]~output_o\ : std_logic;
+SIGNAL \Q[2]~output_o\ : std_logic;
+SIGNAL \Q[1]~output_o\ : std_logic;
+SIGNAL \Q[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \D[9]~input_o\ : std_logic;
+SIGNAL \inst9~q\ : std_logic;
+SIGNAL \D[8]~input_o\ : std_logic;
+SIGNAL \inst8~q\ : std_logic;
+SIGNAL \D[7]~input_o\ : std_logic;
+SIGNAL \inst7~q\ : std_logic;
+SIGNAL \D[6]~input_o\ : std_logic;
+SIGNAL \inst6~feeder_combout\ : std_logic;
+SIGNAL \inst6~q\ : std_logic;
+SIGNAL \D[5]~input_o\ : std_logic;
+SIGNAL \inst5~q\ : std_logic;
+SIGNAL \D[4]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \D[3]~input_o\ : std_logic;
+SIGNAL \inst3~feeder_combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \D[2]~input_o\ : std_logic;
+SIGNAL \inst2~feeder_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \D[1]~input_o\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \D[0]~input_o\ : std_logic;
+SIGNAL \inst~feeder_combout\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+
+BEGIN
+
+Q <= ww_Q;
+ww_CLK <= CLK;
+ww_D <= D;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\Q[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9~q\,
+	devoe => ww_devoe,
+	o => \Q[9]~output_o\);
+
+-- Location: IOOBUF_X33_Y22_N2
+\Q[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8~q\,
+	devoe => ww_devoe,
+	o => \Q[8]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\Q[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~q\,
+	devoe => ww_devoe,
+	o => \Q[7]~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\Q[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~q\,
+	devoe => ww_devoe,
+	o => \Q[6]~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N2
+\Q[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~q\,
+	devoe => ww_devoe,
+	o => \Q[5]~output_o\);
+
+-- Location: IOOBUF_X33_Y12_N9
+\Q[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst4~q\,
+	devoe => ww_devoe,
+	o => \Q[4]~output_o\);
+
+-- Location: IOOBUF_X26_Y31_N2
+\Q[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \Q[3]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\Q[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \Q[2]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N2
+\Q[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \Q[1]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N9
+\Q[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \Q[0]~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N15
+\CLK~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G17
+\CLK~inputclkctrl\ : cycloneiv_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\D[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(9),
+	o => \D[9]~input_o\);
+
+-- Location: FF_X32_Y7_N1
+inst9 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[9]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst9~q\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\D[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(8),
+	o => \D[8]~input_o\);
+
+-- Location: FF_X32_Y22_N9
+inst8 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[8]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst8~q\);
+
+-- Location: IOIBUF_X26_Y31_N8
+\D[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(7),
+	o => \D[7]~input_o\);
+
+-- Location: FF_X29_Y30_N1
+inst7 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[7]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst7~q\);
+
+-- Location: IOIBUF_X33_Y24_N8
+\D[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(6),
+	o => \D[6]~input_o\);
+
+-- Location: LCCOMB_X32_Y19_N8
+\inst6~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~feeder_combout\ = \D[6]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[6]~input_o\,
+	combout => \inst6~feeder_combout\);
+
+-- Location: FF_X32_Y19_N9
+inst6 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst6~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst6~q\);
+
+-- Location: IOIBUF_X29_Y31_N8
+\D[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(5),
+	o => \D[5]~input_o\);
+
+-- Location: FF_X30_Y30_N17
+inst5 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[5]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst5~q\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\D[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(4),
+	o => \D[4]~input_o\);
+
+-- Location: LCCOMB_X32_Y10_N16
+\inst4~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \D[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[4]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X32_Y10_N17
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\D[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(3),
+	o => \D[3]~input_o\);
+
+-- Location: LCCOMB_X30_Y27_N0
+\inst3~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~feeder_combout\ = \D[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[3]~input_o\,
+	combout => \inst3~feeder_combout\);
+
+-- Location: FF_X30_Y27_N1
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst3~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: IOIBUF_X24_Y31_N1
+\D[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(2),
+	o => \D[2]~input_o\);
+
+-- Location: LCCOMB_X23_Y30_N16
+\inst2~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~feeder_combout\ = \D[2]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[2]~input_o\,
+	combout => \inst2~feeder_combout\);
+
+-- Location: FF_X23_Y30_N17
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: IOIBUF_X33_Y24_N1
+\D[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(1),
+	o => \D[1]~input_o\);
+
+-- Location: FF_X32_Y25_N9
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: IOIBUF_X33_Y27_N1
+\D[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(0),
+	o => \D[0]~input_o\);
+
+-- Location: LCCOMB_X32_Y26_N8
+\inst~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst~feeder_combout\ = \D[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[0]~input_o\,
+	combout => \inst~feeder_combout\);
+
+-- Location: FF_X32_Y26_N9
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+ww_Q(9) <= \Q[9]~output_o\;
+
+ww_Q(8) <= \Q[8]~output_o\;
+
+ww_Q(7) <= \Q[7]~output_o\;
+
+ww_Q(6) <= \Q[6]~output_o\;
+
+ww_Q(5) <= \Q[5]~output_o\;
+
+ww_Q(4) <= \Q[4]~output_o\;
+
+ww_Q(3) <= \Q[3]~output_o\;
+
+ww_Q(2) <= \Q[2]~output_o\;
+
+ww_Q(1) <= \Q[1]~output_o\;
+
+ww_Q(0) <= \Q[0]~output_o\;
+END structure;
+
+
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..5ebc801
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho
@@ -0,0 +1,621 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:48:20"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_d_flip_flop IS
+    PORT (
+	Q : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	D : IN std_logic_vector(9 DOWNTO 0)
+	);
+END ten_d_flip_flop;
+
+-- Design Ports Information
+-- Q[9]	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[8]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[7]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[6]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[5]	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[4]	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[3]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[2]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[1]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[0]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[9]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[8]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[7]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[6]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[5]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[4]	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[3]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[2]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[1]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[0]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_d_flip_flop IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Q : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_D : std_logic_vector(9 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Q[9]~output_o\ : std_logic;
+SIGNAL \Q[8]~output_o\ : std_logic;
+SIGNAL \Q[7]~output_o\ : std_logic;
+SIGNAL \Q[6]~output_o\ : std_logic;
+SIGNAL \Q[5]~output_o\ : std_logic;
+SIGNAL \Q[4]~output_o\ : std_logic;
+SIGNAL \Q[3]~output_o\ : std_logic;
+SIGNAL \Q[2]~output_o\ : std_logic;
+SIGNAL \Q[1]~output_o\ : std_logic;
+SIGNAL \Q[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \D[9]~input_o\ : std_logic;
+SIGNAL \inst9~q\ : std_logic;
+SIGNAL \D[8]~input_o\ : std_logic;
+SIGNAL \inst8~q\ : std_logic;
+SIGNAL \D[7]~input_o\ : std_logic;
+SIGNAL \inst7~q\ : std_logic;
+SIGNAL \D[6]~input_o\ : std_logic;
+SIGNAL \inst6~feeder_combout\ : std_logic;
+SIGNAL \inst6~q\ : std_logic;
+SIGNAL \D[5]~input_o\ : std_logic;
+SIGNAL \inst5~q\ : std_logic;
+SIGNAL \D[4]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \D[3]~input_o\ : std_logic;
+SIGNAL \inst3~feeder_combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \D[2]~input_o\ : std_logic;
+SIGNAL \inst2~feeder_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \D[1]~input_o\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \D[0]~input_o\ : std_logic;
+SIGNAL \inst~feeder_combout\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+
+BEGIN
+
+Q <= ww_Q;
+ww_CLK <= CLK;
+ww_D <= D;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\Q[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9~q\,
+	devoe => ww_devoe,
+	o => \Q[9]~output_o\);
+
+-- Location: IOOBUF_X33_Y22_N2
+\Q[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8~q\,
+	devoe => ww_devoe,
+	o => \Q[8]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\Q[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~q\,
+	devoe => ww_devoe,
+	o => \Q[7]~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\Q[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~q\,
+	devoe => ww_devoe,
+	o => \Q[6]~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N2
+\Q[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~q\,
+	devoe => ww_devoe,
+	o => \Q[5]~output_o\);
+
+-- Location: IOOBUF_X33_Y12_N9
+\Q[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst4~q\,
+	devoe => ww_devoe,
+	o => \Q[4]~output_o\);
+
+-- Location: IOOBUF_X26_Y31_N2
+\Q[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \Q[3]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\Q[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \Q[2]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N2
+\Q[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \Q[1]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N9
+\Q[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \Q[0]~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N15
+\CLK~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G17
+\CLK~inputclkctrl\ : cycloneiv_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\D[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(9),
+	o => \D[9]~input_o\);
+
+-- Location: FF_X32_Y7_N1
+inst9 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[9]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst9~q\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\D[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(8),
+	o => \D[8]~input_o\);
+
+-- Location: FF_X32_Y22_N9
+inst8 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[8]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst8~q\);
+
+-- Location: IOIBUF_X26_Y31_N8
+\D[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(7),
+	o => \D[7]~input_o\);
+
+-- Location: FF_X29_Y30_N1
+inst7 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[7]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst7~q\);
+
+-- Location: IOIBUF_X33_Y24_N8
+\D[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(6),
+	o => \D[6]~input_o\);
+
+-- Location: LCCOMB_X32_Y19_N8
+\inst6~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~feeder_combout\ = \D[6]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[6]~input_o\,
+	combout => \inst6~feeder_combout\);
+
+-- Location: FF_X32_Y19_N9
+inst6 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst6~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst6~q\);
+
+-- Location: IOIBUF_X29_Y31_N8
+\D[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(5),
+	o => \D[5]~input_o\);
+
+-- Location: FF_X30_Y30_N17
+inst5 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[5]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst5~q\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\D[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(4),
+	o => \D[4]~input_o\);
+
+-- Location: LCCOMB_X32_Y10_N16
+\inst4~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \D[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[4]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X32_Y10_N17
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\D[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(3),
+	o => \D[3]~input_o\);
+
+-- Location: LCCOMB_X30_Y27_N0
+\inst3~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~feeder_combout\ = \D[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[3]~input_o\,
+	combout => \inst3~feeder_combout\);
+
+-- Location: FF_X30_Y27_N1
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst3~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: IOIBUF_X24_Y31_N1
+\D[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(2),
+	o => \D[2]~input_o\);
+
+-- Location: LCCOMB_X23_Y30_N16
+\inst2~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~feeder_combout\ = \D[2]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[2]~input_o\,
+	combout => \inst2~feeder_combout\);
+
+-- Location: FF_X23_Y30_N17
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: IOIBUF_X33_Y24_N1
+\D[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(1),
+	o => \D[1]~input_o\);
+
+-- Location: FF_X32_Y25_N9
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: IOIBUF_X33_Y27_N1
+\D[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(0),
+	o => \D[0]~input_o\);
+
+-- Location: LCCOMB_X32_Y26_N8
+\inst~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst~feeder_combout\ = \D[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[0]~input_o\,
+	combout => \inst~feeder_combout\);
+
+-- Location: FF_X32_Y26_N9
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+ww_Q(9) <= \Q[9]~output_o\;
+
+ww_Q(8) <= \Q[8]~output_o\;
+
+ww_Q(7) <= \Q[7]~output_o\;
+
+ww_Q(6) <= \Q[6]~output_o\;
+
+ww_Q(5) <= \Q[5]~output_o\;
+
+ww_Q(4) <= \Q[4]~output_o\;
+
+ww_Q(3) <= \Q[3]~output_o\;
+
+ww_Q(2) <= \Q[2]~output_o\;
+
+ww_Q(1) <= \Q[1]~output_o\;
+
+ww_Q(0) <= \Q[0]~output_o\;
+END structure;
+
+
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..e134099
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,437 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_d_flip_flop")
+  (DATE "02/19/2016 16:48:21")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (962:962:962) (959:959:959))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (317:317:317) (339:339:339))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (490:490:490) (486:486:486))
+        (IOPATH i o (2354:2354:2354) (2247:2247:2247))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (569:569:569) (593:593:593))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1172:1172:1172) (1225:1225:1225))
+        (IOPATH i o (2221:2221:2221) (2150:2150:2150))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (567:567:567) (577:577:577))
+        (IOPATH i o (2429:2429:2429) (2341:2341:2341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (816:816:816) (830:830:830))
+        (IOPATH i o (2344:2344:2344) (2237:2237:2237))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (950:950:950) (951:951:951))
+        (IOPATH i o (2211:2211:2211) (2140:2140:2140))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (317:317:317) (339:339:339))
+        (IOPATH i o (2261:2261:2261) (2188:2188:2188))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (562:562:562) (580:580:580))
+        (IOPATH i o (2993:2993:2993) (2959:2959:2959))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (508:508:508) (664:664:664))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (342:342:342) (340:340:340))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1266:1266:1266) (1246:1246:1246))
+        (PORT asdata (1596:1596:1596) (1595:1595:1595))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (495:495:495) (649:649:649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1259:1259:1259) (1242:1242:1242))
+        (PORT asdata (1307:1307:1307) (1312:1312:1312))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (518:518:518) (674:674:674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1280:1280:1280) (1271:1271:1271))
+        (PORT asdata (3261:3261:3261) (3456:3456:3456))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst6\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2937:2937:2937) (3148:3148:3148))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1263:1263:1263) (1248:1248:1248))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (518:518:518) (674:674:674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1280:1280:1280) (1271:1271:1271))
+        (PORT asdata (2931:2931:2931) (3119:3119:3119))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2665:2665:2665) (2867:2867:2867))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1266:1266:1266) (1247:1247:1247))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (669:669:669))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2606:2606:2606) (2789:2789:2789))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1270:1270:1270) (1255:1255:1255))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (498:498:498) (654:654:654))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2637:2637:2637) (2834:2834:2834))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1286:1286:1286) (1276:1276:1276))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (505:505:505) (659:659:659))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1267:1267:1267) (1252:1252:1252))
+        (PORT asdata (3004:3004:3004) (3208:3208:3208))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (669:669:669))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (2658:2658:2658) (2860:2860:2860))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1269:1269:1269) (1254:1254:1254))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+)
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_slow.vho b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..5ebc801
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_slow.vho
@@ -0,0 +1,621 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:48:20"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_d_flip_flop IS
+    PORT (
+	Q : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	D : IN std_logic_vector(9 DOWNTO 0)
+	);
+END ten_d_flip_flop;
+
+-- Design Ports Information
+-- Q[9]	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[8]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[7]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[6]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[5]	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[4]	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[3]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[2]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[1]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[0]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[9]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[8]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[7]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[6]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[5]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[4]	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[3]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[2]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[1]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[0]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_d_flip_flop IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Q : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_D : std_logic_vector(9 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Q[9]~output_o\ : std_logic;
+SIGNAL \Q[8]~output_o\ : std_logic;
+SIGNAL \Q[7]~output_o\ : std_logic;
+SIGNAL \Q[6]~output_o\ : std_logic;
+SIGNAL \Q[5]~output_o\ : std_logic;
+SIGNAL \Q[4]~output_o\ : std_logic;
+SIGNAL \Q[3]~output_o\ : std_logic;
+SIGNAL \Q[2]~output_o\ : std_logic;
+SIGNAL \Q[1]~output_o\ : std_logic;
+SIGNAL \Q[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \D[9]~input_o\ : std_logic;
+SIGNAL \inst9~q\ : std_logic;
+SIGNAL \D[8]~input_o\ : std_logic;
+SIGNAL \inst8~q\ : std_logic;
+SIGNAL \D[7]~input_o\ : std_logic;
+SIGNAL \inst7~q\ : std_logic;
+SIGNAL \D[6]~input_o\ : std_logic;
+SIGNAL \inst6~feeder_combout\ : std_logic;
+SIGNAL \inst6~q\ : std_logic;
+SIGNAL \D[5]~input_o\ : std_logic;
+SIGNAL \inst5~q\ : std_logic;
+SIGNAL \D[4]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \D[3]~input_o\ : std_logic;
+SIGNAL \inst3~feeder_combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \D[2]~input_o\ : std_logic;
+SIGNAL \inst2~feeder_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \D[1]~input_o\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \D[0]~input_o\ : std_logic;
+SIGNAL \inst~feeder_combout\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+
+BEGIN
+
+Q <= ww_Q;
+ww_CLK <= CLK;
+ww_D <= D;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\Q[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9~q\,
+	devoe => ww_devoe,
+	o => \Q[9]~output_o\);
+
+-- Location: IOOBUF_X33_Y22_N2
+\Q[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8~q\,
+	devoe => ww_devoe,
+	o => \Q[8]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\Q[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~q\,
+	devoe => ww_devoe,
+	o => \Q[7]~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\Q[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~q\,
+	devoe => ww_devoe,
+	o => \Q[6]~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N2
+\Q[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~q\,
+	devoe => ww_devoe,
+	o => \Q[5]~output_o\);
+
+-- Location: IOOBUF_X33_Y12_N9
+\Q[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst4~q\,
+	devoe => ww_devoe,
+	o => \Q[4]~output_o\);
+
+-- Location: IOOBUF_X26_Y31_N2
+\Q[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \Q[3]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\Q[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \Q[2]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N2
+\Q[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \Q[1]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N9
+\Q[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \Q[0]~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N15
+\CLK~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G17
+\CLK~inputclkctrl\ : cycloneiv_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\D[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(9),
+	o => \D[9]~input_o\);
+
+-- Location: FF_X32_Y7_N1
+inst9 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[9]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst9~q\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\D[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(8),
+	o => \D[8]~input_o\);
+
+-- Location: FF_X32_Y22_N9
+inst8 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[8]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst8~q\);
+
+-- Location: IOIBUF_X26_Y31_N8
+\D[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(7),
+	o => \D[7]~input_o\);
+
+-- Location: FF_X29_Y30_N1
+inst7 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[7]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst7~q\);
+
+-- Location: IOIBUF_X33_Y24_N8
+\D[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(6),
+	o => \D[6]~input_o\);
+
+-- Location: LCCOMB_X32_Y19_N8
+\inst6~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~feeder_combout\ = \D[6]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[6]~input_o\,
+	combout => \inst6~feeder_combout\);
+
+-- Location: FF_X32_Y19_N9
+inst6 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst6~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst6~q\);
+
+-- Location: IOIBUF_X29_Y31_N8
+\D[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(5),
+	o => \D[5]~input_o\);
+
+-- Location: FF_X30_Y30_N17
+inst5 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[5]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst5~q\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\D[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(4),
+	o => \D[4]~input_o\);
+
+-- Location: LCCOMB_X32_Y10_N16
+\inst4~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \D[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[4]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X32_Y10_N17
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\D[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(3),
+	o => \D[3]~input_o\);
+
+-- Location: LCCOMB_X30_Y27_N0
+\inst3~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~feeder_combout\ = \D[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[3]~input_o\,
+	combout => \inst3~feeder_combout\);
+
+-- Location: FF_X30_Y27_N1
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst3~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: IOIBUF_X24_Y31_N1
+\D[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(2),
+	o => \D[2]~input_o\);
+
+-- Location: LCCOMB_X23_Y30_N16
+\inst2~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~feeder_combout\ = \D[2]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[2]~input_o\,
+	combout => \inst2~feeder_combout\);
+
+-- Location: FF_X23_Y30_N17
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: IOIBUF_X33_Y24_N1
+\D[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(1),
+	o => \D[1]~input_o\);
+
+-- Location: FF_X32_Y25_N9
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: IOIBUF_X33_Y27_N1
+\D[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(0),
+	o => \D[0]~input_o\);
+
+-- Location: LCCOMB_X32_Y26_N8
+\inst~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst~feeder_combout\ = \D[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[0]~input_o\,
+	combout => \inst~feeder_combout\);
+
+-- Location: FF_X32_Y26_N9
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+ww_Q(9) <= \Q[9]~output_o\;
+
+ww_Q(8) <= \Q[8]~output_o\;
+
+ww_Q(7) <= \Q[7]~output_o\;
+
+ww_Q(6) <= \Q[6]~output_o\;
+
+ww_Q(5) <= \Q[5]~output_o\;
+
+ww_Q(4) <= \Q[4]~output_o\;
+
+ww_Q(3) <= \Q[3]~output_o\;
+
+ww_Q(2) <= \Q[2]~output_o\;
+
+ww_Q(1) <= \Q[1]~output_o\;
+
+ww_Q(0) <= \Q[0]~output_o\;
+END structure;
+
+
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..f1b4d56
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,437 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_d_flip_flop")
+  (DATE "02/19/2016 16:48:21")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1037:1037:1037) (1073:1073:1073))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (345:345:345) (382:382:382))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (527:527:527) (546:546:546))
+        (IOPATH i o (2659:2659:2659) (2557:2557:2557))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (616:616:616) (662:662:662))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1265:1265:1265) (1369:1369:1369))
+        (IOPATH i o (2544:2544:2544) (2446:2446:2446))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (615:615:615) (645:645:645))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (877:877:877) (925:925:925))
+        (IOPATH i o (2649:2649:2649) (2547:2547:2547))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1023:1023:1023) (1071:1071:1071))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (345:345:345) (382:382:382))
+        (IOPATH i o (2589:2589:2589) (2486:2486:2486))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (651:651:651))
+        (IOPATH i o (3425:3425:3425) (3387:3387:3387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (390:390:390) (378:378:378))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1430:1430:1430) (1401:1401:1401))
+        (PORT asdata (1778:1778:1778) (1758:1758:1758))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1422:1422:1422) (1399:1399:1399))
+        (PORT asdata (1458:1458:1458) (1444:1444:1444))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (537:537:537) (711:711:711))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1449:1449:1449) (1425:1425:1425))
+        (PORT asdata (3750:3750:3750) (4006:4006:4006))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst6\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3385:3385:3385) (3658:3658:3658))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1428:1428:1428) (1403:1403:1403))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (537:537:537) (711:711:711))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1450:1450:1450) (1425:1425:1425))
+        (PORT asdata (3393:3393:3393) (3633:3633:3633))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3079:3079:3079) (3352:3352:3352))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1431:1431:1431) (1402:1402:1402))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3011:3011:3011) (3264:3264:3264))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1435:1435:1435) (1410:1410:1410))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3064:3064:3064) (3315:3315:3315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1456:1456:1456) (1430:1430:1430))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1432:1432:1432) (1409:1409:1409))
+        (PORT asdata (3461:3461:3461) (3731:3731:3731))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3078:3078:3078) (3341:3341:3341))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1434:1434:1434) (1409:1409:1409))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_fast.vho b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..5ebc801
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_fast.vho
@@ -0,0 +1,621 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "02/19/2016 16:48:20"
+
+-- 
+-- Device: Altera EP4CGX15BF14C6 Package FBGA169
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIV;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	ten_d_flip_flop IS
+    PORT (
+	Q : OUT std_logic_vector(9 DOWNTO 0);
+	CLK : IN std_logic;
+	D : IN std_logic_vector(9 DOWNTO 0)
+	);
+END ten_d_flip_flop;
+
+-- Design Ports Information
+-- Q[9]	=>  Location: PIN_M11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[8]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[7]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[6]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[5]	=>  Location: PIN_N12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[4]	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[3]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[2]	=>  Location: PIN_A6,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[1]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- Q[0]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[9]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- CLK	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[8]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[7]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[6]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[5]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[4]	=>  Location: PIN_K12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[3]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[2]	=>  Location: PIN_B11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[1]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- D[0]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF ten_d_flip_flop IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_Q : std_logic_vector(9 DOWNTO 0);
+SIGNAL ww_CLK : std_logic;
+SIGNAL ww_D : std_logic_vector(9 DOWNTO 0);
+SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \Q[9]~output_o\ : std_logic;
+SIGNAL \Q[8]~output_o\ : std_logic;
+SIGNAL \Q[7]~output_o\ : std_logic;
+SIGNAL \Q[6]~output_o\ : std_logic;
+SIGNAL \Q[5]~output_o\ : std_logic;
+SIGNAL \Q[4]~output_o\ : std_logic;
+SIGNAL \Q[3]~output_o\ : std_logic;
+SIGNAL \Q[2]~output_o\ : std_logic;
+SIGNAL \Q[1]~output_o\ : std_logic;
+SIGNAL \Q[0]~output_o\ : std_logic;
+SIGNAL \CLK~input_o\ : std_logic;
+SIGNAL \CLK~inputclkctrl_outclk\ : std_logic;
+SIGNAL \D[9]~input_o\ : std_logic;
+SIGNAL \inst9~q\ : std_logic;
+SIGNAL \D[8]~input_o\ : std_logic;
+SIGNAL \inst8~q\ : std_logic;
+SIGNAL \D[7]~input_o\ : std_logic;
+SIGNAL \inst7~q\ : std_logic;
+SIGNAL \D[6]~input_o\ : std_logic;
+SIGNAL \inst6~feeder_combout\ : std_logic;
+SIGNAL \inst6~q\ : std_logic;
+SIGNAL \D[5]~input_o\ : std_logic;
+SIGNAL \inst5~q\ : std_logic;
+SIGNAL \D[4]~input_o\ : std_logic;
+SIGNAL \inst4~feeder_combout\ : std_logic;
+SIGNAL \inst4~q\ : std_logic;
+SIGNAL \D[3]~input_o\ : std_logic;
+SIGNAL \inst3~feeder_combout\ : std_logic;
+SIGNAL \inst3~q\ : std_logic;
+SIGNAL \D[2]~input_o\ : std_logic;
+SIGNAL \inst2~feeder_combout\ : std_logic;
+SIGNAL \inst2~q\ : std_logic;
+SIGNAL \D[1]~input_o\ : std_logic;
+SIGNAL \inst1~q\ : std_logic;
+SIGNAL \D[0]~input_o\ : std_logic;
+SIGNAL \inst~feeder_combout\ : std_logic;
+SIGNAL \inst~q\ : std_logic;
+
+BEGIN
+
+Q <= ww_Q;
+ww_CLK <= CLK;
+ww_D <= D;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\);
+
+-- Location: IOOBUF_X29_Y0_N9
+\Q[9]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst9~q\,
+	devoe => ww_devoe,
+	o => \Q[9]~output_o\);
+
+-- Location: IOOBUF_X33_Y22_N2
+\Q[8]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst8~q\,
+	devoe => ww_devoe,
+	o => \Q[8]~output_o\);
+
+-- Location: IOOBUF_X29_Y31_N2
+\Q[7]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst7~q\,
+	devoe => ww_devoe,
+	o => \Q[7]~output_o\);
+
+-- Location: IOOBUF_X33_Y15_N9
+\Q[6]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst6~q\,
+	devoe => ww_devoe,
+	o => \Q[6]~output_o\);
+
+-- Location: IOOBUF_X29_Y0_N2
+\Q[5]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst5~q\,
+	devoe => ww_devoe,
+	o => \Q[5]~output_o\);
+
+-- Location: IOOBUF_X33_Y12_N9
+\Q[4]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst4~q\,
+	devoe => ww_devoe,
+	o => \Q[4]~output_o\);
+
+-- Location: IOOBUF_X26_Y31_N2
+\Q[3]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst3~q\,
+	devoe => ww_devoe,
+	o => \Q[3]~output_o\);
+
+-- Location: IOOBUF_X10_Y31_N2
+\Q[2]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst2~q\,
+	devoe => ww_devoe,
+	o => \Q[2]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N2
+\Q[1]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst1~q\,
+	devoe => ww_devoe,
+	o => \Q[1]~output_o\);
+
+-- Location: IOOBUF_X33_Y25_N9
+\Q[0]~output\ : cycloneiv_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst~q\,
+	devoe => ww_devoe,
+	o => \Q[0]~output_o\);
+
+-- Location: IOIBUF_X16_Y0_N15
+\CLK~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_CLK,
+	o => \CLK~input_o\);
+
+-- Location: CLKCTRL_G17
+\CLK~inputclkctrl\ : cycloneiv_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \CLK~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \CLK~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X33_Y16_N8
+\D[9]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(9),
+	o => \D[9]~input_o\);
+
+-- Location: FF_X32_Y7_N1
+inst9 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[9]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst9~q\);
+
+-- Location: IOIBUF_X33_Y16_N1
+\D[8]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(8),
+	o => \D[8]~input_o\);
+
+-- Location: FF_X32_Y22_N9
+inst8 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[8]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst8~q\);
+
+-- Location: IOIBUF_X26_Y31_N8
+\D[7]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(7),
+	o => \D[7]~input_o\);
+
+-- Location: FF_X29_Y30_N1
+inst7 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[7]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst7~q\);
+
+-- Location: IOIBUF_X33_Y24_N8
+\D[6]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(6),
+	o => \D[6]~input_o\);
+
+-- Location: LCCOMB_X32_Y19_N8
+\inst6~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst6~feeder_combout\ = \D[6]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[6]~input_o\,
+	combout => \inst6~feeder_combout\);
+
+-- Location: FF_X32_Y19_N9
+inst6 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst6~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst6~q\);
+
+-- Location: IOIBUF_X29_Y31_N8
+\D[5]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(5),
+	o => \D[5]~input_o\);
+
+-- Location: FF_X30_Y30_N17
+inst5 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[5]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst5~q\);
+
+-- Location: IOIBUF_X33_Y11_N8
+\D[4]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(4),
+	o => \D[4]~input_o\);
+
+-- Location: LCCOMB_X32_Y10_N16
+\inst4~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst4~feeder_combout\ = \D[4]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[4]~input_o\,
+	combout => \inst4~feeder_combout\);
+
+-- Location: FF_X32_Y10_N17
+inst4 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst4~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst4~q\);
+
+-- Location: IOIBUF_X33_Y27_N8
+\D[3]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(3),
+	o => \D[3]~input_o\);
+
+-- Location: LCCOMB_X30_Y27_N0
+\inst3~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst3~feeder_combout\ = \D[3]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[3]~input_o\,
+	combout => \inst3~feeder_combout\);
+
+-- Location: FF_X30_Y27_N1
+inst3 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst3~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst3~q\);
+
+-- Location: IOIBUF_X24_Y31_N1
+\D[2]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(2),
+	o => \D[2]~input_o\);
+
+-- Location: LCCOMB_X23_Y30_N16
+\inst2~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst2~feeder_combout\ = \D[2]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[2]~input_o\,
+	combout => \inst2~feeder_combout\);
+
+-- Location: FF_X23_Y30_N17
+inst2 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst2~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst2~q\);
+
+-- Location: IOIBUF_X33_Y24_N1
+\D[1]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(1),
+	o => \D[1]~input_o\);
+
+-- Location: FF_X32_Y25_N9
+inst1 : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	asdata => \D[1]~input_o\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst1~q\);
+
+-- Location: IOIBUF_X33_Y27_N1
+\D[0]~input\ : cycloneiv_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_D(0),
+	o => \D[0]~input_o\);
+
+-- Location: LCCOMB_X32_Y26_N8
+\inst~feeder\ : cycloneiv_lcell_comb
+-- Equation(s):
+-- \inst~feeder_combout\ = \D[0]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \D[0]~input_o\,
+	combout => \inst~feeder_combout\);
+
+-- Location: FF_X32_Y26_N9
+inst : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \CLK~inputclkctrl_outclk\,
+	d => \inst~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \inst~q\);
+
+ww_Q(9) <= \Q[9]~output_o\;
+
+ww_Q(8) <= \Q[8]~output_o\;
+
+ww_Q(7) <= \Q[7]~output_o\;
+
+ww_Q(6) <= \Q[6]~output_o\;
+
+ww_Q(5) <= \Q[5]~output_o\;
+
+ww_Q(4) <= \Q[4]~output_o\;
+
+ww_Q(3) <= \Q[3]~output_o\;
+
+ww_Q(2) <= \Q[2]~output_o\;
+
+ww_Q(1) <= \Q[1]~output_o\;
+
+ww_Q(0) <= \Q[0]~output_o\;
+END structure;
+
+
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..13170b7
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,437 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_d_flip_flop")
+  (DATE "02/19/2016 16:48:21")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (567:567:567) (645:645:645))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (177:177:177) (210:210:210))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (271:271:271) (309:309:309))
+        (IOPATH i o (1630:1630:1630) (1619:1619:1619))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (335:335:335) (390:390:390))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (714:714:714) (833:833:833))
+        (IOPATH i o (1555:1555:1555) (1528:1528:1528))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (329:329:329) (377:377:377))
+        (IOPATH i o (1733:1733:1733) (1685:1685:1685))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (488:488:488) (560:560:560))
+        (IOPATH i o (1620:1620:1620) (1609:1609:1609))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (554:554:554) (635:635:635))
+        (IOPATH i o (1545:1545:1545) (1518:1518:1518))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (177:177:177) (210:210:210))
+        (IOPATH i o (1574:1574:1574) (1551:1551:1551))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (325:325:325) (376:376:376))
+        (IOPATH i o (2203:2203:2203) (2192:2192:2192))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (272:272:272) (647:647:647))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (235:235:235) (221:221:221))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (837:837:837) (819:819:819))
+        (PORT asdata (1067:1067:1067) (985:985:985))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (253:253:253) (628:628:628))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (831:831:831) (818:818:818))
+        (PORT asdata (863:863:863) (813:813:813))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (282:282:282) (657:657:657))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (851:851:851) (839:839:839))
+        (PORT asdata (2152:2152:2152) (2359:2359:2359))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst6\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1961:1961:1961) (2173:2173:2173))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (836:836:836) (822:822:822))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (282:282:282) (657:657:657))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (851:851:851) (839:839:839))
+        (PORT asdata (1957:1957:1957) (2122:2122:2122))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1784:1784:1784) (1971:1971:1971))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (838:838:838) (820:820:820))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (273:273:273) (648:648:648))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1740:1740:1740) (1915:1915:1915))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (843:843:843) (828:828:828))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (262:262:262) (637:637:637))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1781:1781:1781) (1959:1959:1959))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (854:854:854) (842:842:842))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (263:263:263) (638:638:638))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (840:840:840) (826:826:826))
+        (PORT asdata (1976:1976:1976) (2170:2170:2170))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (273:273:273) (648:648:648))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1778:1778:1778) (1966:1966:1966))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (842:842:842) (827:827:827))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_modelsim.xrf b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_modelsim.xrf
new file mode 100644
index 0000000..be9e497
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_modelsim.xrf
@@ -0,0 +1,31 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/ten_d_flip_flop.bdf
+source_file = 1, C:/Users/Asus/Documents/GitHub/ten_d_flip_flop/db/ten_d_flip_flop.cbx.xml
+design_name = ten_d_flip_flop
+instance = comp, \Q[9]~output\, Q[9]~output, ten_d_flip_flop, 1
+instance = comp, \Q[8]~output\, Q[8]~output, ten_d_flip_flop, 1
+instance = comp, \Q[7]~output\, Q[7]~output, ten_d_flip_flop, 1
+instance = comp, \Q[6]~output\, Q[6]~output, ten_d_flip_flop, 1
+instance = comp, \Q[5]~output\, Q[5]~output, ten_d_flip_flop, 1
+instance = comp, \Q[4]~output\, Q[4]~output, ten_d_flip_flop, 1
+instance = comp, \Q[3]~output\, Q[3]~output, ten_d_flip_flop, 1
+instance = comp, \Q[2]~output\, Q[2]~output, ten_d_flip_flop, 1
+instance = comp, \Q[1]~output\, Q[1]~output, ten_d_flip_flop, 1
+instance = comp, \Q[0]~output\, Q[0]~output, ten_d_flip_flop, 1
+instance = comp, \CLK~input\, CLK~input, ten_d_flip_flop, 1
+instance = comp, \CLK~inputclkctrl\, CLK~inputclkctrl, ten_d_flip_flop, 1
+instance = comp, \D[9]~input\, D[9]~input, ten_d_flip_flop, 1
+instance = comp, \D[8]~input\, D[8]~input, ten_d_flip_flop, 1
+instance = comp, \D[7]~input\, D[7]~input, ten_d_flip_flop, 1
+instance = comp, \D[6]~input\, D[6]~input, ten_d_flip_flop, 1
+instance = comp, \inst6~feeder\, inst6~feeder, ten_d_flip_flop, 1
+instance = comp, \D[5]~input\, D[5]~input, ten_d_flip_flop, 1
+instance = comp, \D[4]~input\, D[4]~input, ten_d_flip_flop, 1
+instance = comp, \inst4~feeder\, inst4~feeder, ten_d_flip_flop, 1
+instance = comp, \D[3]~input\, D[3]~input, ten_d_flip_flop, 1
+instance = comp, \inst3~feeder\, inst3~feeder, ten_d_flip_flop, 1
+instance = comp, \D[2]~input\, D[2]~input, ten_d_flip_flop, 1
+instance = comp, \inst2~feeder\, inst2~feeder, ten_d_flip_flop, 1
+instance = comp, \D[1]~input\, D[1]~input, ten_d_flip_flop, 1
+instance = comp, \D[0]~input\, D[0]~input, ten_d_flip_flop, 1
+instance = comp, \inst~feeder\, inst~feeder, ten_d_flip_flop, 1
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_vhd.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_vhd.sdo
new file mode 100644
index 0000000..f1b4d56
--- /dev/null
+++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_vhd.sdo
@@ -0,0 +1,437 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CGX15BF14C6 Package FBGA169
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "ten_d_flip_flop")
+  (DATE "02/19/2016 16:48:21")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[9\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1037:1037:1037) (1073:1073:1073))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[8\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (345:345:345) (382:382:382))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[7\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (527:527:527) (546:546:546))
+        (IOPATH i o (2659:2659:2659) (2557:2557:2557))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (616:616:616) (662:662:662))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1265:1265:1265) (1369:1369:1369))
+        (IOPATH i o (2544:2544:2544) (2446:2446:2446))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (615:615:615) (645:645:645))
+        (IOPATH i o (2745:2745:2745) (2674:2674:2674))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (877:877:877) (925:925:925))
+        (IOPATH i o (2649:2649:2649) (2547:2547:2547))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1023:1023:1023) (1071:1071:1071))
+        (IOPATH i o (2534:2534:2534) (2436:2436:2436))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (345:345:345) (382:382:382))
+        (IOPATH i o (2589:2589:2589) (2486:2486:2486))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_obuf")
+    (INSTANCE \\Q\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (611:611:611) (651:651:651))
+        (IOPATH i o (3425:3425:3425) (3387:3387:3387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\CLK\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (527:527:527) (701:701:701))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_clkctrl")
+    (INSTANCE \\CLK\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (390:390:390) (378:378:378))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[9\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst9)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1430:1430:1430) (1401:1401:1401))
+        (PORT asdata (1778:1778:1778) (1758:1758:1758))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[8\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (515:515:515) (688:688:688))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst8)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1422:1422:1422) (1399:1399:1399))
+        (PORT asdata (1458:1458:1458) (1444:1444:1444))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[7\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (537:537:537) (711:711:711))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst7)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1449:1449:1449) (1425:1425:1425))
+        (PORT asdata (3750:3750:3750) (4006:4006:4006))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[6\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst6\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3385:3385:3385) (3658:3658:3658))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst6)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1428:1428:1428) (1403:1403:1403))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[5\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (537:537:537) (711:711:711))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst5)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1450:1450:1450) (1425:1425:1425))
+        (PORT asdata (3393:3393:3393) (3633:3633:3633))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[4\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst4\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3079:3079:3079) (3352:3352:3352))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst4)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1431:1431:1431) (1402:1402:1402))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[3\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst3\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3011:3011:3011) (3264:3264:3264))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst3)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1435:1435:1435) (1410:1410:1410))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[2\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (517:517:517) (691:691:691))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst2\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3064:3064:3064) (3315:3315:3315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst2)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1456:1456:1456) (1430:1430:1430))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[1\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (525:525:525) (698:698:698))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1432:1432:1432) (1409:1409:1409))
+        (PORT asdata (3461:3461:3461) (3731:3731:3731))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_io_ibuf")
+    (INSTANCE \\D\[0\]\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (535:535:535) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiv_lcell_comb")
+    (INSTANCE \\inst\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (3078:3078:3078) (3341:3341:3341))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE inst)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1434:1434:1434) (1409:1409:1409))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/ten_d_flip_flop/ten_d_flip_flop.bdf b/ten_d_flip_flop/ten_d_flip_flop.bdf
new file mode 100644
index 0000000..995a3cc
--- /dev/null
+++ b/ten_d_flip_flop/ten_d_flip_flop.bdf
@@ -0,0 +1,890 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 264 344 432 360)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLK" (rect 5 0 27 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 264 368 432 384)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "D[9..0]" (rect 5 0 40 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 352 392 528 408)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "Q[9..0]" (rect 90 0 124 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 480 256 544 336)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst" (rect 3 68 20 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(line (pt 0 24)(pt 12 24))
+	)
+	(port
+		(pt 32 0)
+		(input)
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
+		(line (pt 32 4)(pt 32 0))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
+		(line (pt 52 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 12 12)(pt 52 12))
+		(line (pt 12 68)(pt 52 68))
+		(line (pt 52 68)(pt 52 12))
+		(line (pt 12 68)(pt 12 12))
+		(line (pt 19 40)(pt 12 47))
+		(line (pt 12 32)(pt 20 40))
+		(circle (rect 28 4 36 12))
+		(circle (rect 28 68 36 76))
+	)
+)
+(symbol
+	(rect 576 256 640 336)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst1" (rect 3 68 26 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(line (pt 0 24)(pt 12 24))
+	)
+	(port
+		(pt 32 0)
+		(input)
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
+		(line (pt 32 4)(pt 32 0))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
+		(line (pt 52 24)(pt 64 24))
+	)
+	(drawing
+		(line (pt 12 12)(pt 52 12))
+		(line (pt 12 68)(pt 52 68))
+		(line (pt 52 68)(pt 52 12))
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+		(line (pt 19 40)(pt 12 47))
+		(line (pt 12 32)(pt 20 40))
+		(circle (rect 28 4 36 12))
+		(circle (rect 28 68 36 76))
+	)
+)
+(symbol
+	(rect 672 256 736 336)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst2" (rect 3 68 26 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(line (pt 0 24)(pt 12 24))
+	)
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+		(pt 32 0)
+		(input)
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+		(line (pt 32 4)(pt 32 0))
+	)
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+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 43 20 48 32)(font "Courier New" (bold)))
+		(line (pt 52 24)(pt 64 24))
+	)
+	(drawing
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+		(line (pt 12 68)(pt 52 68))
+		(line (pt 52 68)(pt 52 12))
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+		(line (pt 12 32)(pt 20 40))
+		(circle (rect 28 4 36 12))
+		(circle (rect 28 68 36 76))
+	)
+)
+(symbol
+	(rect 768 256 832 336)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst3" (rect 3 68 26 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76))
+	)
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+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40))
+	)
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+	)
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+		(circle (rect 28 68 36 76))
+	)
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diff --git a/ten_d_flip_flop/ten_d_flip_flop.bsf b/ten_d_flip_flop/ten_d_flip_flop.bsf
new file mode 100644
index 0000000..f59b6ee
--- /dev/null
+++ b/ten_d_flip_flop/ten_d_flip_flop.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 144 112)
+	(text "ten_d_flip_flop" (rect 5 0 88 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLK" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "CLK" (rect 21 27 44 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "D[9..0]" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "D[9..0]" (rect 21 43 57 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 128 32)
+		(output)
+		(text "Q[9..0]" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "Q[9..0]" (rect 70 27 107 41)(font "Arial" (font_size 8)))
+		(line (pt 128 32)(pt 112 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 112 80))
+	)
+)
diff --git a/ten_d_flip_flop/ten_d_flip_flop.qpf b/ten_d_flip_flop/ten_d_flip_flop.qpf
new file mode 100644
index 0000000..3a93182
--- /dev/null
+++ b/ten_d_flip_flop/ten_d_flip_flop.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 16:32:21  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:32:21  February 19, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ten_d_flip_flop"
diff --git a/ten_d_flip_flop/ten_d_flip_flop.qsf b/ten_d_flip_flop/ten_d_flip_flop.qsf
new file mode 100644
index 0000000..e445baf
--- /dev/null
+++ b/ten_d_flip_flop/ten_d_flip_flop.qsf
@@ -0,0 +1,52 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 16:32:21  February 19, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ten_d_flip_flop_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name DEVICE auto
+set_global_assignment -name TOP_LEVEL_ENTITY ten_d_flip_flop
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:32:21  FEBRUARY 19, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name BDF_FILE ten_d_flip_flop.bdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
\ No newline at end of file
diff --git a/ten_d_flip_flop/ten_d_flip_flop.qws b/ten_d_flip_flop/ten_d_flip_flop.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/ten_d_flip_flop/ten_d_flip_flop.qws