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Diffstat (limited to 'ten_bit_adder/output_files/ten_bit_adder.eda.rpt')
| -rw-r--r-- | ten_bit_adder/output_files/ten_bit_adder.eda.rpt | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/ten_bit_adder/output_files/ten_bit_adder.eda.rpt b/ten_bit_adder/output_files/ten_bit_adder.eda.rpt new file mode 100644 index 0000000..89557c0 --- /dev/null +++ b/ten_bit_adder/output_files/ten_bit_adder.eda.rpt @@ -0,0 +1,107 @@ +EDA Netlist Writer report for ten_bit_adder +Thu Feb 18 22:20:18 2016 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Thu Feb 18 22:20:18 2016 ; +; Revision Name ; ten_bit_adder ; +; Top-level Entity Name ; ten_bit_adder ; +; Family ; Cyclone IV GX ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Tool Name ; ModelSim-Altera (VHDL) ; +; Generate netlist for functional simulation only ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------------------------------------+ +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_slow.vho ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_slow.vho ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_fast.vho ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder.vho ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_85c_vhd_slow.sdo ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_6_1200mv_0c_vhd_slow.sdo ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo ; +; C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/ten_bit_adder_vhd.sdo ; ++-----------------------------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + Info: Processing started: Thu Feb 18 22:20:17 2016 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ten_bit_adder -c ten_bit_adder +Info (204019): Generated file ten_bit_adder_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder.vho in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file ten_bit_adder_vhd.sdo in folder "C:/Users/Asus/Documents/GitHub/ten_bit_adder/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 493 megabytes + Info: Processing ended: Thu Feb 18 22:20:18 2016 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + |