diff options
Diffstat (limited to 'ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo')
| -rw-r--r-- | ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo | 255 |
1 files changed, 255 insertions, 0 deletions
diff --git a/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 0000000..e5c50ae --- /dev/null +++ b/ten_counter/simulation/modelsim/ten_counter_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,255 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP3C16U484C6 Package UFBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP3C16U484C6, +// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "ten_counter") + (DATE "02/26/2016 14:45:46") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\CLK\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (755:755:755) (916:916:916)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\CLK\~inputclkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (140:140:140) (130:130:130)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\cout\~output\\) + (DELAY + (ABSOLUTE + (PORT i (444:444:444) (403:403:403)) + (IOPATH i o (2196:2196:2196) (2184:2184:2184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\count\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (487:487:487) (481:481:481)) + (IOPATH i o (2216:2216:2216) (2204:2204:2204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\count\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (354:354:354) (379:379:379)) + (IOPATH i o (2206:2206:2206) (2194:2194:2194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\count\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (360:360:360) (388:388:388)) + (IOPATH i o (2216:2216:2216) (2204:2204:2204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_obuf") + (INSTANCE \\count\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (358:358:358) (389:389:389)) + (IOPATH i o (2206:2206:2206) (2194:2194:2194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst\~0\\) + (DELAY + (ABSOLUTE + (IOPATH datac combout (312:312:312) (325:325:325)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_io_ibuf") + (INSTANCE \\CLR\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (755:755:755) (916:916:916)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiii_clkctrl") + (INSTANCE \\CLR\~inputclkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (140:140:140) (130:130:130)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT clk (1322:1322:1322) (1342:1342:1342)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1355:1355:1355) (1338:1338:1338)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst2\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (326:326:326)) + (PORT datad (232:232:232) (297:297:297)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT clk (1322:1322:1322) (1342:1342:1342)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1355:1355:1355) (1338:1338:1338)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst5\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (248:248:248) (322:322:322)) + (PORT datad (230:230:230) (295:295:295)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT clk (1322:1322:1322) (1342:1342:1342)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1355:1355:1355) (1338:1338:1338)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE inst17) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (327:327:327)) + (PORT datab (254:254:254) (327:327:327)) + (PORT datad (225:225:225) (287:287:287)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (312:312:312) (325:325:325)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT clk (1322:1322:1322) (1342:1342:1342)) + (PORT d (67:67:67) (78:78:78)) + (PORT clrn (1355:1355:1355) (1338:1338:1338)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (IOPATH (negedge clrn) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiii_lcell_comb") + (INSTANCE \\inst23\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (324:324:324)) + (PORT datab (247:247:247) (322:322:322)) + (PORT datac (361:361:361) (397:397:397)) + (PORT datad (357:357:357) (398:398:398)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) +) |