1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
vendor_name = ModelSim
source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bsf
source_file = 1, C:/Users/Asus/Documents/GitHub/adder/full_adder.bdf
source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
source_file = 1, C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/db/ten_bit_adder_NO_BUS.cbx.xml
design_name = ten_bit_adder_NO_BUS
instance = comp, \Cout~output\, Cout~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S0~output\, S0~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S1~output\, S1~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S2~output\, S2~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S3~output\, S3~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S4~output\, S4~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S5~output\, S5~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S6~output\, S6~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S7~output\, S7~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S8~output\, S8~output, ten_bit_adder_NO_BUS, 1
instance = comp, \S9~output\, S9~output, ten_bit_adder_NO_BUS, 1
instance = comp, \Y9~input\, Y9~input, ten_bit_adder_NO_BUS, 1
instance = comp, \ENY~input\, ENY~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X9~input\, X9~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X8~input\, X8~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y8~input\, Y8~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X7~input\, X7~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y7~input\, Y7~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y6~input\, Y6~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X6~input\, X6~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X5~input\, X5~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y4~input\, Y4~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y2~input\, Y2~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X0~input\, X0~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y0~input\, Y0~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y1~input\, Y1~input, ten_bit_adder_NO_BUS, 1
instance = comp, \X1~input\, X1~input, ten_bit_adder_NO_BUS, 1
instance = comp, \inst9|inst3~0\, inst9|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \X2~input\, X2~input, ten_bit_adder_NO_BUS, 1
instance = comp, \inst10|inst3~0\, inst10|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \X3~input\, X3~input, ten_bit_adder_NO_BUS, 1
instance = comp, \Y3~input\, Y3~input, ten_bit_adder_NO_BUS, 1
instance = comp, \inst11|inst3~0\, inst11|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \X4~input\, X4~input, ten_bit_adder_NO_BUS, 1
instance = comp, \inst12|inst3~0\, inst12|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \Y5~input\, Y5~input, ten_bit_adder_NO_BUS, 1
instance = comp, \inst13|inst3~0\, inst13|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst14|inst3~0\, inst14|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst15|inst3~0\, inst15|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst16|inst3~0\, inst16|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst17|inst3~0\, inst17|inst3~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst8|inst\, inst8|inst, ten_bit_adder_NO_BUS, 1
instance = comp, \inst9|inst2\, inst9|inst2, ten_bit_adder_NO_BUS, 1
instance = comp, \inst10|inst2~0\, inst10|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst11|inst2~0\, inst11|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst12|inst2~0\, inst12|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst13|inst2~0\, inst13|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst14|inst2~0\, inst14|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst15|inst2~0\, inst15|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst16|inst2~0\, inst16|inst2~0, ten_bit_adder_NO_BUS, 1
instance = comp, \inst17|inst2~0\, inst17|inst2~0, ten_bit_adder_NO_BUS, 1
|
