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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747220639 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:40 2016 " "Processing started: Wed Feb 17 22:13:40 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder " "Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747220639 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747221185 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Found entity 1: full_adder" { } { { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1455747221263 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1455747221263 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_adder " "Elaborating entity \"full_adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1455747221292 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1455747221913 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1455747222151 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1455747222151 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7 " "Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1455747222199 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1455747222199 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Implemented 2 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1455747222199 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1455747222199 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "561 " "Peak virtual memory: 561 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:42 2016 " "Processing ended: Wed Feb 17 22:13:42 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747222225 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747224308 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747224309 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:43 2016 " "Processing started: Wed Feb 17 22:13:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747224309 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1455747224309 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1455747224310 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1455747224597 ""}
{ "Info" "0" "" "Project = full_adder" { } { } 0 0 "Project = full_adder" 0 0 "Fitter" 0 0 1455747224598 ""}
{ "Info" "0" "" "Revision = full_adder" { } { } 0 0 "Revision = full_adder" 0 0 "Fitter" 0 0 1455747224598 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1455747224695 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "full_adder EP4CGX15BF14C6 " "Automatically selected device EP4CGX15BF14C6 for design full_adder" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1455747224871 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747224925 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1455747224925 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1455747225031 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1455747225056 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX30BF14C6 " "Device EP4CGX30BF14C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747225637 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CGX22BF14C6 " "Device EP4CGX22BF14C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1455747225637 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1455747225637 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCEO~ N5 " "Pin ~ALTERA_NCEO~ is reserved at location N5" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 21 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ A5 " "Pin ~ALTERA_DATA0~ is reserved at location A5" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 23 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO~ B5 " "Pin ~ALTERA_ASDO~ is reserved at location B5" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 25 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_NCSO~ C5 " "Pin ~ALTERA_NCSO~ is reserved at location C5" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_NCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_NCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 27 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ A4 " "Pin ~ALTERA_DCLK~ is reserved at location A4" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 29 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1455747225639 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1455747225639 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1455747225640 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "5 5 " "No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SUM " "Pin SUM not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { SUM } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 184 848 1024 200 "SUM" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SUM } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 3 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cout " "Pin Cout not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cout } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 264 896 1072 280 "Cout" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 7 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "X " "Pin X not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { X } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 208 360 528 224 "X" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { X } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 4 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Y " "Pin Y not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Y } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 224 360 528 240 "Y" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Y } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 5 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Cin " "Pin Cin not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { Cin } } } { "full_adder.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/full_adder.bdf" { { 240 360 528 256 "Cin" "" } } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Cin } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 0 { 0 ""} 0 6 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1455747225979 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1455747225979 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1455747226208 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1455747226209 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1455747226209 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1455747226209 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1455747226210 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1455747226210 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1455747226210 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1455747226212 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747226212 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1455747226212 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747226212 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1455747226213 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1455747226213 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1455747226213 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1455747226213 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1455747226213 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "5 unused 2.5V 3 2 0 " "Number of I/O pins in group: 5 (unused VREF, 2.5V VCCIO, 3 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1455747226215 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1455747226215 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1455747226215 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "QL0 does not use undetermined 0 0 " "I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 7 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3A does not use undetermined 0 2 " "I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 12 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 12 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 14 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8A does not use undetermined 0 2 " "I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 5 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 5 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 4 0 " "I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1455747226215 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1455747226215 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1455747226215 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747226221 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1455747227476 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747227528 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1455747227535 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1455747227735 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747227735 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1455747229049 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X11_Y0 X21_Y9 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9" { } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y9"} 11 0 11 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1455747229654 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1455747229654 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747229688 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1455747229688 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1455747229688 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1455747229688 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1455747229698 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747229838 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747230025 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1455747230133 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1455747230335 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1455747230763 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/output_files/full_adder.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1455747231303 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "908 " "Peak virtual memory: 908 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:51 2016 " "Processing ended: Wed Feb 17 22:13:51 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747231770 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1455747231770 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1455747234295 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747234296 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:54 2016 " "Processing started: Wed Feb 17 22:13:54 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747234296 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1455747234296 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_asm --read_settings_files=off --write_settings_files=off full_adder -c full_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1455747234297 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1455747235443 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1455747235657 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "518 " "Peak virtual memory: 518 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:13:56 2016 " "Processing ended: Wed Feb 17 22:13:56 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747236557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1455747236557 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1455747237346 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1455747239084 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:13:58 2016 " "Processing started: Wed Feb 17 22:13:58 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta full_adder -c full_adder " "Command: quartus_sta full_adder -c full_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747239085 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1455747239280 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1455747239816 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747239903 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Quartus II" 0 -1 1455747239903 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "full_adder.sdc " "Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1455747240351 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747240352 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747240352 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747240353 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1455747240353 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747240353 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1455747240354 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1455747240362 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1455747240367 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240368 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240385 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240397 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240401 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240405 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747240410 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747240423 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1455747240461 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1455747241333 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747241396 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747241396 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747241397 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747241397 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241397 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241405 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241410 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241416 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241421 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241425 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1455747241436 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1455747241665 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1455747241666 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1455747241666 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1455747241666 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241671 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241676 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241683 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241709 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1455747241729 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747242284 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1455747242284 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "512 " "Peak virtual memory: 512 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 17 22:14:02 2016 " "Processing ended: Wed Feb 17 22:14:02 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747242348 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1455747244542 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 17 22:14:04 2016 " "Processing started: Wed Feb 17 22:14:04 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder " "Command: quartus_eda --read_settings_files=off --write_settings_files=off full_adder -c full_adder" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1455747244543 ""}
{ "Error" "EMSG_PDB_READ_PERMISSION_DENIED" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb " "Can't read database file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb" { } { } 0 114012 "Can't read database file %1!s!" 0 0 "Quartus II" 0 -1 1455747244960 ""}
{ "Error" "EMSG_PDB_READ_PERMISSION_DENIED" "C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb " "Can't read database file C:/Users/Asus/OneDrive - Imperial College London/Documents/FPGA/adder/db/full_adder.map.hdb" { } { } 0 114012 "Can't read database file %1!s!" 0 0 "Quartus II" 0 -1 1455747244960 ""}
{ "Error" "EQNETO_PARTITION_MERGE_NOT_RUN" "full_adder " "Run Partition Merge with top-level entity name \"full_adder\" before running EDA Netlist Writer" { } { } 0 199062 "Run Partition Merge with top-level entity name \"%1!s!\" before running EDA Netlist Writer" 0 0 "Quartus II" 0 -1 1455747244960 ""}
{ "Error" "EQEXE_ERROR_COUNT" "EDA Netlist Writer 3 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 17 22:14:04 2016 " "Processing ended: Wed Feb 17 22:14:04 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747244975 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 12 s " "Quartus II Full Compilation was unsuccessful. 5 errors, 12 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1455747245561 ""}
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