1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
|
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-- DATE "02/17/2016 22:15:19"
--
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS
PORT (
SUM : OUT std_logic;
X : IN std_logic;
Y : IN std_logic;
Cin : IN std_logic;
Cout : OUT std_logic
);
END full_adder;
-- Design Ports Information
-- SUM => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default
-- Cout => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default
-- X => Location: PIN_M4, I/O Standard: 2.5 V, Current Strength: Default
-- Y => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default
-- Cin => Location: PIN_N10, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF full_adder IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_SUM : std_logic;
SIGNAL ww_X : std_logic;
SIGNAL ww_Y : std_logic;
SIGNAL ww_Cin : std_logic;
SIGNAL ww_Cout : std_logic;
SIGNAL \SUM~output_o\ : std_logic;
SIGNAL \Cout~output_o\ : std_logic;
SIGNAL \X~input_o\ : std_logic;
SIGNAL \Cin~input_o\ : std_logic;
SIGNAL \Y~input_o\ : std_logic;
SIGNAL \inst2~0_combout\ : std_logic;
SIGNAL \inst3~0_combout\ : std_logic;
BEGIN
SUM <= ww_SUM;
ww_X <= X;
ww_Y <= Y;
ww_Cin <= Cin;
Cout <= ww_Cout;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
-- Location: IOOBUF_X12_Y0_N9
\SUM~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst2~0_combout\,
devoe => ww_devoe,
o => \SUM~output_o\);
-- Location: IOOBUF_X31_Y0_N2
\Cout~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst3~0_combout\,
devoe => ww_devoe,
o => \Cout~output_o\);
-- Location: IOIBUF_X8_Y0_N1
\X~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_X,
o => \X~input_o\);
-- Location: IOIBUF_X26_Y0_N8
\Cin~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_Cin,
o => \Cin~input_o\);
-- Location: IOIBUF_X8_Y0_N8
\Y~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_Y,
o => \Y~input_o\);
-- Location: LCCOMB_X8_Y1_N24
\inst2~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \inst2~0_combout\ = \X~input_o\ $ (\Cin~input_o\ $ (\Y~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010010101011010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \X~input_o\,
datac => \Cin~input_o\,
datad => \Y~input_o\,
combout => \inst2~0_combout\);
-- Location: LCCOMB_X8_Y1_N2
\inst3~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \inst3~0_combout\ = (\X~input_o\ & ((\Cin~input_o\) # (\Y~input_o\))) # (!\X~input_o\ & (\Cin~input_o\ & \Y~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111101010100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \X~input_o\,
datac => \Cin~input_o\,
datad => \Y~input_o\,
combout => \inst3~0_combout\);
ww_SUM <= \SUM~output_o\;
ww_Cout <= \Cout~output_o\;
END structure;
|
